CN117690472A - Memory device and control method thereof - Google Patents

Abstract

The invention provides a memory device, which comprises a resistor and a controller chip. The resistor is coupled between the connection terminal and the ground terminal. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration of the first set of I/O circuits using the resistors in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration of the second set of I/O circuits using the resistors in response to the second controller calibration request. The first period of time during which the first controller calibration is performed and the second period of time during which the second controller calibration is performed do not overlap.

Description

Memory device and control method thereof

Technical Field

The present invention relates to a memory device, and more particularly, to a nonvolatile memory device and a control method thereof.

Background

To improve signal integrity and enhance signal strength, memory chips employ output drivers and termination resistors to drive and receive signals. However, since the driving force of the output driver and the resistance value of the termination resistor in the memory chip are changed due to the process, voltage and temperature variations, it is necessary to calibrate the output driver and the termination resistor periodically to ensure the signal quality. The ZQ calibration is a calibration method for adjusting the driving force of the output driver and the resistance value of the termination resistor of the chip, and uses a precision ZQ resistor outside the memory chip to calibrate the driving force of the output driver and the resistance value of the termination resistor inside the memory chip.

In ZQ calibration in the related art, each memory chip and controller chip needs to be configured with an independent ZQ resistor, resulting in an increase in circuit area and an increase in manufacturing cost.

Disclosure of Invention

The embodiment of the invention provides a memory device which comprises a resistor and a controller chip. The resistor is coupled between the connection terminal and the ground terminal. The controller chip comprises a first controller, a second controller, a first group of input and output circuits, a second group of input and output circuits, a first calibration circuit, a second calibration circuit and an arbitration circuit. The first controller is configured to transmit a first controller calibration request. The second controller is configured to transmit a second controller calibration request. The first set of input-output circuits is coupled to the first controller. The second set of input-output circuits is coupled to the second controller. The first calibration circuit is coupled to the connection terminal and the first set of input/output circuits, and is used for calibrating a first controller of the first set of input/output circuits by using the resistor. The second calibration circuit is coupled to the connection terminal and the second set of input/output circuits, and is used for performing a second controller calibration of the second set of input/output circuits by using the resistor. The arbitration circuit is coupled to the first controller, the second controller, the first calibration circuit and the second calibration circuit, and is configured to instruct the first calibration circuit to perform the first controller calibration in response to the first controller calibration request, and instruct the second calibration circuit to perform the second controller calibration in response to the second controller calibration request. The first time period when the first calibration circuit performs the first controller calibration and the second time period when the second calibration circuit performs the second controller calibration do not overlap.

The embodiment of the invention also provides a control method of the memory device. The memory device comprises a resistor and a controller chip, the resistor is coupled between the connecting end and the grounding end, the controller chip comprises a first controller, a second controller, a first group of input/output circuits, a second group of input/output circuits, a first calibration circuit, a second calibration circuit and an arbitration circuit, the first group of input/output circuits are coupled to the first controller, the second group of input/output circuits are coupled to the second controller, the first calibration circuit is coupled to the connecting end and the first group of input/output circuits, the second calibration circuit is coupled to the connecting end and the second group of input/output circuits, and the arbitration circuit is coupled to the first controller, the second controller, the first calibration circuit and the second calibration circuit. The control method comprises the steps that a first controller transmits a first controller calibration request, a second controller transmits a second controller calibration request, and an arbitration circuit responds to the first controller calibration request and instructs a first calibration circuit to calibrate the first controller, and responds to the second controller calibration request and instructs a second calibration circuit to calibrate the second controller. The first time period when the first calibration circuit performs the first controller calibration and the second time period when the second calibration circuit performs the second controller calibration do not overlap.

Drawings

FIG. 1 is a schematic diagram of a memory device in an embodiment of the invention;

FIG. 2 is a flow chart of a method of controlling the memory device of FIG. 1;

FIG. 3 is a schematic diagram of another memory device in an embodiment of the invention;

fig. 4 is a flowchart of a control method of the memory device of fig. 3.

Reference numerals illustrate:

1. 3: memory device 10: controller chips 101, 102: controller for controlling a power supply

121: a first set of I/O circuits 122: a second set of I/O circuits 141, 142: calibration circuit

16: arbitration circuit 18: ground Rzq: resistor

NZq: connection end 30: memory chips 301, 302: memory die

200. 400: control methods S202 to S206, S402 to S406: step (a)

Detailed Description

Fig. 1 is a schematic diagram of a memory device 1 in an embodiment of the invention. The memory device 1 includes resistors Rzq and a controller chip 10 coupled to each other. Resistor Rzq is a precision resistor of 240 ohms and is located external to controller chip 10. The controller chip 10 may include multiple controllers, encased by a single package. The I/O circuits of these controllers may share resistor Rzq for calibration of their output drivers and termination resistors. Since these controllers may share resistor Rzq, the number of resistors Rzq in memory device 1 may be reduced, thereby reducing circuit area and reducing manufacturing costs.

Resistor Rzq is coupled between connection Nzq and ground 18. The controller chip 10 may include a first controller 101, a second controller 102, a first set of I/O circuits 121, a second set of I/O circuits 122, a first calibration circuit 141, a second calibration circuit 142, and an arbitration circuit 16. The arbitration circuit 16 may be coupled to the first controller 101, the second controller 102, the first calibration circuit 141 and the second calibration circuit 142. The first set of I/O circuits 121 may be coupled to the first controller 101 and the first calibration circuit 141. The second set of I/O circuits 122 may be coupled to the second controller 102 and the second calibration circuit 142. The first calibration circuit 141 and the second calibration circuit 142 are further coupled to the resistor Rzq via a connection terminal Nzq.

The first set of I/O circuits 121 may include I/O circuits for a set of clock signals, data strobe signals, control signals, and address signals of the first controller 101, and the second set of I/O circuits 122 may include I/O circuits for a set of clock signals, data strobe signals, control signals, and address signals of the second controller 102, each of which may include an output driver and a termination resistor. The first set of I/O circuits 121 and the second set of I/O circuits 122 may be disposed at different locations of the controller chip 10, respectively, e.g., the first set of I/O circuits 121 may be disposed at a north portion of the controller chip 10 and the second set of I/O circuits 122 may be disposed at a south portion of the controller chip 10.

The first calibration circuit 141 may perform a first controller calibration of the first set of I/O circuits 121 using the resistor Rzq to generate a calibration driving force for the output driver and a calibration resistance value for the termination resistor for each of the I/O circuits 121 of the first set. The second calibration circuit 142 may perform a second controller calibration of the second set of I/O circuits 122 using the resistor Rzq to generate a calibration driving force for the output driver and a calibration resistance value for the termination resistor for each of the I/O circuits 122 of the second set. The first calibration circuit 141 and the second calibration circuit 142 may share a resistor Rzq to control calibration of output drivers and termination resistors of the first set of I/O circuits 121 and the second set of I/O circuits 122.

When the first controller calibration is required, the first controller 101 may transmit a first controller calibration request (request) to the arbitration circuit 16. When the second controller calibration is required, the second controller 102 may transmit a second controller calibration request to the arbitration circuit 16. The arbitration circuit 16 may transmit a first controller calibration acknowledgement (ack) to the first calibration circuit 141 in response to the first controller calibration request, thereby instructing the first calibration circuit 141 to perform the first controller calibration, and transmit a second controller calibration acknowledgement to the second calibration circuit 142 in response to the second controller calibration request, thereby instructing the second calibration circuit 142 to perform the second controller calibration. The first period in which the first calibration circuit 141 performs the first controller calibration and the second period in which the second calibration circuit 142 performs the second controller calibration do not overlap.

The arbitration circuit 16 may receive the first controller calibration request and the second controller calibration request, and perform the first controller calibration and the second controller calibration in a time-sharing calibration manner. In some embodiments, the arbitration circuit 16 may receive the second controller calibration request during the first period of time and, after the end of the first period of time, instruct the second calibration circuit 142 to perform the second controller calibration in response to the second controller calibration request. Similarly, the arbitration circuit 16 may receive the first controller calibration request during the second period, and after the second period is completed, instruct the first calibration circuit 141 to perform the first controller calibration in response to the first controller calibration request. In other embodiments, the arbitration circuit 16 may receive the second controller calibration request after the end of the first period of time and instruct the second calibration circuit 142 to perform the second controller calibration in response to the second controller calibration request. Similarly, the arbitration circuit 16 may receive the first controller calibration request after the end of the second period of time, and instruct the first calibration circuit 141 to perform the first controller calibration in response to the first controller calibration request. In other embodiments, the arbitration circuit 16 may receive the first controller calibration request and the second controller calibration request simultaneously, instruct one of the first calibration circuit 141 and the second calibration circuit 142 to perform calibration according to the priority order of the first controller 101 and the second controller 102, and instruct the other of the first calibration circuit 141 and the second calibration circuit 142 to perform calibration after the indicated one finishes calibration. For example, the first controller 101 may have a higher priority than the second controller 102, and when the first controller calibration request and the second controller calibration request are received at the same time, the arbitration circuit 16 may instruct the first calibration circuit 141 to perform the first controller calibration in response to the first controller calibration request, and after the first period of time is over, instruct the second calibration circuit 142 to perform the second controller calibration in response to the second controller calibration request,

the arbitration circuit 16 can determine whether the first period and the second period are over. In some embodiments, the length of the first period and the length of the second period may be equal to the predetermined length of time, the arbitration circuit 16 may determine that the first period ends after transmitting the first controller calibration acknowledgement to the first calibration circuit 141 and the predetermined length of time has elapsed, and may determine that the second period ends after transmitting the second controller calibration acknowledgement to the second calibration circuit 142 and the predetermined length of time has elapsed. In other embodiments, the first calibration circuit 141 may feedback the required time for the first controller calibration to the arbitration circuit 16 after receiving the first controller calibration acknowledgement (i.e. the indication of performing the first controller calibration), and the arbitration circuit 16 may determine that the first period of time is over after transmitting the first controller calibration acknowledgement to the first calibration circuit 141 and passing the required time for the first controller calibration. Similarly, the second calibration circuit 142 may feedback the time required for the second controller calibration to the arbitration circuit 16 after receiving the second controller calibration acknowledgement (i.e., an indication of performing the second controller calibration), and the arbitration circuit 16 may determine that the second period of time is over after transmitting the second controller calibration acknowledgement to the second calibration circuit 142 and passing the time required for the second controller calibration.

Fig. 2 is a flow chart of a control method 200 of the memory device 1. The control method 200 includes steps S202 to S206, where a plurality of calibrations are performed in a time-sharing calibration manner. Any reasonable step change, order, or adjustment is within the scope of the present invention. Steps S202 to S206 are explained as follows:

step S202: the first controller 101 transmits a first controller calibration request;

step S204: the second controller 102 transmits a second controller calibration request;

step S206: the arbitration circuit 16 instructs the first calibration circuit 141 to perform the first controller calibration in response to the first controller calibration request, and instructs the second calibration circuit 142 to perform the second controller calibration in response to the second controller calibration request, the first period in which the first calibration circuit 141 performs the first controller calibration and the second period in which the second calibration circuit 142 performs the second controller calibration do not overlap.

The explanation of steps S202 to S206 can be found in the previous paragraphs, and will not be repeated here.

Fig. 3 is a schematic diagram of another memory device 3 in an embodiment of the invention. The difference between the memory device 3 and the memory device 1 is that the memory device 3 further comprises a memory chip 30. The following explanation is made with respect to the memory chip 30, and the explanation about the calibration of the controller chip 10 can be found in the previous paragraph, and will not be repeated here.

The memory chip 30 may be coupled to the first set of I/O circuits 121, the second set of I/O circuits 122, and the connection terminal Nzq. The memory chip 30 may include a first memory die 301 and a second memory die 302, and the I/O circuitry of the first memory die 301 and the second memory die 302 may share a resistor Rzq for calibration of their output driver and termination resistances. Since the resistor Rzq can be shared, the number of resistors Rzq in the memory device 3 can be reduced, thereby reducing circuit area and reducing manufacturing costs. The first memory die 301 may include a third generation double data rate random access memory (DDR 3 RAM). The second memory die 302 may include a fourth generation double data rate random access memory (DDR 4 RAM). The first memory die 301 and the second memory die 302 may be the same or different types of memory.

The first memory die 301 may be coupled to the connection Nzq and the first set of I/O circuits 121, and a first memory calibration of the first memory die 301 may be performed using the resistor Rzq, the second memory die 302 may be coupled to the connection Nzq and the second set of I/O circuits 122, and a second memory calibration of the second memory die 302 may be performed using the resistor Rzq.

When the first memory calibration is needed, the first memory die 301 may sequentially transmit the first memory calibration request to the arbitration circuit 16 via the first set of I/O circuits 121 and the first controller 101. When a second memory calibration is required, the second memory die 302 may sequentially transmit a second memory calibration request to the arbitration circuit 16 via the second set of I/O circuits 122 and the second controller 102.

The arbitration circuit 16 may receive two or more of the first controller calibration request, the second controller calibration request, the first memory calibration request, the second memory calibration request, and perform 2 calibrations according to the time-sharing calibration method in the previous paragraph. For example, the arbitration circuit 16 may instruct the first calibration circuit 141 to perform a first controller calibration during a first period of time in response to a first controller calibration request, instruct the second calibration circuit 142 to perform a second controller calibration during a second period of time in response to a second controller calibration request, instruct the first memory die 301 to perform the first memory calibration during a third period of time via the first controller 101 and the first set of I/O circuits 121 in response to the first memory calibration request, and/or instruct the second memory die 302 to perform the second memory calibration during a fourth period of time via the second controller 102 and the second set of I/O circuits 122 in response to the second memory calibration request, with the first to fourth periods of time not overlapping.

Fig. 4 is a flow chart of a control method 400 of the memory device 3. The control method 400 includes steps S402 to S406, where a plurality of calibrations are performed in a time-sharing calibration manner. Any reasonable step change, order, or adjustment is within the scope of the present invention. Steps S402 to S406 are explained as follows:

step S402: the first controller 101 transmits a first controller calibration request and/or a first memory calibration request;

step S404: the second controller 102 transmits a second controller calibration request and/or a second memory calibration request;

step S406: the arbitration circuit 16 instructs the first calibration circuit 141, the second calibration circuit 142, the first memory die 301, and/or the second memory die 302 to perform time-sharing calibration in response to the first controller calibration request, the second controller calibration request, the first memory calibration request, and/or the second memory calibration request.

The explanation of steps S402 to S406 can be found in the previous paragraphs, and will not be repeated here.

While the embodiments of fig. 1-4 employ a configuration in which 2 controllers and/or 2 memory dies share a single resistor Rzq to achieve calibration of the output driver and termination resistor, one of ordinary skill in the art may employ other numbers of controllers and/or other numbers of memory dies sharing a single resistor Rzq to accomplish calibration of each controller and/or each memory die in accordance with the spirit of the present invention.

The embodiments of fig. 1-4 employ multiple controllers and/or multiple memory die common resistors Rzq for calibration of output drivers and termination resistors, so that the number of resistors Rzq in the memory device 1 can be reduced, thereby reducing circuit area and manufacturing costs.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (10)

1. A memory device, comprising:

a resistor coupled between a connection terminal and a ground terminal; and

a controller chip, comprising:

a first controller for transmitting a first controller calibration request;

a second controller for transmitting a second controller calibration request;

a first set of input/output circuits coupled to the first controller;

a second set of input/output circuits coupled to the second controller;

the first calibration circuit is coupled to the connecting end and the first group of input/output circuits and is used for calibrating a first controller of the first group of input/output circuits by using the resistor;

the second calibration circuit is coupled to the connecting end and the second group of input/output circuits and is used for calibrating a second controller of the second group of input/output circuits by using the resistor; and

the arbitration circuit is coupled to the first controller, the second controller, the first calibration circuit and the second calibration circuit, and is configured to instruct the first calibration circuit to calibrate the first controller in response to the first controller calibration request, and instruct the second calibration circuit to calibrate the second controller in response to the second controller calibration request, wherein a first period of time during which the first calibration circuit calibrates the first controller and a second period of time during which the second calibration circuit calibrates the second controller do not overlap.

2. The memory device of claim 1, wherein the arbitration circuit receives the second controller calibration request during the first period of time and, after the first period of time has ended, instructs the second calibration circuit to perform the second controller calibration in response to the second controller calibration request.

3. The memory device of claim 1, wherein a length of the first period and a length of the second period are equal to a predetermined length of time.

4. The memory device of claim 1, wherein the first calibration circuit is further configured to feedback a desired time for the first controller calibration to the arbitration circuit after receiving an indication of the first controller calibration.

5. The memory device of claim 1, further comprising:

a memory chip coupled to the first set of input/output circuits, the second set of input/output circuits and the connection terminal, comprising:

a first memory die coupled to the connection terminal and the first set of input/output circuits for performing a first memory calibration of the first memory die using the resistor; and

a second memory die coupled to the connection terminal and the second set of input/output circuits for performing a second memory calibration of the second memory die using the resistor;

wherein the first controller is further configured to transmit a first memory calibration request; and

the arbitration circuit is used for responding to the first memory calibration request and indicating the first memory die to conduct the first memory calibration in a third period through the first controller, wherein the first period, the second period and the third period are not overlapped.

6. A control method of a memory device, the memory device including a resistor and a controller chip, the resistor being coupled between a connection terminal and a ground terminal, the controller chip including a first controller, a second controller, a first set of input-output circuits, a second set of input-output circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit, the first set of input-output circuits being coupled to the first controller, the second set of input-output circuits being coupled to the second controller, the first calibration circuit being coupled to the connection terminal and the first set of input-output circuits, the second calibration circuit being coupled to the connection terminal and the second set of input-output circuits, the arbitration circuit being coupled to the first controller, the second controller, the first calibration circuit, and the second calibration circuit, the control method comprising:

the first controller transmits a first controller calibration request;

the second controller transmits a second controller calibration request; and

the arbitration circuit instructs the first calibration circuit to perform the first controller calibration in response to the first controller calibration request, and instructs the second calibration circuit to perform the second controller calibration in response to the second controller calibration request,

wherein a first period of time during which the first calibration circuit performs the first controller calibration and a second period of time during which the second calibration circuit performs the second controller calibration do not overlap.

7. The control method according to claim 6, characterized by further comprising:

the arbitration circuit receives the second controller calibration request during the first period;

wherein in response to the second controller calibration request, the second calibration circuit is instructed to perform the second controller calibration after the first period of time has ended.

8. The control method of claim 6, wherein a length of the first period and a length of the second period are equal to a predetermined time length.

9. The control method according to claim 6, characterized by further comprising: after receiving an instruction for calibrating the first controller, the first calibration circuit feeds back a required time for calibrating the first controller to the arbitration circuit.

10. The control method according to claim 6, characterized in that:

the memory device further includes a memory chip coupled to the first set of input/output circuits, the second set of input/output circuits, and the connection terminal, and includes a first memory die and a second memory die, the first memory die is coupled to the connection terminal and the first set of input/output circuits, and the second memory die is coupled to the connection terminal and the second set of input/output circuits: and

The control method further includes:

the first controller is further configured to transmit a first memory calibration request; and

the arbitration circuit is used for responding to the first memory calibration request and indicating the first memory die to conduct the first memory calibration in a third period through the first controller, wherein the first period, the second period and the third period are not overlapped.