CN117688896A - Parallel layer distributor for time delay perception under very large scale integrated circuit - Google Patents
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Abstract
The invention provides a parallel layer distributor for time delay perception under a very large scale integrated circuit. In the physical design flow of very large scale integrated circuits, layer distribution is a key link to achieve a high quality 3D overall wiring scheme. A non-default rule-line technique under the advanced process is introduced for optimizing the delay of the net. On the other hand, as the scale of integrated circuits increases, the number of nets that need to be processed increases significantly, and the layer allocation algorithm run time increases to become an important constraint to limit efficient design routing schemes. The invention provides three strategies for reducing the time delay of a layer allocation scheme and improving the efficiency of a layer allocation algorithm: (1) The delay perception stitch removal and redistribution strategy is designed, so that the delay of a wire net can be optimized while overflow is eliminated; (2) Classifying the wire nets based on time delay of the wire nets, and designing different refining strategies for different types of wire nets; (3) According to the dynamic change of wiring space used by the wire network in the parallel layer distribution process, a parallel strategy based on a dynamic conflict graph is provided so as to improve the efficiency of solving a wiring scheme by the layer distributor.
Description
Technical Field
The invention relates to the technical field of computer aided design of a very large scale integrated circuit, in particular to a time delay sensing parallel layer distributor under the very large scale integrated circuit.
Background
With the development of the semiconductor industry, very large scale integrated circuits (Very Large Scale Integration, VLSI) have become an important support for the development of the internet and information technology. In the very large scale integrated circuit physical design flow, the routing stage works to complete the circuit interconnections between pins. On the other hand, higher integration and smaller feature sizes have become the main development direction of very large scale integrated circuits, so that interconnection delay has become a decisive factor affecting the delay of sequential circuits.
Advanced process technology with great potential for delay optimization has become a research hotspot for layer allocation problems. However, the application of advanced process technology requires the introduction of new design rules, which presents new challenges for the design of high performance VLSI circuits. In addition, as the scale of integrated circuits increases, the number of nets that need to be processed increases significantly, and the run time of layer allocation algorithms increases as an important factor limiting the design of efficient wiring schemes.
Disclosure of Invention
In view of the above, the present invention aims to provide a parallel layer distributor for delay sensing under a very large scale integrated circuit, which improves the efficiency of the layer distributor in solving a wiring scheme.
In order to achieve the above purpose, the invention adopts the following technical scheme: a parallel layer distributor for time delay perception under very large scale integrated circuit comprises
(1) Using a multi-stage layer allocation design, including a layer allocation stage with time delay dominant, a layer allocation legalization stage based on negotiation, and a refinement stage;
(2) Providing a delay-aware disconnecting and re-distributing strategy and a key wire network-priority refining strategy;
(3) And a parallel strategy based on the dynamic conflict graph is used for improving the efficiency of solving the wiring scheme by the layer distributor.
In a preferred embodiment, the wiring space is divided in the global wiring and a corresponding mesh map is constructed to construct a mathematical model describing the global wiring; the layer allocation algorithm prevents the routing area from being overly congested by following the following constraints:
TWO(S k ) TWO (S) formula (1)
Where S represents a given 2D overall routing result, k represents the number of layers of routing space, S k The layer allocation result of S is represented; TWO and MWO represent total wire overflow and maximum wire overflow, respectively;
using the two formulas in the through hole perception layer allocation stage and the through hole refining stage based on negotiation, the formula (1) requires that the total wire overflow of the wire mesh 3D wiring scheme is equal to the total wire overflow of the 2D wiring scheme; equation (2) requires that any layer of net 3D routing scheme have a maximum wire overflow equal to the 2D routing scheme maximum wire overflow.
In a preferred embodiment, the delay(s) for a segment s of the net is calculated according to the Elmore model as follows:
wherein R(s) and C(s) respectively represent the resistance and capacitance of the wire network segment s, C down (s) represents the downstream capacitance of net segment s. The delay value of the path is equal to the accumulated sum of the delays of the network segments on the path:
delay(si)＝∑ s∈path(si) delay(s) formula (4)
Where path (si) is the path of the receiver si to the source point; the total delay size of the net is equal to the weighted sum of the path delays of the receivers:
delay(N)＝∑ si∈S(n) α si formula (5) of Xdelay (si)
Wherein alpha is si Is the weight value of the receiver si, indicating the delay factor of the path to the net where it is. In the prior related work [29-31] Assuming that the delay specific gravity of each path is the same, therefore, alpha is calculated si Set to the inverse of the number of network sinks.
In a preferred embodiment, after finishing the input of the 2D wiring scheme and the initialization of wiring resources, an initial layer allocation scheme is constructed by taking time delay as a dominant, and the guidance of net time delay estimation and wiring space congestion condition is provided for the subsequent legal stage and refining stage based on negotiation; the problem of edge overflow is solved through disconnecting and re-distributing in the layer allocation legalization stage based on negotiation, and a legal layer allocation scheme is constructed; each round of stitch removal and re-distribution firstly updates wiring resources in a wiring space; then detecting illegal nets, and detecting all illegal nets in the current layer distribution scheme; screening the illegal wire nets needing to be stripped and re-distributed, and finally, stripping and re-wiring the screened wire nets; if illegal networks still exist in the layer allocation scheme after disconnecting and re-distributing, performing a new round of iteration; if no illegal net exists, entering a refining stage;
in the refining stage, firstly, protective measures are taken for key wire nets in legal layer distribution schemes, so that the used wiring resources are not preempted by other wire nets, and then, the wiring schemes of the wire nets are adjusted one by one to find a better wiring scheme so as to refine the overall layer distribution scheme.
In a preferred embodiment, the wire net needing to be disconnected and re-wired is selected through analyzing the local time sequence criticality of the wire net section in each wiring space; selectively removing a part of wire nets in the process of removing and re-distributing the wire nets, and reserving the wiring result of the part of wire nets can further optimize the time delay of the key wire nets; the timing criticality of a wire net segment in a net at its current wire location is evaluated by the following equation:
wherein od (e, n) is the sequence number of the net n which is descending and ordered according to the time delay value in all the nets using the edge e; dem (e) is the number of nets the current edge e passes by; the smaller the value of APR (e, n) is, the higher the delay criticality of net n at edge e is.
In a preferred embodiment, the wire mesh refining stage firstly performs greedy but non-overflow wire mesh based wire mesh re-distribution on the wire mesh with the highest time delay, if the generated new layer allocation scheme is superior to the original layer allocation scheme, the latest layer allocation scheme is adopted, otherwise, the original layer allocation scheme is reserved; for a through hole key wire network, judging whether the new layer allocation scheme is better than the old layer allocation scheme by judging whether the number of through holes is reduced; and whether the new layer allocation scheme is better than the old layer allocation scheme is judged by whether the time delay of other types of networks is reduced.
In a preferred embodiment, the conflict area of the current wire net is recorded by dynamically constructing a conflict graph in the parallel wire net routing process and is used as an important basis for selecting a net that can be currently routed in parallel without conflict.
Compared with the prior art, the invention has the following beneficial effects:
(1) The delay perception stitch removal and redistribution strategy is designed, so that the delay of a wire net can be optimized while overflow is eliminated; (2) Classifying the wire nets based on time delay of the wire nets, and designing different refining strategies for different types of wire nets; (3) According to the dynamic change of wiring space used by the wire network in the parallel layer distribution process, a parallel strategy based on a dynamic conflict graph is provided so as to improve the efficiency of solving a wiring scheme by the layer distributor.
Drawings
FIG. 1 is a layer allocation problem model of a preferred embodiment of the present invention, wherein (a) wiring space; (b) a 3D mesh map model; (c) a 2D global routing scheme; (D) 3D global routing scheme.
FIG. 2 is a schematic diagram of a wire gauge according to a preferred embodiment of the present invention, wherein (a) the track profile; (b) default rule lines; (c) a wide line; (d) parallel lines.
FIG. 3 is a graph showing the relationship between the density of the conductive wires and the coupling effect according to the preferred embodiment of the present invention.
Fig. 4 is an algorithm flow of a preferred embodiment of the present invention.
Fig. 5 is a high-level congestion diagram of a preferred embodiment of the present invention.
FIG. 6 is a dynamic conflict graph in accordance with a preferred embodiment of the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings and examples.
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application; as used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
The time delay aware parallel layer distributor under the very large scale integrated circuit specifically comprises a problem model, congestion constraint, non-default rule line technology, a time delay model, coupling effect, algorithm overview, time delay aware disconnection and redistribution strategy, a key wire network priority refining strategy and a dynamic conflict graph based parallel strategy, referring to fig. 1-6.
The following is specifically set forth:
1. problem model
The wiring space is typically divided in the global wiring and a corresponding mesh map is constructed to construct a mathematical model describing the global wiring. Fig. 1 (a) shows a multi-layered wiring space divided into 3 x 3, the divided rectangular block is G-cell, A plurality of tracks are arranged on the boundary of two adjacent G-cells on the same metal layer and can accommodate wires, and the wires are used for connecting the adjacent G-cells on the same layer. And G-cells at different layers require via connections. To facilitate the study of layer allocation problems, a mesh map model corresponding thereto can be constructed according to fig. 1 (a), as shown in fig. 1 (b). In fig. 1 (b), each node represents one G-cell in fig. 1 (a), and the grid edges between nodes represent the boundaries between G-cells, the capacity of the edges being assessed by the number of tracks on the boundary. Five tracks can be placed on the boundary between and in fig. 1 (a), the capacity of the connected edge in fig. 1 (b) is 5. The number of tracks is related to the position and area of the obstacle in the actual wiring space, and thus the capacities of the sides at different positions of the different layers may be different. In addition, each metal layer can only allow one routing direction, and the routing directions of the wires of the adjacent metal layers need to be orthogonal.
The multi-layered wiring space is compressed into a single-layered structure, and a 2D mesh pattern model as shown in fig. 1-1 (c) can be obtained. V in FIG. 1-1 (b) 1,1 、v 1,2 And v 1,3 Is compressed into v in fig. 1-1 (c) 1 . Similarly, edge e 1,3 And e 1,1 Is compressed into edge e 1 . The capacity of an edge in the 2D mesh map is the sum of the capacities of the corresponding 3D mesh edges. The layer allocation works to allocate each net segment in the 2D wiring scheme into the multi-layer structure to get the 3D wiring scheme. The net of fig. 1-1 (c) is a 2D global routing scheme, and after layer distribution, the 3D global routing scheme shown in fig. 1-1 (D) can be obtained.
2. Congestion constraints
To ensure routability, layer allocation should avoid overflow by placing a number of wires exceeding its routing capacity on each routing edge. Thus, the layer allocation algorithm of the present invention prevents excessive congestion of the routing area by following the following constraints:
TWO(S k ) TWO (S) formula (1)
Where S represents a given 2D overall routing result, k represents the number of layers of routing space, S k The layer allocation result of S is indicated. TWO and MWO represent total wire overflow and maximum wire overflow, respectively. The two formulas described above are used in the negotiation-based via aware layer allocation phase and the via refinement phase. Equation (1) requires that the total wire overflow of the net 3D routing scheme be equal to the total wire overflow of the 2D routing scheme. On the other hand, since the wires placed on the adjacent layers need to be orthogonal, k/2 layers of wires placed in the horizontal direction are placed in the layer wiring space, and the other k/2 layers of wires placed in the vertical direction are placed. Thus, equation (2) requires that any layer of net 3D routing scheme have a maximum wire overflow equal to the 2D routing scheme maximum wire overflow. The first constraint ensures that wire overflow in the 3D routing area does not exceed wire overflow in the 2D routing area. The second constraint ensures that the maximum wire overflow of an edge in the 2D routing region can be evenly distributed to its corresponding edge in the 3D routing region.
3. Non-default rule line technique
The present invention introduces a non-default rule line technique under the basis of a binary process for conventional wiring based on a double pattern lithography technique. No wires of any width can be manufactured under the sub-16 nanometer process due to the limitation of the manufacturing process, only wires of certain specific widths are compatible with the manufacturing process. For ease of discussion, the present invention refers to a general specification of wires as default rule lines, while other specifications of wires are referred to as non-default rule lines. In the case where a non-default rule line is not applicable, each track can accommodate a segment of the default rule line. Fig. 2 (a) is a graph showing a track profile between two adjacent G-cells. Fig. 2 (b) is a default rule line that occupies one track width. Wider wires have lower resistance and are less affected by coupling effects, and have better performance in terms of time delay. However, due to the limitation of the manufacturing process, the ideal wide line cannot be placed at the lower layer, so that only parallel lines can be used instead of the wide line. The non-default regular lines include wide lines and parallel lines, and wide lines are used as the non-default regular lines in layers 5-8 and parallel lines are used as the non-default regular lines in layers 1-4 to achieve approximately wide line electrical performance due to manufacturing process limitations. As shown in FIGS. 2 (c) and (d)2 (d) shows the use of wide and parallel lines, respectively, for the track. In FIG. 2 (c), since the distance between the wires needs to be larger than the minimum wire pitch, when the wide wire is placed on the track t 3 On track t 2 And t 4 The placement of the wire is not allowed or else the constraint of minimum wire spacing would be violated, so using a wide wire would require 3 tracks to be occupied. Whereas in fig. 2 (d) two parallel default regular lines are used instead of a wide line, the use of parallel lines requires 2 tracks to be occupied.
4. Time delay model
The excellent fidelity by which the Elmore delay model evaluates the delay has become the mainstream delay model of the delay-driven layer allocation work. A wire network is composed of a receiver and a plurality of transmitters, the transmitters are represented as driving resistances in terms of electrical characteristics, and the receiver is represented as a load capacitance. The set of net segments connecting a transmitter to a receiver is defined as a path. The delay(s) for a segment s in the net is calculated according to the Elmore model as follows:
wherein R(s) and C(s) respectively represent the resistance and capacitance of the wire network segment s, C down (s) represents the downstream capacitance of net segment s. The delay value of the path is equal to the accumulated sum of the delays of the network segments on the path:
delay(si)＝∑ s∈path(si) delay(s) formula (4)
Where path (si) is the path of the receiver si to the source point; the total delay size of the net is equal to the weighted sum of the path delays of the receivers:
delay(N)＝∑ si∈S(n) α si formula (5) of Xdelay (si)
Wherein alpha is si Is the weight value of the receiver si, indicating the delay factor of the path to the net where it is. In the prior related work [29-31] Assuming that the delay specific gravity of each path is the same, therefore, alpha is calculated si Set to the inverse of the number of network sinks.
5. Coupling effect
Coupling effects are critical factors in very large scale integrated circuits that affect the timing performance of the circuit. The coupling effect refers to a change in its own electrical characteristics between wires due to electromagnetic interaction. Since the calculation of the time delay has a close relation with the capacitance and resistance of the wire, the influence of the change of the capacitance and resistance of the wire caused by the coupling effect on the time sequence performance of the circuit is generally considered in the time sequence circuit, and the stronger the coupling effect is, the worse the time sequence performance of the wire is.
The distance between the wires is in direct proportion to the strength of the coupling effect, the smaller the distance is, the stronger the coupling effect is, and the larger the distance is, the weaker the coupling effect is. Although specific position information of the wires cannot be accurately obtained in the overall wiring stage, the number of wires passing by the wiring unit boundary can be calculated. Therefore, the invention adopts the same coupling effect evaluation mode based on the wire density as the literature. The wire density of fig. 3 (a) is greater than that of fig. 3 (b), so that the coupling effect between wires of fig. 3 (a) is stronger.
6. Summary of the algorithm
Fig. 4 shows the overall flow of the algorithm, which is divided into three phases: delay-dominated layer allocation, negotiation-based layer allocation validation and refinement.
The purpose of the delay-dominant layer allocation phase is to construct an initial layer allocation scheme. After finishing the input of the 2D wiring scheme and the initialization of wiring resources, the algorithm of the stage constructs an initial layer allocation scheme by taking the time delay as a dominant, and provides guidance of net time delay estimation and wiring space congestion conditions for the subsequent legal stage and refining stage based on negotiation. Because the congestion cost of the first order is smaller than the delay cost, in order to obtain more excellent delay performance in the process of generating a layer distribution scheme, many wires are selected to place wires on the edge with better time sequence performance, so that edge overflow is caused. Thus, while the initial layer allocation scheme can construct a layer allocation scheme with lower latency, there can be a network of violations that use overflow edges.
The legal layer allocation stage based on negotiation solves the problem of edge overflow through disconnecting and re-distributing, and constructs a legal layer allocation scheme. Each round of stitch removal and re-routing firstly updates the wiring resources in the wiring space. And then detecting the illegal nets, and detecting all the illegal nets in the current layer distribution scheme. Then screening the illegal nets needing to be stripped and re-distributed, and finally, stripping and re-distributing the screened nets. And if the illegal network still exists in the layer allocation scheme after disconnecting and re-distributing, performing a new round of iteration. And if no illegal wire network exists, entering a refining stage.
In the refining stage, firstly, protective measures are taken for key wire nets in legal layer distribution schemes, so that the used wiring resources are not preempted by other wire nets, and then, the wiring schemes of the wire nets are adjusted one by one to find a better wiring scheme so as to refine the overall layer distribution scheme.
7. Delay-aware stitch removal and redistribution strategy
The layer allocation legalization stage based on negotiation has the main effect of eliminating the edge overflow phenomenon in the wiring space by continuously iterating and updating the related wiring cost by using the negotiation-based method. In each iteration process, firstly detecting the illegal wire net, and then removing and re-distributing the illegal wire net. The invention strictly selects the wire net needing to be disconnected and re-wired by analyzing the local time sequence criticality of the wire net section in each wiring space.
The layer allocation legalization stage based on negotiation gradually increases the overflow cost in the objective function in the iteration process in order to solve the wire overflow. Therefore, in the initial stage of iteration, the delay occupies a larger proportion in the objective function because the overflow cost of the net is smaller. At this point, the net's objective function is typically dominated by delay, and the net chooses to place wires on the more congested sides in order to achieve less delay.
As shown in FIG. 5, assume that edge e is now 1,9 The wire capacity at this point is 2, and as shown there are 3 nets using edge e 1,9 Wiring resource of (c), edge e 1,9 Overflowing. Wherein the time delay of the wire network is respectively n from high to low 1 、n 2 、n 3 . In the prior layer distribution work, the wire net using overflow edge is required to be fully usedPartially disassembled and re-wired, i.e. net n 1 、n 2 、n 3 All that is required is to disassemble and rewire. However, virtually all of the offending net needs to be rerouted, although the edge e that is reduced during the next iteration can be effectively used 1,9 Congestion conditions, but may limit the effect of delay optimization that some networks ultimately achieve. Therefore, the invention further considers that the wire network needing to be disconnected and re-distributed is screened in the illegal wire network. Since the wire solutions selected by the nets in the early stages of the iteration are more time-lapse-oriented, the removal of all offending nets may result in some nets that would otherwise preferentially use the higher-level wiring resources leaving the higher-level layer due to congestion during subsequent iterations. And selectively removing a part of the wire nets in the process of removing and re-distributing the wire nets, and reserving the wiring result of the part of the wire nets can further optimize the time delay of the key wire nets.
To eliminate e 1,9 Is overflowed by at least 1 pass e 1,9 A wire mesh at the position. If the wire net n is selected to be removed 1 Retaining net n 2 、n 3 Then e in the next iteration 1,9 No excess capacity can be used to place the wires, net n 1 Will select e 1,7 Or the lower level side. However, compared with net n 2 And n 3 Net n 1 The higher the delay, the more preferentially the higher layer of wiring space should be used. On the other hand, the wire specifications of the higher layer perform better than those of the lower layer, so the wire net with lower delay should be removed preferentially at the higher layer to make the wiring space available for the timing critical wire net later, such as removing the wire net with priority n in FIG. 5 3 、n 2 、n 1 . On the contrary, on the lower layer, the time sequence performance of the lower layer wires is not better than that of the higher layer, so that the time sequence key wire net is not suitable for placing wires on the lower layer, and the wire net with lower time delay should be removed preferentially on the lower layer. The invention evaluates the timing criticality of a wire net segment in a net at its current wiring position by the following formula:
where od (e, n) is the sequence number of net n ordered by decreasing value of delay in all nets using edge e. dem (e) is the number of nets the current edge e passes over. The smaller the value of APR (e, n) is, the higher the delay criticality of net n at edge e is. Taking fig. 3-6 as an example, APR (e 1,9 ,n 1 )、APR(e 1,9 ,n 2 ) And APR (e) 1,9 ,n 3 ) The values of (2) are 1/3, 2/3 and 1, respectively.
In very large scale integrated circuits, there are millions of nets, the topology and scale of each net varies greatly, and a large number of nets are interwoven together in the routing space, with a complex structure. One net has a higher disconnect priority on one edge and a lower disconnect priority on the other edge it passes through. Therefore, the timing criticality of the net on each side needs to be comprehensively considered. APR can be obtained by further calculating APR of each net section of net and averaging ave (n) to evaluate the overall delay criticality of net n in the wiring space currently in use. APR (APR) ave (n) time-delay critical conditions of the net as a whole in the wiring space in which it is located. APR (APR) ave The smaller the value of (n) is, the more critical the delay of the net in the wiring space it passes through is. Conversely, APR ave The larger the value of (n) the lower the delay criticality of the net in the wiring space through which it passes. Net n 1 、n 2 And n 3 APR of (C) ave The values of (n) are 2/3, 5/6 and 1, respectively. APR should be removed preferentially at higher layers ave (n) larger value net.
The invention will complain of APR ave The value (n) is used as an important basis for selecting the disconnecting and re-routing network in the layer allocation legal stage based on negotiation, and a disconnecting and re-routing strategy of delay perception is provided. Its algorithm pseudo code is shown in algorithm 1.
The first line traverses each 2D mesh edge e. The second line traverses each 3D grid edge e corresponding to each 2D grid edge k Where k represents the sequence number of the metal layer where the 3D mesh edge is located. Third row to fifth row pair 3D grid edge e k Each net n on the net calculates APR ave The value of the sum of the values,and add net n to the drop net candidate set S. Seventh to twelfth rows, ordered by APR at a higher level for nets in set S ave Is sorted in descending order of values, and is sorted in ascending order at a lower layer. The thirteenth row selects the net of the previous RT (i) in the set as the net that needs to be rerouted. At the high level, the net with lower timing criticality is removed preferentially, the non-timing criticality net gives up precious high-level wiring resources, while at the low level, the net with higher timing criticality is removed preferentially, so that the timing criticality net leaves the low level, and the high level is selected with higher possibility.
8. Refining strategy for critical net prioritization
After the layer allocation validation phase based on negotiation, each net has obtained a legal layer allocation scheme. The purpose of the refinement stage is to adjust the layer allocation scheme for the timing critical nets to further optimize the delay of the timing critical nets. Thus, the present invention proposes a refinement strategy based on critical net prioritization. Its algorithm pseudo code is shown in algorithm 2.
The screening and optimizing pseudocode of the maximum delay candidate net is shown in algorithm 3. The first row initializes the iteration number t to 0. The third row fetches the net n with the largest current delay and not optimized d . Fourth line records current net n d Is a time delay of (a). The fifth line function ripup&The function of the reroute is to wire network n d And (5) performing stitch removal and re-distribution. The sixth row compares the time delay value of the wire net n after the wire net is unraveled and re-distributed with the time delay value of the wire net without the wire net, and if the time delay value of the wire net n after the wire net is unraveled and re-distributed is not optimized, the wire net n is recovered by using the function rec in the seventh row d Layer allocation scheme before re-arrangement without stitch removal. Increasing the value of the coefficient t in the eighth line to the tenth line, if t reaches the threshold t max The iteration is aborted. t is t max Threshold value for user self-determination, t max The larger the value, the more net candidates are selected for maximum delay, however, in experiments the maximum delay occurs in only a very small number of nets, therefore t max Here, a minimum value is set, i.e. 0.01% of the total net count. Eleventh to thirteenth pairs of rows n d Optimizing the time delay of the new layer allocation scheme after disconnecting and re-distributing, and then arranging the wire netn d Added to the set S of maximum delay candidate nets d The iteration is restarted and the selection of the next largest delay candidate net is started.
The wiring resources of the maximum delay candidate net need to be protected after the screening and optimization of the maximum delay candidate net is completed, and the edges used by the maximum delay net are called critical wiring resources. The delay of net n is closely related to not only the wire gauge it uses, but also the wire density of the edge it uses due to the effect of coupling. Therefore, after the layer allocation scheme of the net n is obtained, if the edge used by the net n is changed in the edge wire density due to the adjustment of the wiring scheme of other nets, the time delay of the net n is also changed. The wiring scheme of the wire net candidate with the largest time delay is optimized, high-level wiring resources with smaller wire resistance are generally used, and the high-level wiring resources are also selected for wiring in the refining process of other wire nets in order to further optimize the time delay. In order to reduce the wire density in the wiring space through which the maximum delay candidate net passes, so as to reduce the influence of the coupling effect on the delay, the key wiring resources need to be protected. By increasing the cost of using critical routing resources for subsequent nets, critical routing resources can be effectively protected and their wire density reduced. The non-maximum delay candidate net refinement stage re-selects the layer allocation scheme taking into account the additional cost M (e). When e is a critical wiring resource, M (e) is set to a large value to avoid excessive use of these critical wiring resources by the net; otherwise, the value of M (e) is set to 0 so that it does not affect the net to find a better layer allocation scheme among the non-critical wiring resources.
In the refining stage, classifying the wire nets according to the time delay of the wire nets, and designing different refining strategies for the wire nets, as shown in table 1:
TABLE 1 wire mesh classification and refinement strategy
The nets can be classified into four categories according to the size of each delay: maximum delay candidate net, timing critical net, sub timing critical net, via critical net.
The maximum time delay candidate net is screened by the algorithm 2, and the layer allocation scheme is optimized in the screening process, and the maximum time delay candidate net obtains the current optimal layer allocation scheme. Because the net changes its layer allocation scheme in the refining process, it is necessary to wait for other nets to finish refining, and the refining of the candidate net with the maximum delay has the potential of further optimization after the available resources of the wiring space are changed.
When the time delay sequence of the wire nets is less than 5% of the number of the wire nets, the wire nets are timing key wire nets, the other wire nets have higher time delay, and the layer distribution scheme of the wire nets is allowed to be adjusted by using non-default regular wires in the refining process.
When the time delay sequence of the net is less than 20% of the number of the nets, the net is a secondary time sequence key net, and the net is not allowed to use a non-default rule line in the refining process in order to reduce the influence of the coupling effect on the whole time sequence of the net.
When the order is more than 20% of the number of nets, the net is a through hole key net, and compared with time delay, the through hole has larger optimizing potential.
And in the wire mesh refining stage, firstly, performing greedy but non-overflow wire mesh based wire mesh rearrangement, if the generated new layer allocation scheme is superior to the original layer allocation scheme, adopting the latest layer allocation scheme, otherwise, reserving the original layer allocation scheme. For the via critical net, it is determined whether the new layer allocation scheme is superior to the old layer allocation scheme by whether the number of vias is reduced. And whether the new layer allocation scheme is better than the old layer allocation scheme is judged by whether the time delay of other types of networks is reduced.
9. Parallel policy based on dynamic conflict graph
The 2D topology of the net does not change during layer allocation, and the task of layer allocation is to map the corresponding 2D wiring tree to the 3D wiring space. Therefore, if the 3D wiring space is compressed into the 2D wiring space, the search range of the corresponding 3D wiring space can be predicted according to the topology of the net in the 2D wiring space. Therefore, the invention provides a conflict sensing strategy for parallel wiring, which is characterized in that a conflict area of a current wiring net is recorded by dynamically constructing a conflict graph in the process of parallel wiring of the net and is used as an important basis for selecting the net capable of carrying out parallel wiring without conflict. Each net occupies its corresponding 2D routing space during parallel routing making it a conflict area and freeing the conflict area after routing is completed. The wire nets intersected with the conflict area cannot be routed in parallel due to the problem of resource conflict, and the parallel routing can be started only when the corresponding 2D routing does not exist in the conflict area.
FIG. 6 illustrates the construction and updating of dynamic conflict graphs in a parallel process. FIG. 6 (a) shows the distribution of nets in a 2D view, each small square representing a 2D G-cell, with nodes of different shapes representing nets in different parallel groupings, for a total of four thread groupings. Before the parallel routing begins, there is no conflict area in the conflict graph, and all nets may be selected by their responsible threads and begin parallel routing. Assume the current thread T 0 Select net n 10 . At this time, net n 10 The passing 2D G-cell is the conflict area (red in the figure), and the conflict diagram corresponding to the wiring space is shown in fig. 6 (b). Due to net n 9 The passing 2D G-cell has a collision zone. Thread T 1 The net n cannot be selected currently 9 And performing parallel wiring. At this time, thread T 1 、T 2 And T 3 An alternative non-conflicting wire mesh is shown in FIG. 6 (c). If T 1 Selecting n 2 Parallel wiring is carried out, and n is needed to be arranged in the same way 2 The passed 2D G-cell is updated to the conflict area, and n 4 Due to intersection with conflict area, on-line network n 2 Net that cannot be selected as parallel wiring before wiring is completed. At this time, thread T 2 And T 3 Optionally, aThe selected non-conflicting net is shown in FIG. 6 (d). Similarly, FIG. 6 (e) and FIG. 6 (f) illustrate thread T 2 Select net n 8 And a subsequent thread T 3 Select net n 5 Updating the post-conflict graph, and corresponding non-conflict net which can be wired in parallel. When the net completes routing, then the conflict area that was originally occupied needs to be updated to a non-conflict area. As shown in FIG. 6 (g), the local net n 10 When wiring is completed, the conflict area originally occupied by the wiring will update the non-conflict area, and at this time, net n 9 The non-conflict area is not intersected any more, and the non-conflict area can be selected by the affiliated thread to enter a parallel wiring stage as a non-conflict line network.
By the conflict graph shown in fig. 6, it can be determined whether a current net that has not yet been routed can start parallel routing. In the parallel wiring process, when the thread is idle, the current wire net which can be wired in parallel can be judged and processed according to the wire net wiring sequence under the serial condition.
Claims (7)
1. The parallel layer distributor for time delay perception under the very large scale integrated circuit is characterized by comprising
(1) Using a multi-stage layer allocation design, including a layer allocation stage with time delay dominant, a layer allocation legalization stage based on negotiation, and a refinement stage;
(2) Providing a delay-aware disconnecting and re-distributing strategy and a key wire network-priority refining strategy;
(3) And a parallel strategy based on the dynamic conflict graph is used for improving the efficiency of solving the wiring scheme by the layer distributor.
2. The parallel layer allocator of delay perception under very large scale integrated circuit according to claim 1, wherein the wiring space is divided in the global wiring and corresponding mesh patterns are constructed to construct mathematical models describing the global wiring; the layer allocation algorithm prevents the routing area from being overly congested by following the following constraints:
TWO(S k ) TWO (S) formula (1)
Where S represents a given 2D overall routing result, k represents the number of layers of routing space, S k The layer allocation result of S is represented; TWO and MWO represent total wire overflow and maximum wire overflow, respectively;
using the two formulas in the through hole perception layer allocation stage and the through hole refining stage based on negotiation, the formula (1) requires that the total wire overflow of the wire mesh 3D wiring scheme is equal to the total wire overflow of the 2D wiring scheme; equation (2) requires that any layer of net 3D routing scheme have a maximum wire overflow equal to the 2D routing scheme maximum wire overflow.
3. The parallel layer distributor for delay perception under very large scale integrated circuit according to claim 1, wherein the delay(s) for a certain wire segment s in the wire network is calculated according to the Elmore model as follows:
wherein R(s) and C(s) respectively represent the resistance and capacitance of the wire network segment s, C down (s) represents the downstream capacitance of net segment s; the delay value of the path is equal to the accumulated sum of the delays of the network segments on the path:
delay(si)＝Σ s∈path(si) delay(s) formula (4)
Where path (si) is the path of the receiver si to the source point; the total delay size of the net is equal to the weighted sum of the path delays of the receivers:
delay(N)＝Σ si∈S(n) α si ×delay(si)formula (5)
Wherein alpha is si Is the weight value of the receiver si, which represents the delay proportion of the path to the wire network; in the previous work of relevance [29-31]Assuming that the delay specific gravity of each path is the same, therefore, alpha is calculated si Set to the inverse of the number of network sinks.
4. The parallel layer distributor for delay perception under a very large scale integrated circuit according to claim 1, wherein after finishing the input of a 2D wiring scheme and the initialization of wiring resources, an initial layer distribution scheme is constructed by taking delay as a dominant, and guidance of wire network delay estimation and wiring space congestion conditions is provided for a subsequent legal stage and a refining stage based on negotiation; the problem of edge overflow is solved through disconnecting and re-distributing in the layer allocation legalization stage based on negotiation, and a legal layer allocation scheme is constructed; each round of stitch removal and re-distribution firstly updates wiring resources in a wiring space; then detecting illegal nets, and detecting all illegal nets in the current layer distribution scheme; screening the illegal wire nets needing to be stripped and re-distributed, and finally, stripping and re-wiring the screened wire nets; if illegal networks still exist in the layer allocation scheme after disconnecting and re-distributing, performing a new round of iteration; if no illegal net exists, entering a refining stage;
in the refining stage, firstly, protective measures are taken for key wire nets in legal layer distribution schemes, so that the used wiring resources are not preempted by other wire nets, and then, the wiring schemes of the wire nets are adjusted one by one to find a better wiring scheme so as to refine the overall layer distribution scheme.
5. The parallel layer distributor for delay perception under a very large scale integrated circuit according to claim 1, wherein the wire net needing to be disconnected and re-distributed is selected through the analysis of the local time sequence criticality of the wire net section in each wiring space; selectively removing a part of wire nets in the process of removing and re-distributing the wire nets, and reserving the wiring result of the part of wire nets can further optimize the time delay of the key wire nets; the timing criticality of a wire net segment in a net at its current wire location is evaluated by the following equation:
wherein od (e, n) is the sequence number of the net n which is descending and ordered according to the time delay value in all the nets using the edge e; dem (e) is the number of nets the current edge e passes by; the smaller the value of APR (e, n) is, the higher the delay criticality of net n at edge e is.
6. The parallel layer distributor for delay perception under a very large scale integrated circuit according to claim 1, wherein the wire network refining stage firstly performs greedy but non-overflow wire network-based wire disconnecting redistribution on the wire network with the highest delay, if the generated new layer distribution scheme is superior to the original layer distribution scheme, the latest layer distribution scheme is adopted, otherwise, the original layer distribution scheme is reserved; for a through hole key wire network, judging whether the new layer allocation scheme is better than the old layer allocation scheme by judging whether the number of through holes is reduced; and whether the new layer allocation scheme is better than the old layer allocation scheme is judged by whether the time delay of other types of networks is reduced.
7. The parallel layer distributor for delay perception under very large scale integrated circuit according to claim 1, wherein the conflict area of the current wiring net is recorded by dynamically constructing conflict graph in the process of parallel wiring of net, and is used as the important basis for selecting the net which can be currently wired in parallel without conflict.
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