CN117688888A - Knowledge and data dual-driven multi-task circuit parameter evolution method - Google Patents
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Abstract
The invention discloses a knowledge and data dual-drive multi-task circuit parameter evolution method, relates to the technical field of automatic design, and solves the technical problem of low optimization efficiency of circuit devices in the prior art. The invention comprises the following steps: describing device parameters in a circuit structure by using the parameter vectors, selecting a plurality of device parameters as the parameter vectors, and randomly and uniformly generating m individuals in a solution space to form an initial population; determining a plurality of process angles for an initial population according to the process angle environmental factors of the device, and determining a polygon surrounded by at least a part of the process angles as a constraint range of the initial population; taking each process corner as a project label task, and performing performance evaluation on each individual through a comprehensive performance function under each target task; and selecting the individual with the optimal performance evaluation as the population to be optimized, and optimizing the population until the preset condition is met. Compared with the existing circuit parameter optimization method, the method can effectively accelerate the circuit optimization process, and improves the robustness of the circuit.
Description
Technical Field
The invention relates to the technical field of automatic design, in particular to a knowledge and data dual-drive multi-task circuit parameter evolution method.
Background
Artificial Intelligence (AI) has been applied to analog circuit designs for decades and now has shown great potential. Undoubtedly, artificial intelligence aided design of analog Integrated Circuits (ICs) remains a challenging task today due to the necessary trade-off between extensive design space and various performance factors, because Electronic Design Automation (EDA) of analog ICs is not as mature as EDA of digital ICs. In particular, the problem of EDA involving multiple process corners has so far only been solved manually. This makes it difficult to achieve a robust design due to process variations that lead to uncertainty in the final circuit performance.
The central idea of the process angle is as follows: NMOS and PMOS crystalsThe speed fluctuation range of the body tube is limited to be within a rectangle determined by four corners. As shown in fig. 1, these four angles are respectively: fast NFET and Fast PFET (Fast nMos, fast pMOS, FF), slow NFET and Slow PFET (Slow nMos, slow pMOS, SS), fast NFET and Slow PFET (FS), slow NFET and Fast PFET (SF), where FF corresponds to the upper right corner in fig. 1, SS corresponds to the lower left corner in fig. 1, FS corresponds to the lower right corner in fig. 1, SF corresponds to the upper left corner in fig. 1. For example, transistors with thinner gate oxide, lower threshold voltages, fall near Fast NFET and Fast PFET (Fast nMos, fast pMOS, FF) corners. The process corners SS, TT, FF are referred to as the lower left, center, and upper right corners of the process corner rectangle, respectively. The process corners typically include TT, FF, SS, FS, SF corners of the MOSFETS. As TT, NMOS-Typical and PMOS-Typical are indicated. From a measurement perspective, typical, fast, slow is a reference to the transistor drive current (I ds ) Is the average value, the maximum value, the minimum value. It can also be understood as how fast the carrier mobility is. Carrier mobility refers to the average drift velocity of carriers under the action of a unit electric field. The results of testing the individual devices are normally distributed, and the average, minimum and maximum limit values are respectively TT, SS and FF, and the distribution is shown in figure 2.
At present, the optimization of circuit parameters is based on a Bayesian optimization algorithm, and the Bayesian optimization is a prominent progress for supporting the optimization of the circuit parameters. The dependence relationship among tasks is self-adaptively learned by using a Gaussian process model, so that the integral search of a Bayesian optimization algorithm is improved, and a better effect is obtained. However, bayesian optimization is generally limited to fairly low or medium dimensional problems. This is because the number of data points required to guarantee good spatial coverage (for learning an accurate gaussian process model) grows exponentially as the search space dimension increases (commonly referred to as a cold start problem). Furthermore, the application of bayesian optimization is mainly limited to continuous search spaces and not directly applied to combined search spaces, where the uncertainty kernel may be difficult to handle. Therefore, solving the above-mentioned drawbacks of the bayesian optimization circuit is a technical problem to be solved.
Disclosure of Invention
Aiming at the technical problems to be solved urgently, the invention provides a method for converting multi-process-angle optimization into multi-task optimization, and the optimization efficiency is improved through knowledge migration of each process angle, so that the circuit parameters are optimized efficiently. The preferred technical solutions of the technical solutions provided by the present invention can produce a plurality of technical effects described below.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the invention provides a knowledge and data dual-drive multi-task circuit parameter evolution method, which comprises the following steps:
s100, describing device parameters in a circuit structure by using a parameter vector, selecting a plurality of device parameters as parameter vectors, and randomly and uniformly generating m individuals in a solution space to form an initial population; the number of individuals is the number of devices in the circuit structure, and each individual is an n-dimensional vector formed by n device parameters;
s200, determining a plurality of process angles for the initial population according to the process angle environmental factors of the devices, and determining a polygon surrounded by at least a part of process angles as a constraint range of the initial population;
s300, taking each process corner as a project label task, and performing performance evaluation on each individual under each target task according to a comprehensive performance function;
s400, selecting an individual with optimal performance evaluation as a population to be optimized, and optimizing the population until a preset condition is met.
Further, step S200 includes the steps of:
and taking the subthreshold voltage and the reference current of each device as the process corner environmental factors, and pairing the minimum value, the average value and the maximum value of the subthreshold voltage of the device with the minimum value, the average value and the maximum value of the reference current of the device in pairs to obtain the process corners.
Further, the plurality of process corners includes:
the minimum value of the sub-threshold voltage of the device is paired with the minimum value of the reference current of the device to form the lower left corner; the maximum value of the sub-threshold voltage of the device is paired with the minimum value of the reference current of the device to form the upper left corner; the maximum value of the sub-threshold voltage of the device is paired with the maximum value of the reference current of the device to form the upper right corner; the minimum value of the sub-threshold voltage of the device is paired with the maximum value of the reference current of the device to form a lower right corner; the average value of the sub-threshold voltage of the device is paired with the average value of the reference current of the device to form a center angle.
Further, the constraint range of the initial population is a rectangle surrounded by the lower left corner, the upper right corner, the lower right corner and the lower left corner.
Further, step S300 includes the steps of:
determining the performance factor of each individual and the corresponding performance function thereof; constructing the comprehensive performance function according to the performance factors and the performance function; according to the device parameters and the performance functions of each individual, carrying out multiple simulation on each individual under all target tasks to obtain a plurality of performance values corresponding to each individual; and calculating the comprehensive performance function value of each individual according to the plurality of performance values to obtain different comprehensive performance function values of each individual under different target tasks.
Further, the comprehensive performance function FoM has the following formula:
；
where k is the number of performance factors, f i (x) A performance function corresponding to an ith performance factor in the circuit structure;maximum value of performance function corresponding to ith performance factor, +.>The minimum value of the performance function corresponding to the ith performance factor; weight (weight) i The weight corresponding to the ith performance factor is given; x is an n-dimensional vector of n of said device parameters.
Further, step S400 includes the steps of:
s410, taking the population to be optimized as a current population;
s420, generating a offspring population from the current population by adopting a genetic operator;
s430, under the selected target task, performing one-time performance evaluation on each offspring population according to the method in the step S300;
s440, combining the evaluated offspring population with the current population to form a new population;
s450, updating scalar fitness and skill factors of each individual of the new population, and selecting the individual with the highest scalar fitness from the updated new population to form the next current population; returning to step S420 until the preset number of evolutions is reached.
Further, determining a factor cost for the individual;
ith individual p i At j-th performance factor T j Cost of the factorThe method comprises the following steps:
；
wherein λ is a penalty factor, anFor individual p i At the performance factor T j The total number of constraint ranges is not satisfied; />For individual p i At the performance factor T j Performance evaluation values.
Further, determining the scalar fitness of an individual;
ith individual p i At j-th performance factor T j Scalar fitness Φ on i The method comprises the following steps:
；
wherein,for individual p i At the performance factor T j Upper factor level, which is individual p after ascending order according to the factor cost i And the index value in the population list is min which is a function taking the minimum value, and k is the number of performance factors.
Further, determining the skill factor of an individual; the skill factor of the individual is an index of the performance factor corresponding to the highest value of all the performance function values of the individual.
By implementing one of the technical schemes, the invention has the following advantages or beneficial effects:
the knowledge and data dual-driven multi-task circuit parameter evolution method provided by the invention converts multi-process angle optimization into multi-task optimization, and improves the optimization efficiency through knowledge migration of each process angle. The multi-task learning is to learn all tasks simultaneously by sharing information between different tasks so as to improve the overall generalization performance. In particular, the objective of multitasking optimization is to facilitate efficient resolution of multiple problems while facilitating a larger collaborative search by facilitating an omnidirectional knowledge transfer. Therefore, compared with the existing circuit parameter optimization method, the method provided by the invention can effectively accelerate the circuit optimization process, and improves the robustness of the circuit.
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For a clearer description of the technical solutions of embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art, in which:
FIG. 1 is a process corner schematic diagram based on NMOS and PMOS device speeds;
FIG. 2 is a normal distribution of NMOS process corner test results;
FIG. 3 is a flow chart of a knowledge and data dual-driven multi-tasking circuit parameter evolution method in accordance with an embodiment of the present invention;
FIG. 4 is a flowchart of an algorithm for optimizing a population to be optimized in step S400 according to an embodiment of the present invention;
FIG. 5 is a circuit diagram to be optimized of an embodiment of the invention;
FIG. 6 is a schematic diagram of the simulation results of the reference circuit according to the embodiment of the present invention using the knowledge and data dual-driven multi-tasking circuit parameter evolution method according to the embodiment of the present invention.
Detailed Description
For a better understanding of the objects, technical solutions and advantages of the present invention, reference should be made to the various exemplary embodiments described hereinafter with reference to the accompanying drawings, which form a part hereof, and in which are described various exemplary embodiments which may be employed in practicing the present invention. The same reference numbers in different drawings identify the same or similar elements unless expressly stated otherwise. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. It is to be understood that they are merely examples of processes, methods, apparatuses, etc. that are consistent with certain aspects of the present disclosure as detailed in the appended claims, other embodiments may be utilized, or structural and functional modifications may be made to the embodiments set forth herein without departing from the scope and spirit of the present disclosure.
In order to illustrate the technical solutions of the present invention, the following description is made by specific embodiments, only the portions related to the embodiments of the present invention are shown.
Embodiment one: as shown in fig. 3-4, the present invention provides a knowledge and data dual-driven method for evolution of a multi-task circuit parameter, comprising the steps of:
s100, describing device parameters in a circuit structure by using the parameter vectors, selecting a plurality of device parameters as the parameter vectors, and randomly and uniformly generating m individuals in a solution space to form an initial population. The number of individuals is the number of devices in the circuit structure, and each individual is formed by n device parameters into an n-dimensional vector. The device parameters of the present example include, but are not limited to, channel length, channel width, and finger (finger) count (i.e., a single MOS may be formed by connecting several MOS transistors of the same size in parallel, where the finger count is the finger count of MOS transistors of the same size);
s200, determining a plurality of process angles for an initial population according to the process angle environmental factors of the device, and determining a polygon enclosed by at least a part of the process angles as a constraint range of the initial population;
s300, taking each process corner as a project label task, and performing performance evaluation on each individual under each target task according to the comprehensive performance function;
s400, selecting an individual with optimal performance evaluation as a population to be optimized, and optimizing the population until a preset condition is met. Wherein the performance evaluation optimum may be the overall performance function FoM maximum as described below.
The knowledge and data dual-driven multi-task circuit parameter evolution method provided by the embodiment converts multi-process angle optimization into a multi-task optimization problem, and improves the optimization efficiency through knowledge migration of each process angle. The multi-task learning is to share information among different tasks and learn all tasks at the same time so as to improve the overall generalization performance. In particular, the objective of multitasking optimization is to facilitate efficient resolution of multiple problems while facilitating a larger collaborative search by facilitating an omnidirectional knowledge transfer. Therefore, compared with the existing circuit parameter optimization method, the circuit optimization method provided by the embodiment can effectively accelerate the circuit optimization process, and the robustness of the circuit is improved.
According to the method, the process angle analysis is regarded as knowledge and integrated into an algorithm, and related data of a circuit device is combined with the process angle analysis, the individual skill factors are regarded as worst performance combinations of the individual in all process angles as skill factors (specifically, the worst performance combinations with the maximum power consumption, the highest temperature coefficient and the worst linearity) so as to realize multitasking optimization of circuit parameters under the dual driving of knowledge and data.
Note that, the circuit structure of the present embodiment generally refers to: the selection of the device types in the circuit design completes the connection relation between the devices, the connection relation between the power supply and the ground, and completes the circuit diagram defined by the input and output ports. I.e. a circuit diagram in which only the parameter optimization of the circuit device is not completed. Further, in step S100, after the circuit structure to be optimized is selected, a vector expression is required for a plurality of device parameters to be optimized in the circuit structure. The vector is used for describing the device parameters, so that a search direction is provided for space optimization of the evolutionary algorithm, and the optimization efficiency of the algorithm can be improved.
As an example, step S200 includes the steps of:
and taking the subthreshold voltage and the reference current of each device as process corner environmental factors, and pairing the minimum value, the average value and the maximum value of the subthreshold voltage of the device with the minimum value, the average value and the maximum value of the reference current of the device in pairs to obtain a plurality of process corners. It should be noted that the process corner environment factors include, but are not limited to, the sub-threshold voltage and reference current of the device.
It should be noted that the minimum value, the average value and the maximum value may be different device specification values, may also be theoretical values of the devices, or may also be obtained by simulation by hspice software.
Further, the plurality of process corners includes:
the lower left corner formed by pairing the minimum value of the sub-threshold voltage of the device with the minimum value of the reference current of the device; the maximum value of the sub-threshold voltage of the device is paired with the minimum value of the reference current of the device to form the upper left corner; the maximum value of the sub-threshold voltage of the device is paired with the maximum value of the reference current of the device to form the upper right corner; the minimum value of the sub-threshold voltage of the device is paired with the maximum value of the reference current of the device to form the lower right corner; the average value of the sub-threshold voltage of the device is paired with the average value of the reference current of the device to form a center angle.
Still further, the constraint range of the initial population is a rectangle surrounded by the lower left corner, the upper right corner, the lower right corner and the lower left corner.
As an example, step S300 includes the steps of:
determining the performance factor of each individual and the corresponding performance function thereof; constructing a comprehensive performance function according to the performance factors and the performance function; according to the device parameters and the performance functions of each individual, carrying out multiple simulation (such as simulation by hspice software) on each individual under all target tasks to obtain a plurality of performance values corresponding to each individual; and calculating the comprehensive performance function value of each individual according to the plurality of performance values to obtain different comprehensive performance function values of each individual under different target tasks.
As an example, the overall performance function FoM has the formula:
（1）；
where k is the number of performance factors, f i (x) The performance function corresponding to the ith performance factor in the circuit structure; f (f) i max (x) For the maximum value of the performance function corresponding to the ith performance factor, f i min (x) The minimum value of the performance function corresponding to the ith performance factor; weight (weight) i The weight corresponding to the ith performance factor is given; x is an n-dimensional vector of n device parameters.
F is the same as the above i (x) The value representing performance such as temperature coefficient, linearity, power supply voltage and power consumption can be given, and x is parameters such as channel length, channel width and finger (finger) number of the MOS transistor, which are determined according to practical situations. f (f) i max (x)、f i min (x) And normalizing the performance factors for normalizing factors, so as to ensure the reasonable range of the performance factors. The normalization factor may be specified or may be obtained through the above simulation. weight (weight) i May be given by a circuit expert.
As an example, each corner is considered as a set of optimization tasks. Namely, according to n initialized device parameters corresponding to each individual, simulating (such as hspice software to simulate) to obtain the corresponding performance of each individual under different angles, such as temperature coefficient, power consumption and the like, and screening out the individual with the performance obtained by simulation within the constraint range. And according to the initialized device parameters corresponding to the screened individuals, calculating the comprehensive performance function value of each individual according to the obtained multiple performance values corresponding to each individual and a formula (1), and obtaining different comprehensive performance function values of each individual under different target tasks. Finally, the individuals under different angles are subjected to cross mutation (the process of performing cross mutation on solutions under different angles is called knowledge migration), and each angle is a task, so that the method is a multi-task evolution algorithm.
It should be noted that, the criterion of selecting the individual with the optimal performance evaluation is that the individual corresponding to the maximum value or the minimum value of the comprehensive performance function value is the individual with the optimal performance evaluation. Since n device parameters can affect the sub-threshold voltage and the reference current, the sub-threshold voltage and the reference current can be obtained by simulation using the device parameters.
In this embodiment, the multitasking evolution uses process corner environmental factors (subthreshold voltages and reference currents as described above) of individual members of a population to implicitly divide the population into five process corners, forming non-overlapping task groups, each group focusing on optimizing one process corner, the task consisting of individual members of all the same skill factors. On this basis, knowledge transfer, selective mating (assortative mating) and selective mimicking (selective imitation) are achieved through genetic mechanisms that work cooperatively to allow knowledge transfer to different task groups. In particular, selective mating allows two individuals with different skill factors (and therefore belonging to different task groups) to mate with a probability (through crossover operations) that is controlled by the algorithm parameter rmp, yielding two offspring. Each of the resulting offspring then mimics any of the parents by inheriting the skills factors of the parent and evaluating only the tasks corresponding to the inherited skills factors, which is the effect of the selective mimicking. Second, each child inheriting a skill factor competes with an existing member of the task group to enter the task group. By utilizing the correlation algorithm module described above, MFEA (Multi-factoral evolutionary algorithm, multi-factor evolution algorithm) can control the transfer of knowledge across tasks from both parents and offspring. The architecture of the multitasking algorithm is thus as follows:
as an example, step S400 includes the steps of:
s410, taking the population to be optimized as a current population;
s420, generating offspring population from the current population by adopting a genetic operator;
s430, under the selected target task, performing one-time performance evaluation on each offspring population according to the method in the step S300;
s440, combining the evaluated offspring population with the current population to form a new population;
s450, updating scalar fitness and skill factors of each individual in the new population, and selecting the individual with the highest scalar fitness from the updated new population to form the next current population; step S420 is returned until a preset number of evolutions is reached, for example, 500 iterations.
It should be noted that in step S430, a target task may be selected, that is, one process corner (e.g., the same process corner as the parent) is selected from the above 5 process corners, and only one simulation is performed. Therefore, the optimization strategy based on the multi-task evolution only needs to simulate the same process angle as that of the parent, so that a large number of simulation times are saved in the optimization process, and algorithm convergence is effectively accelerated.
Further, as an example, determining a factor cost for the individual;
ith individual p i At j-th performance factor T j Cost of the factorThe method comprises the following steps:
（2）；
wherein λ is a penalty factor, anFor individual p i At the performance factor T j The total number of constraint ranges is not satisfied; />For individual p i At the performance factor T j Performance evaluation values.
As one example, further comprising determining a scalar fitness of the individual;
ith individual p i At j-th performance factor T j Scalar fitness Φ on i The method comprises the following steps:
（3）；
wherein,for individual p i At the performance factor T j The upper factor level is the individual p after the ascending order of the factor cost i And the index value in the population list is min which is a function taking the minimum value, and k is the number of performance factors.
As one example, further comprising determining skill factors of the individual; the individual skill factor is an index of the performance factor corresponding to the highest value (such as the highest power consumption, the highest temperature coefficient, the worst linearity, etc.) of all the performance function values of the individual. Specifically, individual p i Skill factors of (a)Index of the performance factor corresponding to the highest value in all the performance function values for the individual, namely:
（4）；
wherein,for individual p i The performance function under the jth performance factor, argmax is taken as +.>The highest value of the sequence corresponds to a function of the index.
It is noted that if and only if the individual p i Is what is shown asWith global optimum among a plurality of tasks, then the individual p is said i Is multi-factor optimal.
It should be noted that a key feature of multitasking evolution is that two randomly selected parent candidates must meet certain conditions to cross. It indicates that individuals prefer mating with those same cultural backgrounds. Skill factor in multitasking evolution) Representing the individual optimum process angle. Thus, two randomly selected parent candidates can freely cross if they possess the same skill factors. Instead, if their skill factors differ, the crossover is performed at a specified random mating probability (rmp) or other mutation pattern. The parameter rmp is used in this algorithm to balance the overhead and exploration of the search space. An rmp value close to 0 means that no mating can take place, whereas a value close to 1 allows a completely random mating, indeed mating occurring at a larger value of rmp (close to 1) increases the exploration of the whole search space, thus helping to escape local optimization, thus rmp is a vital parameter.
Further, the genetic operators in step S420 include the following algorithms:
(1) Randomly selecting two individuals p from a current population a 、p b As a parent;
(2) Generating a random number rand between 0 and 1;
(3) If individual p a Skill factors of (a)Equal to individual p b Skill factors of (1)>Or the random number is smaller than the random mating probability rmp, the following steps are executed: (If (/ -)>==/>)or(rand＜rmp)then:)
Parent p a， p b Performing cross operation to generate two offspring c a ,c b ；
Otherwise, the following steps are executed: (else:)
(a) Parent p a Randomly selecting two individuals with the same skill factors from the current population to perform DE operator (Differential Evolution Algorithm, differential evolution algorithm operator) operation to generate offspring c a；
(b) Parent p b Randomly selecting two individuals with the same skill factors from the current population to perform DE operator operation to generate offspring c b 。
Further, a differential evolution algorithm operator obtains variation vectors corresponding to the parameter vectors one by one according to the parameter vectors; randomly selecting 2 individuals p from the current population a1 、p a2 The obtained variation vector is:
c a =p a +F*(p a1 -p a2 ) （5）；
wherein a. Noteq.a1. Noteq.a2, p a1 -p a2 Is a differential vector delta a1,a2 ，p a ,p a1 ,p a2 The parameter vectors can be respectively 3 independent devices (individuals), and F is the scaling factor of the mutation algorithm. c b And as such, will not be described in detail herein.
It should be noted that, the above-mentioned interleaving operation may be an interleaving process of a differential algorithm in the prior art, which is not described herein.
In summary, through the steps, the problem of converting the multi-process angle optimization into the multi-task optimization is realized, and the optimization efficiency is improved through knowledge migration of each process angle. Therefore, compared with the existing circuit parameter optimization method, the circuit optimization method provided by the embodiment can effectively accelerate the circuit optimization process, and the robustness of the circuit is improved.
Embodiment two: as shown in fig. 5-6, the present embodiment provides a specific embodiment of optimizing parameters of the mosfet (M identified in the circuit diagram) of the circuit in fig. 5 according to the knowledge and data dual-driven multi-task circuit parameter evolution method described in embodiment one to obtain an optimized result.
In this embodiment, fig. 5 is a reference source circuit, which is composed of a start-up circuit, a bias circuit, and an operational amplifier circuit. Wherein the dotted line part is a bias circuit, and the starting circuit comprises a MOS tube M6 and a MOS tube M s1 MOS tube M s2 MOS tube M s3 The operational amplifier circuit comprises a MOS tube M 1 MOS tube M 2 MOS tube M 3 MOS tube M 4 An operational amplifier OPA. The performance factors of the circuit structure are temperature coefficient, linearity, chip area and working current (which can be obtained by simulation through hspice software according to a specific circuit). The parameters of the device are the channel length, the channel width and the number of the fingers of the MOS tube. The process angle is as follows: NFET-fast reader&PFET-fast corner (FF corner), NFET-fast corner&PFET-slow burner (FS process corner), NFET-slow burner&PFET-fast corner, NFET-slow corner&PFET-slow burner (SS Process corner), NFET-Typical burner&PFET-type corner (TT process corner).
It should be noted that Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) can be divided into two different types, one being NFET and the other being PFET. NFETs are n-type source/drain diffusions in a p-type substrate; a positive threshold voltage (corresponding to a voltage v_ { GS } greater than the threshold, current will pass); one end needs to be connected to GND (ground line) 1.PFET is p-type source/drain diffused in n-type substrate; a negative threshold voltage (v_ { GS } voltage is less than the threshold, current will pass); one end needs to be connected to VDD (power supply) 1. Only NFETs are used in the pulluown circuit and only PFETs are used in the pullup circuit. NFET on when a "1" passes through the NFET; when a "0" passes through the NFET, the NFET is off; PFET on when a "0" passes through the PFET; PFET is off when a "1" passes through it; 1. by combining NFETs and PFETs, CMOS (complementary MOS) can be constructed.
The simulation results obtained by performing the step in implementation are shown in fig. 6. The FoM values in the graph are all small in the difference between the five curves when the FoM values are converged at the end, so that the algorithm in the first embodiment can realize small error of multiple process angles. Further, the existing optimization strategy based on the mode of detecting the direct current working point needs to simulate the performance of each process corner in one iteration; the optimization strategy based on the multi-task evolution only needs to simulate the same process angle as that of the parent, so that a large number of simulation times are saved in the optimization process, and algorithm convergence is effectively accelerated. The multi-task optimization of the embodiment is to study to solve a plurality of optimization problems (tasks) at the same time so as to independently improve the performance of solving each task, so that the simultaneous optimization of the performance of multiple process angles can be realized; the existing direct current working point detection-based mode ensures that the working mode of each process corner circuit is normal under the condition of breaking the circuit.
In summary, the method for evolution of the multi-task circuit parameters providing knowledge and data dual driving in the first embodiment effectively accelerates the circuit optimization process, and improves the robustness of the circuit.
It should be understood that, although the steps in the flowcharts related to the above embodiments are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flow according to the embodiments above may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
The foregoing is only illustrative of the preferred embodiments of the invention, and it will be appreciated by those skilled in the art that various changes in the features and embodiments may be made and equivalents may be substituted without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. The knowledge and data double-driven multi-task circuit parameter evolution method is characterized by comprising the following steps of:
s100, describing device parameters in a circuit structure by using a parameter vector, selecting a plurality of device parameters as parameter vectors, and randomly and uniformly generating m individuals in a solution space to form an initial population; the number of the individuals is the number of devices in the circuit structure, and each individual is formed by n device parameters into an n-dimensional vector;
s200, determining a plurality of process angles for the initial population according to the process angle environmental factors of the devices, and determining a polygon surrounded by at least a part of process angles as a constraint range of the initial population;
s300, taking each process corner as a project label task, and performing performance evaluation on each individual under each target task according to a comprehensive performance function;
s400, selecting an individual with optimal performance evaluation as a population to be optimized, and optimizing the population until a preset condition is met.
2. The knowledge and data dual driven multi-tasking circuit parameter evolution method of claim 1 wherein step S200 comprises the steps of:
and taking the subthreshold voltage and the reference current of each device as the process corner environmental factors, and pairing the minimum value, the average value and the maximum value of the subthreshold voltage of the device with the minimum value, the average value and the maximum value of the reference current of the device in pairs to obtain the process corners.
3. The knowledge and data dual driven multitasking circuit parameter evolution method of claim 2, wherein said plurality of process corners comprises:
the minimum value of the sub-threshold voltage of the device is paired with the minimum value of the reference current of the device to form the lower left corner;
the maximum value of the sub-threshold voltage of the device is paired with the minimum value of the reference current of the device to form the upper left corner;
the maximum value of the sub-threshold voltage of the device is paired with the maximum value of the reference current of the device to form the upper right corner;
the minimum value of the sub-threshold voltage of the device is paired with the maximum value of the reference current of the device to form a lower right corner;
the average value of the sub-threshold voltage of the device is paired with the average value of the reference current of the device to form a center angle.
4. The knowledge and data dual driven multi-tasking circuit parameter evolution method of claim 3 wherein the constraint range of the initial population is a rectangle bounded by the lower left corner, the upper right corner, the lower left corner.
5. The knowledge and data dual driven multi-tasking circuit parameter evolution method of claim 1 wherein step S300 comprises the steps of:
determining the performance factor of each individual and the corresponding performance function thereof; constructing the comprehensive performance function according to the performance factors and the performance function; according to the device parameters and the performance functions of each individual, carrying out multiple simulation on each individual under all target tasks to obtain a plurality of performance values corresponding to each individual; and calculating the comprehensive performance function value of each individual according to the plurality of performance values to obtain different comprehensive performance function values of each individual under different target tasks.
6. The knowledge and data dual driven multi-tasking circuit parameter evolution method of claim 5 wherein said integrated performance function FoM is formulated as:
；
where k is the number of performance factors, f i (x) A performance function corresponding to an ith performance factor in the circuit structure;maximum value of performance function corresponding to ith performance factor, +.>The minimum value of the performance function corresponding to the ith performance factor; weight (weight) i The weight corresponding to the ith performance factor is given; x is an n-dimensional vector of n of said device parameters.
7. The knowledge and data dual driven multi-tasking circuit parameter evolution method of claim 1 wherein step S400 comprises the steps of:
s410, taking the population to be optimized as a current population;
s420, generating a offspring population from the current population by adopting a genetic operator;
s430, under the selected target task, performing one-time performance evaluation on each offspring population according to the method in the step S300;
s440, combining the evaluated offspring population with the current population to form a new population;
s450, updating scalar fitness and skill factors of each individual of the new population, and selecting the individual with the highest scalar fitness from the updated new population to form the next current population; returning to step S420 until the preset number of evolutions is reached.
8. The knowledge and data dual driven multi-tasking circuit parameter evolution method of claim 7 further comprising determining a factor cost for an individual;
ith individual p i At j-th performance factor T j Cost of the factorThe method comprises the following steps:
；
wherein λ is a penalty factor, anFor individual p i At the performance factor T j The total number of constraint ranges is not satisfied; />For individual p i At the performance factor T j Performance evaluation values.
9. The knowledge and data dual driven multitasking circuit parameter evolution method of claim 8, further comprising determining said scalar fitness of an individual;
ith individual p i At j-th performance factor T j Scalar fitness Φ on i The method comprises the following steps:
；
wherein,for individual p i At the performance factor T j Upper factor level, which is individual p after ascending order according to the factor cost i And the index value in the population list is min which is a function taking the minimum value, and k is the number of performance factors.
10. The knowledge and data dual driven multi-tasking circuit parameter evolution method of claim 7 further comprising determining said skill factors of an individual; the skill factor of the individual is an index of the performance factor corresponding to the highest value of all the performance function values of the individual.
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