CN117678054A - Graphene substrate and method of forming the same - Google Patents

Graphene substrate and method of forming the same Download PDF

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CN117678054A
CN117678054A CN202280049432.4A CN202280049432A CN117678054A CN 117678054 A CN117678054 A CN 117678054A CN 202280049432 A CN202280049432 A CN 202280049432A CN 117678054 A CN117678054 A CN 117678054A
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graphene
metal oxide
layer
oxide layer
substrate
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塞巴斯蒂安·狄克逊
雅斯普里特·卡因特
伊沃尔·吉尼
托马斯·詹姆士·巴德科克
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Paragraf Ltd
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Priority claimed from PCT/EP2022/068476 external-priority patent/WO2023285194A1/en
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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Abstract

Provided is a graphene substrate including: a graphene layer structure directly on the metal oxide layer, the metal oxide layer directly on the support layer; wherein the metal oxide layer has a thickness of less than 5nm and is selected from the group consisting of Al 2 O 3 、HfO 2 、MgO、MgAl 2 O 4 、Ta 2 O 5 、Y 2 O 3 、ZrO 2 And YSZ; and wherein the support layer is BN, alN, GaN, siC, diamond, or combinations thereof.

Description

Graphene substrate and method of forming the same
The invention provides a graphene substrate, which is a graphene substrate comprising a graphene layer structure on a metal oxide layer. In particular, the metal oxide layer is directly on the support layer. More specifically, the support layer is boron nitride, aluminum nitride, gallium nitride, silicon carbide, diamond, or a combination thereof. The invention also provides a method of forming a graphene substrate. In particular, the method comprises: providing a growth substrate comprising or consisting of a support layer formed of BN, alN, gaN, siC, diamond or a combination thereof; a metal oxide layer is formed on the growth substrate, and then a graphene layer structure is formed. More specifically, the metal oxide layer is formed by ALD, and the graphene layer structure is formed by CVD.
Graphene has been attracting attention as a two-dimensional material due to its unique electronic characteristics and its use in electronic devices. Graphene is common in the art to manufacture on catalytic metal substrates such as copper by techniques such as lift-off or by CVD. The graphene produced by such a method is then transferred to a substrate compatible with the electronic device, such as silicon dioxide, for fabrication of the electronic device.
It is also known in the art that graphene can be synthesized, fabricated, formed directly on a non-metallic surface of a substrate. These substrates include silicon, sapphire, and III-V semiconductor substrates. The inventors have found that the most efficient method for manufacturing high quality graphene, especially directly on such non-metallic surfaces, is the method disclosed in WO 2017/029470. The publication discloses a method for manufacturing graphene; these methods rely primarily on: heating a substrate held in a reaction chamber to a temperature within a decomposition range of a carbon-based precursor for graphene growth; introducing a precursor into the reaction chamber through a relatively cool inlet so as to establish a slave matrixThe sufficiently steep thermal gradient of the plate surface extending away from the point where the precursor enters the reaction chamber is such that the proportion of precursor reacted in the gas phase is low enough to allow graphene formation from carbon released from the decomposed precursor. Preferably, the apparatus comprises a showerhead having a plurality of precursor entry points or inlets, the spacing of the showerhead from the substrate surface being variable and preferably less than 100mm. The process of WO 2017/029470 is desirably carried out using a MOCVD reactor. Although MOCVD is derived from metal-organic precursors such as AlMe due to its origin 3 (TMAL) and GaMe 3 (TMGa) manufacture of semiconductor materials such as AlN and GaN, represents metal organic chemical vapor deposition, but such apparatus and reactors are well known to those skilled in the art and are understood to be suitable for use with non-metal organic precursors. MOCVD may be used synonymously with Metal Organic Vapor Phase Epitaxy (MOVPE).
While the method of WO 2017/029470 enables the production of high quality graphene with excellent uniformity and constant number of layers (as needed) over the whole area on a substrate without additional carbon fragments or carbon islands, the stringent requirements in the field of electronic device fabrication mean that there is still a need to further improve the electronic properties of graphene and to provide a more reliable and efficient method for industrial fabrication of graphene, especially large area graphene on non-metallic substrates.
However, it is known that electron-phonon coupling between graphene and substrate may adversely affect carrier mobility compared to the theoretical value of freestanding graphene. Polar phonons are able to induce an electric field in adjacent layers that causes remote phonon scattering of electrons in the layers. Such coupling is long-range and may also be referred to asAnd (3) coupling.
Electron-phonon coupling has been studied theoretically and experimentally, particularly with respect to substrates such as silicon dioxide. Nature Nanotechnology 3,206, 206-209 (2008) "Intrinsic and Extrinsic Performance Limits of Graphene Devices on SiO 2 "and Phys. Rev. B77,195415 (20)08 "Substrate limited electron dynamics in graphene" studied such as SiO 2 And the effect of the polarizable substrate of SiC on carrier dynamics in graphene.
Nature Nanotechnology 5,722, 722-726 (2010) "Boron nitride substrates for high-quality graphene electronics" and appl. Phys. Lett.115,043104 (2019) "Role of remote interfacial phonons in the resistivity of graphene" are examples demonstrating the benefit of hexagonal boron nitride (h-BN) as a promising substrate, because the optical phonon mode of h-BN is energetically superior to other dielectrics (e.g., siO) 2 And HfO 2 ) Much higher. The energy of the relevant phonon mode is SiO 2 The mid phonon mode is about twice as large. The ubiquitous presence of lower energy phonon modes in oxide substrates results in remote phonon scattering and greater resistivity (i.e., a decrease in carrier mobility) in graphene provided on the oxide substrate.
US2012/261640 A1 relates to an electronic device employing a graphene layer as a charge carrier layer sandwiched between a material having a highly ordered crystal structure and a high dielectric constant, such as SiO 2 、HfO 2 And Al 2 O 3 Between the layers of the composition. In some embodiments, the graphene layer is disposed on an interface layer, rather than on a highly ordered crystalline material, the interface layer being a thin layer of dielectric nonpolar material. Suitable non-polar materials include polymers such as polyethylene, polypropylene and polystyrene.
US2010/200839 A1 relates to a substrate having a graphene layer grown thereon and an electro-optical integrated circuit formed in such a substrate. This document discloses that an aluminum oxide formed on a single crystal silicon substrate having an average thickness of 10nm or more and 500nm or less, an average thickness of less than 10nm, is undesirable.
The underlying substrate to graphene, in particular h-BN, siC, siO, was evaluated by means of an integrated monte carlo simulator at 10 th spanish electronics conference (Spanish Conference on Electron Devices, CDE) "Monte Carlo modeling of mobility and microscopic charge transport in supported graphene" in 2015 2 And HfO 2 Mobility in (a)And the effect of electron transport.
There remains a need in the art for graphene disposed on a substrate with reduced electron-phonon coupling in order to improve the electronic properties of the graphene and methods of forming the graphene on a suitable substrate. The inventors developed the object of the present invention to solve at least these problems.
According to a first aspect of the present invention, there is provided a graphene substrate comprising:
a graphene layer structure directly on the metal oxide layer, the metal oxide layer directly on the support layer;
wherein the metal oxide layer has a thickness of less than 5nm and is selected from the group consisting of Al 2 O 3 、HfO 2 、MgO、MgAl 2 O 4 、Ta 2 O 5 、Y 2 O 3 、ZrO 2 And YSZ; and is also provided with
Wherein the support layer is BN, alN, gaN, siC, diamond or a combination thereof.
In another aspect, a method of forming a graphene substrate is provided, the method comprising:
providing a growth substrate comprising or consisting of a support layer formed of BN, alN, gaN, siC, diamond or a combination thereof;
forming a metal oxide layer on the support layer by ALD, wherein the metal oxide layer has a thickness of less than 5nm and is selected from the group consisting of Al 2 O 3 、HfO 2 、MgO、MgAl 2 O 4 、Ta 2 O 5 、Y 2 O 3 、ZrO 2 And YSZ; and
a graphene layer structure is formed on the metal oxide layer by CVD.
The present disclosure will now be further described. In the following paragraphs, different aspects/embodiments of the present disclosure are defined in more detail. Each aspect/embodiment so defined may be combined with any other aspect/embodiment or aspects/embodiments unless clearly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any one or more other features indicated as being preferred or advantageous.
The present invention relates to a graphene substrate itself and a method of forming a graphene substrate, the method comprising forming graphene. Formation may be considered synonymous with synthesis, manufacture, production and growth. Graphene is a well-known two-dimensional material that refers to an allotrope of carbon comprising a monolayer of carbon atoms in a hexagonal lattice. As used herein, graphene refers to one or more layers of graphene. The present invention is thus directed to the formation of single layers of graphene as well as multi-layer graphene (which may be referred to as a graphene layer structure). As used herein, graphene refers to a graphene layer structure preferably having 1 to 10 monolayers of graphene. In many subsequent applications of the graphene substrate, one monolayer of graphene is particularly preferred. Thus, the graphene-based sheets preferably comprise a graphene monolayer directly on the metal oxide layer. The graphene produced in the methods disclosed herein is preferably a monolayer graphene. However, for other applications, multilayer graphene is preferred, and 2 or 3 layers of graphene may be preferred. As described herein, it is particularly preferred that the graphene is obtainable, preferably by CVD (where CVD refers to CVD growth of the graphene directly on the metal oxide layer).
A graphene substrate will be understood to include graphene and be suitable for a substrate for subsequent use. In particular, graphene substrates are suitable for preparing graphene-based electronic devices. As used herein, the term substrate may be used to refer to a material suitable for depositing another layer thereon. The term substrate is generally synonymous with wafer. Thus, each of the support layer and the metal oxide may be referred to as a substrate independently of each other.
The graphene substrate further includes a metal oxide layer and a support layer. The graphene layer structure is disposed directly on the metal oxide layer. That is, there is no intervening layer or material and one surface of the graphene is in direct substantially continuous contact with the surface of the metal oxide layer. It should be appreciated that the graphene may include wrinkles, which are physical deformations of the graphene away from the substrate surface. However, the graphene is preferably a single continuous sheet/layer of carbon atoms (or a plurality of individually stacked continuous sheets/layers, wherein the graphene is a multi-layer graphene). Similarly, the metal oxide layer is disposed directly on the support layer.
The inventors have found that a thin metal oxide layer may be provided on the support layer in order to provide a preferred surface for the formation of graphene, particularly by CVD, even more particularly by CVD according to WO 2017/029470. The inventors have found that a thin metal oxide layer, while made of a material known to exhibit the necessary phonon modes of appropriate energy to couple with electrons in an adjacent layer, enables graphene to be disposed immediately adjacent to a support layer made of a material exhibiting the desired phonon band structure, which results in reduced electron-phonon coupling. Thus, in the case of providing a sufficiently thin metal oxide layer, electron-phonon coupling is not significantly observed. The inventors have found that a metal oxide layer having a thickness of less than 5nm is sufficient to provide such advantages. Even more preferably, the metal oxide layer has a thickness of less than 4nm.
Although it is preferable to have as small a thickness as possible in view of the possibility of coupling between the metal oxide and the graphene, a sufficiently thick metal oxide layer is required to provide an improvement in growing graphene directly on this layer by CVD. The inventors have found that a metal oxide layer thickness of at least 0.5nm is sufficient, but preferably a thickness of at least 1nm, more preferably at least 2nm. Therefore, the thickness of the metal oxide layer is preferably 0.5nm to 5nm, 1nm to 4nm, and most preferably 2nm to 4nm.
The metal oxide layer is selected from Al 2 O 3 、HfO 2 、MgO、MgAl 2 O 4 、Ta 2 O 5 、Y 2 O 3 、ZrO 2 And YSZ. That is, the layer is composed of the material. The inventors have found that such metal oxides are particularly suitable for growing graphene directly thereon by CVD. Without wishing to be bound by theory, the inventors have found that these materialsThe material has sufficiently low carbon solubility that high quality uniform graphene can be grown during the high temperatures of CVD without defects that may be present when grown directly on materials such as those of the support layer. Thus, the use of a metal oxide layer provides advantages for CVD grown graphene, despite the expected drawbacks with respect to electron-phonon coupling. However, the inventors overcome this problem by using a sufficiently thin metal oxide layer.
As will be appreciated, the stoichiometry of the metal oxide need not be precise (e.g., al 2 O 3 ). The stoichiometry of such materials may vary, as is known in the art. For example, alumina may be referred to as AlO x Wherein x is about 3/2. Preferably, the metal oxide layer is Al 2 O 3 、HfO 2 Or YSZ, which are materials that allow the formation of particularly high quality graphene.
In the graphene substrate, the support layer is formed of a material selected from the group consisting of BN, alN, gaN, siC, diamond, or alternatively combinations thereof. That is, the layer is composed of the material. The inventors have identified such materials as materials having a desired phonon band structure in which the active phonon modes and associated symmetries and energies advantageously reduce electron-phonon coupling relative to other suitable substrates, i.e., dielectric and/or semiconductor substrates, for electronic device fabrication. Thus, while the inventors have identified BN, alN, gaN, siC, diamond and combinations thereof as suitable materials that exhibit such advantageous properties, the skilled artisan can identify equivalent materials by routine experimentation, such that the technical benefits of the invention can be realized and utilized using such equivalents. Such materials may be referred to as "low phonon density" materials in view of the reduced density of available correlated phonon modes coupled with corresponding electrons in adjacent graphene.
Preferably, the support layer is formed of BN, alN, gaN or a combination thereof. These materials have particularly low phonon densities so as not to inhibit mobility of the overlying graphene. Preferably, the BN is hexagonal boron nitride (i.e., h-BN), but cubic boron nitride (i.e., c-BN) may also be used. AlN and GaN are known to crystallize in groups of cubic spaces. Most preferably, the support layer is formed of (consists essentially of) AlN.
Although graphene is known to be disposed directly on "low phonon density" materials such as boron nitride and on materials such as SiO 2 And HfO 2 But there is no need in the art to combine such materials as described herein to provide a multilayer substrate. Graphene in the art is typically provided by growth on a copper substrate and is transferred directly to the desired substrate by a polymer (typically PMMA). Although the inventors sought to fabricate graphene directly on the desired low phonon density materials by CVD, the carbon solubility and/or formation of strong covalent bonds (e.g., si—c bonds when grown on SiC) in these materials inhibited the formation of the high uniformity required for graphene-based electronic applications. Defects such as these introduce a source of charge scattering, thereby reducing carrier mobility. These problems do not occur when graphene is transferred onto the substrate surface as is typical in the art. On the other hand, the usual physical transfer of graphene from copper introduces many defects that negatively affect the electronic properties of graphene. Furthermore, such processes are not suitable for large scale manufacturing (e.g., on CMOS substrates in a manufacturing facility). Unintentional doping, particularly from catalytic metal substrates with etching solutions, can also lead to inconsistent production of graphene from sample to sample and from commercial to commercial production.
The inventors have surprisingly found that a thin metal oxide layer is sufficient to allow high quality graphene formation directly by CVD, but without introducing unwanted electron-phonon coupling that would otherwise reduce carrier mobility.
Preferably, the support layer has a thickness of at least 5nm, preferably at least 15nm, more preferably at least 50nm. In some embodiments, the support layer preferably has a thickness of at least 100 nm. In other embodiments, the support layer may have a thickness of at least 2nm, for example, where the metal oxide layer is particularly thin. It is generally preferred that the metal oxide layer is not thicker than the support layer.
Preferably, the support layer is disposed on the wafer. The wafer under the combination of the support layer, the metal oxide layer, and the graphene is not particularly limited. Preferably, the wafer is a sapphire wafer or a silicon wafer. As will be appreciated, silicon wafers include "pure" silicon wafers (consisting essentially of doped or undoped silicon) or wafers that may be referred to as CMOS wafers that include additional related circuitry.
The method of the present invention includes providing a growth substrate that includes or consists of a support layer formed of BN, alN, gaN, siC, diamond, or a combination thereof. The growth substrate preferably further comprises a wafer, preferably a sapphire wafer or a silicon wafer.
In some preferred embodiments, the method further comprises etching away or separating the wafer after forming the graphene layer structure. The wafer provides support for the growth of graphene in the CVD reactor chamber, however, the wafer may be removed by etching or separation, thereby reducing the thickness of the graphene substrate, which is preferred for electronics applications.
The method further comprises forming a metal oxide layer on the support layer by ALD, wherein the metal oxide layer has a thickness of less than 5nm and is selected from the group consisting of Al 2 O 3 、HfO 2 、MgO、MgAl 2 O 4 、Ta 2 O 5 、Y 2 O 3 、ZrO 2 And YSZ.
The inventors have found that forming a metal oxide layer by ALD is particularly beneficial for providing a highly conformal (uniform thickness) layer, which is essential when forming such thin layers (down to 0.5nm thick). ALD involves the sequential introduction of at least two chemical precursors (e.g., ozone and trimethylaluminum to form an aluminum oxide, as is known in the art, although other suitable materials for the metal oxides described herein are well known). Considering the self-limiting nature of ALD growth, the thickness of the layer may be controlled by varying the number of such cycles.
The method further includes forming a graphene layer structure on the metal oxide layer by CVD. CVD generally refers to a series of chemical vapor deposition techniques, each of which involves vacuum deposition to produce a thin film material, for example a two-dimensional crystalline material such as graphene. The volatile precursors in the gas phase or suspended in the gas are decomposed to release the necessary nuclides to form the desired material, in the case of graphene carbon.
Preferably, the method involves forming graphene by thermal CVD such that the decomposition is the result of heating the precursor. Preferably, the CVD reactor used in the methods disclosed herein is a cold wall reactor wherein the heater coupled to the substrate is the only heat source for the chamber. As will be understood, the substrate refers to the support layer and the metal oxide layer, as well as the underlying wafer, if present.
In a particularly preferred embodiment, the CVD reactor comprises a closely coupled showerhead having a plurality of precursor entry points or an array of precursor entry points. Such CVD apparatus comprising closely coupled showerhead may be known for use in MOCVD processes. Thus, the process may alternatively be considered to be performed using a MOCVD reactor comprising a tightly coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum spacing of less than 100mm, more preferably less than 25mm, even more preferably less than 10mm between the surface of the substrate and the plurality of precursor entry points. As will be understood, by constant spacing is meant that the minimum spacing between the surface of the substrate and each precursor entry point is substantially the same. The minimum spacing refers to the minimum spacing between the precursor entry point and the substrate surface (i.e., the surface of the metal oxide layer). Thus, such embodiments relate to a "vertical" arrangement whereby the plane containing the precursor entry points is substantially parallel to the plane of the substrate surface.
The precursor entry point into the reaction chamber is preferably cooled. The inlet or spray head when in use is preferably actively cooled by an external coolant, such as water, in order to maintain a relatively cool temperature of the precursor entry points such that the precursor temperature at the time of entry into the reaction chamber through the plurality of precursor entry points is below 100 ℃, preferably below 50 ℃.
Preferably, a combination of sufficiently small spacing between the substrate surface and the multiple precursor entry points and cooling the precursor entry points, plus heating the substrate to decomposition of the precursorWithin the scope, a sufficiently steep thermal gradient is generated extending from the substrate surface to the precursor entry point to allow graphene to form on the substrate surface. As disclosed in WO 2017/029470, a very steep thermal gradient may be used to facilitate the formation of high quality and uniform graphene directly on a non-metallic substrate, preferably across the entire surface of the substrate. The substrate may have a diameter of at least 5cm (2 inches), at least 15cm (6 inches), or at least 30cm (12 inches). Particularly suitable devices for the methods described herein includeClose-Coupled Reactor and->A TurboDisk reactor.
Thus, in a particularly preferred embodiment wherein the method of the invention relates to the use of a method as disclosed in WO 2017/029470, the method comprises:
disposing a substrate on a heating susceptor in a tightly coupled reaction chamber, the substrate comprising a support layer and a metal oxide layer, the tightly coupled reaction chamber having a plurality of cooled inlets arranged such that, in use, the inlets are distributed over the substrate and have a constant spacing from a surface of the substrate (i.e., the metal oxide layer);
cooling the inlet to below 100 ℃ (i.e. to cool the precursor);
introducing a precursor in a gas phase and/or suspended in a gas through an inlet and into a CVD reaction chamber, thereby decomposing the precursor and forming graphene on the metal oxide layer of the substrate; and
heating the susceptor to a temperature at least 50 ℃ above the decomposition temperature of the precursor to provide a thermal gradient between the substrate surface and the inlet that is sufficiently steep to allow graphene formation from carbon released from the decomposed precursor;
wherein the constant spacing is less than 100mm, preferably less than 25mm, even more preferably less than 10mm.
Preferably, the method further comprises forming one or more further layers on the graphene layer structure. Preferably, this comprises forming a further metal oxide layer on the graphene layer structure by ALD, wherein the further metal oxide layer has a thickness of less than 5nm and is selected from the group consisting of Al 2 O 3 、HfO 2 、MgO、MgAl 2 O 4 、Ta 2 O 5 、Y 2 O 3 、ZrO 2 And YSZ. Likewise, the method preferably further comprises forming a further layer on the further metal oxide layer, wherein the further layer is BN, alN, gaN, siC, diamond or a combination thereof.
In another aspect, there is provided an electrical device comprising a graphene substrate as described herein or obtainable by the methods disclosed herein. That is, the electrical device may be fabricated from graphene-based sheets, thereby bonding the graphene layer structure directly on the metal oxide layer directly on the support layer, as described herein. Additional steps for forming electrical devices are known in the art and may include patterning, such as by photolithography, laser and/or plasma etching, and/or depositing additional layers and materials, such as dielectric layers and/or metal ohmic contacts.
In view of the advantageous properties provided by graphene, particularly the improvement in carrier mobility, electrical devices comprising such graphene substrates may be improved over prior art devices. For example, an electro-optic modulator is a preferred electrical device that may benefit from greater carrier mobility. In particular, an electro-optic modulator comprising a graphene substrate may operate with a greater bandwidth. Other preferred electrical devices include transistors (i.e., graphene transistors), such as radio frequency graphene field effect transistors (RF GFETs), which rely on high carrier mobility to be "on" and "off at such high frequencies. Biosensors are also preferred electrical devices that benefit from the higher mobility of graphene due to the associated reduction in sheet resistance, thereby reducing the power required for operation. Another particularly preferred electrical device is a hall effect sensor. The sensitivity of such devices can be improved at higher carrier mobilities.
Drawings
The invention will now be further described with reference to the following non-limiting drawings, in which:
fig. 1 is a graph of graphene mobility as a function of the number of ALD cycles.
Fig. 2 is a graph of carrier scattering time as a function of the number of ALD cycles.
Fig. 3 is a raman spectrum of graphene grown directly on AlN, and fig. 4 is an AFM image of the graphene.
FIG. 5 growth in AlO x AlO of AlN stack x Raman spectra of graphene on the layer,
fig. 6 is an AFM image of the graphene.
Fig. 7 is a cross-section of an electrolyte gated field effect transistor comprising a graphene substrate of the present invention.
Fig. 8-12 are graphs of current versus gate voltage, respectively, of the transistor of fig. 7.
The data shown in fig. 1 and 2 were obtained from four graphene substrates according to the present invention. The graphene-based plate includes a sapphire wafer having an AlN support layer thereon. The aluminum oxide layer is then formed at different thicknesses by varying the number of cycles during atomic layer deposition. Graphene is then formed on the aluminum oxide layer by CVD according to the methods described herein.
Fig. 1 shows that the improvement of the carrier mobility of graphene formed on the metal oxide layer increases with the increase of the metal oxide thickness. The thickness (in nm) of the metal oxide layer is about 1/10 of the number of ALD cycles. Although electron-phonon coupling may lead to reduced carrier mobility, the inventors have found that a metal oxide layer of less than 5nm may result in improved carrier mobility. The inventors have found that 2nm to 4nm provides the best thickness for carrier mobility.
Fig. 2 similarly shows an improvement in carrier scattering time as the thickness of the metal oxide layer increases up to about 3nm, where the increased thickness results in a decrease in carrier scattering time. Thus, 1nm to 4nm, preferably 2nm to 3nm, provides an optimal thickness with respect to carrier scattering time.
Fig. 3 is a raman spectrum of graphene grown directly on AlN using a method according to an example, except that the ALD step of metal oxide growth is omitted. Fig. 4 is an AFM image of the same sample.
FIG. 5 is a schematic illustration of an AlO x AlO of AlN stack x Raman spectra of graphene grown on the layer. Fig. 6 is an AFM image of the same sample.
Fig. 7 is a schematic cross-section of an electrolyte gated GFET 100 fabricated according to examples described herein. The transistor 100 comprises a graphene substrate according to the present invention. The graphene substrate is formed from a sapphire wafer 105, a 100nm to 250nm thick aluminum nitride layer 110, and an approximately 3nm thick aluminum oxide layer 115 thereon, with a final graphene monolayer 120 across the surface of the aluminum oxide 115.
The transistor 100 also includes silver (Ag) -coated contacts 125a, 125b coated on the surface of the graphene monolayer 120 so as to leave an exposed surface of the graphene monolayer therebetween that can receive the electrolyte 130. The contacts 125a, 125b serve as source and drain electrodes of the transistor. In use, an electrolyte 130, such as a 100mM potassium chloride (KCl) electrolyte, is deposited on the surface of the graphene monolayer 120, and conventional silver/silver chloride (Ag/AgCl) particle probes 135 are immersed in the electrolyte and used as gate electrodes to provide a gate voltage.
Fig. 8-12 depict graphs of current versus gate voltage, respectively, for a plurality of electrolyte gated GFETs 100 fabricated on a single common sapphire wafer. For each transistor, the gate voltage varied between-0.4V to +0.6v, and the drain-source current (a) was measured (drain voltage 40 mV). Drain-source currents are plotted in the range of 10 μa for each transistor. These results indicate that each transistor can be gated with a sensible dirac gate voltage.
Example
A growth substrate comprising or consisting of a support layer is placed on a substrate for a metal oxide (MO x ) In the grown ALD chamber. In both examples described herein, the growth substrate consists of an aluminum nitride support layer on a silicon wafer or sapphire wafer. The thickness of the aluminum nitride layer may be between 100nm and 250 nm. The substrate was held in the chamber at a deposition temperature of 150 ℃ under a vacuum of about 220 millitorr (about 27 Pa), the chamber temperature and pressure were equilibrated with a flow of 27 seem nitrogen gas, and any moisture from the sample surface was desorbed. Then Trimethylaluminum (TMAL) and deionized water (DI H) are used respectively 2 O) or ozone (O) 3 ) Deposition of Al as a metal organic precursor and an oxidizer precursor 2 O 3 Nitrogen is used as both a carrier gas and a purge gas to introduce the precursor into the deposition chamber. The precursor was pulsed into the chamber at a ratio of 3:2 for a pulse time of 0.6 seconds and purge times for TMAl and DI H 2 O or O 3 20 seconds and 18 seconds or 25 seconds, respectively. Films were deposited at 150 ℃ in different numbers of cycles (between 5 and 100 cycles) depending on the desired film thickness.
The ALD-coated substrate was positioned on a silicon carbide coated graphite susceptor within a MOCVD reactor chamber. The reactor chamber itself is protected in an inert atmosphere within the glove box. The reactor was then sealed closed and purged at a rate of 10,000sccm to 60,000sccm under a stream of nitrogen, argon or hydrogen. The susceptor is rotated at a rate of 40rpm to 60 rpm. The pressure in the reactor chamber was reduced to 30 mbar to 100 mbar. Optical probes are used to monitor substrate reflectivity and temperature during growth, where the substrate is still in its unheated state, and they are rotated under the probes to establish a baseline signal. The substrate is then heated to a set point of 1000 ℃ to 1500 ℃ at a rate of 0.1K/s to 3.0K/s using a resistive heater coil positioned below the susceptor. The substrate is optionally baked under a hydrogen stream for 10 to 60 minutes, after which the ambient gas is switched to nitrogen or argon and the pressure is reduced to 30 to 50 mbar. The substrate is annealed at growth temperature and pressure for a period of 5 minutes to 10 minutes after which hydrocarbon precursors are allowed to enter the chamber. The hydrocarbon precursor is transported from its liquid state in a bubbler by passing a carrier gas (nitrogen, argon or hydrogen) through a liquid maintained at a constant temperature and pressure. Vapor enters the gas mixing manifold and travels through the showerhead to the reactor chamber via a plurality of small inlets commonly referred to in the art as plenums, which ensures uniform vapor distribution and growth across the surface of the substrate. The substrate is exposed to hydrocarbon vapor at a constant flow rate, pressure and temperature for a duration of 1,800 seconds to 10,800 seconds, at which time the precursor supply valve is closed. The substrate is then cooled at a rate of 0.1K/min to 4K/min under a continuous flow of nitrogen, argon or hydrogen. Once the substrate temperature reaches below 200 ℃, the chamber is pumped to vacuum and purged with an inert gas. The rotation is stopped and the heater is turned off. Once the heater temperature reaches below 150 ℃, the reactor chamber is opened and the graphene coated substrate is removed from the susceptor.
The formed graphene is then characterized using standard techniques including raman spectroscopy and Atomic Force Microscopy (AFM). AFM data in fig. 6 shows the morphology of graphene grown on a thin (< 5 nm) alumina layer on aluminum nitride using a sapphire wafer according to an example. Graphene grows as a continuous monolayer, rather than as lines or flakes of discrete graphene, making it useful for applications in electronic devices. Even graphene grown on a thin metal oxide layer shows significantly improved D/G ratio, as well as improved mobility and carrier scattering time, compared to graphene grown directly on aluminum nitride on a sapphire wafer (fig. 4), as shown in fig. 2 and 3.
To produce the transistor of fig. 7, after performing the above steps, a rectangular chip, measured about 6mm along one side and about 2mm along the other side, is then scribed. Silver paint strips along the edges Shi Tubao of the short (2 mm) sides to form source/drain contacts. The coating was dried. About 2mm in the center of the chip 2 In (2) a few μl of 10mM KCl was transferred onto the graphene surface. The Ag/AgCl particle reference electrode was immersed in an electrolyte, and the potential applied thereto was used as a gate voltage.
As used herein, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. The use of the term "comprising" is intended to be interpreted as including such features, but not excluding the inclusion of additional features, and also to include the option of being necessarily limited to those features described. In other words, unless the context clearly indicates otherwise, the term also includes the limitations of "consisting essentially of … …" (intended to mean that certain additional components may be present, so long as they do not materially affect the basic characteristics of the described feature) and "consisting of … …" (intended to mean that other features may not be included, such that if components are expressed as percentages in their proportions, these will add to 100%) taking into account any unavoidable impurities.
The foregoing detailed description has been provided by way of illustration and description, and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments described herein will be apparent to those of ordinary skill in the art and remain within the scope of the appended claims and their equivalents.

Claims (13)

1. A graphene substrate, comprising:
a graphene layer structure directly on the metal oxide layer, the metal oxide layer directly on the support layer;
wherein the metal oxide layer has a thickness of less than 5nm and is selected from the group consisting of Al 2 O 3 、HfO 2 、MgO、MgAl 2 O 4 、Ta 2 O 5 、Y 2 O 3 、ZrO 2 And YSZ; and is also provided with
Wherein the support layer is BN, alN, gaN, siC, diamond, or a combination thereof.
2. The graphene substrate according to claim 1, wherein the support layer is BN, alN, gaN or a combination thereof.
3. A graphene substrate according to claim 1 or 2, wherein the support layer is provided on a wafer, preferably a sapphire wafer or a silicon wafer.
4. A graphene substrate according to any preceding claim, wherein the graphene layer structure is a graphene monolayer.
5. A graphene substrate according to any preceding claim, wherein the metal oxide layer has a thickness of less than 4nm.
6. A graphene substrate according to any preceding claim, wherein the metal oxide layer has a thickness of at least 0.5nm, preferably at least 1nm, more preferably at least 2nm.
7. A graphene substrate according to any preceding claim, wherein the support layer has a thickness of at least 5nm, preferably at least 15nm, preferably at least 50nm.
8. An electrical device comprising a graphene substrate according to any preceding claim.
9. A method of forming a graphene substrate, the method comprising:
providing a growth substrate comprising or consisting of a support layer formed of BN, alN, gaN, siC, diamond or a combination thereof;
forming a metal oxide layer on the support layer by ALD, wherein the metal oxide layer has a thickness of less than 5nm and is selected from the group consisting of Al 2 O 3 、HfO 2 、MgO、MgAl 2 O 4 、Ta 2 O 5 、Y 2 O 3 、ZrO 2 And YSZ; and
and forming a graphene layer structure on the metal oxide layer by CVD.
10. The method of claim 9, wherein the growth substrate further comprises a wafer, preferably a sapphire wafer or a silicon wafer.
11. The method of claim 10, wherein the method further comprises etching away or separating the wafer after forming the graphene layer structure.
12. The method of any of claims 9 to 11, wherein the method further comprises forming one or more additional layers on the graphene layer structure.
13. The method of claim 12, wherein the method comprises forming an additional metal oxide layer on the graphene layer structure by ALD, wherein the additional metal oxide layer has a thickness of less than 5nm and is selected from the group consisting of Al 2 O 3 、HfO 2 、MgO、MgAl 2 O 4 、Ta 2 O 5 、Y 2 O 3 、ZrO 2 And YSZ; and
forming a further layer on the further metal oxide layer, wherein the further layer is BN, alN, gaN, siC, diamond or a combination thereof.
CN202280049432.4A 2021-07-12 2022-07-04 Graphene substrate and method of forming the same Pending CN117678054A (en)

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