CN117677938A

CN117677938A - Method and device for managing data

Info

Publication number: CN117677938A
Application number: CN202180100185.1A
Authority: CN
Inventors: 李会嵩; 王金伟; 孙亚萍
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-09-07
Filing date: 2021-09-07
Publication date: 2024-03-08
Also published as: WO2023035120A1

Abstract

A method and a device for managing data relate to the technical field of storage, can effectively prolong the service life of a storage device on the basis of not increasing extra material cost, and can improve the duration of a high-performance stage of the performance of the storage device and improve user experience. The method comprises the following steps: writing data into the memory element, wherein the memory area comprises a dynamic SLC area, and the data writing mode of any memory cell in the dynamic SLC area is an SLC mode or a non-SLC mode; when the storage area of the storage device is determined to be updated, the dynamic SLC area is divided into a static SLC area and a non-SLC area, the data writing mode of any storage unit in the static SLC area is an SLC mode, and the data writing mode of any storage unit in the non-SLC area is a non-SLC mode; or when the storage area of the storage device is determined to need to be updated, updating the dynamic SLC area into the non-SLC area. The method is used for a process of writing data to a memory device.

Description

Method and device for managing data

Technical Field

The present disclosure relates to the field of storage technologies, and in particular, to a method and an apparatus for managing data.

Background

The Solid State Disk (SSD) is a new type of memory device, mainly composed of a controller unit and a memory unit of nonvolatile media particles. The memory Cells in the granule may be classified into Single-Level Cells (SLC), multi-Level Cells (MLC), tri-Level Cells (TLC), quad-Level Cells (QLC), and the like according to the number of bit stored in the memory Cells. The higher the storage density of the grain, the worse the performance of the grain, the lower the lifetime, when the number of bits stored in the memory cell is greater.

SSD is an important component of memory devices in consumer PC and cell-phone fields, in order to compromise performance and storage density, in consumer fields, SLC mode and TLC mode are mostly adopted, and there are two modes on the storage mode: one is a static SLC mode, which can be understood as a mode with a fixed SLC capacity size and storage area; the other is dynamic SLC mode, which can be understood as a mode that does not limit its size and storage area. In the dynamic SLC mode, both SLC-mode blocks and TLC-mode blocks exist in the storage area.

In addition, in the static SLC mode, the service life of the particles is long, but the capacity of the storage area of the static SLC mode is usually small, and the static SLC area needs to occupy a medium space which is three times the capacity of the TLC mode. Although the dynamic SLC mode does not require separate division of regions and the storage region capacity of the dynamic SLC mode is greater than that of the static SLC mode, the loss of medium life when the dynamic SLC mode is used is three times that when used in TLC mode. Therefore, how to extend the lifetime of particles and compromise storage performance in the case of a combination of SLC mode and TLC mode is a technical problem that is currently in need of solution.

Disclosure of Invention

The embodiment of the application provides a method and a device for managing data, which can effectively prolong the service life of a storage device on the basis of not increasing additional material cost, and simultaneously improve the duration of a high-performance stage of the performance of the storage device and promote user experience.

In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:

in a first aspect, there is provided a method of managing data, the method being applied to a memory device, the method comprising: writing data into the memory device, wherein a storage area of the memory device comprises a dynamic single-layer cell SLC area, and the data writing mode of any storage unit in the dynamic SLC area is an SLC mode or a non-SLC mode; the SLC mode is to write 1 bit of data into the memory cell, and the non-SLC mode is to write at least 2 bits of data into the memory cell; when the storage area of the storage device is determined to be updated, the dynamic SLC area is divided into a static SLC area and a non-SLC area, wherein the data writing mode of any storage unit in the static SLC area is an SLC mode, and the data writing mode of any storage unit in the non-SLC area is a non-SLC mode; or when the storage area of the storage device is determined to be updated, updating the dynamic SLC area into a non-SLC area, wherein the data writing mode of any storage unit in the non-SLC area is a non-SLC mode.

Therefore, in the application, aiming at the problems that when the static SLC area is adopted to write data at present, the static SLC area occupies a virtual space, and when the dynamic SLC area is adopted to write data, the service life loss of the medium is large, the application can break the inherent limit of the static SLC area and the dynamic SLC area, and can adopt different strategies in different service life stages. In the early life, a dynamic SLC region can be adopted, the data writing mode of any storage unit in the dynamic region SLC region can be an SLC mode or a non-SLC mode, namely, all idle blocks can write data according to the needs in the SLC mode or the non-SLC mode, and the storage performance of the storage device can be improved. In the later period of service life, a static SLC region and a non-SLC region can be adopted, namely, fixed regions can be divided, a part of regions are used in an SLC mode, and a part of regions are used in a non-SLC mode, wherein data writing performance can be improved through writing data in the static SLC region, and writing data into idle blocks in the non-SLC mode can be considered. Therefore, the division of the storage areas under different life stages of the storage device is combined, so that the high performance in the whole life stage can be ensured, and the performance in the early life stage can be further improved.

In one possible design, determining that the memory region of the memory device needs to be updated includes: the memory area of the memory device is determined to be updated based on at least one of the write volume requirements of the memory device, the number of remaining program and erase PEs, the device write amplification value, and the user time. It can be understood that when the remaining writing amount of the memory device is smaller, or the number of times of remaining PE is smaller, or the write amplification effect of the device is poor, or the user use time is longer, it can be determined that the memory device enters the lifetime end stage, so as to partition the memory area of the memory device again, so that the partitioned memory area is suitable for the lifetime end stage, and the lifetime of the device is prolonged.

In one possible design, the dynamic SLC region includes a first pool of free blocks corresponding to the dynamic SLC region prior to beginning writing data to the memory device;

writing data to the memory device includes: when determining that data is required to be written in an SLC mode, determining a first idle block from a first idle block pool, and writing the data to the first idle block in the SLC mode; and marking the first idle block after writing the data as a first identifier, wherein the first identifier indicates that the writing mode of the first idle block after writing the data is an SLC mode. It is to be understood that in determining to write data in SLC mode, data may also be selected from and written to SLC blocks that have been written with data but are not full. In the early life of the memory device, the static SLC area and the dynamic SLC area are not distinguished, the whole area can be determined to be the dynamic SLC area, the first idle block pool is used for serving the whole area, namely the dynamic SLC area, and a user can write data in an SLC mode or a non-SLC mode according to requirements, so that the performance of the memory device can be improved.

In one possible design, the method may further include, prior to writing the data to the memory device: determining the area size ratio of a static SLC area and a dynamic SLC area in the memory device according to the device specification of the memory device; the static SLC region and the dynamic SLC region in the memory device are determined according to the region size ratio. The design considers that some memory devices do not support the division of the whole area into dynamic SLC areas in the early life, so that the static SLC area and the dynamic SLC area can be divided in the early life, and it can be understood that the dynamic SLC area can also write data in an SLC mode. Therefore, the user can write data to both the static SLC area and the dynamic SLC area in an SLC mode in the early life of the device, and the requirement that the user writes data in the SLC mode is met. And the data can be written into the dynamic SLC area in a non-SLC mode, so that the requirement of a user for writing the data in the non-SLC mode is met.

In one possible design, the static SLC region includes a second pool of free blocks and the dynamic SLC region includes a third pool of free blocks;

writing data to the memory device includes: when determining that data is required to be written in an SLC mode, determining to write data to a dynamic SLC area or write data to a static SLC area according to the area size proportion; when determining to write data to the static SLC area, determining a second idle block from a second idle block pool, writing data to the second idle block in an SLC mode, marking the second idle block after writing the data as a first mark, wherein the first mark indicates that the writing mode of the block is the SLC mode; when the data is confirmed to be written into the dynamic SLC area, a third idle block is confirmed from a third idle block pool, the data is written into the third idle block in an SLC mode, the third idle block after the data is written is marked as a first mark, and the writing mode of the first mark indication block is the SLC mode. In this design, data can be written in the SLC mode to the static SLC region or in the SLC mode to the dynamic SLC region due to the early life, and particularly when data is written in the SLC mode, the static SLC region or the dynamic SLC region is selected and can be determined according to the size ratio of the two regions. For example, when writing data in SLC mode, the determined selection mode is: 1 data is written to the static SLC area, 2 data is written to the dynamic SLC area, and 1 data is written to the static SLC area.

In one possible design, the method further comprises: when the first idle block is fully written, recording the block number of the first idle block in a list, wherein the list comprises a plurality of block numbers of blocks which are marked as a first mark and are fully written in a dynamic SLC area recorded according to time; when the number of blocks in the idle block pool corresponding to the dynamic SLC area is smaller than a first threshold value, determining the number of first block numbers to be recorded in a list, wherein the number of the first block numbers is the number of the blocks marked as a first mark and written fully; starting from the first recorded block number of the list, determining M block numbers exceeding the first block number; m is an integer greater than or equal to 1; selecting at least one source block to be moved from the blocks marked as the second mark and the blocks indicated by M block numbers in the dynamic SLC area, and moving the effective data in the at least one source block to at least one target block of an idle block pool in the dynamic SLC area in a non-SLC mode; the second flag indicates that the write mode of the block is a non-SLC mode.

Therefore, when M block numbers exceeding the number of the first block number are determined by using the list and data is moved, the block number recorded in the list at the earliest time (the data in the corresponding block can be understood as cold data) can be selected by the GC waterline, and the block number recorded in the list at the latest can fully exert the hot data filtering effect because the data is not stable, so that the data in the block number recorded in the list at the latest can be naturally disabled, invalid data movement is avoided, the device loss is reduced, and the service life of the device is prolonged.

In one possible design, determining the number of first block numbers to record in the list includes: determining a reference number of the first block number according to the total number of blocks in the memory device, the number of blocks capable of writing data in a non-SLC manner, and a first threshold; when the reference number is greater than or equal to the minimum block number of the list and less than or equal to the maximum block number of the list, determining the first block number as the reference number; when the reference number is smaller than the minimum block number of the list, determining that the first block number is the minimum block number; and when the reference number is larger than the maximum block number, determining that the first block number is the maximum block number. The list here may be a FIFO queue, following the first-in-first-out principle. Determining the number of first block numbers to record in the list may be understood as determining the queue length of the FIFO queue.

The implementation of the determination of the queue length of the FIFO queue may be:

the reference queue length of the FIFO queue may be determined from the total number of blocks in the memory device, the number of blocks that can write data in TLC mode, and the first threshold; when the length of the reference queue is greater than or equal to the minimum queue length and less than or equal to the maximum queue length of the FIFO queue, determining the queue length of the FIFO queue as the reference queue length; when the reference queue length is smaller than the minimum queue length, determining that the queue length of the FIFO queue is the minimum queue length; and when the reference queue length is larger than the maximum queue length of the FIFO queue, determining the queue length of the FIFO queue as the maximum queue length.

The minimum queue length and the maximum queue length are preset values. The minimum queue length corresponds to the minimum block number, and the maximum queue length corresponds to the maximum block number. The reference queue length corresponds to the above-mentioned reference number. The minimum queue length is used to guarantee the most basic hot data function, preventing the queue length from being calculated as a minimum value, even 0. The maximum queue length is set taking into account: the longer the queue length, which equates to a longer time interval for data to be written to and moved from, facilitates the natural invalidation of hot data for the plurality of SLC blocks at the tail of the queue, the closer the data is ejected from the queue to relatively stable cold data. However, as the length of the queue increases, the rate of natural thermal data failure may slow down, and further increases in the length of the queue may not result in a significant increase in the number of thermal data failures. I.e. the continued increase in queue length has the negative effect of increasing the cost of the queue, and therefore a maximum queue length needs to be set.

In one possible design, selecting at least one source block to be moved from among the blocks marked as the second identifier and the blocks indicated by the M block numbers in the dynamic SLC region, and moving valid data in the at least one source block to at least one destination block in the free block pool in a non-SLC manner includes: determining a first source block with the least effective data quantity in a block marked as a second mark and fully written in the dynamic SLC area and blocks indicated by M block numbers, and selecting a first target block from an idle block pool corresponding to the dynamic SLC area; moving the effective data in the first source block to a first destination block in a non-SLC mode, erasing the ineffective data in the first source block, and marking the erased first source block as an idle block in a first idle block pool; determining whether the number of idle blocks in an idle block pool corresponding to the dynamic SLC region is equal to a first threshold value; stopping data movement when the number of the idle blocks is equal to a first threshold value; when the number of the idle blocks is smaller than a first threshold value, continuing to determine a second source block with the least effective data amount in the rest blocks in the blocks marked as a second mark and written in the dynamic SLC area and the blocks indicated by M block numbers; and when the first destination block is not fully written, moving the effective data in the second source block into the first destination block in a non-SLC mode, erasing the ineffective data in the second source block, and marking the erased second source block as an idle block in the first idle block pool.

Thus, during the early life, the effective data moving process is performed on the M blocks recorded earliest, so that more free blocks can be vacated for writing more effective data. Further, the hot data filtering effect on the data in the block recorded later can be exerted, and invalid movement of the data can be avoided.

In a second aspect, there is provided a memory device comprising: the writing module is used for writing data into the memory device, and the memory area of the memory device comprises a dynamic single-layer cell SLC area, wherein the data writing mode of any memory cell in the dynamic SLC area is an SLC mode or a non-SLC mode; the SLC mode is to write 1 bit of data into the memory cell, and the non-SLC mode is to write at least 2 bits of data into the memory cell;

the block management module is used for dividing the dynamic SLC area into a static SLC area and a non-SLC area when the storage area of the storage device is required to be updated, wherein the data writing mode of any storage unit in the static SLC area is an SLC mode, and the data writing mode of any storage unit in the non-SLC area is a non-SLC mode; or the block management module is used for updating the dynamic SLC area into the non-SLC area when the storage area of the storage device is required to be updated, and the data writing mode of any storage unit in the non-SLC area is the non-SLC mode.

In one possible design, the block management module is to: the memory area of the memory device is determined to be updated based on at least one of the write volume requirements of the memory device, the number of remaining program and erase PEs, the device write amplification value, and the user time.

In one possible design, the dynamic SLC region includes a first pool of free blocks corresponding to the dynamic SLC region before the write module is used to write data to the memory device;

the block management module is specifically configured to: when determining that data is required to be written in an SLC mode, determining a first idle block from a first idle block pool, and indicating a writing module to be used for writing the data to the first idle block in the SLC mode; the writing module is used for marking the first idle block after writing data as a first identifier, and the first identifier indicates that the writing mode of the first idle block after writing data is an SLC mode.

In one possible design, the block management module is configured to, prior to the write module being configured to write data to the memory device: determining the area size ratio of a static SLC area and a dynamic SLC area in the memory device according to the device specification of the memory device; the static SLC region and the dynamic SLC region in the memory device are determined according to the region size ratio.

The block management module is used for: when determining that data is required to be written in an SLC mode, determining to write data to a dynamic SLC area or write data to a static SLC area according to the area size proportion; when determining to write data to the static SLC area, determining a second idle block from a second idle block pool, indicating a writing module to write data to the second idle block in an SLC mode, marking the second idle block after writing the data as a first mark, wherein the writing mode of the first mark indicating block is the SLC mode; when the data is confirmed to be written into the dynamic SLC area, a third idle block is confirmed from a third idle block pool, the writing module is instructed to write the data into the third idle block in an SLC mode, the third idle block after the data is written is marked as a first mark, and the writing mode of the first mark instruction block is the SLC mode.

In one possible design, the system further comprises a list management module for: when the first idle block is fully written, recording the block number of the first idle block in a list, wherein the list comprises a plurality of block numbers of blocks which are marked as a first mark and are fully written in a dynamic SLC area recorded according to time; when the number of blocks in the idle block pool corresponding to the dynamic SLC area is smaller than a first threshold value, determining the number of first block numbers to be recorded in a list, wherein the number of the first block numbers is the number of the blocks marked as a first mark and written fully; starting from the first recorded block number of the list, determining M block numbers exceeding the first block number; m is an integer greater than or equal to 1; selecting at least one source block to be moved from the blocks marked as the second mark and the blocks indicated by M block numbers in the dynamic SLC area, and moving the effective data in the at least one source block to at least one target block of an idle block pool in the dynamic SLC area in a non-SLC mode; the second flag indicates that the write mode of the block is a non-SLC mode.

In one possible design, the list management module is configured to: determining a reference number of the first block number according to the total number of blocks in the memory device, the number of blocks capable of writing data in a non-SLC manner, and a first threshold; when the reference number is greater than or equal to the minimum block number of the list and less than or equal to the maximum block number of the list, determining the first block number as the reference number; when the reference number is smaller than the minimum block number of the list, determining that the first block number is the minimum block number; and when the reference number is larger than the maximum block number, determining that the first block number is the maximum block number.

In one possible design, the list management module is configured to: determining a first source block with the least effective data quantity in a block marked as a second mark and fully written in the dynamic SLC area and blocks indicated by M block numbers, and selecting a first target block from an idle block pool corresponding to the dynamic SLC area; moving the effective data in the first source block to a first destination block in a non-SLC mode, erasing the ineffective data in the first source block, and marking the erased first source block as an idle block in a first idle block pool; determining whether the number of idle blocks in an idle block pool corresponding to the dynamic SLC region is equal to a first threshold value; stopping data movement when the number of the idle blocks is equal to a first threshold value; when the number of the idle blocks is smaller than a first threshold value, continuing to determine a second source block with the least effective data amount in the rest blocks in the blocks marked as a second mark and written in the dynamic SLC area and the blocks indicated by M block numbers; and when the first destination block is not fully written, moving the effective data in the second source block into the first destination block in a non-SLC mode, erasing the ineffective data in the second source block, and marking the erased second source block as an idle block in the first idle block pool.

In a third aspect, a memory device is provided, comprising a processor and a memory, the processor being coupled to the memory; a memory for storing a computer program or instructions; a processor for executing a computer program or instructions stored in a memory to cause the apparatus to perform the method as described in the first aspect and any one of the possible designs of the first aspect.

In a third aspect, there is provided a readable storage medium comprising a program or instructions which, when executed by a processor, performs a method as described in the first aspect and any one of the possible designs of the first aspect.

In a fourth aspect, there is provided a computer program product for, when run on a computer, causing an electronic device to perform the method as described in the first aspect and any one of the possible designs of the first aspect.

It should be appreciated that any of the above-described storage devices, computer-readable storage media, or computer program products, etc. may be applied to the corresponding methods provided above, and thus, the benefits achieved by the above-described storage devices, computer-readable storage media, or computer program products may refer to the benefits in the corresponding methods, and are not described herein.

These and other aspects of the present application will be more readily apparent from the following description.

Drawings

Fig. 1 is a schematic diagram of different storage units in an SSD according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of performing data movement using DQs in an SSD according to an embodiment of the present application;

FIG. 3A is a storage network architecture according to an embodiment of the present application;

FIG. 3B is a flowchart illustrating a method for managing data according to an embodiment of the present disclosure;

FIG. 4 is a flowchart of a method for managing data according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating a memory region division of a memory device in the early life of the memory device according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a memory region of a memory device divided into dynamic SLC regions according to an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating a memory area division in the late lifetime of a memory device according to an embodiment of the present application;

FIG. 8 is a schematic diagram illustrating the division of a memory area in the later life of a memory device according to an embodiment of the present application;

FIG. 9 is a flowchart of a method for managing data according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram illustrating a memory region division of a memory device in the early life of the memory device according to an embodiment of the present application;

FIG. 11 is a schematic diagram illustrating a memory area division at a later life of a memory device according to an embodiment of the present application;

Fig. 12 is a schematic structural diagram of a memory device according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a memory device according to an embodiment of the present application.

Detailed Description

For ease of understanding, an illustration of some of the concepts related to the embodiments of the present application is given by way of example for reference. The following is shown:

SSD: the fixed disk for short is mainly composed of a controller unit and a solid-state electronic memory chip array. For example, the solid-state electronic memory chip can be nonvolatile medium particles such as NAND Flash, and has the characteristics of high read-write speed, low power consumption, no noise, vibration resistance, low heat, small volume, large working temperature range and the like.

For solid-state electronic memory chips, they are composed of a plurality of memory cells. The solid-state electronic memory chip can be divided into SLC, MLC, TLC and QLC memory cells according to the number of stored bit in each memory cell. The solid state electronic memory chip may include a plurality of blocks (blocks), each of which may include a plurality of pages (pages), each of which may include a plurality of memory cells. Thus, blocks can be classified into SLC blocks, MLC blocks, TLC blocks, and QLC blocks of the QLC mode according to the number of bits of a memory cell.

As shown in fig. 1, the SLC can be understood as a memory cell that can store 1bit data for storing both 0 and 1 charge values. Similarly, MLC is understood to be a memory cell that can store 2 bits of data for storing four charge values, 11, 10, 01, and 00. TLC can be understood as a memory cell that can store 3bit data for storing eight charge values 111, 110, 011, 101, 100, 010, 001, and 000. QLC is understood as a memory cell that can store 4bit data for sixteen charge values (not shown in fig. 1).

In order to achieve both performance and storage density, in the consumer level field, an SLC mode and a TLC mode are often used in combination, and in the area division mode, there are two areas, i.e., a static SLC area and a dynamic SLC area.

Static SLC region: its storage capacity size and area are fixed, data can be written to the static SLC area in SLC fashion, and blocks in the static SLC area can be referred to as SLC blocks. It is also understood that the memory cells of the SLC blocks in the static SLC region are SLCs.

Dynamic SLC region: the storage capacity size and area are not limited and the capacity is greater than that of the static SLC area. Data may be written to the dynamic SLC region in an SLC manner, or data may be written to the dynamic SLC region in a non-SLC manner. If the non-SLC mode is TLC mode, both SLC blocks and TLC blocks are present in the dynamic SLC region. It is also understood that some of the memory cells of the block in the dynamic SLC region are SLC and some of the memory cells of the block may be TLC.

In the case of dividing the static SLC area, the NAND Flash has a long service life, but since each memory cell (SLC) of the SLC block stores 1bit data and each memory cell (TLC) of the TLC block stores 3 bits data, the capacity of the static SLC area needs to be three times the medium space of the capacity of the TLC area, and thus the capacity of the static SLC area is generally small.

In addition, according to the physical structure of the NAND Flash, the NAND Flash stores data through an insulating layer. When data is to be written, a voltage needs to be applied and an electric field is formed, so that electrons can enter the memory cell through the insulator, and writing of data is completed. If the data of the memory cell is to be erased, a voltage is again applied to let electrons pass through the insulating layer, so that the data leave the memory cell. Therefore, NAND Flash must delete the original data before re-writing new data. Since 1 storage unit of TLC block can store 3 bits of data, it is necessary to use different voltages for implementation in order to distinguish. Besides being able to realize 000 (TLC) =0 (SLC) and 111 (TLC) =1 (SLC) as same as SLC, there are six other data formats that must be distinguished by using other different voltages, so that different numbers of electrons enter the memory cells to realize different data expressions. Thus, TLC blocks can only achieve the purpose of storing more data per unit memory cell than SLC blocks and MLC blocks. Since eight different voltage states are required for writing data into the TLC block, applying the different voltage states, especially the relatively high voltages, requires a longer time to be achieved. Thus, in TLC blocks, the data requires longer access time and therefore transmission speed is slower. The time required for the controller unit to control programming and erasing the memory cells of a TLC block is also increasing. The physical loss of the silicon oxide of the insulator can be caused in the voltage applying process of each writing or erasing of the memory cell, and the TLC block adopts different voltage states and has more storage capacity, so that the number of times of breakdown of the insulating layer is more than that of other mediums, and the loss process of the insulating layer is accelerated. Therefore, in the dynamic SLC region, i.e., in the case where the NAND Flash includes a TLC block, the dynamic SLC has three times as much lifetime loss of the NAND Flash as the TLC.

Headspace (over provisioning, OP): when a block of SSD is full, additional space is needed to accept the newly written data before the garbage collection (Garbage Collection, GC) waterline is started, this additional space being referred to as a headspace. The size of the OP can be understood as the value of the actual capacity of the SSD minus the available capacity of the user. In short, the OP can improve wear leveling (wear-leveling) of the SSD, reduce write amplification, and improve the performance of SSD random writing, thereby improving the service life of the SSD.

GC waterline: the purpose is space reuse, i.e. writing valid data by means of the recovered space size.

Device write amplification value: it can be understood as the amount of data eventually written to the NAND Flash/the amount of data written by the Host (Host). For example, when a Host is to write 4KB of data to a data block, if there is no space available in the data block, but invalid data is present in the data block that can be erased, the controller unit may move all of the data in the data block to the cache, then erase the data of the data block, and update the contents of the entire data block in the cache, i.e., write the 4KB of data. After the update is completed, the controller unit moves the content of the updated whole data block back to the data block, and the write amplification caused by the whole operation can be understood as follows: host only needs to write 4KB of data, but brings about a write operation of the whole data block (assuming 1024 KB), and the device write amplification value is equal to 1024/4=256 times.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Wherein, in the description of the embodiments of the present application, "/" means or is meant unless otherwise indicated, for example, a/B may represent a or B; "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, in the description of the embodiments of the present application, "plurality" means two or more than two.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

The present application may be applied to a process of writing data to an SSD.

Aiming at the problems that the static SLC area occupies a virtual space when the data is written in the static SLC area at present and the service life loss of the medium is larger when the data is written in the dynamic SLC area, the method and the device can break the inherent limit of the static SLC area and the dynamic SLC area and can adopt different strategies in different service life stages. In the early life, a dynamic SLC region can be adopted, the data writing mode of any storage unit in the dynamic region SLC region can be an SLC mode or a non-SLC mode, namely, all idle blocks can write data according to the needs in the SLC mode or the non-SLC mode, and the storage performance of the storage device can be improved. In the later stage of life, a static SLC region and a non-SLC region can be adopted, namely, fixed regions can be divided, a part of regions are used in an SLC mode, and a part of regions are used in a non-SLC mode, wherein data writing performance can be improved through writing data in the static SLC region. Therefore, the division of the storage areas under different life stages of the storage device is combined, so that the high performance in the whole life stage can be ensured, and the performance in the early life stage can be further improved.

In addition, in order to improve the lifetime of a memory device, such as the NAND Flash described above, the academic world has currently proposed an N-bin scheme, mainly oriented to an enterprise-level SSD, which may be applied to a memory area where data is written in TLC or a memory area where data is written in SLC. N-bins may be understood as a plurality of gears. This scheme sets a Delay Queue (DQ) and if a block is full, the block may be closed, e.g., labeled "closed", and the closed blocks are queued into the head of the DQ, as shown in fig. 2, with invalid data and valid data in each closed block. When the sum of the failed pages of all blocks in the DQ exceeds a set fixed threshold (which is less than the OP of the device), which may include multiple pages, the multiple blocks at the tail of the DQ queue are drained and are organized into different bins, e.g., bin 0 (0 th), bin 1 (1 st), …, bin N (N-th) in fig. 2, according to the amount of valid data for the drained multiple blocks. Different bins correspond to different effective data size ranges, i.e., each bin may have multiple expelled blocks, with the effective data size range of bin 0 being the largest, the highest range, the effective data size range of bin N being the smallest, and the lowest range. When the GC waterline is started, the top block in the lowest gear bin can be selected for recycling. Reclamation is understood here as moving valid data in a block into a free block and erasing invalid data in a block, the erased block being marked as a "free block". The bin of the lowest gear may be, for example, N gear in fig. 2. The head-most block may be understood as the block that enters the DQ earliest in time, e.g., block 20 in fig. 2 is the block selected by the GC waterline.

According to the scheme, the plurality of blocks discharged from the tail of the DQ are archived and data are recovered, the newly written data from the head of the DQ are considered, namely, the plurality of blocks from the head of the DQ contain a large amount of data which can be invalid in a short period, so that hot data filtering can be performed, further, the moving of the part of invalid data in the short period is reduced, the loss of a storage device is reduced, and the service life of the storage device is prolonged.

However, at present, the OP in the consumer storage device is small, the dynamic SLC occupies a virtual space due to the blocks in the SLC mode, and the queue length of the DQ is set based on the OP. On the one hand, in the case where the OP is small, if the queue length of the DQ is too short, the above-mentioned hot data filtering effect may be poor, and a case may occur in which data is not yet stabilized and is moved into an idle block. On the other hand, if it is determined whether data reclamation is necessary based on the sum of the dead pages, excessive SLC blocks are likely to be accumulated in DQ, so that GC is frequent and the data transfer amount is increased.

In this regard, in the early life of the storage device, a list may be added to the dynamic SLC area, where the list is used to record the identifiers of the blocks according to the time sequence for the full blocks, and the number of identifiers to be recorded in the list is determined according to the optimal matching of the number of SLC blocks and the number of non-SLC blocks in the dynamic SLC area, and the valid data in the blocks corresponding to the identifiers of the N blocks exceeding the number of identifiers recorded earliest according to the number of identifiers is recovered, so as to vacate a sufficient number of idle blocks, and write more data. And the thermal data filtering effect of the dynamic SLC area can be fully exerted for the later recorded blocks, the frequency of GC is reduced, the loss of the memory device is reduced, and the service life of the device is prolonged.

The present application may be applied to storage network architectures. As shown in fig. 3A, the storage network architecture may include at least one Host (Host) and a storage device. Host may be used for read or write access to the memory device. The storage device may be, for example, an SSD. Taking an SSD as an example, the SSD includes a controller and a storage area, and the storage area may include a plurality of blocks, each of which may include a plurality of pages, and in which data may be written in at least one of a SLC method, a TLC method, an MLC method, a QLC method, or the like.

The embodiments of the present application are described below with application to a storage network architecture of the present application.

An embodiment of the present application provides a method for managing data, as shown in fig. 3B, including:

301. the memory device writes data to the memory device, wherein the memory area of the memory device comprises a dynamic SLC area, and the data writing mode of any memory cell in the dynamic SLC area is an SLC mode or a non-SLC mode; SLC mode is to write 1 bit of data to a memory cell, and non-SLC mode is to write at least 2 bits of data to a memory cell. Then, step 302 or 303 is performed.

It can be appreciated that there are two ways of memory cells in the dynamic SLC region during the early life of the memory device: there are two ways of writing data, SLC and non-SLC. Accordingly, both SLC blocks and non-SLC blocks may be present in the dynamic SLC region.

For example, when the non-SLC is TLC, there may be two ways of writing data to the dynamic SLC region: SLC mode and TLC mode, respectively, the dynamic SLC region has both SLC blocks and TLC blocks.

302. When the memory device determines that the memory area of the memory device needs to be updated, the dynamic SLC area is divided into a static SLC area and a non-SLC area, wherein the data writing mode of any memory cell in the static SLC area is an SLC mode, and the data writing mode of any memory cell in the non-SLC area is a non-SLC mode.

The storage device may determine that there may be a plurality of conditions for updating the storage area, and when at least one of the conditions is satisfied, it may be considered that the storage area needs to be updated.

For example, the conditions may include the write volume requirements of the memory device, the number of remaining program and erase (Programmable and Erasable, PE) times, the device write amplification value, and the user time of use, among others. The specific manner of determination will be described later.

It is to be appreciated that the memory device can be considered to enter the end of life when it is determined that the memory region of the memory device needs to be updated. At this time, the dynamic SLC region can be divided into two parts: static SLC regions and non-SLC regions. Wherein the static SLC region can write data in a SLC manner, i.e., there are a plurality of SLC blocks; the non-SLC region may write data in a non-SLC manner, i.e., there are multiple non-SLC blocks. For example, when the non-SLC region is a TLC region, the TLC region is written with data by TLC, and a plurality of TLC blocks exist.

In this way, the present application may employ different storage strategies at different life stages. In the early life, a dynamic SLC region can be adopted, the data writing mode of any storage unit in the dynamic region SLC region can be an SLC mode or a non-SLC mode, namely, all idle blocks can write data according to the needs in the SLC mode or the non-SLC mode, and the storage performance of the storage device can be improved. In the later period of service life, a static SLC region and a non-SLC region can be adopted, namely, fixed regions can be divided, a part of regions are used in an SLC mode, and a part of regions are used in a non-SLC mode, wherein data writing performance can be improved through writing data in the static SLC region, and writing data into idle blocks in the non-SLC mode can be considered. Therefore, the division of the storage areas under different life stages of the storage device is combined, so that the high performance in the whole life stage can be ensured, and the performance in the early life stage can be further improved.

303. When the memory device determines that the memory area of the memory device needs to be updated, the dynamic SLC area is updated to be a non-SLC area, and the data writing mode of any memory cell in the non-SLC area is a non-SLC mode.

The implementation of determining that the storage area of the storage device needs to be updated in step 303 may refer to the description of step 302.

In some embodiments, for devices that do not support division of the full area of the memory device into dynamic SLC regions, the memory device may be divided into static SLC regions and dynamic SLC regions early in the life of the device. When it is determined that the memory device enters the end of life, the dynamic SLC region is updated to a non-SLC region. I.e., the memory device enters the late-life phase, the memory region includes both static SLC regions and non-SLC regions, the benefits set forth in step 302 may be achieved as well.

The following implementation for the cases of step 301 and step 302 may refer to embodiment 1, and for the implementation for the cases of step 301 and step 303 may refer to embodiment 2. Of course, the present application is not limited to the methods set forth in these two examples.

Example 1

The present application provides a method for managing data, as shown in fig. 4, the method includes:

401. the memory device writes data to the memory device, and the memory region of the memory device is a dynamic SLC region.

The present application describes dynamic SLC regions as writing data in both SLC and TLC modes. It is understood that the TLC method may be replaced by MLC method, QLC method, or the like.

In some embodiments, the full area of the memory device may be divided into dynamic SLC areas, as shown in fig. 5, during the early life of the memory device, where the data writing mode of any memory cell in the dynamic SLC area is SLC mode or non-SLC mode. SLC mode is understood to mean that 1bit of data can be written to a memory cell, and non-SLC mode is understood to mean that at least 2 bits of data can be written to a memory cell. By way of example, the non-SLC mode may include an MLC mode, a TLC mode, and a QLC mode, wherein the MLC mode represents writing 2 bits of data to a memory cell at a time; the TLC mode indicates writing 3 bits of data to the memory cell each time; the QLC scheme indicates that 4 bits of data are written to a memory cell at a time.

I.e., early life, the memory device does not distinguish between dynamic and static SLC regions, and all blocks of the full region can be used in SLC or TLC mode. Of course, once a block is determined to be used in SLC mode, the block can only write data in SLC mode. Likewise, once it is determined that a block is used in TLC, the block can only write data in TLC.

In other words, a dynamic SLC region may include blocks that write data in SLC fashion, which may be understood as SLC blocks in the present application, and also include blocks that write data in TLC fashion, which may be understood as TLC blocks in the present application.

When writing data to a dynamic SLC region in an SLC manner or a TLC manner, as shown in fig. 6, the entire region of the memory device can also be understood to include an SLC region and a TLC region, but the SLC region and the TLC region are not two separate fixed regions, but there are two types of memory cells, that is, SLC and TLC. The user can write data in SLC or TLC as desired.

In addition, when the full area is the dynamic SLC area, it may be understood that the dynamic SLC area includes a fixed capacity first free block pool, an SLC area, and a TLC area, where the first free block pool is used to serve the SLC area and the TLC area at the same time, that is, the free blocks in the first free block pool may be acquired to write data in the SLC manner or write data in the TLC manner.

In some embodiments, when the controller writes data to the dynamic SLC area, if it is determined that the data needs to be written in the SLC mode, the controller may determine a first free block from the first free block pool, write the data to the first free block in the SLC mode, mark the first free block after writing the data as a first identifier, where the first identifier indicates that the writing mode of the first free block after writing the data is the SLC mode. It is also understood to be labeled as SLC blocks in the dynamic SLC region.

In addition, when the controller writes data to the dynamic SLC region, if it is determined that the data is to be written in the SLC mode, the controller may also determine one SLC block from the unwritten SLC blocks and write the data to the SLC block.

When the controller writes data to the dynamic SLC area, if it is determined that the data needs to be written in a TLC mode, the controller can determine a free block from a free block pool, write the data in a TLC mode, or determine a TLC block from the unwritten TLC blocks, and write the data to the TLC block.

402. The memory device performs data reclamation for the dynamic SLC region.

In order to be able to write more data in the dynamic SLC area, data reclamation can be performed for the dynamic SLC area.

In some embodiments, when the controller determines that the first free block is full, the block number of the first free block may be recorded in a list including a plurality of block numbers of the first identified and full blocks marked for the dynamic SLC region recorded chronologically. When the controller determines that the number of blocks in the free block pool corresponding to the dynamic SLC area is smaller than the first threshold, the number of free blocks in the free block pool is considered to be insufficient, and the GC waterline needs to be started. At this time, the controller may determine the number of first block numbers to be recorded in the list, where the number of first block numbers is the number of block numbers marked as the first identifier and written as full, that is, determine the block number capacity of the list.

Starting from the first recorded block number of the list, M block numbers exceeding the first block number are determined, M being an integer greater than or equal to 1. And selecting at least one source block to be moved from the blocks marked as the second mark and the blocks indicated by the M block numbers in the dynamic SLC area, or selecting at least one source block to be moved from the blocks written with data in a non-SLC mode and the blocks indicated by the M block numbers in the dynamic SLC area, and moving the effective data in the at least one source block to at least one destination block in an idle block pool in the dynamic SLC area in the non-SLC mode. The second flag indicates that the write mode of the block is a non-SLC mode. Here, GC selection is performed on the valid data of the block fully written in the dynamic SLC area in the non-SLC mode and the blocks indicated by the M block numbers, the valid data in the selected block are sorted into the free blocks, and the invalid data in the selected block are erased, so that the free blocks are added into the free block pool.

The M block numbers exceeding the first block number are determined from the first recorded block number in the list, and the fact that the data in the block corresponding to the block number recorded later is not stable is considered, so that thermal data filtering is possibly caused, namely invalid data in the block is naturally invalid and erased, GC recovery is not needed, invalid moving is avoided, and the thermal data filtering effect is fully exerted.

Wherein the number of first block numbers to be recorded in the list can be determined by an optimal ratio of the number of blocks in the dynamic SLC area where data can be written in SLC mode and the number of blocks in the non-SLC mode.

For example, the controller may determine the reference number of the first block number based on the total number of blocks in the memory device, the number of blocks capable of writing data in a non-SLC manner, and the first threshold; when the reference number is greater than or equal to the minimum block number and less than or equal to the maximum block number of the list, determining the first block number as the reference number; when the reference number is smaller than the minimum block number of the list, determining that the first block number in the list is the minimum block number; and when the reference number is larger than the maximum block number of the list, determining that the first block number is the maximum block number.

At least one source block to be moved is selected from the blocks marked as the second identifier and the blocks indicated by the M block numbers in the dynamic SLC area, and effective data in the at least one source block is moved to at least one destination block of the free block pool in the dynamic SLC area in a non-SLC manner.

Among them, greedy GC can be understood as: and selecting effective data in at least one block with the least effective data amount from the blocks marked as the second mark and the blocks indicated by the M block numbers in the dynamic SLC area for moving, moving the effective data block to an idle block in a first idle block pool, and erasing invalid data in the selected block.

A dual greedy GC can be understood as: and determining the effective data duty ratio (effective data/block capacity in the blocks) of the blocks marked as the second mark and the blocks indicated by the M block numbers in the dynamic SLC area, selecting the effective data of the block which is written full earliest in the blocks within a certain effective data duty ratio range, moving the effective data block to the idle block in the first idle block pool, and erasing the ineffective data in the selected block.

When the GC selection policy is greedy GC, the implementation manner of selecting at least one source block to be moved from the blocks marked as the second identifier and the blocks indicated by the M block numbers in the dynamic SLC area, and moving the valid data in the at least one source block to at least one destination block in the free block pool in a non-SLC manner may be as follows:

determining a first source block with the least effective data quantity in a block marked as a second mark and fully written in the dynamic SLC area and blocks indicated by M block numbers, and selecting a first target block from an idle block pool corresponding to the dynamic SLC area;

Moving the effective data in the first source block to a first destination block in a non-SLC mode, erasing the ineffective data in the first source block, and marking the erased first source block as an idle block in a first idle block pool;

determining whether the number of idle blocks in an idle block pool corresponding to the dynamic SLC region is equal to a first threshold value;

stopping data movement when the number of the idle blocks is equal to a first threshold value;

when the number of the idle blocks is smaller than a first threshold value, continuing to determine a second source block with the least effective data amount in the rest blocks in the blocks marked as a second mark and written in the dynamic SLC area and the blocks indicated by M block numbers;

and when the first destination block is not fully written, moving the effective data in the second source block into the first destination block in a non-SLC mode, erasing the ineffective data in the second source block, and marking the erased second source block as an idle block in the first idle block pool. Until the number of free blocks in the first free block pool reaches a first threshold.

To further illustrate the data reclamation process, in the method of recording block identifications according to a list as described above, the list may be a software implemented FIFO queue that follows a first-in-first-out principle for queuing a plurality of block identifications that are fully written in SLC fashion. It will be appreciated that the FIFO queue may be implemented in hardware, and the FIFO queue may be a queue that queues a plurality of blocks that are written full in SLC mode, or may be a queue that queues a plurality of blocks that are written full in SLC mode, which is not limited in this application.

For example, when the non-SLC mode is TLC mode, the controller may add the full block to the tail of the FIFO queue if the FIFO queue is a queue of blocks that are full in SLC mode when the controller determines that the first free block is full. Then, each time the controller determines a full block, it can check whether the number of free blocks in the next first free block pool is less than a first threshold. And if the number of the blocks in the first free block pool is determined to be smaller than a first threshold value, determining that the GC waterline needs to be started. At this point, the queue length of the FIFO queue, i.e., the number of SLC blocks to be queued into the FIFO queue, may be determined first. Then, starting from the head of the FIFO queue, M SLC blocks are determined that exceed the length of the queue. For example, the M SLC blocks in FIG. 6 are 1. And selecting at least one source block which is required to be moved from the TLC blocks in the dynamic SLC area and M SLC blocks (GC alternative area) according to a GC selection strategy, wherein the source block can be an SLC block or a TLC block. The valid data in the at least one source block is moved to the at least one destination block of the first free block pool by TLC. The destination block may be understood as a free block in the first free block pool. After the free block is written with data in TCL mode, a TLC block is obtained. In addition, invalid data in the selected source block is required to be erased, and the erased source block is marked as a free block and is classified into a first free block pool.

The GC block selection policy may select M blocks with the smallest amount of valid data according to the order of the valid data amount from less to more, and perform valid data movement.

The above-mentioned TLC blocks in the dynamic SLC region and at least one source block to be moved from the M SLC blocks according to a GC selection policy, and in an implementation manner of moving the valid data in the at least one source block to at least one destination block in the first free block pool in a TLC manner, the GC selection policy may be a greedy GC, a double greedy GC, or other manners, which is not limited in this application.

Among them, greedy GC can be understood as: and selecting effective data in at least one block with the least effective data amount from TLC blocks and M SLC blocks in the dynamic SLC area for moving, namely moving the effective data block to an idle block in a first idle block pool, and erasing invalid data in the selected block.

A dual greedy GC can be understood as: the method comprises the steps of determining the effective data duty ratio (effective data/block capacity in blocks) of TLC blocks and M SLC blocks in a dynamic SLC area, selecting effective data of the block which is fully written earliest in the blocks within a certain effective data duty ratio range, moving the effective data block to an idle block in a first idle block pool, and erasing invalid data in the selected block.

When the GC selection policy is greedy GC, selecting at least one source block to be moved according to the GC selection policy from the TLC blocks and the M SLC blocks in the dynamic SLC region, and moving the valid data in the at least one source block to at least one destination block in the free block pool in the TLC manner may be understood as:

determining a block which writes data in a TLC mode in a dynamic SLC area and a first source block with the least effective data quantity in M SLC blocks, and selecting a first destination block from a free block pool corresponding to the dynamic SLC area;

moving the effective data in the first source block to the first destination block in a TLC mode, erasing the ineffective data in the first source block, and marking the erased first source block as an idle block in a first idle block pool;

determining whether the number of free blocks in the first pool of free blocks is equal to a first threshold;

when the number of the idle blocks is smaller than a first threshold value, continuing to determine a block for writing data in a TLC mode in the dynamic SLC area and a second source block with the least effective data amount in the rest blocks in the M SLC blocks;

and when the first destination block is not fully written, moving the effective data in the second source block into the first destination block in a TLC mode, erasing the ineffective data in the second source block, marking the erased second source block as an idle block in a first idle block pool until the number of the idle blocks in the first idle block pool reaches a first threshold value.

The determination of the queue length of the FIFO queue can be understood as:

the controller may determine a reference queue length of the FIFO queue based on a total number of blocks in the storage device, a number of blocks capable of writing data in a TLC manner, and a first threshold; when the length of the reference queue is greater than or equal to the minimum queue length and less than or equal to the maximum queue length of the FIFO queue, determining the queue length of the FIFO queue as the reference queue length; when the reference queue length is smaller than the minimum queue length, determining that the queue length of the FIFO queue is the minimum queue length; and when the reference queue length is larger than the maximum queue length of the FIFO queue, determining the queue length of the FIFO queue as the maximum queue length.

Illustratively, the minimum queue length and the maximum queue length are preset values. The minimum queue length corresponds to the minimum block number, and the maximum queue length corresponds to the maximum block number. The reference queue length corresponds to the above-mentioned reference number. Wherein:

the minimum queue length is used to guarantee the most basic hot data function, preventing the queue length from being calculated as a minimum value, even 0. For example, assuming a queue length of 1 SLC block guarantees that 20% of the data has failed in dequeuing, while the negative impact of a queue length of 1 SLC block is negligible, so a minimum queue length can be set, preventing the queue length from returning to 0.

The maximum queue length is set taking into account: the longer the queue length, which equates to a longer time interval for data to be written to and moved from, facilitates the natural invalidation of hot data for the plurality of SLC blocks at the tail of the queue, the closer the data is ejected from the queue to relatively stable cold data. However, as the length of the queue increases, the rate of natural thermal data failure may slow down, and further increases in the length of the queue may not result in a significant increase in the number of thermal data failures. I.e. the continued increase in queue length has the negative effect of increasing the cost of the queue, and therefore a maximum queue length needs to be set. For example, a queue length of 1 SLC block may invalidate 10% of the data; 18% of the data may be invalidated for a queue length of 2 SLC blocks. 40% of the data may be invalidated for a queue length of 5 SLC blocks and 43% of the data may be invalidated for a queue length of 6 SLC blocks. A queue length of 16 SLC blocks may invalidate 43.5% of the data. It can be seen that from 6 to 16 does not significantly increase the effect of data failure, but increases the maintenance cost of a 10 length queue, so the maximum queue length can be set to 6 SLC blocks.

The reference queue length may be determined by: it will be appreciated that for the dynamic SLC region, the number of SLC blocks + the number of TLC blocks + the number of free blocks = the total number of blocks. Thus, when the number of free blocks in the free block pool is maintained constant, i.e., the first threshold, the number of TLC blocks is smaller if the number of SLC blocks is greater, the longer the queue length of the FIFO queue. Queue length is determined primarily taking into account the balance of increasing the positive benefit of the SLC region and decreasing the negative benefit of the TLC region. The positive benefit is understood to be that the larger the SLC area is, the longer the queue length of the FIFO queue is, and the better the filtering effect of the hot data is. Negative benefit is understood to be that the smaller the capacity of the TLC zone, the greater the data movement pressure, requiring multiple data movements to free up more free blocks for writing data in TLC mode.

Assuming that each SLC block can store y Byte data, each TLC block can store 3y Byte data, the total data amount is data_all (including the data amount stored in the SLC block and the data amount stored in the TLC), the total block number of the dynamic SLC region is num_blk, and the TLC optimal additional space ratio is op_tlc (the number of redundant blocks allocated to the TLC region/the number of blocks actually required for the TLC region). If all Data is stored in the TLC area, the optimal number of blocks needed in the TLC area is data_all/3y (1+op_tlc), and the reference queue length of the FIFO available for the SLC area is: num_blk-TLC requires the optimal number of blocks-GC watermark value (first threshold).

After determining the reference queue length, the reference queue length may be compared to the minimum queue length and the maximum queue length to determine the queue length of the FIFO queue.

For example, there are 20 blocks in the current dynamic SLC region, the first threshold is 2 SLC blocks, the dynamic SLC region stores 120K data in total, wherein the storage mode of 80K data is TLC mode, the storage mode of 40K data is SLC mode, each SLC block can store 4K data, each TLC block can store 12K data, and when the optimal additional space ratio of TLC is 10%, the TLC region needs to: 120/12 x 1.1=11 blocks, then there may be 20-11-2=7 blocks available for SLC, 7 is greater than the preset minimum queue length 1 and less than the preset maximum queue length 8, so the optimal length is 7 SLC blocks at this time, but there are 40/4=10 SLC blocks in the current FIFO queue, and therefore the first 3 SLC blocks need to be drained.

403. The memory device determines that a memory area of the memory device needs to be updated.

When the controller determines that the storage of the memory device needs to be updated, it means that the memory device enters the end of life.

In some embodiments, the controller may determine that the storage area of the storage device needs to be updated based on at least one of a write volume requirement of the storage device, a number of PEs remaining, a device write amplification value, and a user use time.

Illustratively, determining that the storage area of the storage device needs to be updated with the writing volume requirement of the full life cycle of the storage device may be, for example: the write-quantity requirement of the memory device is 70TB, and when the controller determines that 30TB has been written, it is determined that the memory device enters the end of life.

The determination of the memory area of the memory device to be updated by the remaining PE number of the memory device may be, for example: the total number of PEs for the memory device may be 3000, and when the memory device has performed 2000 PEs, it may be determined that the memory device enters the end of life.

The determining of the memory area of the memory device according to the device write amplification value, the number of remaining PEs, the minimum writing amount requirement in the lifetime and the current written data amount of the memory device may be, for example: the period of life is the period of life when the storage device (the number of remaining PEs: the storage device capacity/the device write amplification value) > (the minimum write amount requirement in the lifetime of the storage device-the current data amount written by the storage device), and the period of life is determined when the storage device (the number of remaining PEs: the storage device capacity/the device write amplification value) < (the minimum write amount requirement in the lifetime of the storage device-the current data amount written by the storage device).

Taking the use time of the user as an example, the determination that the storage area of the storage device needs to be updated may be, for example: assuming that the memory device has been used for 2 years, when entering year 3, it is determined that the memory device enters the end of life.

404. The memory device divides the dynamic SLC region into a static SLC region and a non-SLC region.

As shown in fig. 7, assuming that the blocks of dynamic SLC regions are identified as 1-300, the blocks of block identifications 1-50 may be divided into static SLC regions, and the blocks of block identifications 51-300 may be divided into TLC regions. I.e. the static SLC region has a region division independent of the TLC region, blocks are not used across regions, blocks in the static SLC region can only be used in SLC mode, blocks in the TLC region can only be used in TLC mode.

As shown in fig. 8, the partitioned static SLC region further includes a second free block pool for writing data to free blocks in SLC manner, and the blocks after writing data are marked with a first identifier, i.e., SLC blocks.

The divided TLC area further includes a third free block pool for writing data to free blocks in a TLC manner, the blocks after writing data being marked as second identifications, i.e. TLC blocks.

405. The memory device writes data to the static SLC region in an SLC manner and writes data to the non-SLC region in a non-SLC manner.

In some embodiments, when writing data to the static SLC region in SLC mode, the controller may obtain one free block from the second free block pool, write in SLC mode, and obtain one SLC block after writing, where the number of free blocks in the second free block pool is reduced by 1.

It should be appreciated that the static SLC region may also be managed in a FIFO queue with reference to step 402, but unlike step 402, the queue length in step 404 is less than the queue length in step 402 when FIFO queuing SLC blocks that are full of the static SLC region. Assuming that the first S SLC blocks of the queue head are selected from the FIFO queue corresponding to the static SLC region, S is an integer greater than or equal to 1, when the 1 st SLC block of the first S SLC blocks is selected according to the first GC policy, valid data in the 1 st SLC block may be moved to a destination block in the second free block pool, invalid data in the 1 st SLC block may be erased, and the erased block may be marked as a block in the second free block pool.

Unlike the implementation of step 402, the effective data recovery for the TLC area, i.e., the GC blocking policy for the TLC area, may be a greedy GC or a dual greedy GC or other policy, which is not limited in this application.

Wherein, greedy GC in step 405 can be understood as: and selecting the effective data in at least one TLC block with the least effective data amount from all TLC blocks in the TLC area for moving, namely moving the effective data block to an idle block in a third idle block pool corresponding to the TLC area, and erasing the ineffective data in the selected TLC block.

The double greedy GC in step 405 can be understood as: determining the effective data ratio (effective data/TLC block capacity) of each TLC block in the TLC area, selecting the effective data in the earliest full TLC block in the TLC blocks within a certain effective data ratio range, moving the effective data block to the idle block in the third idle block pool corresponding to the TLC area, and erasing the invalid data in the selected TLC block.

In this way, all the idle blocks can write data according to the requirement in an SLC mode or a non-SLC mode in the early life of the memory device, and the memory performance of the memory device can be improved. In the later life of the memory device, the data writing performance can be improved by writing data in the static SLC area, and the writing of data into the idle block in a non-static SLC mode can be considered. The division of the storage areas under different life stages of the storage device is combined, so that the high performance of the storage device in the whole life stage can be ensured, and the performance in the early life stage can be further improved.

Example 2

The present application provides a method for managing data, as shown in fig. 9, the method includes:

901. the memory device writes data to the memory device, and the memory region of the memory device is a static SLC region and a dynamic SLC region.

For some memory devices, the dynamic SLC region is not supported by the full region in the early life, so the memory region of the memory device can be divided into two independent regions in the early life: a static SLC region and a dynamic SLC region. As shown in fig. 10, the region division diagram is shown when the dynamic SLC region includes SLC-mode written blocks and TLC-mode written blocks.

The manner of determining the region sizes of the static SLC region and the dynamic non-SLC region may be:

the controller determines the area size ratio of a static SLC area and a dynamic SLC area in the memory device according to the device specification of the memory device;

the controller determines a static SLC region and a dynamic SLC region in the memory device based on the region size ratio. For example, a total capacity of 300 blocks of the memory area may be divided into static SLC areas for blocks numbered 1-50 and dynamic SLC areas for blocks numbered 51-300.

Wherein the region size ratio of the static SLC region and the dynamic SLC region may be determined according to a capacity specification of the memory device. For example, for a 128G memory device, the ratio may be 1:31, where 4G is the size of the static SLC region and 124G is the size of the dynamic SLC region. The number of SLC blocks of the static SLC region and the number of blocks of the dynamic SLC region that are required can then be determined based on the storage capacity of each SLC block and the storage capacity of each TLC block. And then, block numbers corresponding to the number of blocks in the static SLC area and block numbers corresponding to the number of blocks in the dynamic SLC area can be determined, thereby dividing the full area into the static SLC area and the dynamic TLC area.

902. The memory device performs data reclamation for the static SLC region and the dynamic SLC region, respectively.

In some embodiments, after determining the area size ratio of the static SLC area and the dynamic SLC area, assuming that the writing manner of the memory cells in the dynamic SLC area is SLC or TLC, if the user determines to write data in the SLC manner, the controller may cross-access the static SLC area and the dynamic SLC area according to the ratio. For example, the ratio is 1:2, and the corresponding cross access mode under the ratio can be: access to 1 static SLC region, access to 2 dynamic SLC region, access to 1 static SLC region.

It will be appreciated that the static SLC region includes a second pool of free blocks for SLC mode writing and the dynamic SLC region includes a third pool of free blocks for SLC mode and non-SLC mode writing.

For the static SLC region, the FIFO queue and GC policy may be used to recover the valid data of the selected fully written SLC blocks in a manner similar to that in step 402, and the recovered free blocks may be marked as free blocks in the static SLC region.

For the dynamic SLC area, for example, when writing in the SLC or TLC mode, the FIFO queue and GC policy may be used to recover the valid data of the selected full block, and the recovered idle block may be marked as the idle block in the dynamic SLC area in a similar manner as in step 402.

903. The memory device determines that a memory area of the memory device needs to be updated.

An implementation of this step may be seen in step 403.

904. The memory device updates the dynamic SLC region to a non-SLC region.

For example, the non-SLC region may be a TLC region, then the updated storage region includes a static SLC region and a TLC region as shown in fig. 11.

905. The memory device continues to write data to the static SLC region in SLC mode and to write data to the non-SLC region in non-SLC mode.

For example, in the process of writing data to the static SLC area in the SLC mode, the FIFO queue and the GC policy may be continuously used to recover the valid data of the selected fully written SLC block, and the recovered idle block may be marked as an idle block in the static SLC area.

When the non-SLC area is a TLC area, the TLC area also comprises a free block pool capable of writing data in a TLC mode, the greedy GC, the double greedy GC or other GC block selection strategies can be adopted, the effective data of the selected full TLC blocks can be recovered, and the recovered free blocks can be marked as free blocks in the TLC area.

In this way, in the early life of the memory device, data can be written to the blocks in the static SLC area or the dynamic SLC area according to the SLC mode as required, and data can be written to the blocks in the dynamic SLC area in a non-SLC mode so as to write data as much as possible, thereby improving the memory performance of the memory device. In the later life of the memory device, data can be written into the static SLC area in an SLC mode, so that the data writing performance can be improved, and data can be written into the non-SLC area in a non-SLC mode. The division of the storage areas under different life stages of the storage device is combined, so that the high performance of the storage device in the whole life stage can be ensured, and the performance in the early life stage can be further improved.

It will be appreciated that in order to achieve the above-described functionality, the electronic device comprises corresponding hardware and/or software modules that perform the respective functionality. The steps of an algorithm for each example described in connection with the embodiments disclosed herein may be embodied in hardware or a combination of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Those skilled in the art may implement the described functionality using different approaches for each particular application in conjunction with the embodiments, but such implementation is not to be considered as outside the scope of this application.

The present embodiment may divide the functional modules of the electronic device according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated modules described above may be implemented in hardware. It should be noted that, in this embodiment, the division of the modules is schematic, only one logic function is divided, and another division manner may be implemented in actual implementation.

In the case of dividing the respective functional modules with the respective functions, fig. 12 shows a schematic diagram of one possible composition of the memory device 120 involved in the above-described embodiment, and as shown in fig. 12, the memory device 120 includes a controller 1201 and a memory area 1202. The controller 1201 may include a write module, a Block (BLK) management module, a GC module, and a FIFO queue maintenance module, among others. The writing module, the BLK management module, the GC module, and the FIFO queue maintenance module may all be implemented in software, and the FIFO queue maintenance module may also be implemented in hardware.

The BLK management module is used for managing the idle blocks, dividing the idle block resources into a write module and a GC module, and determining whether the write data mode of the allocated blocks is an SLC mode or a non-SLC mode according to the current service life stage of the storage device and the use mode required by a user;

and the writing module can be used for being responsible for writing the user data. For example, the BLK management module may be applied for free block resources for writing user data, and may interact with the FIFO queue maintenance module, so that the writing module determines whether a full block enters the end of the FIFO queue;

The GC module is used for starting a GC recycling process when the number of the existing idle blocks in the storage device is lower than a set GC starting waterline (such as the first threshold), and selecting a source block and a destination block according to a GC block selection strategy to carry out effective data movement;

the FIFO queue maintenance module can be used for maintaining the FIFO queue, determining the queue length of the FIFO queue according to the state in the storage device, and discharging the blocks exceeding the FIFO queue length from the head of the queue, so that the non-discharged blocks are not selected by the GC module, and the hot data filtering effect can be exerted.

Applying the method of managing data of the present application, in some embodiments,

the BLK management module may be configured to assign a block number of a block of data to be written to the write module when it is determined that the data writing operation is to be performed, so that the write module may be configured to write the data to the memory device. In the early life of the memory device, the memory area of the memory device comprises a dynamic single-layer cell SLC area, wherein the data writing mode of any memory cell in the dynamic SLC area is an SLC mode or a non-SLC mode; the SLC mode is to write 1 bit of data into the memory cell, and the non-SLC mode is to write at least 2 bits of data into the memory cell;

The BLK management module is further configured to divide the dynamic SLC area into a static SLC area and a non-SLC area when determining that the storage area of the storage device needs to be updated, wherein the data writing mode of any storage unit in the static SLC area is an SLC mode, and the data writing mode of any storage unit in the non-SLC area is a non-SLC mode;

or, the BLK management module may be further configured to update the dynamic SLC region to a non-SLC region when it is determined that the storage region of the storage device needs to be updated, where a data writing manner of any storage unit in the non-SLC region is a non-SLC manner.

In some embodiments, the BLK management module may be specifically configured to: the memory area of the memory device is determined to be updated based on at least one of the write volume requirements of the memory device, the number of remaining program and erase PEs, the device write amplification value, and the user time.

In some embodiments, the dynamic SLC region includes a first pool of free blocks corresponding to the dynamic SLC region prior to the write module being used to write data to the memory device.

The BLK management module may be specifically configured to: when determining that data is required to be written in an SLC mode, determining a first idle block from a first idle block pool, and indicating a writing module to write the data to the first idle block in the SLC mode;

The writing module is used for marking the first idle block after writing data as a first identifier, and the first identifier indicates that the writing mode of the first idle block after writing data is an SLC mode.

In some embodiments, if the storage device does not support a full region as a dynamic SLC region, the BLK management module may be further configured to: determining the area size ratio of a static SLC area and a non-SLC area in the memory device according to the device specification of the memory device; the static SLC region and the dynamic SLC region in the memory device are determined according to the region size ratio.

In this case, the BLK management module, upon determining to write data to the storage device: if it is determined that data is to be written in SLC mode, it may be determined to write data to a dynamic SLC area or to write data to a static SLC area according to the area size ratio. Further, if it is determined that data is written to the static SLC area, determining a second idle block from the second idle block pool to indicate that the writing module is used for writing data to the second idle block in the SLC mode, the writing module marks the second idle block after writing the data as a first identifier, and the writing mode of the first identifier indicates that the writing mode of the block is the SLC mode; and the BLK management module is used for determining a third idle block from the third idle block pool when determining to write data into the dynamic SLC area so as to instruct the writing module to write the data into the third idle block in an SLC mode, and the writing module marks the third idle block after writing the data as a first mark, wherein the first mark indicates that the writing mode of the block is the SLC mode.

In some embodiments, the BLK management module may be configured to: when it is determined that the first free block is full, the block number of the block may be sent to the FIFO queue maintenance module. If the FIFO queue maintained by the FIFO queue maintenance module is a queue of blocks that are full in SLC, the FIFO queue maintenance module may add the full blocks to the tail of the FIFO queue. Then, the BLK management module may check whether the number of free blocks in the next first free block pool is less than a first threshold value every time a full block is determined. And if the number of the blocks in the first free block pool is determined to be smaller than a first threshold value, determining that the GC waterline needs to be started. At this time, the FIFO queue maintenance module may first determine the queue length of the FIFO queue, i.e. the number of SLC blocks to be queued into the FIFO queue. Then, starting from the head of the FIFO queue, M SLC blocks are determined that exceed the length of the queue. For example, the M SLC blocks in FIG. 6 are 1. The FIFO queue maintenance module informs the GC module of the block numbers of the M SLC blocks. The GC module may be configured to select at least one source block, which may be an SLC block or a TLC block, from TLC blocks in the dynamic SLC region and M SLC blocks (GC candidate region) according to a GC selection policy, where the source block is to be moved. The GC module is then used to move the valid data in at least one source block to at least one destination block of the free block pool in a TLC manner. The destination block may be understood as a free block in the free block pool. After the free block is written with data in TCL mode, a TLC block is obtained. In addition, the GC module needs to erase invalid data in the selected source block, and the erased source block is marked as a free block and is classified into a free block pool.

In some embodiments, if the GC module uses a greedy GC's blocking policy, the GC module may be specifically configured to:

the GC module determines a block for writing data in a dynamic SLC area in a TLC mode and a first source block with the least effective data quantity in M SLC blocks, and selects a first destination block from a free block pool corresponding to the dynamic SLC area;

the GC module moves the effective data in the first source block to the first destination block in a TLC mode, erases the ineffective data in the first source block, and marks the erased first source block as an idle block in a first idle block pool;

the GC module determining whether the number of free blocks in the first free block pool is equal to a first threshold, which may also be understood as the GC module querying the BLK management module for the number of free blocks in the first free block pool;

the GC module stops data movement when determining that the number of the idle blocks is equal to a first threshold value;

when the GC module determines that the number of the idle blocks is smaller than a first threshold value, continuing to determine a block for writing data in a TLC mode in the dynamic SLC area and a second source block with the least effective data amount in the rest blocks in the M SLC blocks;

and when the first destination block is not fully written yet, the GC module moves the effective data in the second source block into the first destination block in a TLC mode, erases the ineffective data in the second source block, marks the erased second source block as an idle block in the first idle block pool until the number of the idle blocks in the first idle block pool reaches a first threshold value.

Of course, the GC blocking policy may also be a double greedy GC or other blocking policy.

In some embodiments, the manner in which the FIFO queue maintenance module is configured to determine the queue length of the FIFO queue may be: the FIFO queue maintenance module may determine a reference queue length of the FIFO queue based on a total number of blocks in the storage device, a number of blocks capable of writing data in a TLC manner, and a first threshold; when the length of the reference queue is greater than or equal to the minimum queue length and less than or equal to the maximum queue length of the FIFO queue, the FIFO queue maintenance module determines the queue length of the FIFO queue as the reference queue length; when the reference queue length is smaller than the minimum queue length, the FIFO queue maintenance module determines that the queue length of the FIFO queue is the minimum queue length; when the reference queue length is greater than the maximum queue length of the FIFO queue, the FIFO queue maintenance module determines the queue length of the FIFO queue to be the maximum queue length.

It will be appreciated that the specific implementation of the write module, BLK management module, GC module, and FIFO queue maintenance module in the controller may be referred to above in the description of the corresponding method embodiments of fig. 4 or 9.

In one embodiment, when the controller 1201 is a memory controller and the memory area is a memory, the memory device according to the present embodiment may be an SSD having the structure shown in fig. 13.

It will be appreciated by those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to perform all or part of the functions described above.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another apparatus, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and the parts displayed as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or a part contributing to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions for causing a device (may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A method of managing data, the method being applied to a memory device, the method comprising:

writing data into the memory device, wherein a storage area of the memory device comprises a dynamic single-layer cell SLC area, and the data writing mode of any memory cell in the dynamic SLC area is an SLC mode or a non-SLC mode; the SLC mode is to write 1 bit of data into the storage unit, and the non-SLC mode is to write at least 2 bits of data into the storage unit;

when the storage area of the storage device is determined to be updated, the dynamic SLC area is divided into a static SLC area and a non-SLC area, wherein the data writing mode of any storage unit in the static SLC area is the SLC mode, and the data writing mode of any storage unit in the non-SLC area is the non-SLC mode;

Or when the storage area of the storage device is determined to be updated, updating the dynamic SLC area into a non-SLC area, wherein the data writing mode of any storage unit in the non-SLC area is the non-SLC mode.
The method of claim 1, wherein the determining that the storage area of the storage device is to be updated comprises:

and determining that the storage area of the storage device needs to be updated according to at least one of the writing quantity requirement of the storage device, the number of remaining programming and erasing PEs, the device writing amplification value and the use time of a user.
The method of claim 1 or 2, wherein the dynamic SLC region includes a first pool of free blocks corresponding to dynamic SLC regions prior to commencing writing data to the memory device;

the writing data to the memory device includes:

when determining that data is required to be written in the SLC mode, determining a first idle block from the first idle block pool, and writing the data to the first idle block in the SLC mode;

and marking the first idle block after writing data as a first identifier, wherein the first identifier indicates that the writing mode of the first idle block after writing data is the SLC mode.
The method of claim 1 or 2, wherein prior to writing data to the memory device, the method further comprises:

determining a region size ratio of the static SLC region and the dynamic SLC region in the memory device according to a device specification of the memory device; the static SLC region and the dynamic SLC region in the memory device are determined according to the region size ratio.
The method of claim 4, wherein the static SLC region comprises a second pool of free blocks and the dynamic SLC region comprises a third pool of free blocks;

the writing data to the memory device includes:

when determining that the data is required to be written in the SLC mode, determining to write the data to the dynamic SLC area or write the data to the static SLC area according to the area size proportion;

determining a second idle block from the second idle block pool when writing data to the static SLC area, writing the data to the second idle block in the SLC mode, marking the second idle block after writing the data as a first mark, wherein the writing mode of the first mark indicating block is the SLC mode;

when the data writing to the dynamic SLC area is determined, a third idle block is determined from the third idle block pool, the data is written to the third idle block in the SLC mode, the third idle block after the data writing is marked as a first mark, and the writing mode of the first mark indicating block is the SLC mode.
A method according to claim 3, characterized in that the method further comprises:

when the first idle block is fully written, recording the block number of the first idle block in a list, wherein the list comprises a plurality of block numbers of the blocks which are marked as the first mark and are fully written, and are recorded according to time;

when the number of blocks in the idle block pool corresponding to the dynamic SLC area is smaller than a first threshold value, determining the number of first blocks to be recorded in the list, wherein the number of first blocks is the number of blocks marked as the first mark and written fully;

starting from the first recorded block number of the list, determining M block numbers exceeding the first block number; m is an integer greater than or equal to 1;

selecting at least one source block to be moved from the blocks marked as the second mark in the dynamic SLC area and the blocks indicated by the M block numbers, and moving the effective data in the at least one source block to at least one destination block of an idle block pool in the dynamic SLC area in the non-SLC mode; the writing mode of the second identification indication block is the non-SLC mode.
The method of claim 6, wherein determining the number of first block numbers to record in the list comprises:

Determining a reference number of the first block number according to the total number of blocks in the memory device, the number of blocks capable of writing data in the non-SLC mode, and the first threshold;

when the reference number is greater than or equal to the minimum block number of the list and less than or equal to the maximum block number of the list, determining that the first block number is the reference number;

when the reference number is smaller than the minimum block number of the list, determining that the first block number is the minimum block number; and when the reference number is larger than the maximum block number, determining that the first block number is the maximum block number.
The method of claim 6, wherein the selecting at least one source block to be moved from among the blocks marked as second identification in the dynamic SLC region and the blocks indicated by the M block numbers, moving valid data in the at least one source block into at least one destination block in the free block pool with the non-SLC includes:

determining a first source block with the least effective data quantity in the blocks marked as the second mark and written in the dynamic SLC area and the blocks indicated by the M block numbers, and selecting a first destination block from an idle block pool corresponding to the dynamic SLC area;

Moving the effective data in the first source block to the first destination block in the non-SLC mode, erasing the ineffective data in the first source block, and marking the erased first source block as an idle block in the first idle block pool;

determining whether the number of idle blocks in an idle block pool corresponding to the dynamic SLC region is equal to the first threshold;

stopping data movement when the number of the idle blocks is equal to the first threshold value;

when the number of the idle blocks is smaller than the first threshold value, continuing to determine a second source block with the least effective data amount in the remaining blocks in the blocks marked as the second mark and fully written in the dynamic SLC area and the blocks indicated by the M block numbers;

and when the first destination block is not fully written, moving the effective data in the second source block into the first destination block in the non-SLC mode, erasing the ineffective data in the second source block, and marking the erased second source block as an idle block in the first idle block pool.
A memory device, comprising:

the writing module is used for writing data into the memory device, and the memory area of the memory device comprises a dynamic single-layer cell SLC area, wherein the data writing mode of any memory cell in the dynamic SLC area is an SLC mode or a non-SLC mode; the SLC mode is to write 1 bit of data into the storage unit, and the non-SLC mode is to write at least 2 bits of data into the storage unit;

The block management module is used for dividing the dynamic SLC area into a static SLC area and a non-SLC area when the storage area of the storage device is required to be updated, wherein the data writing mode of any storage unit in the static SLC area is the SLC mode, and the data writing mode of any storage unit in the non-SLC area is the non-SLC mode;

or, the block management module is configured to update the dynamic SLC area to a non-SLC area when it is determined that the storage area of the storage device needs to be updated, where a data writing manner of any storage unit in the non-SLC area is the non-SLC manner.
The memory device of claim 9, wherein the block management module is to:

and determining that the storage area of the storage device needs to be updated according to at least one of the writing quantity requirement of the storage device, the number of remaining programming and erasing PEs, the device writing amplification value and the use time of a user.
The memory device of claim 9 or 10, wherein the dynamic SLC region includes a first pool of free blocks corresponding to dynamic SLC regions prior to the write module being configured to write data to the memory device;

The block management module is specifically configured to:

when determining that the data is required to be written in the SLC mode, determining a first idle block from the first idle block pool, and indicating the writing module to be used for writing the data to the first idle block in the SLC mode;

the writing module is used for marking the first idle block after writing data as a first identifier, and the first identifier indicates that the writing mode of the first idle block after writing data is the SLC mode.
The memory device of claim 9 or 10, wherein the block management module is configured to, prior to the write module being configured to write data to the memory device:

determining a region size ratio of the static SLC region and the dynamic SLC region in the memory device according to a device specification of the memory device; the static SLC region and the dynamic SLC region in the memory device are determined according to the region size ratio.
The memory device of claim 12, wherein the static SLC region comprises a second pool of free blocks and the dynamic SLC region comprises a third pool of free blocks;

the block management module is used for:

when determining that the data is required to be written in the SLC mode, determining to write the data to the dynamic SLC area or write the data to the static SLC area according to the area size proportion;

Determining a second idle block from the second idle block pool when determining to write data to the static SLC area, indicating the writing module to write data to the second idle block in the SLC mode, marking the second idle block after writing data as a first identifier, wherein the writing mode of the first identifier indicating block is the SLC mode;

when the data is confirmed to be written into the dynamic SLC area, a third idle block is confirmed from the third idle block pool, the writing module is instructed to write the data into the third idle block in the SLC mode, the third idle block after the data is written is marked as a first mark, and the writing mode of the first mark indicating block is the SLC mode.
The memory device of claim 11, further comprising a list management module to:

when the first idle block is fully written, recording the block number of the first idle block in a list, wherein the list comprises a plurality of block numbers of the blocks which are marked as the first mark and are fully written, and are recorded according to time;

when the number of blocks in the idle block pool corresponding to the dynamic SLC area is smaller than a first threshold value, determining the number of first blocks to be recorded in the list, wherein the number of first blocks is the number of blocks marked as the first mark and written fully;

Starting from the first recorded block number of the list, determining M block numbers exceeding the first block number; m is an integer greater than or equal to 1;

selecting at least one source block to be moved from the blocks marked as the second mark in the dynamic SLC area and the blocks indicated by the M block numbers, and moving the effective data in the at least one source block to at least one destination block of an idle block pool in the dynamic SLC area in the non-SLC mode; the writing mode of the second identification indication block is the non-SLC mode.
The memory device of claim 14, wherein the list management module is configured to:

determining a reference number of the first block number according to the total number of blocks in the memory device, the number of blocks capable of writing data in the non-SLC mode, and the first threshold;

when the reference number is greater than or equal to the minimum block number of the list and less than or equal to the maximum block number of the list, determining that the first block number is the reference number;

when the reference number is smaller than the minimum block number of the list, determining that the first block number is the minimum block number; and when the reference number is larger than the maximum block number, determining that the first block number is the maximum block number.
The memory device of claim 14, wherein the list management module is configured to:

determining a first source block with the least effective data quantity in the blocks marked as the second mark and written in the dynamic SLC area and the blocks indicated by the M block numbers, and selecting a first destination block from an idle block pool corresponding to the dynamic SLC area;

moving the effective data in the first source block to the first destination block in the non-SLC mode, erasing the ineffective data in the first source block, and marking the erased first source block as an idle block in the first idle block pool;

determining whether the number of idle blocks in an idle block pool corresponding to the dynamic SLC region is equal to the first threshold;

stopping data movement when the number of the idle blocks is equal to the first threshold value;

when the number of the idle blocks is smaller than the first threshold value, continuing to determine a second source block with the least effective data amount in the remaining blocks in the blocks marked as the second mark and fully written in the dynamic SLC area and the blocks indicated by the M block numbers;

and when the first destination block is not fully written, moving the effective data in the second source block into the first destination block in the non-SLC mode, erasing the ineffective data in the second source block, and marking the erased second source block as an idle block in the first idle block pool.
A memory device comprising a memory controller and a memory, the memory controller coupled to the memory;

the memory is used for storing a computer program or instructions;

the memory controller for executing a computer program or instructions stored in the memory to cause the apparatus to perform the method of any one of claims 1 to 8.
A computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any of the preceding claims 1-8.
A computer program product, characterized in that the computer program product, when run on a computer or a processor, causes the computer or the processor to perform the method of any of the preceding claims 1-8.