CN117674827A

CN117674827A - Delay phase-locked loop and phase locking method and storage device thereof

Info

Publication number: CN117674827A
Application number: CN202211090071.6A
Authority: CN
Inventors: 方海彬; 黄碧云
Original assignee: Shanghai Geyi Electronic Co ltd
Current assignee: Shanghai Geyi Electronic Co ltd
Priority date: 2022-09-07
Filing date: 2022-09-07
Publication date: 2024-03-08

Abstract

The invention provides a delay phase-locked loop, a phase-locked method thereof and a storage device. Since the first coarse tuning step is larger than the subsequent second coarse tuning step, after the rising edge of DQS is forced to be rightwards adjusted by at least one beat by the first coarse tuning step, the rising edge of DQS is far away from the falling edge of VCLK, so that when the delay of the delay phase-locked loop is reduced due to power supply noise, the probability that the rising edge of DQS returns to the left side of the falling edge of VCLK is greatly reduced, and the locking time of the DLL is less influenced by the power supply noise.

Description

Delay phase-locked loop and phase locking method and storage device thereof

Technical Field

The present invention relates to the field of delay locked loops, and in particular, to a delay locked loop, a phase locking method thereof, and a storage device.

Background

Delay-Locked Loop (DLL) technology is widely used in the timing field, and particularly, when an external clock signal applied from an external device is used inside a corresponding semiconductor device, a Delay or clock offset caused by an internal circuit may be generated, and the DLL may achieve synchronization of the internal clock signal and the external clock signal by compensating for such Delay so that phases of the internal clock signal and the external clock signal coincide (or, edge alignment, phase locking).

For example, in the field of storage devices such as DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random-Access Memory), a DLL can implement phase locking (i.e., a phase difference within a predetermined range) between an external clock signal input from outside and an internal clock signal DQS (or DQ) inside the storage device, so as to ensure that Data is transferred to or read from the storage device without errors. However, during the phase locking of the DLL, the power supply voltage thereof may generate jitter due to noise, thereby causing a delay change in the internal clock signal DQS path of the memory device, thereby causing the phase locking time of the DLL to become long.

Disclosure of Invention

The invention aims to provide a delay locked loop, a phase locking method thereof and a storage device, which can improve the DLL locking process, weaken the influence of power supply noise on the DLL locking time and avoid the problem of lengthening the DLL locking time caused by the power supply noise.

In order to achieve the above object, the present invention provides a phase locking method of a delay locked loop, in the locking process of the delay locked loop, delay coarse adjustment is performed first, and then delay fine adjustment is performed until the phase of an internal clock signal output by the delay locked loop is consistent with the phase of an external clock signal received by the delay locked loop, where the step of delay coarse adjustment performed by the delay locked loop includes:

S1, coarse-adjusting delay by a first coarse-adjusting step length, so that the internal clock signal is integrally adjusted to the right by a plurality of beats until the rising edge of the internal clock signal reaches the right side of the falling edge of the external clock signal;

s2, continuing coarse adjustment of delay by the first coarse adjustment step length so as to force the whole internal clock signal to adjust at least one beat rightwards;

s3, coarse-tuning delay is performed in a second coarse-tuning step smaller than the first coarse-tuning step, so that the internal clock signal is integrally adjusted to the right by a plurality of beats until the rising edge of the internal clock signal reaches the right side of the next rising edge after the falling edge of the external clock signal.

Optionally, the second coarse tuning step is a minimum coarse tuning step of the delay phase locked loop, the first coarse tuning step is p times of the second coarse tuning step, where p is a positive integer, and in step S2, the internal clock signal is forced to be adjusted to the right by one beat as a whole by the first coarse tuning step.

Optionally, after step S3, the step of performing coarse delay adjustment by the delay locked loop further includes: and S4, continuing coarse adjustment of delay by the second coarse adjustment step length, so that the whole internal clock signal is adjusted to the left by a plurality of beats until the rising edge of the internal clock signal reaches the left side of the next rising edge after the falling of the external clock signal.

Optionally, the step of performing delay fine adjustment by the delay locked loop includes:

s5, finely adjusting delay by a first fine adjustment step smaller than the second coarse adjustment step so that the whole internal clock signal is adjusted to the right by a plurality of beats until the rising edge of the internal clock signal reaches the right side of the next rising edge after the falling of the external clock signal again;

s6, finely adjusting delay with a second fine adjustment step smaller than the first fine adjustment step, so that the internal clock signal is integrally adjusted to the left by a plurality of beats until the rising edge of the internal clock signal reaches the left side of the next rising edge after the falling of the external clock signal again;

and S7, finely adjusting delay by the second fine adjustment step length, so that the whole internal clock signal is adjusted to the right by a plurality of beats until the rising edge of the internal clock signal reaches the right side of the next rising edge after the falling of the external clock signal again.

Optionally, the second fine tuning step is a minimum fine tuning step of the delay phase locked loop, the second coarse tuning step is n times the second fine tuning step, the first fine tuning step is m times the second fine tuning step, where m and n are both powers of 2, and m is smaller than n.

Optionally, the phase locking method further includes: and S8, when the number of times that the rising edge of the internal clock signal passes through to the left side or the right side of the next rising edge after the falling of the external clock signal reaches a certain threshold value, judging that the phases of the internal clock signal and the external clock signal are consistent.

Based on the same inventive concept, the present invention also provides a delay locked loop, comprising:

a delay chain configured to receive and delay an external clock signal to output a corresponding internal clock signal;

the control circuit is coupled with the delay chain and is configured to control the delay chain to perform coarse delay adjustment and fine delay adjustment in the locking process of the delay phase-locked loop so as to enable the phases of the internal clock signal and the external clock signal to be consistent and complete locking of the delay phase-locked loop;

wherein, in performing the coarse delay adjustment, the control circuit is further configured to perform the steps of:

s1, controlling the delay chain to coarsely adjust delay by a first coarse adjustment step length so that the whole internal clock signal is adjusted to the right by a plurality of beats until the rising edge of the internal clock signal reaches the right side of the falling edge of the external clock signal;

S2, controlling the delay chain to continue coarse adjustment of delay by the first coarse adjustment step length so as to force the whole internal clock signal to adjust at least one beat rightwards;

s3, controlling the delay chain to coarsely adjust delay with a second coarse adjustment step smaller than the first coarse adjustment step, so that the internal clock signal is adjusted to the right by a plurality of beats as a whole until the rising edge of the internal clock signal reaches the right side of the next rising edge after the falling edge of the external clock signal.

Optionally, the second coarse tuning step is a minimum coarse tuning step of the delay chain, and the first coarse tuning step is p times of the second coarse tuning step, wherein p is a positive integer; in performing coarse delay adjustment, the control circuit is further configured to: in step S2, the delay chain is controlled to continue coarse tuning the delay with the first coarse tuning step to force the internal clock signal to adjust one beat to the right as a whole.

Optionally, the control circuit is further configured to: after step S3, step S4 is executed, and the delay chain is controlled to continue coarse tuning delay with the second coarse tuning step, so that the internal clock signal is adjusted to the left by a plurality of beats as a whole, until the rising edge of the internal clock signal reaches the left side of the next rising edge after the falling of the external clock signal.

Optionally, the control circuit is further configured to perform the steps of:

s5, controlling the delay chain to finely adjust delay with a first fine adjustment step length smaller than the second coarse adjustment step length, so that the internal clock signal is integrally adjusted to the right by a plurality of beats until the rising edge of the internal clock signal reaches the right side of the next rising edge after the falling of the external clock signal again;

s6, controlling the delay chain to finely adjust delay with a second fine adjustment step length smaller than the first fine adjustment step length, so that the internal clock signal is integrally adjusted to the left by a plurality of beats until the rising edge of the internal clock signal reaches the left side of the next rising edge after the falling of the external clock signal again;

and S7, controlling the delay chain to finely adjust the delay by the second fine adjustment step length, so that the whole internal clock signal is adjusted to the right by a plurality of beats until the rising edge of the internal clock signal reaches the right side of the next rising edge after the falling of the external clock signal again.

Optionally, the control circuit includes a state machine coupled to the delay chain, a state indication signal is disposed in the state machine, the state indication signal turns over the external clock signal according to the rising edge of the internal clock signal, the state machine enters different states according to the turning over of the state indication signal, and the state machine is in different states, and controls the delay chain to adjust delay in different adjustment steps or adjustment directions, wherein the state machine determines that the state enters the state of the step S3 from the state of the step S1 according to the turning over of the state indication signal, and before controlling the delay chain to adjust the step S3, the state machine forces the delay chain to maintain the adjustment steps and adjustment directions of the step S1 and readjust at least one beat.

Optionally, the delay locked loop further includes:

a clock buffer circuit coupled to the delay chain and configured to: outputting the clock signal output by the delay chain as the internal clock signal;

a replica clock buffer circuit coupled to the delay chain and configured to: generating a feedback clock signal according to the clock signal output by the delay chain;

A phase detector coupled to the replica clock buffer circuit and the control circuit and configured to: the phase difference between the external clock signal and the feedback clock signal is compared such that the control circuit controls the delay adjustment of the delay chain according to the phase difference.

Optionally, the delay locked loop further includes a configuration circuit, coupled to the control circuit, configured to perform or skip step S2 during the controlling of the delay chain to perform the coarse delay adjustment.

Optionally, the configuration circuit is an electronic fuse or a one-time programmable memory.

Based on the same inventive concept, the invention also provides a storage device, comprising the delay phase-locked loop, wherein the delay phase-locked loop receives an external clock signal from the outside of the storage device and outputs an internal clock signal delayed relative to the external clock signal, the internal clock signal selects a pulse signal for data of the storage device, and the delay phase-locked loop locks after adjusting the internal clock signal to be consistent with the phase of the external clock signal.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

1. After the rising edge of the internal clock signal DQS is adjusted to the right of the falling edge of the external clock signal VCLK by a first coarse step (e.g., 2C), the rising edge of DQS is forced to adjust to the right by at least one beat by the first coarse step. Since the first coarse tuning step is larger than the subsequent second coarse tuning step, after the rising edge of DQS is forced to be rightwards adjusted by at least one beat by the first coarse tuning step, the rising edge of DQS is far away from the falling edge of VCLK, so that when the delay of the delay phase-locked loop is reduced due to power supply noise, the probability that the rising edge of DQS returns to the left side of the falling edge of VCLK is greatly reduced, and the locking time of the DLL is less influenced by the power supply noise.

2. The scheme does not need a complex detection circuit to detect whether the rising edge of the internal clock signal DQS is in fact jittered (caused by power supply noise), and the circuit is simple and easy to implement.

Drawings

Fig. 1 is a timing diagram of a DDR memory device according to the prior art.

Fig. 2 is a schematic diagram of the architecture of a prior art DLL.

Fig. 3 is a schematic diagram of a locking process of a DLL in the related art.

Fig. 4 is a schematic diagram of a phase locking method of a DLL according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of the DLL architecture according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of the architecture of a DLL according to another embodiment of the present invention.

Fig. 7 is a circuit diagram illustrating a coarse tuning delay unit in a DLL according to an embodiment of the present invention.

Fig. 8 is a schematic diagram of the architecture of a memory device (provided with a DLL of the present invention) according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention. It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element is referred to as being "connected to," "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

While the DDR memory device has a high requirement for clock accuracy, the DDR memory device has two clocks, one is an external clock signal VCLK input from an external bus, and the other is an internal clock signal DQS required for the operation of an internal circuit, please refer to fig. 1, which receives an instruction cmd (e.g., a Read instruction Read cmd) from the outside according to the external clock signal VCLK, and an internal clock signal DQS (DQ strobe, data select pulse) signal is generated by the DDR memory device when receiving the Read instruction Read cmd, as a clock for sending the data DQ signal outwards, that is, the external clock signal VCLK is used by the DDR memory device to receive the Read instruction Read cmd, and the internal clock signal DQS is used by the DDR memory device to collect the data DQ. In theory, these two clocks should be synchronized, but for various reasons, such as that the internal circuit and the external circuit of the DDR memory device are not perfectly matched, the internal clock signal DQS (i.e., the data selection pulse signal) is not aligned (i.e., not synchronized) with the external clock signal VCLK, and when the data reading is directly performed based on the misaligned internal clock signal DQS and the external clock signal VCLK and the Read command Read cmd, the eye pattern of the data sent out by the DDR memory device may be reduced. It is therefore necessary to add a DLL to the DDR memory device to align its internal clock signal DQS with the external clock signal VCLK, thereby aligning the Read command Read cmd and the data DQ to avoid the problem of eye shrinkage. After DQS and CLK are aligned, and the transfer of data DQ occurs on the rising and falling edges of VCLK.

Referring to fig. 2, fig. 2 is a block diagram of a conventional DLL, which includes a Delay chain (i.e., delay Line) 10, a clock buffer circuit 11, a Phase Detector (PD) 12, a control circuit 13, and a replica clock buffer circuit 14. The replica clock buffer circuit 14 is a replica circuit of the clock buffer circuit 11. The delay chain 10 receives an externally input external clock signal VCLK, delays the external clock signal VCLK, and feeds back the delayed clock signal CLKout to the phase detector 12 via the replica clock buffer circuit 14, wherein the phase detector 12 provides a feedback clock signal DQS to the external clock signal VCLK and the replica clock buffer circuit 14 _fb After the phase comparison, the obtained phase difference is sent to the control circuit 13, the control circuit 13 controls the delay chain 10 to increase or decrease the delay according to the phase difference obtained by the phase detector 12, adjusts the phase difference between VCLK and DQS, and when the phase difference between the input external clock signal VCLK and the output internal clock signal DQS reaches a preset range (i.e., the phase difference can be regarded as 0), the DLL finishes locking, and at this time, the external clock signal VCLK is aligned (i.e., synchronized) with the output internal clock signal DQS.

Referring to fig. 2 and 3, the control circuit 13 controls the delay chain 10 to increase or decrease the delay, and generally includes a Coarse delay adjustment (Coarse adjustment) and a Fine delay adjustment (Fine adjustment), and the unit length of the Coarse delay adjustment is 1Coarse (denoted as 1C), which represents the minimum delay (i.e., the minimum Coarse delay step) that the delay chain 10 can increase or decrease during the Coarse delay adjustment; the unit length of the delay Fine is 1Fine (denoted as F), which represents the minimum delay (i.e., the minimum Fine step size) that the delay chain 10 (delay line) can increase or decrease during the delay Fine adjustment, and 1 f=c/k, k is a positive integer greater than 1. As an example, k=16.

In general, the control circuit 13 is internally provided with a state machine 13a, the state machine 13a internally has a state signal, the state signal is inverted according to the sampling level, the state machine 13a enters different states according to the inversion of the state signal, and (1) to (7) in fig. 3 are different states of the state machine 13 a. The rising edge of DQS samples VCLK, and the 1 st sampling obtains a high level, that is, corresponds to the (1) state of the state machine 13a, the 1 st sampling obtains a low level, that is, corresponds to the (2) state of the state machine 13a, and the sampling obtains a high level, that is, corresponds to the (3) state of the state machine 13a, and so on, to obtain the (4) to (7) states of the state machine 13 a. When the state machine 13a is in different states, the delay chain can be controlled to adjust the delay with different adjusting step sizes step and adjusting directions, so that coarse delay adjustment and fine delay adjustment can be performed in the locking process of the DLL, and the delay adjustment can be performed until the DLL is locked.

Specifically, assuming that the initial position of the rising edge of DQS is at (1) in FIG. 3 (i.e., the rising edge of DQS is to the right of the first rising edge of VCLK and to the left of the falling edge of VCLK), the ideal locking process of the DLL is as follows:

first, the control circuit 13 controls the whole delay chain 10 to coarsely adjust the delay in coarse steps of 2C, so that the DQS is adjusted to the right as a whole until the rising edge of the DQS reaches the right of the falling edge of VCLK, as shown in (2) of fig. 3, at this time, from (1) to (2), if the DQS is adjusted to the right by m1 beats (i.e., the delay of the delay chain 10 is coarsely adjusted by m1 steps), the DQS is delayed by m1×2c as a whole;

Next, the control circuit 13 controls the whole delay chain 10 to coarsely adjust the delay in coarse steps of 1C, so that the DQS continues to adjust the whole right until the DQS rising edge reaches the right of the second rising edge of VCLK (i.e., the next rising edge after the falling edge of VCLK), as shown in (3) of fig. 3, at this time, from (2) to (3), if the DQS is adjusted by m2 beats in the whole right (i.e., the delay of the delay chain 10 is coarsely adjusted by m2 steps), the DQS is again delayed by m2×c;

then, the control circuit 13 controls the whole delay chain 10 to coarsely adjust the delay by a coarse adjustment step of 1C, so that the DQS continues to adjust overall to the left until the DQS rising edge reaches the left of the second rising edge of VCLK, as shown at (4) in fig. 3, at which time, from (3) to (4), if the DQS overall is adjusted to the left by m3 beats (i.e., the delay of the delay chain 10 is coarsely adjusted by m3 steps), and m3< m2, the DQS overall is advanced by m3×c;

next, the control circuit 13 controls the whole delay chain 10 to fine-adjust the delay by a fine-adjustment step of 4F so that the DQS is again adjusted overall to the right until the DQS rising edge reaches the right of the second rising edge of VCLK, as shown at (5) in fig. 3, at which time, from (4) to (5), if the DQS is adjusted overall to the right by m4 beats (i.e., the delay of the delay chain 10 is fine-adjusted by m4 steps), the DQS is delayed overall by m4 x 4F;

Then, the control circuit 13 controls the delay chain 10 to fine-adjust the delay by a fine-adjustment step of 1F so that the DQS is adjusted again as a whole to the left until the DQS rising edge reaches the left of the second rising edge of VCLK, as shown at (6) in fig. 3, at which time, from (5) to (6), if the DQS is adjusted as a whole to the left by m5 beats (i.e., the delay of the delay chain 10 is fine-adjusted by m5 steps), the DQS is advanced as a whole by m5×f;

thereafter, the control circuit 13 controls the delay chain 10 to fine-tune the delay chain by a fine-tuning step of 1F so that the DQS is again adjusted overall to the right until the DQS rising edge reaches the right of the second rising edge of VCLK, as shown at (7) in fig. 3, at which time, from (6) to (7), if the DQS is adjusted overall to the right by m6 beats (i.e., the delay of the delay chain 10 is fine-tuned by m6 steps), and m6< m5, the DQS is advanced overall by m6 by F. To this end, the DQS rising crosses (cross) the second rising edge of VCLK twice at a fine step of 1F, the control circuit 13 considers that the phase difference of DQS and VCLK reaches the preset range (i.e., can be considered as phase difference 0), the delay of the delay chain 10 is no longer changed, and the DLL completes the lock.

However, during the lock-up of the DLL, the power supply voltage VDD may generate jitter due to noise, which may cause a delay change on the DQS path, thereby causing a lock-up time change of the DLL. Specifically, with continued reference to FIG. 3, assuming that the initial location of the DQS rising edge is at (1) as in FIG. 3, the actual locking process of the DLL is as follows:

When the control circuit 13 controls the delay chain 10 to coarsely delay in coarse steps of 2C to adjust the rising edge of DQS to the right at (2), the power supply voltage VDD of the delay chain 10 increases due to noise, so that the delay of the delay chain 10 decreases, thereby causing the rising edge of DQS to return to (3) 'where the rising edge of DQS is sampled VCLK, then the rising edge of DQS is sampled again to a high level, i.e., corresponding to cause the state machine 13a to mistakenly consider that the rising edge of DQS has arrived at (3), the control circuit 13 controls the delay chain 10 to start coarsely adjusting the rising edge of DQS in coarse steps of 1C to adjust the rising edge of DQS to the left, at this time the power supply voltage VDD again decreases due to noise, so that the delay of the delay chain 10 increases, thereby causing the rising edge of DQS to return to (4)' where the rising edge of DQS is sampled VCLK, then the rising edge of DQS is sampled again to a low level, i.e., corresponding to cause the rising edge of DQS to mistakenly consider that the rising edge of DQS has arrived at (4), and the control circuit 13 controls the delay chain 10 to start to finely adjust the rising edge of DQS to the right at (5) until the rising edge of DQS has arrived at (5) and after the delay chain has arrived at (5).

Obviously, in the above process, after the jitter of the power supply voltage VDD occurs, an adjustment process from (4) 'to (5) may occur, and the adjustment process adjusts DQS by about half a clock cycle in a step of 4F, and since 4f=c/4, the lock time from (4)' to (5) in a step of 4F is approximately 4 times the original lock time from (2) to (5), eventually resulting in a significantly longer lock time of the DLL.

In view of this, the present invention provides a delay locked loop, a locking method thereof, and a memory device, which forces the rising edge of DQS to be adjusted to the right of the falling edge of VCLK by a first coarse adjustment step (e.g., 2C) and then adjusts the rising edge of DQS by at least one beat to the right by the first coarse adjustment step. Because the first coarse adjustment step is longer than the subsequent second coarse adjustment step, after the rising edge of DQS is forced to rightwards adjust at least one beat by the first coarse adjustment step, the rising edge of DQS is far away from the falling edge of VCLK, when the delay of the DLL is reduced due to power supply noise, the probability that the rising edge of DQS returns to the left side of the falling edge of VCLK due to the power supply noise is greatly reduced, thereby reducing the influence of the power supply noise on the locking time of the DLL and avoiding the problem that the locking time of the DLL is prolonged due to the power supply noise.

The technical scheme provided by the invention is further described in detail below with reference to the attached drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

Referring to fig. 4 and 5, an embodiment of the present invention provides a phase locking method of a Delay Locked Loop (DLL), wherein the DLL receives an external clock signal VCLK and outputs a corresponding internal clock signal DQS based on the external clock signal VCLK, and the DLL can achieve locking by adjusting the delay of the delay chain 10 so that the phases of the internal clock signal DQS and the external clock signal VCLK are identical (or the edge alignment, the phase locking, or the phase difference is 0). The phase locking method of the DLL of the embodiment can firstly perform coarse delay adjustment and then perform fine delay adjustment in the locking process of the DLL until the phase of the internal clock signal DQS output by the DLL is consistent with the phase of the external clock signal received by the DLL.

Referring to fig. 4, assuming that the initial position of the rising edge of the DQS is at (1) in fig. 4 (i.e. the rising edge of the DQS is on the right side of the first rising edge of VCLK and on the left side of the falling edge of VCLK), the step of performing coarse delay adjustment in the phase locking method of the DLL of the present embodiment includes:

s1, coarse tuning the delay by a first coarse tuning step delta t1, causing DQS to adjust a number of beats to the right as a whole until the rising edge of DQS reaches the right of the falling edge of VCLK, as shown at (2) in FIG. 4. At this time, from (1) to (2), if DQS is adjusted by n1 beats in its entirety to the right (i.e., the delay of delay chain 10 is coarsely adjusted by n1 steps), n1 is an integer, and DQS is delayed by n1×Δt1 in its entirety, it is apparent that the magnitude of n1 depends on Δt1 and the clock cycles experienced at rising edges (1) to (2) of DQS.

S2, coarse tuning of the delay continues with a first coarse tuning step Δt1 to force DQS to adjust the whole right by at least one beat, at which time the rising edge of DQS reaches as shown at (2)' in FIG. 4. I.e., step S2 is completed, the rising edge of DQS is between the falling edge of VCLK and the next rising edge. At this time, from (2) to (2)' the DQS is adjusted by n2 beats to the right (i.e. the delay of the delay chain 10 is coarsely adjusted by n2 steps), n2 is an integer and 1.ltoreq.n2 < n1, and the DQS is again delayed by n2 x Δt1. It is noted that since at step S2 the state signal state inside state machine 13a may not be flipped any more, state machine 13a forces DQS to adjust n2 beats to the right as a whole. In one embodiment, n2=1 or 2, but the present invention is not limited thereto.

S3, coarse tuning is delayed by a second coarse tuning step size Δt2 (i.e., Δt2 </Δt1) smaller than Δt1, so that DQS is adjusted by a plurality of beats as a whole to the right until the rising edge of DQS reaches the right side of the second rising edge of VCLK (i.e., the next rising edge after the falling edge of VCLK, hereinafter referred to as the second rising edge of VCLK), as shown at (3) in FIG. 4. At this time, from (2)' to (3), if the DQS is adjusted to the right by n3 beats (i.e., the delay of the delay chain 10 is coarsely adjusted by n3 steps), n3 is an integer, the DQS is again delayed by n3 t2. It is apparent that the magnitude of n3 depends on the delta t2 and the clock cycles experienced at rising edges (2)' to (3) of DQS. It should be appreciated that when Δt1 is p times Δt2, n3 may be equal to m2 as required from (2) to (3) in fig. 3, or may be equal to m2-p n2, or may be a suitable integer between (m 2-p n 2) and m 2. As an example, Δt2 is the minimum coarse tuning step 1C of the delay locked loop, and Δt1=2c, i.e. p takes a value of 2.

The phase locking method of this embodiment further includes a coarse tuning process of step S4 after step S3, specifically, the coarse tuning delay is continued by the second coarse tuning step Δt2, so that the DQS is adjusted by a plurality of beats in the whole left until the rising edge of the DQS reaches the left side of the second rising edge of VCLK, as shown in (4) of fig. 4. At this time, from (3) to (4), if DQS is adjusted to the left by n4 beats (i.e., the delay of delay chain 10 is coarsely adjusted by n4 steps) and n4< n3, DQS is advanced by n4 x Δt2.

In the phase locking method of this embodiment, after step S1 (i.e. after the rising edge of DQS is adjusted to the right of the falling edge of VCLK), DQS is forced to adjust at least one beat right by the first coarse adjustment step delta t1, and since the step of delta t1 is longer, the rising edge of DQS can be further away from the falling edge of VCLK at this time, when the delay of delay chain 10 is reduced due to power noise, the probability that the rising edge of DQS returns to the left of the falling edge of VCLK is greatly reduced, so that both step S3 and the subsequent locking process can be normally performed, and the locking time is less affected by the power noise.

After the above steps S1 to S4 are completed, the process of delaying the coarse adjustment is completed, that is, the process of coarse adjusting the phase of the rising edge of DQS is completed, and then the process of delaying the fine adjustment is entered, that is, the process of fine adjusting the phase of the rising edge of DQS is entered.

Specifically, in the phase locking method of the present embodiment, after the steps S1 to S4 are completed, the step of performing delay fine adjustment includes:

s5, fine-tuning the delay by a first fine-tuning step size Δt3 (i.e., Δt3< <Δt2) less than Δt2, such that DQS is again adjusted overall to the right until the DQS rising edge reaches the right of the second rising edge of VCLK, as shown at (5) in FIG. 4, at which time, from (4) to (5), if DQS is adjusted overall to the right by n5 beats (i.e., delay of delay chain 10 is fine-tuned by n5 steps), DQS is delayed overall by n5×t3.

S6, fine-tuning the delay by a second fine-tuning step size Δt4 (i.e., Δt4< <Δt3) less than Δt3, such that DQS is again adjusted overall to the left until the DQS rising edge reaches the left of the second rising edge of VCLK, as shown at (6) in FIG. 4, at which time, from (5) to (6), if DQS is adjusted overall to the left by n6 beats (i.e., delay of delay chain 10 is fine-tuned by n6 steps), n6 is an integer, DQS is advanced overall by n6 x Δt4.

S7, continuing to fine tune the delay chain by the second fine tuning step delta t4, so that DQS is again adjusted to the right as a whole until the DQS rising edge reaches the right of the second rising edge of VCLK, as shown at (7) in fig. 4, at which time, from (6) to (7), if DQS is adjusted to the right as a whole by n7 beats (i.e. the delay of delay chain 10 is fine tuned by n7 steps), and n7< n6, DQS is advanced as a whole by n7 t4.

It should be understood that the rule that DQS and VCLK are in phase correspondence is preset in the delay locked loop, so that the phase locking method of this embodiment further includes: s8, in the process of adjusting the delay of the delay chain by the minimum fine step, when the number of times that the rising edge of DQS crosses to the left or right of the second rising edge of VCLK reaches a preset threshold (the preset threshold may be any suitable value such as 2, 3 or 4), it is determined that the DQS and VCLK are in phase.

As an example, the predetermined threshold is 2, and it is required that the DQS and VCLK are phase-matched when the number of times the rising edge of DQS crosses to the second rising edge of VCLK (only crossing may be determined, or crossing to the left or right may not be determined) reaches the predetermined threshold 2 in the process of fine-tuning the delay of the delay chain with the minimum fine-tuning step. Thus, when Δt4 is the minimum fine tuning step (i.e. Δt4=1f), steps S6-S7 are all processes of fine tuning the delay of the delay chain with the minimum fine tuning step, and when step S7 is finished, the number of times that the rising edge of DQS crosses the rising edge of VCLK is 2 (i.e. the rising edge of DQS crosses (cross) twice the second rising edge of VCLK back and forth at the fine tuning step of Δt4), reaching the preset threshold and meeting the rule of presetting the phase of DQS and VCLK to be consistent in the delay phase-locked loop, i.e. the phase difference of DQS and VCLK reaches the preset range, the delay of the delay chain 10 is not changed any more, and the DLL completes the locking. Summarizing, Δt2 is the minimum coarse tuning step size 1C of the delay locked loop, Δt4 is the minimum fine tuning step size 1F of the delay locked loop, 1c=n×f, Δt1=p×Δt2=p×c, Δt3=m×Δt4=m×f, where p is an integer, where m <n and m and n are each powers of 2. p is an integer, and p is determined by the number of delay branches added per adjustment in step S1 with reference to the coarse tuning delay unit 10a shown in fig. 7 later. The circuit (details not shown) of the fine delay unit 10b divides 1C into 16F by, for example, 4-bit binary code values, i.e., (2) ⁴ =16), and so on, so m and n are each powers of 2. Of course, the invention is not limited in this regard and m and n are integers and may not be powers of 2 in embodiments where coarse delay unit 10a and fine delay unit 10b are implemented using other circuits.

As an example, Δt2 is the minimum coarse tuning step size 1C of the delay locked loop, Δt4 is the minimum fine tuning step size 1F of the delay locked loop, 1c=16f, Δt1=2×Δt2=2c, Δt3=4×Δt4=4f, and in step S2, n=1 forces DQS to be adjusted one beat to the right as a whole.

Referring to fig. 5, an embodiment of the present invention further provides a DLL (delay locked loop) including a delay chain 10, a clock buffer circuit 11, a phase detector 12, a control circuit 13, and a replica clock buffer circuit 14. The replica clock buffer circuit 14 is a replica circuit of the clock buffer circuit 11. The delay chain 10 receives an externally input external clock signal VCLK, delays the external clock signal VCLK, and outputs a delayed clock signal CLKout. The clock buffer circuit 11 is coupled to the delay chain 10, and outputs the delayed clock signal CLKout outputted from the delay chain 10 as an internal clock signal DQS. The replica clock buffer circuit 14 is coupled to the delay chain 10 and generates a feedback clock signal DQS according to the delayed clock signal CLKout output from the delay chain 10 _fb Is provided to the phase detector 12. The phase detector 12 outputs a feedback clock signal DQS and an external clock signal VCLK _fb After the phase comparison, the obtained phase difference is sent to the control circuit 13, the control circuit 13 controls the delay chain 10 to perform delay adjustment (i.e. increase or decrease delay) according to the phase difference obtained by the phase detector 12, and adjusts the phase difference between the VCLK and the DQS, when the phase difference between the input external clock signal VCLK and the output internal clock signal DQS reaches a preset range, the phase difference between the DQS and the VCLK can be regarded as 0, i.e. the phase of the DQS is consistent with the phase of the VCLK at this time, so that the DLL finishes locking, and the external clock signal VCLK is aligned (i.e. synchronized) with the output internal clock signal DQS at this time.

The delay chain 10 includes a coarse delay unit 10a and a fine delay unit 10b, where the coarse delay unit 10a is configured to perform coarse delay adjustment with a larger adjustment step under the control of the control circuit 13, that is, perform coarse phase adjustment on the rising edge of the DQS with a larger adjustment step until the rising edge of the DQS reaches the right side of the next rising edge after the falling edge of the VCLK beyond the falling edge of the VCLK. The fine delay unit 10b is configured to perform delay fine adjustment with a smaller adjustment step under the control of the control circuit 13, that is, perform phase fine adjustment on the rising edge of the DQS with a smaller adjustment step, so that the rising edge of the DQS passes through the next rising edge after the falling edge of the VCLK to the left and right until the phase difference between the VCLK and the DQS reaches a preset range, thereby completing DLL locking.

Therefore, the control circuit 13 of the present embodiment has the basic function of executing steps S1, S3 to S7 in the phase locking method described above, that is, is configured to control the delay chain 10 to perform coarse delay adjustment and then fine delay adjustment during the locking process of the DLL, so that the phase of VCLK is consistent with the phase of DQS, and the locking of the DLL is completed.

During the lock-up of the DLL, the power supply voltage VDD may generate jitter due to noise, which may cause a delay change on the DQS path, thereby causing a lock-up time of the DLL to change. Therefore, in order to reduce the influence of the power supply noise on the DLL lock time, and avoid the problem of the DLL lock time lengthening caused by the power supply noise, the control circuit 13 in the DLL of the present embodiment is further given a forced coarse adjustment function capable of executing step S2 in the above-described phase locking method, specifically, please make a coarse adjustment with a second coarse adjustment step of Δt2 (< > t 1) after the control circuit 13 controls the delay chain 10 to adjust the rising edge of the DQS to the right at the first coarse adjustment step of Δt1 to (2) (i.e., the rising edge of the DQS reaches the right of the falling edge of the VCLK) and before the control circuit 13 controls the delay chain 10 to adjust the rising edge of the DQS to the right at the second coarse adjustment step of Δt2 (< } t 1) to the right at (3) (i.e., the rising edge of the DQS reaches the right of the falling edge of the VCLK) on the assumption that the initial position in fig. 4). Control delay chain 10 continues to coarsely adjust the delay by a first coarse adjustment step Δt1 to force the rising edge of DQS to adjust at least one beat to the right when the rising edge of DQS reaches (2)' (when the rising edge of DQS is still to the right of the falling edge of VCLK and to the left of the second rising edge of VCLK), i.e., control circuitry 13 is configured to: after the step S1 is performed and before the step S3 is performed, the step S2 is performed.

As an example, the control circuit 13 is internally provided with a state machine 13a, the state machine 13a internally has a state indicating signal state which is inverted according to the level of the sampling VCLK at the rising edge of the DQS, the state machine 13a enters different states according to the inversion of the state signal, and (1) to (7) in fig. 4 are different states of the state machine 13 a. Specifically, VCLK is sampled at the rising edge of DQS, and the 1 st sampling obtains a high level, that is, corresponds to the (1) state of the state machine 13 a; sampling for the 1 st time to obtain a low level, namely, correspondingly obtaining the (2) state of the state machine 13 a; the 2 nd sampling obtains a high level, namely the (3) state corresponding to the state machine 13 a; sampling for the 2 nd time to obtain a low level, namely, a (4) state corresponding to the state machine 13 a; the 3 rd sampling obtains a high level, namely the (5) state corresponding to the state machine 13 a; sampling for the 3 rd time to obtain a low level, namely, a state (6) corresponding to the state machine 13 a; the 4 th sample gets a high level, corresponding to the (7) state of state machine 13 a. When the state machine 13a of the state machine is in different states, the delay chain 10 can be controlled to adjust the delay in different adjustment steps or adjustment directions, so that in the locking process of the DLL, the control circuit 13 can control the delay chain 10 to sequentially perform the coarse delay adjustment process of the steps S1 to S4, and then control the delay chain 10 to sequentially perform the fine delay adjustment of the steps S5 to S7 until the DLL is locked.

That is, in performing the coarse delay adjustment, the control circuit 13 is further configured to perform the steps of:

s1, controlling a delay chain 10 to coarsely delay by a first coarse adjustment step delta t1, so that DQS is wholly adjusted to the right by a plurality of beats until the rising edge of DQS reaches the right side of the falling edge of VCLK;

s2, controlling the delay chain 10 to continue coarse tuning the delay by a first coarse tuning step delta t1 so as to force the DQS to integrally adjust at least one beat to the right;

s3, controlling the delay chain 10 to coarsely adjust delay by a second coarse adjustment step delta t2 smaller than the first coarse adjustment step delta t1, so that DQS is wholly adjusted to the right by a plurality of beats until the rising edge of DQS reaches the right side of the rising edge of VCLK;

s4, the delay chain 10 is controlled to continue coarse tuning the delay by the second coarse tuning step delta t2, so that the DQS is adjusted to the left by a plurality of beats as a whole until the rising edge of the DQS reaches the left side of the next rising edge after the falling edge of VCLK.

In performing the delay fine-tuning, the control circuit 13 is further configured to perform the steps of:

s5, controlling the delay chain 10 to finely adjust the delay by a first fine adjustment step delta t3 smaller than a second coarse adjustment step delta t2, so that the DQS is integrally adjusted to the right by a plurality of beats until the rising edge of the DQS reaches the right side of the rising edge of the VCLK again;

S6, controlling the delay chain 10 to finely adjust the delay by a second fine adjustment step size delta t4 smaller than the first fine adjustment step size delta t3, so that the DQS is integrally adjusted to the left by a plurality of beats until the rising edge of the DQS reaches the left side of the rising edge of the VCLK again;

s7, the delay chain 10 is controlled to fine tune the delay by a second fine tuning step delta t3, so that the DQS is adjusted by a plurality of beats as a whole to the right until the rising edge of DQS reaches the right side of the rising edge of VCLK again.

It should be noted that, in the present embodiment, the state machine 13a determines that the state corresponding to the above step S1 is entered from the state corresponding to the above step S3 according to the inversion of the state indication signal state, and after the control delay chain 10 completes the step S1 and before the control delay chain 10 performs the adjustment of the step S3, the state machine 13a forces the delay chain 10 to maintain the first coarse adjustment step size and the adjustment direction of the step S1 for at least one beat.

Referring to fig. 6, in order to make the application range of the DLL circuit of the present invention wider, a configuration circuit 15 is further added in the DLL of other embodiments of the present invention, which is coupled to the control circuit 13 and configured such that the control circuit 13 can selectively execute or skip the step S2 in the process of controlling the delay chain 10 to perform coarse delay adjustment.

Alternatively, the configuration circuit 15 may be any suitable circuit design such as an Electronic Fuse (EFUSE) or other one-time programmable memory.

When the configuration circuit 15 is a one-time programmable memory, the user can select whether to turn on the forced adjustment function of the control circuit 13 by setting the one-time programmable memory EFUSE, so that the user can select the control circuit 13 to execute or skip the step S2 described above in the course of controlling the delay chain 10 to perform the coarse delay adjustment. For example, if a specific memory bit (bit) of the one-time programmable memory EFUSE is set to "1", it means that the user selects the control circuit 13 to perform the step S2 described above in the course of controlling the delay chain 10 to perform coarse delay adjustment, at this time, the state machine 13a in the control circuit 13 of the DLL receives the information of the set "1" sent by the one-time programmable memory EFUSE, and after entering the state (2), forces the delay chain 10 to adjust DQS to the right by at least one beat with at 1, and then controls the delay chain 10 to adjust DQS to the right by at 2 to enter the state (3); if the specified memory bit of EFUSE is set to "0", it indicates that the user selection control circuit 13 skips the step S2 described above in the course of controlling the delay chain 10 to perform coarse delay adjustment, and the state machine 13a will normally operate, and after entering the state (2), directly controlling the delay chain 10 to adjust DQS right by Δt2 to enter the state (3).

It should be appreciated that the delay chain 10 in the various embodiments described above may be implemented using any suitable circuit design known in the art.

As an example, referring to fig. 7, the coarse tuning delay unit 10a in the delay chain 10 includes cascaded w delay branches 1 to w, each of the delay branches 1 to w is coupled to the state machine 13a of the control circuit 13 and is connected to the corresponding control signals D0, D1 … … Dw (only D0, D1 are shown in fig. 7 for simplicity), and the circuit structures of each of the delay branches 1 to w may be the same, for example, each of the delay branches includes at least three nand gates and one inverter. Specifically, the delay branch 1 includes at least three NAND gates NAND0_1 to NAND0_3 and an inverter INV0, and the delay branch 2 includes at least three NAND gates NAND1_1 to NAND1_3 and an inverter INV1. One input end of the NAND gate NAND0_1 is coupled to one input end of the NAND gate NAND0_2 and is connected to VCLK, the other input end of the NAND gate NAND0_1 is coupled to the input end of the inverter INV0 and is connected to the control signal D0, the output end of the NAND gate NAND0_1 is coupled to one input end of the NAND gate NAND1_1 of the delay branch 2 and one input end of the NAND gate NAND1_2, the other input end of the NAND gate NAND0_2 is coupled to the output end of the inverter INV0, the output end of the NAND gate NAND0_2 is coupled to one input end of the NAND gate NAND0_3, the other input end of the NAND gate NAND0_3 is coupled to the output end of the NAND gate NAND1_3 in the delay branch 2, and the clkd end of the NAND gate NAND0_3 outputs the clock signal out after the delay of the delay unit 10 a. The other input end of the NAND gate NAND1_1 is coupled to the input end of the inverter INV1 and is connected with the control signal D1, the other input end of the NAND gate NAND1_2 is coupled to the output end of the inverter INV1, and the output end of the NAND gate NAND1_2 is coupled to one input end of the NAND gate NAND 1_3. By analogy, the cascading of w delay branches 1-w in the coarse delay unit 10a may be completed, thereby forming a delay line in the coarse delay unit 10 a.

The number of delay branches connected to the coarse delay unit 10a may be gradually increased or decreased by changing the control signals D0 to Dw by the control circuit 13, that is, the number of nand gates connected to the delay line of the coarse delay unit 10a may be gradually increased or decreased, so as to gradually adjust the total delay of CKout with respect to VCLK, thereby implementing steps S1 to S4 described above. Each time a delay branch is added, the total delay of CKout relative to VCLK is increased (i.e., the adjustment direction is adjusted to the right) by a minimum coarse adjustment step (i.e., 1C), and each time a delay branch is reduced, the total delay of CKout relative to VCLK is reduced (i.e., the adjustment direction is adjusted to the left) by a minimum coarse adjustment step (i.e., 1C), so that the minimum coarse adjustment step 1C represents an increase or decrease in the delay of 2 (or other) nand gates.

Specifically, when the control signal D0 is 0 and D1-Dw are all 1 at the beginning, the access delay branch 1, VCLK is output as CKout after only the delays of the NAND gates NAND0_2 and NAND0_3, and CKout is delayed by only the minimum coarse tuning step 1C relative to VCLK. If the rising edge of CKout does not reach the designated position, the control signal D0 is further adjusted to 1, D1 is 0, D2-Dw are maintained to 1, delay branch 2 is connected, VCLK is outputted as CKout through 4 NAND gates of NAND gates NAND0_1, NAND1_2, NAND1_3 and NAND0_3, CKout is delayed by 2C … … with respect to VCLK, and so on.

Obviously, by the control circuit 13 changing the control signals D0 to Dw of the outputs thereof stepwise, the total delay generated by the coarse delay unit 10a and the adjustment step size for controlling the total delay of the coarse delay unit 10a can be changed until the rising edge of CKout reaches the designated position of VCLK. The adjustment step of the total delay of the coarse delay unit 10a is related to the delay of the nand gate through which VCLK passes, and the change (or jitter) of the power supply voltage VDD of the DLL causes the delay of the accessed nand gate to change. In the DLL of the present embodiment, when the rising edge of CKout reaches the right side of the falling edge of VCLK in the coarse delay adjustment process with the larger first coarse adjustment step Δt1, the control circuit 13 can force the rising edge of CKout to adjust at least one beat to the right with the larger first coarse adjustment step Δt1 by maintaining the control signals D0 to Dw, thereby reducing the probability that the power noise returns the rising edge of CKout to the left side of the falling edge of VCLK, and thus the total locking time of the DLL is less affected by the power noise.

It should be understood that the above-mentioned schematic diagram of the delay line of the coarse tuning delay unit 10a is merely an example, and the delay line (i.e. each delay branch of the cascade) may be implemented by other circuits.

Based on the same inventive concept, please refer to fig. 8, an embodiment of the present invention further provides a memory device, which includes the DLL of the present invention, wherein the DLL receives an external clock signal VCLK from outside the memory device and outputs a corresponding internal clock signal DQS, the internal clock signal DQS selects a pulse signal for data of the memory device, and the DLL locks after adjusting the internal clock signal DQS to be consistent with the external clock signal VCLK.

The memory device also has internal circuitry (not labeled) having a memory array for storing data, which uses the internal clock signal DQS to collect corresponding data DQ in the memory array for a data read operation.

The foregoing description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way, and any alterations and modifications made by those skilled in the art in light of the above disclosure shall fall within the scope of the present invention.

Claims

1. The phase locking method of the delay phase locked loop is characterized in that in the locking process of the delay phase locked loop, coarse delay adjustment is performed first, and then fine delay adjustment is performed until the phases of an internal clock signal output by the delay phase locked loop and an external clock signal received by the delay phase locked loop are consistent, wherein the step of performing coarse delay adjustment by the delay phase locked loop comprises the following steps:

2. A phase locking method as defined in claim 1, wherein the second coarse step is a minimum coarse step of the delay phase locked loop, the first coarse step is p times the second coarse step, wherein p is a positive integer, and in step S2, the internal clock signal is forced to adjust one beat to the right as a whole with the first coarse step.

3. The phase locking method as claimed in claim 1 or 2, wherein after step S3, the step of performing coarse delay adjustment by the delay locked loop further comprises: and S4, continuing coarse adjustment of delay by the second coarse adjustment step length, so that the whole internal clock signal is adjusted to the left by a plurality of beats until the rising edge of the internal clock signal reaches the left side of the next rising edge after the falling edge of the external clock signal.

4. A phase locking method as claimed in claim 3, wherein the step of delay-locked loop performing delay fine tuning comprises:

s5, finely adjusting delay by a first fine adjustment step smaller than the second coarse adjustment step, so that the internal clock signal is integrally adjusted to the right by a plurality of beats until the rising edge of the internal clock signal reaches the right side of the next rising edge after the falling edge of the external clock signal again;

s6, finely adjusting delay by a second fine step smaller than the first fine step, so that the internal clock signal is integrally adjusted to the left by a plurality of beats until the rising edge of the internal clock signal reaches the left side of the next rising edge after the falling edge of the external clock signal again;

and S7, finely adjusting delay by the second fine adjustment step length so that the whole internal clock signal is adjusted to the right by a plurality of beats until the rising edge of the internal clock signal reaches the right side of the next rising edge after the falling edge of the external clock signal again.

5. A phase locking method as defined in claim 4, wherein the second fine step is a minimum fine step of the delay phase locked loop, the second coarse step is n times the second fine step, the first fine step is m times the second fine step, where m and n are both powers of 2, and m is less than n.

6. The phase locking method of claim 4, further comprising: and S8, when the number of times that the rising edge of the internal clock signal passes through to the left side or the right side of the next rising edge after the falling edge of the external clock signal reaches a certain threshold value, judging that the phases of the internal clock signal and the external clock signal are consistent.

7. A delay locked loop, comprising:

8. A delay locked loop as defined in claim 7, wherein the second coarse step is a minimum coarse step of the delay chain, the first coarse step is p times the second coarse step, wherein p is a positive integer; in performing coarse delay adjustment, the control circuit is further configured to: in step S2, the delay chain is controlled to continue coarse tuning the delay with the first coarse tuning step to force the internal clock signal to adjust one beat to the right as a whole.

9. The delay locked loop of claim 7, wherein in performing coarse delay adjustment, the control circuit is further configured to: after step S3, step S4 is performed, and the delay chain is controlled to continue coarse tuning the delay with the second coarse tuning step, so that the internal clock signal is adjusted to the left by a plurality of beats as a whole, until the rising edge of the internal clock signal reaches the left side of the next rising edge after the falling edge of the external clock signal.

10. The delay locked loop of claim 9, wherein in performing delay fine tuning, the control circuit is further configured to perform the steps of:

s5, controlling the delay chain to finely adjust delay with a first fine adjustment step length smaller than the second coarse adjustment step length, so that the internal clock signal is integrally adjusted to the right by a plurality of beats until the rising edge of the internal clock signal reaches the right side of the next rising edge after the falling edge of the external clock signal again;

s6, controlling the delay chain to finely adjust delay with a second fine adjustment step length smaller than the first fine adjustment step length, so that the internal clock signal is integrally adjusted to the left by a plurality of beats until the rising edge of the internal clock signal reaches the left side of the next rising edge after the falling edge of the external clock signal again;

and S7, controlling the delay chain to finely adjust the delay by the second fine adjustment step length so that the whole internal clock signal is adjusted to the right by a plurality of beats until the rising edge of the internal clock signal reaches the right side of the next rising edge after the falling edge of the external clock signal again.

11. A delay locked loop as defined in claim 10, wherein the second fine tuning step is a minimum fine tuning step of the delay locked loop, the second coarse tuning step is n times the second fine tuning step, the first fine tuning step is m times the second fine tuning step, wherein m and n are both powers of 2, and m is less than n.

12. A delay locked loop as claimed in any one of claims 7 to 11, wherein said control circuit comprises a state machine coupled to said delay chain, said state machine having a state indication signal provided therein, said state indication signal toggling the level of said external clock signal according to the rising edge of said internal clock signal, said state machine entering a different state according to the toggling of said state indication signal, and said state machine being in a different state, controlling said delay chain to adjust the delay in a different adjustment step or adjustment direction, wherein said state machine determines to enter the state of said step S3 from the state of said step S1 according to the toggling of said state indication signal, said state machine forcing said delay chain to maintain said adjustment step and adjustment direction of said step S1 for at least one beat before controlling said delay chain to adjust said step S3.

13. The delay locked loop of claim 12, further comprising:

14. A delay locked loop as claimed in any one of claims 7 to 11 or 13, further comprising configuration circuitry coupled to said control circuitry for configuring said control circuitry to perform or skip step S2 in controlling said delay chain to perform coarse delay adjustment.

15. The delay locked loop of claim 14, wherein the configuration circuit is an electronic fuse or a one-time programmable memory.

16. A memory device comprising a delay locked loop as claimed in any one of claims 7 to 15, said delay locked loop receiving an external clock signal from outside said memory device and outputting an internal clock signal delayed with respect to said external clock signal, said internal clock signal selecting a pulse signal for data of said memory device, said delay locked loop locking after adjusting said internal clock signal to be phase coincident with said external clock signal.