CN117674821A - Analog signal multiplier circuit - Google Patents
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Abstract
The invention relates to the technical field of circuit design, in particular to an analog signal multiplier circuit. The invention provides an analog signal multiplier circuit, which comprises a first input end, a second input end and an output end, wherein the analog signal multiplier circuit also comprises a first current mirror circuit, a reference end of the first current mirror circuit is connected with the first input end, and the output end of the first current mirror circuit is the output end of the analog signal multiplier circuit; one end of the fixed resistor circuit is connected with the output end of the first current mirror circuit, and the other end of the fixed resistor circuit is connected with the grounding end; and one end of the variable resistance circuit is connected with the first input end, the other end of the variable resistance circuit is connected with the grounding end, and the adjusting end is connected with the second input end. The analog signal multiplier circuit provided by the invention can reduce the influence of factors such as process parameters of electric elements such as field effect transistors and the like and environmental temperature on output signals by adjusting circuit design, thereby improving the accuracy and stability of the operation work of the multiplier circuit.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to an analog signal multiplier circuit.
Background
Multiplication circuit (Multi)plying circuit) is an electronic device or circuit that performs the multiplication of two mutually uncorrelated analog signals. The most widely used multiplication circuit in the prior art is the gilbert cell multiplier. As shown in FIG. 1, the Gilbert cell multiplier circuit mainly comprises three pairs of differential amplifiers, specifically a field effect transistor M 01 -M 06 Each matched in pairs. M is M 01 、M 02 Differential amplifier and M 03 、M 04 The input signals of the differential amplifier are V in And the output ends of the two differential amplifiers are short-circuited, i.e. output signal V out ＝Av1*V in -Av2*V in ＝(Av1-Av2)*V in . Wherein Av1 and Av2 are M respectively 01 、M 02 Differential amplifier and M 03 、M 04 The gains of the differential amplifier are formed, and Av1 and Av2 are respectively formed by field effect transistors M 05 、M 06 Is determined by the current magnitude of V cont1 、V cont2 And (5) controlling.
Specifically, the gain av= -gm×r of the differential amplifier is known D Where gm is the transconductance of the field effect transistor. Transconductance of a semiconductor deviceWherein u is n 、C ox The w and L are the technological parameters of the field effect transistorI D Is the saturation current of the field effect transistor. Saturation current->Combining the symmetrical characteristic of the difference to obtain I D1＝ 1/2I D5 Will I D And gm is brought into the gain Av formula, the gain Av is obtainedIn the same way, the method can be used for preparing the composite material,setting upField effect transistor M 01 -M 04 Technological parameters are the same, field effect tube M 05 、M 06 The process parameters are the same, finally the ∈>I.e. output signal V out And input signal V in Sum (V) cont1 -V cont2 ) Is related to the product of (a).
However, in the multiplier circuit of the prior art, the output signal V out Also with the technological parameters of the field effect transistorHowever, k is greatly affected by the manufacturing process of the field effect transistor and the ambient temperature, so that the overall temperature and process stability of the multiplier circuit are poor.
Disclosure of Invention
In view of the above, the present invention provides an analog signal multiplier circuit. The analog signal multiplier circuit provided by the invention can reduce the influence of factors such as process parameters of electric elements such as field effect transistors and the like and environmental temperature on output signals by adjusting circuit design, thereby improving the accuracy and stability of the operation work of the multiplier circuit.
In the technical scheme of the invention, the analog signal multiplier circuit comprises a first input end, a second input end, an output end and a first current mirror circuit, wherein a reference end of the first current mirror circuit is connected with the first input end, and the output end of the first current mirror circuit is the output end of the analog signal multiplier circuit; one end of the fixed resistor circuit is connected with the output end of the first current mirror circuit, and the other end of the fixed resistor circuit is connected with the grounding end; and one end of the variable resistance circuit is connected with the first input end, the other end of the variable resistance circuit is connected with the grounding end, and the adjusting end is connected with the second input end.
According to the technical scheme of the invention, the reference end of the first current mirror circuit is respectively connected with the first input end and the variable resistance circuit, namely, the current of the reference end of the first current mirror circuit is the ratio of the first input signal of the first input end to the resistance value of the variable resistance circuit. The second input signal with the second input end controls and adjusts the resistance value of the variable resistance circuit, wherein the resistance value of the variable resistance circuit is the ratio of the technological parameter of the variable resistance circuit to the second input signal, namely the reference end current of the first current mirror circuit is related to the first input signal, the product of the second input signal and the technological parameter of the variable resistance circuit. The reference end current of the first current mirror circuit is mirrored to the output end of the first current mirror circuit, the output end of the first current mirror circuit is connected with a fixed resistance circuit, the output end of the first current mirror circuit, namely the output signal of the analog signal multiplier circuit, is the product of the output end current of the first current mirror circuit and the resistance value of the fixed resistance circuit, so that the fixed resistance circuit is matched with the technological parameters of the variable resistance circuit, the influence of the technological parameters on the output signal of the analog signal multiplier circuit is counteracted, and the accuracy and the stability of the operation work of the multiplier circuit are improved.
Preferably, in the technical scheme of the invention, the first current mirror circuit in the analog signal multiplier circuit comprises a first constant current field effect transistor and a second constant current field effect transistor, the reference end of the first current mirror circuit is the drain electrode of the first constant current field effect transistor, the output end of the first current mirror circuit is the drain electrode of the second constant current field effect transistor, the source electrodes of the first constant current field effect transistor and the second constant current field effect transistor are connected and connected to the power supply end, and the grid electrodes of the first constant current field effect transistor and the second constant current field effect transistor are connected and connected to the reference end of the first current mirror circuit.
According to the technical scheme of the invention, the current mirror circuit formed by the two field effect transistors can accurately copy the current signal of the reference end to the output end, thereby playing a role of a current control current source. In addition, the influence of the parameters of the electric element on the current output can be avoided as much as possible by matching the parameters of the two field effect transistors.
In the technical scheme of the invention, a variable resistor circuit in an analog signal multiplier circuit is composed of a first field effect transistor, a grid electrode of the first field effect transistor is connected with a second input end, a drain electrode of the first field effect transistor is respectively connected with a first input end and a reference end of a first current mirror circuit, and a source electrode of the first field effect transistor is connected with a grounding end. According to the technical scheme of the invention, the first field effect transistor is enabled to work in the variable resistance area, so that the drain current of the first field effect transistor is changed along with the input voltage, and the effect of resistance is realized.
Preferably, in the technical scheme of the present invention, the analog signal multiplier circuit further includes a first input adjusting circuit connected between the first input terminal and the variable resistance circuit, the first input adjusting circuit includes an amplifier and a first input field effect transistor, the non-inverting input terminal of the amplifier is connected to the first input terminal, the inverting input terminal of the amplifier is connected to the variable resistance circuit, and the output terminal of the amplifier is connected to the gate of the first input field effect transistor; the drain electrode of the first input field effect tube is connected with the reference end of the first current mirror circuit, and the source electrode of the first input field effect tube is respectively connected with the variable resistance circuit and the inverting input end of the amplifier.
According to the technical scheme of the invention, the first input signal of the first input end is input to the non-inverting input end of the amplifier, the amplifier is in short-circuit arrangement, the inverting input end of the amplifier is also the first input signal of the first input end, and the first input signal of the first input end is input to the reference end of the first current mirror circuit through the first input field effect transistor.
Similarly, in the technical scheme of the invention, the analog signal multiplier circuit further comprises a second input regulating circuit, wherein the second input regulating circuit is connected between the second input end and the regulating end of the variable resistance circuit, the second input regulating circuit comprises a second input field effect transistor, the grid electrode of the second input regulating circuit is connected with the second input end, and the source electrode of the second input regulating circuit is connected with the grounding end through a first resistor; the reference end of the second current mirror circuit is connected with the drain electrode of the second input field effect transistor; the drain electrode of the third input field effect transistor is connected with the output end of the second current mirror circuit, the source electrode of the third input field effect transistor is connected with the ground end through the second resistor, and the grid electrode of the third input field effect transistor is respectively connected with the output end of the second current mirror circuit and the regulating end of the variable resistance circuit; and the drain electrode of the fourth input field effect tube is connected with the source electrode of the third input field effect tube through the second resistor, the source electrode is connected with the grounding end, and the grid electrode is connected with the drain electrode of the fourth input field effect tube. And transmitting a second input signal to the variable resistance circuit through a second input adjusting circuit, and adjusting the resistance value of the variable resistance circuit. And the process parameters of the electric elements at the input end are counteracted by the parameter setting of the input field effect transistor, and the influence of the parameters of the electric elements on the current output is utilized.
In the same technical scheme of the invention, the second current mirror circuit in the analog signal multiplier circuit comprises a third constant current field effect transistor and a fourth constant current field effect transistor, the reference end of the second current mirror circuit is the drain electrode of the third constant current field effect transistor, the output end of the second current mirror circuit is the drain electrode of the fourth constant current field effect transistor, the sources of the third constant current field effect transistor and the fourth constant current field effect transistor are connected and connected with the power supply end, and the grids of the third constant current field effect transistor and the fourth constant current field effect transistor are connected and connected with the reference end of the second current mirror circuit.
According to the technical scheme of the invention, the current mirror circuit formed by the two field effect transistors can accurately copy the current signal of the reference end to the output end, thereby playing a role of a current control current source. In addition, the influence of the parameters of the electric element on the current output can be avoided as much as possible by matching the parameters of the two field effect transistors.
In the technical scheme of the invention, the fixed resistor circuit in the analog signal multiplier circuit is composed of a second field effect transistor, the drain electrode of the second field effect transistor is connected with the output end, and the source electrode of the second field effect transistor is connected with the grounding end. According to the technical scheme of the invention, the drain current of the second field effect transistor is changed along with the input voltage, so that the effect of resistance is realized.
In the technical scheme of the invention, the analog signal multiplier circuit further comprises an output regulating circuit, wherein the output regulating circuit is connected with the grid electrode of the second field effect transistor, the output regulating circuit comprises an output field effect transistor, the drain electrode of the output regulating circuit is connected with the power supply end and the grid electrode of the second field effect transistor, the source electrode of the output regulating circuit is connected with the ground end, and the grid electrode of the output regulating circuit is connected with the drain electrode of the output field effect transistor; the third resistor is connected between the drain electrode of the output field effect transistor and the grid electrode of the second field effect transistor; one end of the current source is connected with the power end, and the other end of the current source is respectively connected with the grid electrode of the second field effect transistor and the third resistor. According to the technical scheme of the invention, the technological parameters of the electric element at the output end can be counteracted by the parameter setting of the output field effect transistor, and the influence of the parameters of the electric element on the current output is utilized.
Drawings
FIG. 1 is a schematic diagram of a prior art multiplier circuit;
FIG. 2 is a schematic diagram of an analog signal multiplier provided in an embodiment of the present invention;
fig. 3 is a schematic diagram of a preferred analog signal multiplier provided in an embodiment of the present invention.
Reference numerals illustrate: 1-first current mirror circuit, 2-variable resistance circuit, 3-fixed resistance circuit, 4-first input regulation circuit, 41-amplifier, 5-second input regulation circuit, 51-second current mirror circuit, 6-output regulation circuit, power supply terminal VDD, ground terminal GND, current source I 0 Field effect transistor M 01 -M 06 Output field effect transistor M 0 First field effect transistor M 1 Second field effect transistor M 2 First constant current field effect transistor M 11 Second constant current field effect transistor M 12 Third constant current field effect transistor M 13 Fourth constant current field effect transistor M 14 First input field effect transistor M 21 Second input field effect transistor M 22 Third input field effect transistor M 23 Fourth input field effect transistor M 24 First resistor R 1 A second resistor R 2 Third resistor R 3 First input signal V A Second input signal V B Output signal V out 。
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Fig. 2 is a schematic diagram of an analog signal multiplier provided in an embodiment of the invention.
In an embodiment of the invention, as shown in FIG. 2, an analog signal multiplier circuit is providedComprises a first input end, a second input end and an output end, wherein the first input end is connected with a first input signal V A The second input end is connected with the second input signal V B The analog signal multiplier circuit multiplies the first input signal V A And a second input signal V B Multiplication is carried out to obtain an output signal V out Outputs via the output terminal.
The analog signal multiplier circuit also comprises a first current mirror circuit 1, wherein the first current mirror circuit 1 comprises a first constant current field effect transistor M 11 And a second constant current field effect transistor M 12 The reference end of the first current mirror circuit 1 is a first constant current field effect transistor M 11 The output end of the first current mirror circuit 1 is a second constant current field effect transistor M 12 Drain electrode of the first constant current field effect transistor M 11 And a second constant current field effect transistor M 12 A first constant current field effect transistor M connected to the source electrode of the power supply terminal VDD 11 Gate electrode of (c) and second constant current field effect transistor M 12 The gate of the first constant current field effect transistor M is connected with the reference end of the first current mirror circuit 1 11 Is formed on the drain electrode of the transistor. The reference end of the first current mirror circuit 1 is connected with the first input end to receive the first input signal V A The output end of the first current mirror circuit 1 sends out an output signal V for the output end of the analog signal multiplier circuit out 。
First constant current field effect transistor M 11 And a second constant current field effect transistor M 12 The first current mirror circuit 1 can play a role of mirror image shunt, and accurately copy the current signal of the reference end of the first current mirror circuit 1 to the output end of the first current mirror circuit 1, so that the second constant current field effect transistor M 12 Drain current I of (2) M12 Equal to the first constant current field effect transistor M 11 Drain current I of (2) M11 Acting as a current-controlled current source. And, can pass through the first constant current field effect transistor M 11 And a second constant current field effect transistor M 12 Parameter matching is performed to avoid the influence of the parameters of the electrical components on the current output as far as possible.
Variable resistance circuit 2, one end of variable resistance circuit 2 is connected to the first input terminal, and the other end is connected to the ground terminalGND, the regulation end is connected with the second input end. The reference end of the first current mirror circuit 1 is connected with the first input end and the variable resistance circuit 2, and the reference end current of the first current mirror circuit 1 is the first input signal V of the first input end A The ratio of the reference end current of the first current mirror circuit 1 to the resistance value R of the variable resistance circuit is the first constant current field effect transistor M 11 Drain current I of (2) M11 ＝V A R, mirror image copy is carried out by the first current mirror circuit 1, and the current at the output end of the first current mirror circuit 1 is the second constant current field effect transistor M 12 Drain current I of (2) M12 ＝V A /R。
The adjusting terminal of the variable resistance circuit 2 is connected to the second input terminal for receiving the second input signal V B Resistance R of the variable resistor circuit 2 and the second input signal V B Inversely proportional, i.e. r=k/V B Where k is a constant related to the parameters of the variable resistance circuit 2 itself. Let r=k/V B Is brought into the above formula I M12 ＝V A R is available, I M12 ＝V A *V B /k。
A fixed resistor circuit 3, one end of which is connected with the output end of the first current mirror circuit 1, and the other end of which is connected with the ground end GND; the output end current of the first current mirror circuit 1 is I M12 ＝V A *V B The resistance of the first current mirror circuit 1 is the resistance R of the fixed resistance circuit 3 0 The output voltage of the first current mirror circuit 1, i.e. the output signal V, can be obtained out ＝V A *V B* R 0 /k。
In summary, on the basis of the above circuit structure, the process parameters of the fixed resistance circuit 3 and the variable resistance circuit 2 are matched to cancel the influence V of the process parameters on the output signal of the analog signal multiplier circuit out Reducing influence on the output signal V out To make the output signal V out Can approach to only two input signals V A 、V B The related signals are used for improving the accuracy and stability of the operation of the analog signal multiplier circuit.
Fig. 3 is a schematic diagram of a preferred analog signal multiplier provided in an embodiment of the present invention.
As shown in fig. 3, a preferred analog signal multiplier is provided in an embodiment of the present invention. The variable resistance circuit 2 in the analog signal multiplier circuit is composed of a first field effect transistor M 1 Is composed of the first field effect transistor M 1 The gate of which is connected to the second input terminal, the drain is connected to the first input terminal and the reference terminal of the first current mirror circuit 1, respectively, and the source is connected to the ground terminal GND. Make the first field effect transistor M 1 Operate in the variable resistance region to make the first FET M 1 Is associated with the drain current of the first field effect transistor M 1 The input voltage of the gate of (c) is varied to achieve the effect of resistance.
The analog signal multiplier circuit further comprises a first input regulator circuit 4 connected between the first input terminal and the variable resistance circuit 2, the first input regulator circuit 4 comprising an amplifier 41 and a first input FET M 21 The non-inverting input of the amplifier 41 is connected to the first input for receiving the first input signal V A The inverting input end of the amplifier 41 is connected with the variable resistance circuit 2, and the output end of the amplifier 41 is connected with the first input field effect transistor M 21 A gate electrode of (a); first input field effect transistor M 21 The drain electrode of the first input field effect transistor M is connected with the reference end of the first current mirror circuit 1 21 The sources of (a) are connected to the variable resistance circuit 2 and the inverting input terminal of the amplifier 41, respectively.
In the first input adjusting circuit 4, the first input signal V at the first input terminal A Is input to the non-inverting input of the amplifier 41, and the voltage value at the inverting input of the amplifier 41 is equal to the first input signal V at the first input according to the imaginary short characteristic of the amplifier 41 A The first input signal of the first input terminal is input to the reference terminal of the first current mirror circuit 1 through the first input field effect transistor. First input signal V A ＜V GS1 -V TH1 First field effect transistor M 1 Operating in the linear region, the first FET M 1 The resistance formula of the linear region of the field effect transistor is satisfied:obtainingCombine the first input signal V A Applied to the first fet M via the inverting input of the amplifier 41 1 Drain of->Wherein I is 1 V is the current value of the first current mirror circuit 1 GS1 Is a first field effect transistor M 1 Gate-source voltage of V TH1 Is a first field effect transistor M 1 U is equal to the threshold voltage of (u) n Carrier mobility, C, of field effect transistor ox The unit area capacitance of the gate oxide layer is w is the width of the field effect transistor channel, L is the length of the field effect transistor channel, and u n 、C ox And w and L are the technological parameters of the field effect transistor.
Similarly, in the embodiment of the present invention, the analog signal multiplier circuit further comprises a second input adjusting circuit 5 connected to the second input terminal and the adjusting terminal of the variable resistor circuit 2 (first field effect transistor M 1 Gate of (c) the second input regulating circuit 5 comprises a second input field effect transistor M 22 Second input field effect transistor M 22 A gate connected to the second input terminal, a source connected to the first resistor R 1 Is connected to the ground GND; the reference end of the second current mirror circuit 51 is connected with the second input field effect transistor M 22 A drain electrode of (2); third input field effect transistor M 23 The drain electrode of the second current mirror circuit 51 is connected with the output end, and the source electrode passes through the second resistor R 2 Connected to the ground GND, and a gate connected to the output of the second current mirror circuit 51 and the regulating end of the variable resistor circuit 2 (first FET M 1 A gate of (2); fourth input field effect transistor M 24 The drain electrode passes through a second resistor R 2 Is connected with a third input field effect tube M 23 The source electrode is connected to the ground GND, and the gate electrode is connected to the fourth input FET M 24 Is formed on the drain electrode of the transistor.
Specifically, the second current mirror circuit 51 includes a third constant current field effect transistor M 13 And a fourth constant current field effect transistor M 14 Second currentThe reference end of the mirror circuit 51 is a third constant current field effect transistor M 13 The output end of the second current mirror circuit 51 is a fourth constant current field effect transistor M 14 Drain electrode of the third constant current field effect transistor M 13 And a fourth constant current field effect transistor M 14 A third constant current field effect transistor M connected with the source electrode of the power supply terminal VDD 13 Gate electrode of (c) and fourth constant current field effect transistor M 14 Is connected to the reference terminal of the second current mirror circuit 51, namely, the third constant current field effect transistor M 13 Is formed on the drain electrode of the transistor. The reference terminal of the second current mirror circuit 51 is connected to the first input terminal for receiving the second input signal V B The output end of the second current mirror circuit 51 is connected to the adjusting end (first field effect transistor M 1 A gate electrode of (c).
Third constant current field effect transistor M 13 And a fourth constant current field effect transistor M 14 The second current mirror circuit 51 can play a role of mirror image shunt, and accurately copy the current signal of the reference end of the second current mirror circuit 51 to the output end of the second current mirror circuit 51, so that the fourth constant current field effect transistor M 14 Drain current I of (2) M14 Equal to the third constant current field effect transistor M 13 Drain current I of (2) M13 Acting as a current-controlled current source. And, can pass through the third constant current field effect transistor M 13 And a fourth constant current field effect transistor M 14 Parameter matching is performed to avoid the influence of the parameters of the electrical components on the current output as far as possible.
Second input signal V B Input to a second input field effect transistor M 22 Can obtain V B ＝V GS22 +R 1 *I 2 Wherein V is GS22 Is a second input field effect transistor M 22 Gate-source voltage of I 2 Is the current value of the second current mirror circuit 51. Similarly, a first field effect transistor M 1 Is V GS1 ＝V GS23 +R 1 *I 2 +V GS24 . In the present embodiment, the second input field effect transistor M is symmetrically arranged 22 And a third input field effect transistor M 23 Parameters (u) n 、C ox W, L, etc.) match, second input field effect transistor M 22 And a third input field effect transistor M 2 All work in the saturation region, and according to the field effect transistor saturation region current formula:and a second input field effect transistor M 22 And a third input field effect transistor M 23 The drain currents of the second input field effect transistor M are equal to each other 22 And a third input field effect transistor M 23 Is equal to the gate-source voltage of V GS23 ＝V GS22 . The equality relation V is set GS23 ＝V GS22 Substituted into V B ＝V GS22 +R 1 *I 2 And V GS1 ＝V GS23 +R 1 *I 2 +V GS24 In the process, a first field effect transistor M can be obtained 1 Is V GS1 ＝V B +V GS24 。
Combining the first input signal V A Input to a first FET M 1 Gate of (2), i.eWill V GS1 ＝V B +V GS24 Substituting the above formula to obtainI.e. < ->
Similarly, in the present embodiment, the fixed resistor circuit 3 in the analog signal multiplier circuit is formed by the second fet M 2 Is composed of the second field effect transistor M 2 The drain of (2) is connected to the output terminal and the source is connected to the ground terminal GND. Make the second field effect transistor M 2 Is associated with the drain current of the second field effect transistor M 2 The input voltage of the gate of (c) is varied to achieve the effect of resistance.
Further, in the present embodiment, the analog signal multiplier circuit further includes an output regulator circuit 6 connected to the second fet M 2 Is output to regulate electricityThe circuit comprises an output field effect transistor M 0 Output field effect transistor M 0 Is connected with the power supply terminal VDD and the second field effect transistor M 2 The source electrode is connected with the ground end GND, and the gate electrode is connected with the output field effect transistor M 0 A drain electrode of (2); third resistor R 3 Is connected to the output field effect tube M 0 Drain electrode of (d) and second field effect transistor M 2 Is between the gates of (a); current source I 0 One end is connected with the power supply end VDD, and the other end is respectively connected with the second field effect tube M 2 Gate of (d) and third resistor R 3 。
Current source I 0 The signal of (2) is input into the fixed resistance circuit 3, namely the second field effect transistor M 2 Can obtain V GS2 ＝V GS0 +R 3 *I 0 Second field effect transistor M 2 The drain electrode of (2) is connected with the output end and outputs a signal V OUT ＜V GS2 -V TH2 Second field effect transistor M 2 Operating in the linear region, the second FET M 2 The resistance formula of the linear region of the field effect transistor is satisfied:obtain->And then obtainWherein I is 1 V is the current value of the first current mirror circuit 1 GS0 To output field effect transistor M 0 Gate-source voltage of V TH2 Is a second field effect transistor M 2 U is equal to the threshold voltage of (u) n Carrier mobility, C, of field effect transistor ox The unit area capacitance of the gate oxide layer is w is the width of the field effect transistor channel, L is the length of the field effect transistor channel, and u n 、C ox And w and L are the technological parameters of the field effect transistor.
In summary, it willSubstituted intoCan be obtainedRegulating output field effect transistor M 0 And a fourth input field effect transistor M 24 Aspect ratio of (2) such that V GS0 ≈V TH2 ，V GS24 ≈V TH1 Simplify the above->
By the multiplier circuit, the process parameters of the fixed resistance circuit and the variable resistance circuit are matched, and the process parameters (u) n 、C ox Etc.) to the output signal of the analog signal multiplier circuit, thereby improving the accuracy and stability of the operation of the multiplier circuit.
The technical solution of the present invention has been described so far with reference to the accompanying drawings. However, it will be readily appreciated by those skilled in the art that the scope of the present invention is not limited to the above-described specific embodiments. Equivalent modifications and substitutions for related technical features may be made by those skilled in the art without departing from the principles of the present invention, and such modifications and substitutions will fall within the scope of the present invention.
Claims (8)
1. An analog signal multiplier circuit comprising a first input, a second input and an output, the analog signal multiplier circuit further comprising
The reference end of the first current mirror circuit is connected with the first input end, and the output end of the first current mirror circuit is the output end of the analog signal multiplier circuit;
one end of the fixed resistor circuit is connected with the output end of the first current mirror circuit, and the other end of the fixed resistor circuit is connected with the grounding end;
and one end of the variable resistance circuit is connected with the first input end, the other end of the variable resistance circuit is connected with the grounding end, and the adjusting end is connected with the second input end.
2. The analog signal multiplier circuit of claim 1, wherein the first current mirror circuit comprises a first constant current field effect transistor and a second constant current field effect transistor, wherein the reference terminal of the first current mirror circuit is the drain electrode of the first constant current field effect transistor, the output terminal of the first current mirror circuit is the drain electrode of the second constant current field effect transistor, the source electrode of the first constant current field effect transistor and the source electrode of the second constant current field effect transistor are connected and connected to a power supply terminal, and the gate electrode of the first constant current field effect transistor and the gate electrode of the second constant current field effect transistor are connected and connected to the reference terminal of the first current mirror circuit.
3. An analog signal multiplier circuit according to claim 2, wherein said variable resistance circuit is formed by a first field effect transistor having a gate connected to said second input terminal, a drain connected to said first input terminal and a reference terminal of said first current mirror circuit, respectively, and a source connected to ground.
4. An analog signal multiplier circuit according to claim 3, further comprising a first input modulation circuit connected between said first input terminal and said variable resistance circuit, said first input modulation circuit comprising an amplifier and a first input field effect transistor,
the non-inverting input end of the amplifier is connected with the first input end, the inverting input end of the amplifier is connected with the variable resistance circuit, and the output end of the amplifier is connected with the grid electrode of the first input field effect transistor;
the drain electrode of the first input field effect transistor is connected with the reference end of the first current mirror circuit, and the source electrode of the first input field effect transistor is respectively connected with the variable resistance circuit and the inverting input end of the amplifier.
5. An analog signal multiplier circuit according to claim 4, further comprising a second input adjusting circuit connected between said second input terminal and an adjusting terminal of said variable resistance circuit, said second input adjusting circuit comprising
The grid electrode of the second input field effect tube is connected with the second input end, and the source electrode of the second input field effect tube is connected with the grounding end through the first resistor;
the reference end of the second current mirror circuit is connected with the drain electrode of the second input field effect transistor;
the drain electrode of the third input field effect transistor is connected with the output end of the second current mirror circuit, the source electrode of the third input field effect transistor is connected with the ground end through a second resistor, and the grid electrode of the third input field effect transistor is respectively connected with the output end of the second current mirror circuit and the regulating end of the variable resistor circuit;
and the drain electrode of the fourth input field effect tube is connected with the source electrode of the third input field effect tube through the second resistor, the source electrode of the fourth input field effect tube is connected with the ground terminal, and the grid electrode of the fourth input field effect tube is connected with the drain electrode of the fourth input field effect tube.
6. The analog signal multiplier circuit of claim 5, wherein said second current mirror circuit comprises a third constant current field effect transistor and a fourth constant current field effect transistor, wherein a reference terminal of said second current mirror circuit is a drain of said third constant current field effect transistor, an output terminal of said second current mirror circuit is a drain of said fourth constant current field effect transistor, a source of said third constant current field effect transistor and a source of said fourth constant current field effect transistor are connected to a power terminal, and a gate of said third constant current field effect transistor and a gate of said fourth constant current field effect transistor are connected to a reference terminal of said second current mirror circuit.
7. An analog signal multiplier circuit according to claim 6, wherein said fixed resistor circuit is formed by a second field effect transistor having a drain connected to the output of said analog signal multiplier circuit and a source connected to ground.
8. An analog signal multiplier circuit according to claim 7, further comprising an output regulator circuit connected to the gate of said second fet, said output regulator circuit comprising an output fet, the drain connected to the power supply terminal and the gate of said second fet, the source connected to the ground terminal, the gate connected to the drain of said output fet;
the third resistor is connected between the drain electrode of the output field effect transistor and the grid electrode of the second field effect transistor;
and one end of the current source is connected with the power supply end, and the other end of the current source is respectively connected with the grid electrode of the second field effect transistor and the third resistor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211099913.4A CN117674821A (en) | 2022-09-07 | 2022-09-07 | Analog signal multiplier circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211099913.4A CN117674821A (en) | 2022-09-07 | 2022-09-07 | Analog signal multiplier circuit |
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| CN117674821A true CN117674821A (en) | 2024-03-08 |
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| CN202211099913.4A Pending CN117674821A (en) | 2022-09-07 | 2022-09-07 | Analog signal multiplier circuit |
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