CN117673219A - Light-emitting diode chip and manufacturing method thereof - Google Patents
Light-emitting diode chip and manufacturing method thereof Download PDFInfo
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 19
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 18
- 239000012790 adhesive layer Substances 0.000 claims description 16
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- 238000003475 lamination Methods 0.000 abstract description 9
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The disclosure provides a light emitting diode chip and a manufacturing method thereof, and belongs to the technical field of semiconductors. The chip comprises: an epitaxial stack, a first electrode, and a third electrode; the epitaxial lamination comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially laminated, wherein a groove extending from the surface of the second semiconductor layer to the first semiconductor layer is formed in the epitaxial lamination; the first electrode is positioned on one side of the second semiconductor layer far away from the light-emitting layer and is electrically connected with the second semiconductor layer, and comprises a first adhesion layer, a reflecting metal layer, a first barrier layer, a compressive stress layer, a second barrier layer, a tensile stress layer and a second adhesion layer which are sequentially laminated; the third electrode is located in the groove and is electrically connected with the first semiconductor layer. The internal structure of the first electrode is stable and is not easy to damage, and the reliability of the light-emitting diode chip can be improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and in particular, to a light emitting diode chip (Light Emitting Diode, LED) and a method of fabricating the same.
Background
The LED chip is a semiconductor electronic element capable of converting electric energy into light energy, has the advantages of low power consumption, small volume, quick response time, energy conservation, environmental protection and the like, and is widely applied to various fields such as display, illumination, urban night scenes and the like.
A flip LED chip is one of the LED chips, and in the related art, the flip LED chip generally includes a substrate, an epitaxial stack, a first electrode, a second electrode, and a third electrode. The epitaxial lamination comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially laminated on a substrate, wherein the second semiconductor layer is provided with a groove exposing the first semiconductor layer. The first electrode is positioned on the second semiconductor layer, and the second electrode is connected with the first electrode. The third electrode is connected to the first semiconductor layer in the recess, and the first electrode is typically a thin metal layer with reflective capability.
The first electrode is easy to fall off or damage in the manufacturing process of the LED chip due to poor adhesiveness and thermal stability of the first electrode, so that the reliability of the LED chip is reduced.
Disclosure of Invention
The embodiment of the disclosure provides a light emitting diode chip and a manufacturing method thereof, which can improve the reliability of the light emitting diode chip.
In one aspect, embodiments of the present disclosure provide a light emitting diode chip, the light emitting diode chip including: an epitaxial stack, a first electrode, and a third electrode. The epitaxial lamination comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially laminated, and grooves extending from the surface of the second semiconductor layer to the first semiconductor layer are formed in the epitaxial lamination. The first electrode is located at one side of the second semiconductor layer far away from the light-emitting layer and is electrically connected with the second semiconductor layer, and the first electrode comprises a first adhesion layer, a reflective metal layer, a first barrier layer, a compressive stress layer, a second barrier layer, a tensile stress layer and a second adhesion layer which are sequentially stacked. The third electrode is located in the groove and is electrically connected with the first semiconductor layer.
Optionally, the compressive stress layer and the tensile stress layer are NiW layers.
Optionally, the thickness of the compressive stress layer is in the range ofThe tensile stress layer has a thickness in the range +.>
Optionally, the first barrier layer and the second barrier layer are Ni layers.
Optionally, the light emitting diode chip further includes a second electrode, the second electrode includes a first sub-electrode and a second sub-electrode, the first sub-electrode and the second sub-electrode are sequentially stacked on the first electrode, one side of the first sub-electrode, which is close to the second sub-electrode, is a Cr layer, a Pt layer and a Ti layer, which are sequentially stacked, and the Ti layer in the first sub-electrode is connected with the second sub-electrode. The third electrode comprises a third sub-electrode and a fourth sub-electrode, the third sub-electrode and the fourth sub-electrode are sequentially laminated on the first semiconductor layer, one side, close to the fourth sub-electrode, of the third sub-electrode is a Cr layer, a Pt layer and a Ti layer which are sequentially laminated, and the Ti layer of the third sub-electrode is connected with the fourth sub-electrode.
Optionally, in the first sub-electrode, the thickness of the Cr layer ranges fromThe thickness of the Pt layer is in the range of +.>The thickness of the Ti layer is in the range of +.>In the third sub-electrode, the thickness of the Cr layer is in the range +.>The thickness of the Pt layer is in the range of +.> The thickness of the Ti layer is in the range of +.>
Optionally, the light emitting diode chip further includes a passivation layer, and the passivation layer includes a first passivation layer and a second passivation layer. The first passivation layer covers the first electrode and the epitaxial stack, and the first passivation layer is provided with a first through hole exposing the first electrode and a second through hole exposing the first semiconductor layer. The first sub-electrode is connected with the first electrode through the first through hole, and the third sub-electrode is connected with the first semiconductor layer through the second through hole. The second passivation layer covers the first passivation layer, the first sub-electrode and the third sub-electrode, and the second passivation layer is respectively provided with a third through hole exposing the first sub-electrode and a fourth through hole exposing the third sub-electrode. The second sub-electrode is connected with the first sub-electrode through the third through hole, and the fourth sub-electrode is connected with the third sub-electrode through the fourth through hole. The first passivation layer comprises an aluminum oxide layer and a silicon oxide layer which are sequentially stacked on the first electrode, and the second passivation layer comprises an aluminum oxide layer and a silicon oxide layer which are sequentially stacked on the first passivation layer.
Optionally, the thickness of the alumina layer in the first passivation layer is in the range ofThe thickness of the silicon oxide layer in the first passivation layer is in the range of +.>The thickness of the alumina layer in the second passivation layer is in the range of +.>The thickness of the silicon oxide layer in the second passivation layer is in the range of
In another aspect, an embodiment of the present disclosure provides a method for manufacturing a light emitting diode chip, including: forming an epitaxial stack comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in this order, the epitaxial stack having a recess therein extending from a surface of the second semiconductor layer to the first semiconductor layer;
forming a first electrode, wherein the first electrode is positioned on one side of the second semiconductor layer far away from the light-emitting layer and is electrically connected with the second semiconductor layer, and the first electrode comprises a first adhesion layer, a reflective metal layer, a first barrier layer, a compressive stress layer, a second barrier layer, a tensile stress layer and a second adhesion layer which are sequentially stacked;
and forming a third electrode, wherein the third electrode is positioned in the groove and is electrically connected with the first semiconductor layer.
Optionally, the compressive stress layer and the tensile stress layer are NiW layers, and the compressive stress layer has a vacuum degree of 2E -3 pa ～ 4E -3 pa in the reaction chamber, the tensile stress layer is formed in a vacuum degree of 1E -3 pa ～ 2E -3 pa is formed in the reaction chamber.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that at least:
in the light emitting diode chip provided by the embodiment of the disclosure, the first electrode includes a first adhesion layer, a reflective metal layer, a first barrier layer, a compressive stress layer, a second barrier layer, a tensile stress layer and a second adhesion layer which are sequentially stacked, and the first electrode is manufactured on one side of the second semiconductor layer far away from the light emitting layer and is electrically connected with the second semiconductor layer. Wherein the first and second adhesive layers ensure the connection performance between the first electrode and other structures to which it is connected. The reflective metal layer can reflect light rays emitted to the first electrode to the light emitting surface, so that the brightness of the light emitting diode chip is increased. The first blocking layer and the second blocking layer can block the outward diffusion of the material of the reflecting metal layer, and can also protect the reflecting metal layer from oxidation or corrosion, so that the service performance of the first electrode is ensured. The compressive stress layer can generate compressive stress to increase the adhesiveness between the reflective metal layer and other structures, and the tensile stress layer can generate tensile stress to balance the compressive stress generated by the compressive stress layer, so that the stability of the reflective metal layer can be further ensured, and the stress between the structures of each layer in the first electrode can be regulated to balance the stress, so that the internal structure of the first electrode is stable and is not easy to damage, and the reliability of the light-emitting diode chip is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic cross-sectional structure of a light emitting diode chip according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of a first electrode according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram of a second electrode or a third electrode according to an embodiment of the disclosure;
fig. 4 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the disclosure.
The various labels in the figures are described below:
100: a substrate; 110: filling a leveling layer; 120, a buffer layer;
200: epitaxial lamination; 210: a first semiconductor layer; 220: a light emitting layer; 230: a second semiconductor layer;
310: a current spreading layer; 320: an insulating layer; 321: a fifth through hole; 322: a sixth through hole;
400: a first electrode; 410: a first adhesive layer; 420: a reflective metal layer; 430: a first barrier layer; 440: a compressive stress layer; 450: a second barrier layer; 460: a tensile stress layer; 470: a second adhesive layer;
500: a passivation layer; 510: a first passivation layer; 511: a first through hole; 512: a second through hole; 520: a second passivation layer; 521: a third through hole; 522: a fourth through hole;
610: a second electrode; 611: a first sub-electrode; 612: a second sub-electrode;
620: a third electrode; 621: a third sub-electrode; 622: and a fourth sub-electrode.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 is a schematic cross-sectional structure of a light emitting diode chip according to an embodiment of the disclosure, and fig. 2 is a schematic structural diagram of a first electrode according to an embodiment of the disclosure. As shown in fig. 1, the light emitting diode chip includes: an epitaxial stack 200, a first electrode 400 and a third electrode 620.
The epitaxial stack 200 includes a first semiconductor layer 210, a light emitting layer 220, and a second semiconductor layer 230 stacked in this order, and the epitaxial stack 200 has a groove extending from a surface of the second semiconductor layer 230 to the first semiconductor layer 210.
The first electrode 400 is located at a side of the second semiconductor layer 230 remote from the light emitting layer 220, and is electrically connected to the second semiconductor layer 230. The third electrode 620 is located in the groove and is electrically connected to the first semiconductor layer 210.
As shown in fig. 2, the first electrode 400 includes a first adhesive layer 410, a reflective metal layer 420, a first barrier layer 430, a compressive stress layer 440, a second barrier layer 450, a tensile stress layer 460, and a second adhesive layer 470, which are sequentially stacked, and the second adhesive layer 470 is connected to the second electrode 610.
In the light emitting diode chip provided in the embodiment of the disclosure, the first electrode 400 includes a first adhesion layer 410, a reflective metal layer 420, a first barrier layer 430, a compressive stress layer 440, a second barrier layer 450, a tensile stress layer 460, and a second adhesion layer 470, which are sequentially stacked, and the first electrode 400 is fabricated on a side of the second semiconductor layer 230 away from the light emitting layer 220 and is electrically connected to the second semiconductor layer 230. Wherein the first adhesive layer 410 and the second adhesive layer 470 secure the connection performance between the first electrode 400 and other structures to which it is connected. The reflective metal layer 420 can reflect the light emitted to the first electrode 400 to the light emitting surface, so as to increase the brightness of the led chip. The first barrier layer 430 and the second barrier layer 450 can block the outward diffusion of the material of the reflective metal layer 420, and can also protect the reflective metal layer 420 from oxidation or corrosion, thereby ensuring the performance of the first electrode 400. The compressive stress layer 440 can generate compressive stress to increase the adhesion between the reflective metal layer 420 and other structures, and the tensile stress layer 460 can generate tensile stress to balance the compressive stress generated by the compressive stress layer 440, so that the stability of the reflective metal layer 420 can be further ensured, and the stress between the structures of the first electrode 400 can be adjusted to balance the stress, so that the internal structure of the first electrode 400 is stable and is not easy to be damaged, thereby improving the reliability of the light emitting diode chip.
Alternatively, the first adhesion layer 410 and the second adhesion layer 470 are Ti layers, the reflective metal layer 420 is an Ag layer, and the first barrier layer 430 and the second barrier layer 450 are Ni layers. The Ti layer has good adhesion, and thus the first adhesion layer 410 and the second adhesion layer 470 can secure connection stability between the first electrode 400 and other structures. The Ag layer has high reflectivity, and can effectively improve the light emitting efficiency of the light emitting diode chip. The Ni layer has high hardness and good corrosion resistance, can prevent the Ag layer from diffusing, and can prevent the Ag layer from being oxidized or corroded.
Optionally, the compressive stress layer 440 and the tensile stress layer 460 are NiW layers.
The NiW layer is a metal layer capable of generating a larger compressive stress or tensile stress, so that the compressive stress layer 440 can generate a larger compressive stress to increase the adhesion between the reflective metal layer 420 and other structures, and the same material is used as the tensile stress layer 460, so as to achieve the effect of stress balance. Finally, the first electrode 400 with stable internal structure and less damage is obtained, thereby improving the reliability of the light emitting diode chip.
Optionally, the thickness of the compressive stress layer 440 ranges fromThe tensile stress layer 460 has a thickness in the range ofThis thickness range ensures that sufficient stress is provided, and avoids excessive stress due to excessive thickness, which in turn causes cracking or damage to the first electrode 400.
Optionally, the thickness of the compressive stress layer 440 and the tensile stress layer 460 are equal.
Illustratively, the thickness of the compressive stress layer 440 and the tensile stress layer 460 are bothThe thickness of the compressive stress layer 440 can generate larger compressive stress, and the equal thickness of the compressive stress layer 440 and the tensile stress layer 460 is convenient for generating the compressive stress and the tensile stress with the same size, thereby achieving the effect of pressure balance.
In the present embodiment, the thickness of the first adhesive layer 410 isThe thickness of the reflective metal layer 420 is +.>The thickness of the first barrier layer 430 is +.>The thickness of the compressive stress layer 440 is +.>The second barrier layer 450 has a thickness ofThe tensile stress layer 460 has a thickness of +>The thickness of the second adhesive layer 470 is +.>
The thickness ensures that the first adhesion layer 410 and the second adhesion layer 470 have good adhesion, the reflective metal layer 420 has good light reflection, the first barrier layer 430 and the second barrier layer 450 have good protection to the reflective metal layer 420, and the stress generated by the compressive stress layer 440 and the tensile stress layer 460 is moderate. The problem of too high manufacturing cost caused by too thick layers is avoided while the good performance effect of each layer is ensured.
Optionally, the light emitting diode chip further includes a substrate 100, where the substrate 100 is located on a side of the first semiconductor layer 210 away from the light emitting layer 220 and is connected to the first semiconductor layer 210. The substrate 100 may be a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate 100 may be a flat substrate or a patterned substrate.
In the embodiment of the present disclosure, one of the first semiconductor layer 210 and the second semiconductor layer 230 is a p-type layer, and the other of the first semiconductor layer 210 and the second semiconductor layer 230 is an n-type layer.
As one example, the first semiconductor layer 210 is an n-type layer and the second semiconductor layer 230 is a p-type layer.
In the embodiments of the present disclosure, the n-type layer is an n-type AlGaN layer. Optionally, the n-type AlGaN layer is doped with silicon, and the doping concentration is 1-5E 18.
Optionally, an n-type waveguide layer is further included between the n-type layer and the light-emitting layer, and the n-type waveguide layer can be used for providing electrons to improve the composite light-emitting efficiency of the light-emitting layer.
In the embodiments of the present disclosure, the n-type waveguide layer is n-type In 0.01 Ga 0.99 And N layers.
As an example, the thickness of the n-type AlGaN layer ranges from 700nm to 900nm, e.g., 800nm, n-type In 0.01 Ga 0.99 The thickness of the N layer ranges from 200nm to 300nm, for example 230nm.
In an embodiment of the present disclosure, the p-type layer comprises Mg-doped p-type Al 0.15 In 0.03 Ga 0.82 N-layer, mg-doped p-Ga 0.98 In 0.02 N-layer, mg-doped p-Al 0.11 In 0.02 Ga 0.87 An N layer and a Mg-doped p-type GaN layer. The material structure of the p-type layer optimizes the transmission characteristic of carriers, thereby improving the luminous efficiency of the light-emitting diode chip.
Optionally, an electron blocking layer is further included between the p-type layer and the light emitting layer, and the electron blocking layer can be used to reduce electron leakage from the light emitting layer.
In the embodiment of the disclosure, the electron blocking layer is a p-type AlGaN layer doped with Mg.
As an example, the thickness of the p-type AlGaN layer ranges from 30nm to 40nm, such as 33nm; p-type Al 0.15 In 0.03 Ga 0.82 The thickness of the N layer ranges from 25nm to 30nm, for example 28nm; p-type Ga 0.98 In 0.02 The thickness of the N layer ranges from 15nm to 25nm, for example 20nm; p-type Al 0.11 In 0.02 Ga 0.87 The thickness of the N layer ranges from 20nm to 30nm, for example 25nm; the thickness of the p-type GaN layer ranges from 45nm to 55nm, for example, 50nm.
In other embodiments, the n-type layer and the p-type layer may be other materials and other layer structures, which are not limited by the embodiments of the present disclosure.
Alternatively, the light emitting layer 220 may be a multiple quantum well layer. The material adopted by the multi-quantum well layer can be AlGaN/AlGaN, inAlGaN/InAlGaN or InGaN/AlGaN.
Illustratively, the multiple quantum well layer may include 3 to 8 periods of Al alternately laminated x Ga 1-x N quantum well layer and Al y Ga 1-y N quantum barrier layer, wherein 0 < x < y < 1.
As an example, in the presently disclosed embodiments, the multiple quantum well layer includes 5 periods of Al alternately stacked x Ga 1-x N quantum well layer and Al y Ga 1-y N quantum barrier layer, and Al x Ga 1-x The thickness of the N quantum well layer is 5nm, al y Ga 1-y The thickness of the N quantum barrier layer was 8nm.
Optionally, the light emitting diode chip further comprises a second electrode 610. The second electrode 610 is located at a side of the first electrode 400 remote from the substrate 100, and is connected to the first electrode 400.
In the embodiment of the present disclosure, the materials and structures of the second electrode 610 and the third electrode 620 are the same, and in other embodiments, the materials and structures of the second electrode 610 and the third electrode 620 may be different, which is not limited in the embodiment of the present disclosure. The following is an exemplary explanation taking the same material and structure of the second electrode 610 and the third electrode 620 as examples.
Fig. 3 is a schematic structural diagram of a second electrode or a third electrode according to an embodiment of the disclosure.
As shown in fig. 1, the second electrode 610 includes a first sub-electrode 611 and a second sub-electrode 612, the first sub-electrode 611 and the second sub-electrode 612 are sequentially stacked on the first electrode 400, and the first sub-electrode 611 is connected with the first electrode 400. The third electrode 620 includes a third sub-electrode 621 and a fourth sub-electrode 622, the third sub-electrode 621 and the fourth sub-electrode 622 are sequentially stacked on the first semiconductor layer 210, and the third sub-electrode 621 is connected to the first semiconductor layer 210.
As shown in fig. 3, the Cr layer, the Pt layer, and the Ti layer are sequentially stacked on the side of the first sub-electrode 611 near the second sub-electrode 612, and the Ti layer in the first sub-electrode 611 is connected to the second sub-electrode 612. The third sub-electrode 621 has a Cr layer, a Pt layer, and a Ti layer sequentially stacked on one side thereof adjacent to the fourth sub-electrode 622, and the Ti layer in the third sub-electrode 621 is connected to the fourth sub-electrode 622.
The Cr layer, the Pt layer, and the Ti layer are sequentially stacked on the side of the first sub-electrode 611 adjacent to the second sub-electrode 612, and the Cr layer, the Pt layer, and the Ti layer are sequentially stacked on the side of the third sub-electrode 621 adjacent to the fourth sub-electrode 622, so that the adhesion between the first sub-electrode 611 and the second sub-electrode 612, and between the third sub-electrode 621 and the fourth sub-electrode 622 can be further enhanced, thereby improving the reliability of the second electrode 610 and the third electrode 620.
In the embodiment of the present disclosure, the first sub-electrode 611 and the third sub-electrode 621 each include a Cr layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer, and a Ti layer, which are sequentially stacked, and the second sub-electrode 612 and the fourth sub-electrode 622 each include a Cr layer, a Pt layer, an Au layer, a Ni layer, a Pt layer, a Ti layer, and an AuSn layer, which are sequentially stacked.
In the prior art, the first sub-electrode 611 and the third sub-electrode 621 are typically a Ni layer, a Pt layer, an Au layer, a Pt layer and a Ti layer that are sequentially stacked, and compared to the material structure of the first sub-electrode 611 and the third sub-electrode 621 in the embodiment of the present disclosure, the manufacturing cost is lower while the adhesion between the electrodes is increased.
In other embodiments, the first sub-electrode 611, the second sub-electrode 612, the third sub-electrode 621, and the fourth sub-electrode 622 may also be different combinations of other metal materials, which are not limited by the embodiments of the present disclosure.
Alternatively, the Cr layers in the first sub-electrode 611 and the third sub-electrode 621 have a thickness in the range of The thickness of the Pt layer is in the range +.>The thickness of the Ti layer is in the range +.>
In the present embodiment, the Cr layer in the first sub-electrode 611 and the third sub-electrode 621 has a thickness ofThe thickness of the Pt layer is->The thickness of the Ti layer is->At this thickness, the first sub-electrode 611 and the third sub-electrode 621 have strong adhesion, and the manufacturing cost is not excessively high.
Optionally, referring again to fig. 1, the light emitting diode chip further includes a passivation layer 500, and the passivation layer 500 includes a first passivation layer 510 and a second passivation layer 520.
The first passivation layer 510 covers the first electrode 400 and the epitaxial stack 200, and the first passivation layer 510 has therein a first via 511 exposing the first electrode 400 and a second via 512 exposing the first semiconductor layer 210, respectively. The first sub-electrode 611 is connected to the first electrode 400 through the first via 511, and the third sub-electrode 621 is connected to the first semiconductor layer 210 through the second via 512.
The second passivation layer 520 covers the first passivation layer 510, the first sub-electrode 611, and the third sub-electrode 621, and the second passivation layer 520 has a third through hole 521 exposing the first sub-electrode 611 and a fourth through hole 522 exposing the third sub-electrode 621 therein, respectively. The second sub-electrode 612 is connected to the first sub-electrode 611 through a third through hole 521, and the fourth sub-electrode 622 is connected to the third sub-electrode 621 through a fourth through hole 522.
The passivation layer 500 can protect the first electrode 400, the first sub-electrode 611, and the third sub-electrode 621, and prevent the first electrode 400, the first sub-electrode 611, and the third sub-electrode 621 from being oxidized or corroded in a subsequent process, thereby ensuring the reliability of the light emitting diode chip.
Alternatively, the first passivation layer 510 includes an aluminum oxide layer and a silicon oxide layer sequentially stacked on the first electrode 400, and the second passivation layer 520 includes an aluminum oxide layer and a silicon oxide layer sequentially stacked on the first passivation layer 510.
Due to the different refractive indexes of the aluminum oxide layer and the silicon oxide layer, the composite film layer formed by the first passivation layer 510 and the second passivation layer 520 can form a distributed Bragg reflector (Distributed Bragg Reflector, DBR) layer, and the high reflectivity of the DBR layer can reflect light emitted to the DBR layer to the light emitting surface, so that the light emitting efficiency is improved, and the light emitting efficiency of the light emitting diode chip is further improved.
In addition, the heat conductivity coefficient of aluminum oxide is 0.2W/cm.K, and the heat conductivity coefficient of silicon oxide is 0.014W/cm.K, so that the passivation layer 500 formed by the aluminum oxide layer and the silicon oxide layer has good heat conductivity, and the heat dissipation effect of the LED chip during operation can be improved.
Optionally, the thickness of the alumina layer in the first passivation layer 510 ranges fromThe thickness of the silicon oxide layer in the first passivation layer 510 ranges from +.>The thickness of the aluminum oxide layer in the second passivation layer 520 ranges from +.>The thickness of the silicon oxide layer in the second passivation layer 520 ranges from +.>The thickness range can better protect the first electrode 400, the first sub-electrode 611 and the third sub-electrode 621, and meanwhile, the heat dissipation effect of the LED chip during operation is avoided because the thickness is too thick.
In the disclosed embodiment, the thickness of the alumina layer in the first passivation layer 510 isThe thickness of the silicon oxide layer in the first passivation layer 510 is +.>The thickness of the aluminum oxide layer in the second passivation layer 520 is +.>The thickness of the silicon oxide layer in the second passivation layer 520 is +.>The thickness can play a good role in protecting the first electrode 400 while avoiding a decrease in heat dissipation effect due to an excessive thickness.
Testing the embodiment of the disclosure and the existing light emitting diode chip: the package specifications are 3570-45 x 6, the temperature is measured after the temperature is stabilized for 10min under the driving condition of 32W, the surface temperature of the LED chip of the embodiment is 100.2 ℃, and the surface temperature of the existing LED chip is 110.3 ℃; the light emitting diode chip of the embodiment has a light emitting power of 1120mW and the existing light emitting diode chip has a light emitting power of 1100mW under the condition of 700mA current by using an IS standard LED tester.
The existing light emitting diode chips described in the present disclosure are several common chips in the market, and the experimental values are averaged. According to the experimental results, the heat dissipation effect and the luminous power of the light emitting diode chip in the embodiment of the disclosure are improved.
Optionally, the light emitting diode chip further includes a buffer layer 120, as shown in fig. 1, the buffer layer 120 is located between the substrate 100 and the first semiconductor layer 210, and the buffer layer 120 is connected to the first semiconductor layer 210. The buffer layer 120 can reduce quality problems between the substrate 100 and the first semiconductor layer 210 due to heteroepitaxy.
Optionally, the buffer layer 120 is an AlN layer.
Optionally, the substrate 100 is a patterned substrate, and the light emitting diode chip further includes a leveling layer 110, and the leveling layer 110 is located between the substrate 100 and the buffer layer 120, for leveling the pattern on the surface of the substrate 100.
Optionally, the fill layer 110 is SiO 2 A layer.
Wherein SiO is 2 The layer can well fill the surface of the substrate 100, so that the surface of the substrate 100 is smoother, thereby improving the growth quality of the subsequent epitaxial structure. The AlN layer can effectively reduce the influence caused by lattice mismatch between heterogeneous materials, reduce dislocation density of a subsequent epitaxial structure, and enable the quality of other layers grown in a subsequent epitaxial mode to be good.
Referring again to fig. 1, in the embodiment of the disclosure, the light emitting diode chip further includes a current spreading layer 310 and an insulating layer 320, the current spreading layer 310 is located on a surface of the second semiconductor layer 230 remote from the substrate 100, the insulating layer 320 covers the current spreading layer 310 and the epitaxial stack 200, and the insulating layer 320 has a fifth through hole 321 exposing the current spreading layer 310 and a sixth through hole 322 exposing the first semiconductor layer.
The current spreading layer 310 can form ohmic contact with the second semiconductor layer 230, so that an externally injected current is more uniformly transferred to the entire second semiconductor layer 230, and a current spreading function is achieved. The insulating layer 320 has a fifth via 321 exposing the current spreading layer 310 and a sixth via 322 exposing the first semiconductor layer 210 therein, so that the first electrode 400 is connected to the current spreading layer 310 through the fifth via 321, and the third electrode 620 is connected to the first semiconductor layer 210 through the sixth via 322.
Alternatively, the material of the current spreading layer 310 may be any one of indium tin oxide, zinc tin oxide, gallium indium tin oxide, indium gallium oxide, and the like.
Alternatively, the material of the insulating layer 320 may be any one or any combination of silicon oxide, aluminum oxide, and silicon nitride.
Fig. 4 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the disclosure. The method can be used for manufacturing the light-emitting diode chip. As shown in fig. 4, the manufacturing method includes:
step S11: an epitaxial stack is formed.
As shown in fig. 1, the epitaxial stack includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer, which are sequentially stacked, and in which a groove extending from a surface of the second semiconductor layer to the first semiconductor layer is formed.
Optionally, step S11 includes: the first semiconductor layer, the light emitting layer, and the second semiconductor layer are sequentially formed.
In implementation, the first semiconductor layer, the light emitting layer, and the second semiconductor layer may be epitaxially grown in this order on the substrate. The growth of the epitaxial structure is the prior art, and is not described herein.
Optionally, step S11 includes: a recess is formed extending from a surface of the second semiconductor layer to the first semiconductor layer.
When the method is realized, firstly, the light-emitting diode epitaxial wafer is cleaned, then the first semiconductor layer, the light-emitting layer and the second semiconductor layer are etched through the photoetching technology and the dry etching technology, and part of the first semiconductor layer is etched through the second semiconductor layer and the light-emitting layer, so that a groove extending from the surface of the second semiconductor layer to the first semiconductor layer is formed.
Optionally, the method further comprises: before step S11, a fill layer and a buffer layer are sequentially formed on the substrate.
When the method is realized, firstly, a filling layer is deposited on a substrate, the filling layer is polished and then is put into a Metal-organic chemical vapor deposition (Metal-Organic Chemical Vapor Deposition, MOCVD) reaction chamber, ammonia and trimethylaluminum are introduced as reactants, and a buffer layer is grown under the conditions that the growth pressure is 90torr and the temperature is 1200 ℃.
It should be noted that when the substrate is not a patterned substrate, the fill-in layer need not be formed.
Optionally, step S11 further includes: and forming a current expansion layer and an insulating layer on the surface of the second semiconductor layer away from the substrate.
In the embodiment of the disclosure, the current expansion layer is located on the surface of the second semiconductor layer far away from the substrate, and the insulating layer covers the current expansion layer and the epitaxial lamination layer, and has a fifth through hole exposing the current expansion layer and a sixth through hole exposing the first semiconductor layer.
When the method is realized, a conductive material layer is sputtered firstly, then the conductive material layer is subjected to patterning treatment to obtain a current expansion layer which covers most of the second semiconductor layer, and finally O is introduced under the condition of 590 DEG C 2 Annealing for 3 minutes; and depositing a layer of insulating material layer by a plasma enhanced chemical vapor deposition method, covering the current expansion layer and the epitaxial lamination layer by the insulating material layer, and then etching through the insulating material layer to form a fifth through hole exposing the current expansion layer and a sixth through hole exposing the first semiconductor layer, thereby finally forming the insulating layer.
Optionally, the method further comprises: and carrying out deep etching (ISO) photoetching on the light-emitting diode chip before forming the current expansion layer so as to form a cutting channel, thereby facilitating the subsequent chip cutting process.
Step S12: the first electrode is formed on a side of the second semiconductor layer remote from the light emitting layer.
As shown in fig. 1 and 2, the first electrode is connected to the second semiconductor layer, and the first electrode includes a first adhesive layer, a reflective metal layer, a first barrier layer, a compressive stress layer, a second barrier layer, a tensile stress layer, and a second adhesive layer, which are sequentially stacked.
When the method is realized, the first adhesion layer, the reflective metal layer, the first blocking layer, the compressive stress layer, the second blocking layer, the tensile stress layer and the second adhesion layer are sequentially evaporated on the insulating layer to form the first electrode, and the first electrode is connected with the current expansion layer through the third through hole.
Optionally, the compressive stress layer and the tensile stress layer are NiW layers, and the vacuum degree of the compressive stress layer is 2E -3 pa ～ 4E -3 pa is formed in the reaction chamber, and the tensile stress layer is formed in the vacuum degree of 1E -2 pa～2E -2 pa is formed in the reaction chamber.
Because TiW is a metal material with larger stress, when the NiW material is used for manufacturing the compressive stress layer and the tensile stress layer, the vacuum degree in the reaction cavity is set to be 2E -3 pa ～ 4E -3 pa, the formed compressive stress layer can generate a compressive stress of about 1000Mpa to 1500Mpa, which applies a compressive force in a direction from the reflective metal layer to the epitaxial stack, thereby increasing adhesion between the reflective metal layer and other structures. Setting the vacuum degree in the reaction cavity to be 1E -2 pa～2E -2 pa, the tensile stress layer formed is accordingly capable of generating a tensile stress of about 1000Mpa to 1500Mpa, thereby allowing stress balancing between the layers of the first electrode.
As an example, the vacuum degree in the reaction chamber is set to 3.0E -3 pa, the formed compressive stress layer can generate compressive stress of about 1500Mpa, and the vacuum degree in the reaction chamber is set to be 1.3E -2 pa, the tensile stress layer formed can correspondingly generate tensile stress of about 1500Mpa, so that the stress balance effect is good.
Step S13: and forming a third electrode which is positioned in the groove and connected with the first semiconductor layer.
In an embodiment of the present disclosure, step 13 further includes: and forming a second electrode which is positioned on one side of the first electrode away from the second semiconductor layer and is connected with the first electrode.
Optionally, step 13 includes the steps of:
and forming a first passivation layer, wherein the first passivation layer covers the first electrode and the epitaxial lamination.
In a first step, the first passivation layer includes an aluminum oxide layer and a silicon oxide layer.
When the method is realized, trimethylaluminum and water are used as reactant precursors, an atomic layer deposition technology is used for depositing an aluminum oxide layer at the temperature of 200 ℃, and a plasma enhanced chemical vapor deposition technology is used for depositing a silicon oxide layer. Finally, the composite film layer is etched through by using a photoetching technology, a first through hole exposing the first electrode and a second through hole exposing the first semiconductor layer are formed, so that the first sub-electrode is connected with the first electrode through the first through hole, and the third sub-electrode is connected with the first semiconductor layer through the second through hole, and finally, the first passivation layer is formed.
The first passivation layer can better protect the first electrode, avoid the first electrode to be corroded or oxidized, and meanwhile, the heat conductivity coefficients of the aluminum oxide layer and the silicon oxide layer are higher, so that the heat dissipation effect is better.
And forming a first sub-electrode and a third sub-electrode, wherein the first sub-electrode is connected with the first electrode, and the third sub-electrode is connected with the first semiconductor layer.
In practice, a Cr layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer, and a Ti layer may be sequentially deposited on the first electrode and the first semiconductor layer, respectively, to form a first sub-electrode and a third sub-electrode.
And thirdly, forming a second passivation layer to cover the first sub-electrode, the third sub-electrode and the first passivation layer.
In this embodiment, the second passivation layer includes an aluminum oxide layer and a silicon oxide layer.
When the method is realized, trimethylaluminum and water are used as reactant precursors, an atomic layer deposition technology is used for depositing an aluminum oxide layer at the temperature of 200 ℃, and a plasma enhanced chemical vapor deposition technology is used for depositing a silicon oxide layer. And then the composite film layer is etched through by using a photoetching technology to form a third through hole exposing the first sub-electrode and a fourth through hole exposing the third sub-electrode, so that the second sub-electrode is connected with the first sub-electrode through the third through hole, and the fourth sub-electrode is connected with the third sub-electrode through the fourth through hole, and finally the second passivation layer is formed.
The passivation layer formed by the first passivation layer and the second passivation layer not only can protect the first electrode, the first sub-electrode and the third sub-electrode, but also can serve as a DBR layer to reflect light emitted to the passivation layer to the light emitting surface, so that the light emitting efficiency of the light emitting diode chip is improved, and the light emitting efficiency of the light emitting diode chip is improved. Meanwhile, in the manufacturing process of the passivation layer, the temperature is 200 ℃, and the damage to the light-emitting diode chip is small.
And a fourth step of forming a second sub-electrode and a fourth sub-electrode, wherein the second sub-electrode is connected with the first sub-electrode, and the fourth sub-electrode is connected with the third sub-electrode.
In implementation, a Cr layer, a Pt layer, an Au layer, a Ni layer, a Pt layer, a Ti layer, and an AuSn layer may be sequentially deposited on the first sub-electrode and the third sub-electrode, respectively, to form a second sub-electrode and a fourth sub-electrode.
Optionally, the method further comprises: thinning the light emitting diode chip to 160 μm by mechanical thinning; and finally, obtaining the light-emitting diode chip which can be used independently through laser hidden cutting and splitting.
The disclosed embodiments use MOCVD techniques to grow the external delay, with TMGa, TEGa, TMIn as the group III precursor reactant, NH3 as the group V precursor reactant, siH4 and CP2Mg as the n-type dopant and p-type dopant.
In the light emitting diode chip provided by the embodiment of the disclosure, the first electrode includes a first adhesion layer, a reflective metal layer, a first barrier layer, a compressive stress layer, a second barrier layer, a tensile stress layer and a second adhesion layer which are sequentially stacked, and the first electrode is manufactured on one side of the second semiconductor layer far away from the light emitting layer and is electrically connected with the second semiconductor layer. The first adhesive layer and the second adhesive layer ensure the connection performance between the first electrode and other structures connected with the first electrode, and the reflective metal layer can reflect light emitted to the first electrode to the light emitting surface, so that the brightness of the light emitting diode chip is increased. The first blocking layer and the second blocking layer can block the outward diffusion of the material of the reflecting metal layer, and can also protect the reflecting metal layer from oxidation and corrosion, so that the service performance of the first electrode is ensured. The compressive stress layer can generate compressive stress to increase the adhesiveness between the reflective metal layer and other structures, and the tensile stress layer can generate tensile stress to balance the compressive stress generated by the compressive stress layer, so that the stability of the reflective metal layer can be further ensured, and the stress between the structures of each layer in the first electrode can be regulated to balance the stress, so that the internal structure of the first electrode is stable and is not easy to damage, and the reliability of the light-emitting diode chip is improved.
The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.
Claims (10)
1. A light emitting diode chip, the light emitting diode chip comprising:
an epitaxial stack (200) comprising a first semiconductor layer (210), a light emitting layer (220) and a second semiconductor layer (230) stacked in this order, the epitaxial stack (200) having a recess therein extending from a surface of the second semiconductor layer (230) to the first semiconductor layer (210);
a first electrode (400) located at a side of the second semiconductor layer (230) away from the light emitting layer (220) and electrically connected to the second semiconductor layer (230), the first electrode (400) including a first adhesive layer (410), a reflective metal layer (420), a first barrier layer (430), a compressive stress layer (440), a second barrier layer (450), a tensile stress layer (460), and a second adhesive layer (470) stacked in this order;
and a third electrode (620) located in the groove and electrically connected to the first semiconductor layer (210).
2. The light emitting diode chip of claim 1, wherein the compressive stress layer (440) and the tensile stress layer (460) are NiW layers.
3. The light emitting diode chip of claim 2, wherein the compressive stress layer (440) has a thickness in the range ofThe tensile stress layer (460) has a thickness in the range +.>
4. The light emitting diode chip of claim 1, wherein the first barrier layer (430) and the second barrier layer (450) are Ni layers.
5. The light-emitting diode chip according to any one of claims 1 to 4, further comprising a second electrode (610), the second electrode (610) comprising a first sub-electrode (611) and a second sub-electrode (612), the first sub-electrode (611) and the second sub-electrode (612) being sequentially laminated on the first electrode (400), one side of the first sub-electrode (611) close to the second sub-electrode (612) being a Cr layer, a Pt layer and a Ti layer sequentially laminated, and the Ti layer in the first sub-electrode (611) being connected to the second sub-electrode (612);
the third electrode (620) comprises a third sub-electrode (621) and a fourth sub-electrode (622), the third sub-electrode (621) and the fourth sub-electrode (622) are sequentially stacked on the first semiconductor layer (210), one side, close to the fourth sub-electrode (622), of the third sub-electrode (621) is a Cr layer, a Pt layer and a Ti layer which are sequentially stacked, and the Ti layer of the third sub-electrode (621) is connected with the fourth sub-electrode (622).
6. The led chip of claim 5, wherein said Cr layer has a thickness in the range of said first sub-electrode (611)The thickness of the Pt layer is in the range of +.> The thickness of the Ti layer is in the range of +.>
In the third sub-electrode (621), the thickness of the Cr layer is in the range ofThe thickness of the Pt layer is in the range of +.>The thickness of the Ti layer is in the range of +.>
7. A light emitting diode chip according to any one of claims 1 to 3, characterized in that the light emitting diode chip further comprises a passivation layer (500) comprising a first passivation layer (510) and a second passivation layer (520);
the first passivation layer (510) covers the first electrode (400) and the epitaxial stack (200), and the first passivation layer (510) is provided with a first through hole (511) exposing the first electrode (400) and a second through hole (512) exposing the first semiconductor layer (210) respectively, the first sub-electrode (611) is connected with the first electrode (400) through the first through hole (511), and the third sub-electrode (621) is connected with the first semiconductor layer (210) through the second through hole (512);
the second passivation layer (520) covers the first passivation layer (510), the first sub-electrode (611) and the third sub-electrode (621), and the second passivation layer (520) is respectively provided with a third through hole (521) exposing the first sub-electrode (611) and a fourth through hole (522) exposing the third sub-electrode (621), the second sub-electrode (612) is connected with the first sub-electrode (611) through the third through hole (521), and the fourth sub-electrode (622) is connected with the third sub-electrode (621) through the fourth through hole (522);
wherein the first passivation layer (510) includes an aluminum oxide layer and a silicon oxide layer sequentially stacked on the first electrode (400), and the second passivation layer (520) includes an aluminum oxide layer and a silicon oxide layer sequentially stacked on the first passivation layer (510).
8. The light emitting diode chip of claim 7, wherein the thickness of the aluminum oxide layer in the first passivation layer (510) ranges fromThe thickness of the silicon oxide layer in the first passivation layer (510) ranges from
The thickness of the alumina layer in the second passivation layer (520) ranges fromThe thickness of the silicon oxide layer in the second passivation layer (520) is within the range +.>
9. A method for manufacturing a light emitting diode chip, the method comprising:
forming an epitaxial stack comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in this order, the epitaxial stack having a recess therein extending from a surface of the second semiconductor layer to the first semiconductor layer;
forming a first electrode, wherein the first electrode is positioned on one side of the second semiconductor layer far away from the light-emitting layer and is electrically connected with the second semiconductor layer, and the first electrode comprises a first adhesion layer, a reflective metal layer, a first barrier layer, a compressive stress layer, a second barrier layer, a tensile stress layer and a second adhesion layer which are sequentially stacked;
and forming a third electrode, wherein the third electrode is positioned in the groove and is electrically connected with the first semiconductor layer.
10. The method of claim 9, wherein the compressive stress layer and the tensile stress layer are NiW layers;
the vacuum degree of the compressive stress layer is 2E -3 pa ～ 4E -3 pa is formed in the reaction chamber;
the tensile stress layer has a vacuum degree of 1E -2 pa～2E -2 pa is formed in the reaction chamber.
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