CN117673134A - Insulated gate bipolar transistor integrated with bipolar junction transistor and preparation method - Google Patents

Insulated gate bipolar transistor integrated with bipolar junction transistor and preparation method Download PDF

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CN117673134A
CN117673134A CN202211062521.0A CN202211062521A CN117673134A CN 117673134 A CN117673134 A CN 117673134A CN 202211062521 A CN202211062521 A CN 202211062521A CN 117673134 A CN117673134 A CN 117673134A
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dielectric layer
doping concentration
bipolar junction
junction transistor
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段宝兴
唐春萍
杨银堂
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Xidian University
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Xidian University
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    • H01L29/0692—Surface layout
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    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

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Abstract

The invention relates to a bipolar junction transistor structure, in particular to an insulated gate bipolar transistor integrated with a bipolar junction transistor and a preparation method thereof, which are used for solving the defect that the forward turn-on voltage VF and turn-off loss Eoff of the insulated gate bipolar transistor cannot be optimized at the same time when the breakdown characteristic of the insulated gate bipolar transistor is maintained. The insulated gate bipolar transistor integrated with the bipolar junction transistor comprises a gate dielectric layer, and a high-resistance silicon substrate and a bipolar junction transistor structure which are respectively arranged at two sides of the gate dielectric layer; the drift region area of the conventional structure is reduced, so that a P1N1N+P2 structure similar to a bipolar junction transistor with an accumulation effect is formed, and the drift region area is integrated with an IGBT structure through a gate dielectric layer. Meanwhile, the invention discloses a preparation method of the insulated gate bipolar transistor integrated with the bipolar junction transistor.

Description

Insulated gate bipolar transistor integrated with bipolar junction transistor and preparation method
Technical Field
The invention relates to a bipolar junction transistor structure, in particular to an insulated gate bipolar transistor integrated with a bipolar junction transistor and a preparation method thereof.
Background
The insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) can be equivalently a PNP transistor driven by a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), can simultaneously consider the advantages of the MOSFET and the bipolar transistor, and is an ideal power electronic switching device in the field of medium and high voltage at present. Along with the increasing requirements of industry on energy conservation, environmental protection, energy utilization rate and the like, IGBTs are widely focused and developed at a high speed because of the superior performances of high input impedance, low forward voltage, small switching loss and the like.
The design optimization of the IGBT mainly comprises static characteristics such as breakdown voltage VB, forward on voltage VF and the like, and dynamic characteristics such as turn-off time Toff, turn-off loss Eoff and the like. Two main contradictions exist in these characteristics, one is the contradiction relation between the breakdown voltage and the forward on voltage, and the other is the contradiction relation between the forward on voltage and the turn-off loss. Although the contradictory relation between the IGBT breakdown voltage VB and the forward on voltage VF can be solved by terminal designs such as field plate technology, partition doping technology, superjunction technology, surface electric field reduction technology, etc., the electric field modulation effect caused by the contradictory relation between the forward on voltage and the turn-off loss is aggravated due to the increase of turn-off loss.
Disclosure of Invention
The invention aims to solve the defect that the forward on voltage VF and the turn-off loss Eoff cannot be optimized simultaneously when the breakdown characteristic of an insulated gate bipolar transistor is maintained, and provides an insulated gate bipolar transistor integrated with a bipolar junction transistor and a preparation method thereof.
In order to solve the defects existing in the prior art, the invention provides the following technical solutions:
an insulated gate bipolar transistor integrated with a bipolar junction transistor, characterized by: the high-resistance silicon substrate and bipolar junction transistor structure are respectively arranged at two sides of the gate dielectric layer;
the upper part of the high-resistance silicon substrate is sequentially provided with a P-type base region, an emitter region and a cathode from bottom to top, the emitter region is positioned at the upper part of the P-type base region, the emitter region comprises an N+ emitter region and a P+ emitter region, the N+ emitter region is arranged close to the gate dielectric layer, and the cathode is arranged on the top surface of the emitter region; the lower part of the high-resistance silicon substrate is provided with an N-type buffer layer, a P+ collector region and an anode from top to bottom in sequence; drift regions are arranged among the P-type base region, the N-type buffer layer and the gate dielectric layer, and the drift regions are of N type or P type;
the top surface of the gate dielectric layer is equal to the top surface of the emitting region, and the bottom surface of the gate dielectric layer is lower than the top surface of the P+ collector region and higher than the bottom surface of the P+ collector region;
the bipolar junction transistor structure comprises a P1 region, an N1 region, an N+ region and a P2 region which are sequentially arranged from top to bottom and are mutually connected, wherein the P1 region corresponds to the position of an emitter region and the position of a P-type base region and has the same thickness, and the N1 region and the N+ region correspond to the position of the P-type base region, the position of a drift region and the position of an N-type buffer region respectively and have the same thickness; the top surface of the P1 region is provided with a gate electrode;
and the P+ collector region is contacted with the bottom surface of the gate dielectric layer and the bottom surface of the P2 region.
Further, the doping concentration of the N1 region is equal to that of the drift region and is 1×10 14 cm -3 ～1×10 15 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the N+ region is 1 multiplied by 10 19 cm -3 ～1×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the P1 region and the P2 region is the same and is 5 multiplied by 10 15 cm -3 ～5×10 16 cm -3 。
Further, the thickness of the P1 region is 2-4 mu m; the thickness of the P2 region is 1-4 mu m; the thickness of the N+ region is 1-2 mu m.
Further, the doping concentration of the P-type base region (6) is 1 multiplied by 10 16 cm -3 ～1×10 17 cm -3 ；
The doping concentration of the N-type buffer layer is 1 multiplied by 10 17 cm -3 ～5×10 17 cm -3 ；
The P+ collector regionIs not less than 1×10 in doping concentration 19 cm -3 。
Further, the thickness of the drift region is set according to the required breakdown voltage range, and the width is 1-8 mu m.
Further, the gate dielectric layer is made of silicon dioxide or a high-K material, and the width of the gate dielectric layer is 0.05-2 mu m.
Further, the doping concentration of the N1 region is equal to that of the drift region and is 1×10 14 cm -3 ～5×10 14 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the N+ region is 5 multiplied by 10 19 cm -3 ～1×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the P1 region and the P2 region is the same and is 1 multiplied by 10 16 cm -3 ～5×10 16 cm -3 。
Further, the doping concentration of the P-type base region is 3×10 16 cm -3 ～8×10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the N-type buffer layer is 3 multiplied by 10 17 cm -3 ～5×10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the P+ collector region is 3×10 19 cm -3 ～8×10 19 cm -3 。
Meanwhile, the invention provides a preparation method of the insulated gate bipolar transistor integrated with the bipolar junction transistor, which is characterized by comprising the following steps:
step 1, selecting a high-resistance silicon substrate with required doping concentration as a device drift region;
step 2, forming a P-type base region on the upper part of the high-resistance silicon substrate through ion implantation, forming an emitter region on the upper part of the P-type base region, wherein the emitter region comprises an N+ emitter region and a P+ emitter region, and forming a cathode on the top surface of the emitter region through deposition of metal;
step 3, forming an N-type buffer layer and a P+ collector region in sequence under the high-resistance silicon substrate through ion implantation, and forming an anode on the bottom surface of the P+ collector region through metal deposition;
step 4, forming a groove on the high-resistance silicon substrate on one side of the cathode, which is close to the N+ emission region, by etching, wherein the thickness of the groove is smaller than that of the high-resistance silicon substrate;
step 5, growing a gate dielectric layer on the inner wall of one side of the groove close to the cathode, wherein the thickness of the gate dielectric layer is equal to that of the groove, and the width of the gate dielectric layer is smaller than that of the groove;
step 6, a P2 region, an N+ region, an N1 region and a P1 region are sequentially grown in the groove from bottom to top;
step 7, forming a gate electrode on the top surface of the P1 region by depositing metal;
and 8, forming a passivation layer on the whole surface obtained in the step 7, and completing the preparation of the insulated gate bipolar transistor integrated with the bipolar junction transistor.
Compared with the prior art, the invention has the beneficial effects that:
the invention relates to an insulated gate bipolar transistor integrated with a bipolar junction transistor, which comprises a gate dielectric layer, and a high-resistance silicon substrate and a bipolar junction transistor structure which are respectively arranged at two sides of the gate dielectric layer; according to the invention, the drift region area of a conventional structure is reduced, so that a P1N1N+P2 structure similar to a bipolar junction transistor with an accumulation effect is formed, and the drift region area is integrated with an IGBT structure through a gate dielectric layer;
the drift region in the structure can be of an N type or a P type, and has an optimization function compared with a conventional structure;
the bipolar junction transistor structure in the structure of the invention presents a cut-off state in forward and reverse voltages, and the interface of the N1 region near the gate dielectric layer has approximately constant positive voltage, so that an electron accumulation layer is formed in the drift region near the gate dielectric layer, thereby effectively reducing forward conduction voltage VF; the approximately constant positive voltage is the difference between the gate electrode voltage and the nearby pn junction turn-on voltage (about 0.7V);
when the drift region in the structure is of an N type, compared with a conventional IGBT structure, the structure can lower forward on-voltage VF by 46.45% on the basis of maintaining breakdown characteristics compared with the conventional structure;
when the drift region in the structure is of the P type, the Miller capacitance of the structure is far smaller than that of the conventional structure and the structure with the N type drift region at the beginning of turn-off, so that the turn-off voltage is slowly increased, the turn-off loss Eoff is effectively reduced, the forward turn-on voltage VF is reduced by 45.81% and the turn-off loss Eoff is reduced by 38.71% on the basis of keeping the breakdown characteristic compared with the conventional structure.
Drawings
Fig. 1 is a schematic diagram of an insulated gate bipolar transistor integrated with a bipolar junction transistor according to the present invention;
FIG. 2 is a schematic diagram showing the comparison of breakdown voltages of an embodiment of the present invention and a conventional structure;
FIG. 3 is a schematic diagram showing the comparison of the conduction characteristics of the embodiment of the present invention and the conventional structure;
FIG. 4 is a schematic diagram showing comparison of the shutdown characteristics of the embodiment of the present invention and the conventional structure;
FIG. 5 is a graph showing the comparison of Miller capacitance characteristics of an embodiment of the present invention and a conventional structure.
The reference numerals are explained as follows: 1-a cathode; 2-gate dielectric layer; a 3-gate electrode; a 4-p+ emitter region; a 5-n+ emitter region; a 6-P1 region; a 7-P type base region; 8-N1 region; a 9-drift region; 10-n+ region; an 11-N type buffer layer; a 12-P2 region; 13-p+ collector region; 14-anode.
Detailed Description
The invention is further described below with reference to the drawings and exemplary embodiments.
In the forward conduction process of the IGBT, a large amount of holes are injected into the drift region by the P+ collector region under the action of voltage, and in order to maintain the electric neutrality in the drift region, equivalent movable electrons are generated in the drift region, which is the conductivity modulation phenomenon which is inevitably present in the IGBT. In the turn-off process, a large number of electron-holes cause larger tailing current to appear when the device is turned off, so that turn-off loss is increased, which is the most main technical problem in the IGBT design optimization process.
In order to solve the technical problem, the invention discloses an insulated gate bipolar transistor integrated with a bipolar junction transistor, as shown in fig. 1, comprising a gate dielectric layer 2, and a high-resistance silicon substrate and a bipolar junction transistor structure respectively arranged at two sides of the gate dielectric layer 2.
The upper part of the high-resistance silicon substrate is sequentially provided with a P-type base region 7, an emitter region and a cathode 1 from bottom to top, wherein the emitter region is a silicon nitride filmThe emitter region is positioned at the upper part of the P-type base region 7, the emitter region comprises an N+ emitter region 5 and a P+ emitter region 4, the N+ emitter region 5 is arranged close to the gate dielectric layer 2, and the cathode 1 is arranged on the top surface of the emitter region; the doping concentration of the P-type base region 7 is 3 multiplied by 10 16 cm -3 ～8×10 16 cm -3 The thickness is 1-2 μm and the width is equal to the drift region 9.
The lower part of the high-resistance silicon substrate is provided with an N-type buffer layer 11, a P+ collector region 13 and an anode 14 from top to bottom in sequence; the doping concentration of the N-type buffer layer 11 is 3×10 17 cm -3 ～5×10 17 cm -3 The thickness is 1-2 mu m; the doping concentration of the P+ collector region 13 is 3×10 19 cm -3 ～8×10 19 cm -3 。
A drift region 9 with a thickness of 30 μm is arranged among the P-type base region 7, the N-type buffer layer 11 and the gate dielectric layer 2, the drift region 9 can be N-type or P-type, and the doping concentration is 1×10 14 cm -3 ～5×10 14 cm -3 The thickness is set according to the required breakdown voltage range, and the width is 1-8 mu m.
The top surface of the gate dielectric layer 2 is equal to the top surface of the emitter region, and the bottom surface of the gate dielectric layer 2 is lower than the top surface of the P+ collector region 13 and higher than the bottom surface of the P+ collector region 13; the gate dielectric layer 2 can be made of silicon dioxide or high-K dielectric, and has a width of 0.05-2 μm.
The bipolar junction transistor structure comprises a P1 region 6, an N1 region 8, an N+ region 10 and a P2 region 12 which are sequentially arranged from top to bottom and are mutually connected, wherein the P1 region 6 corresponds to the position of an emitter region and the position of a P-type base region 7, the thicknesses of the P1 region and the N+ region 10 are equal, and the N1 region 8 and the N+ region 10 correspond to the position of the P-type base region 7, the position of a drift region 9 and the position of an N-type buffer layer 11 respectively, and the thicknesses of the N1 region and the N+ region are equal; the doping concentration of the P1 region 6 and the P2 region 12 is the same and is 1 multiplied by 10 16 cm -3 ～5×10 16 cm -3 The thickness of the P1 region 6 is 2-4 mu m, and the thickness of the P2 region 12 is 1-4 mu m; the doping concentration of the N1 region 8 is equal to that of the drift region 9 and is 1 multiplied by 10 14 cm -3 ～5×10 14 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the N+ region 10 is 5×10 19 cm -3 ～1×10 20 cm -3 The thickness of the N+ region 10 is 1-2 μm.
The structure width of the bipolar junction transistor can be reasonably set according to the process limit, and the bipolar junction transistor should be not smaller than 1 μm, and also should conform to the principle that the smaller the cell area is, the higher the integration level is.
The top surface of the P1 region 6 is provided with a gate electrode 3.
The P+ collector region 13 is in contact with the bottom surface of the gate dielectric layer 2 and the bottom surface of the P2 region 12.
The preparation method of the insulated gate bipolar transistor integrated with the bipolar junction transistor comprises the following steps:
step 1, selecting a high-resistance silicon substrate with required doping concentration as a device drift region 9;
step 2, forming a doping concentration of 3×10 on the upper part of the high-resistance silicon substrate by ion implantation 16 cm -3 ～8×10 16 cm -3 Forming an emitter region on the upper part of the P-type base region 7, and forming a cathode 1 on the top surface of the emitter region by depositing metal; the thickness of the P-type base region 7 is 1-2 mu m;
step 3, forming doping concentration of 3×10 on the lower part of the high-resistance silicon substrate sequentially by ion implantation 17 cm -3 ～5×10 17 cm -3 N-type buffer layer 11 of (a) and a doping concentration of 3×10 19 cm -3 ～8×10 19 cm -3 The P+ collector region 13 of (2) and forming an anode 14 by depositing metal on the bottom surface of the P+ collector region 13;
step 4, forming a groove on the high-resistance silicon substrate on one side of the cathode 1, which is close to the N+ emission region 5, by etching, wherein the thickness of the groove is smaller than that of the high-resistance silicon substrate;
step 5, growing a gate dielectric layer 2 on the inner wall of one side of the groove close to the cathode 1, wherein the thickness of the gate dielectric layer 2 is equal to that of the groove, and the width of the gate dielectric layer 2 is smaller than that of the groove; the gate dielectric layer 2 can be made of silicon dioxide or high-K dielectric with the width of 0.05-2 mu m;
step 6, growing a P2 region 12, an N+ region 10, an N1 region 8 and a P1 region 6 in the groove from bottom to top in sequence;
step 7, forming a gate electrode 3 on the top surface of the P1 region 6 by depositing metal;
and 8, forming a passivation layer on the whole surface obtained in the step 7, and completing the preparation of the insulated gate bipolar transistor integrated with the bipolar junction transistor.
The simulation result of the invention is as follows:
referring to fig. 2, the breakdown voltage comparison of the inventive structure with the conventional structure illustrates: the structure of the invention maintains the same breakdown characteristic as the conventional structure, and can reach the voltage withstanding range of 600V when the drift region 9 is 30 mu m.
Referring to fig. 3, the comparison of the conduction characteristics of the inventive structure with those of the conventional structure illustrates: the structure of the invention can reduce the forward conduction voltage VF by about 46 percent while maintaining the breakdown characteristic of the device regardless of whether the structure is provided with an N-type drift region or a P-type drift region.
Referring to fig. 4 and 5, the turn-off characteristics and miller capacitance comparison results of the inventive structure versus the conventional structure are illustrated: when the drift region 9 is of an N type, the variation trend of the Miller capacitance is not obviously changed compared with that of the conventional structure, so that the turn-off characteristic of the invention is not obviously changed; when the drift region 9 is P-type, since the miller capacitance of the structure of the invention at the time of initial turn-off is much smaller than that of a conventional IGBT and the structure of the invention having an N-type drift region, the voltage rise becomes significantly slower at the time of turn-off, so that the structure of the invention can make the turn-off loss Eoff (1.0713 mJ/cm 2 ) Compared with the conventional structure, the switch-off loss Eoff (1.7480 mJ/cm 2 ) The drop is 38.71%.
The IGBT in this embodiment may be a P-channel, and its structure is equivalent to that of the N-channel IGBT in this embodiment.
The foregoing embodiments are merely for illustrating the technical solutions of the present invention, and not for limiting the same, and it will be apparent to those skilled in the art that modifications may be made to the specific technical solutions described in the foregoing embodiments, or equivalents may be substituted for some of the technical features thereof, without departing from the spirit of the technical solutions protected by the present invention.

Claims (9)

1. An insulated gate bipolar transistor integrated with a bipolar junction transistor, characterized by: the high-resistance silicon-based semiconductor device comprises a gate dielectric layer (2), high-resistance silicon substrates and a bipolar junction transistor structure, wherein the high-resistance silicon substrates and the bipolar junction transistor structure are respectively arranged on two sides of the gate dielectric layer (2);
the upper part of the high-resistance silicon substrate is sequentially provided with a P-type base region (7), an emitter region and a cathode (1) from bottom to top, the emitter region is positioned at the upper part of the P-type base region (7), the emitter region comprises an N+ emitter region (5) and a P+ emitter region (4), the N+ emitter region (5) is close to the gate dielectric layer (2), and the cathode (1) is arranged on the top surface of the emitter region; the lower part of the high-resistance silicon substrate is provided with an N-type buffer layer (11), a P+ collector region (13) and an anode (14) from top to bottom in sequence; a drift region (9) is arranged among the P-type base region (7), the N-type buffer layer (11) and the gate dielectric layer (2), and the drift region (9) is of an N type or a P type;
the top surface of the gate dielectric layer (2) is equal to the top surface of the emitting region, the bottom surface of the gate dielectric layer (2) is lower than the top surface of the P+ collector region (13) and higher than the bottom surface of the P+ collector region (13);
the bipolar junction transistor structure comprises a P1 region (6), an N1 region (8), an N+ region (10) and a P2 region (12) which are sequentially arranged from top to bottom and are mutually connected, wherein the P1 region (6) corresponds to the position of an emission region and the position of a P-type base region (7) and has the same thickness, and the N1 region (8) and the N+ region (10) correspond to the position of a drift region (9) and the position of an N-type buffer layer (11) respectively and have the same thickness; the top surface of the P1 region (6) is provided with a gate electrode (3);
the P+ collector region (13) is in contact with the bottom surface of the gate dielectric layer (2) and the bottom surface of the P2 region (12).
2. An insulated gate bipolar transistor integrated with a bipolar junction transistor according to claim 1, wherein: the doping concentration of the N1 region (8) is equal to that of the drift region (9), and is 1 multiplied by 10 14 cm -3 ～1×10 15 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the N+ region (10) is 1 multiplied by 10 19 cm -3 ～1×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the P1 region (6) and the P2 region (12) is the same and is 5 multiplied by 10 15 cm -3 ～5×10 16 cm -3 。
3. An insulated gate bipolar transistor integrated with a bipolar junction transistor according to claim 2, wherein: the thickness of the P1 region (6) is 2-4 mu m; the thickness of the P2 region (12) is 1-4 mu m; the thickness of the N+ region (10) is 1-2 mu m.
4. An insulated gate bipolar transistor integrated with a bipolar junction transistor according to claim 3, wherein: the doping concentration of the P-type base region (7) is 1 multiplied by 10 16 cm -3 ～1×10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the N-type buffer layer (11) is 1 multiplied by 10 17 cm -3 ～5×10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The P+ collector region (13) has a doping concentration of not less than 1×10 19 cm -3 。
5. An insulated gate bipolar transistor integrated with a bipolar junction transistor according to any of claims 1 to 4, wherein: the thickness of the drift region (9) is set according to the required breakdown voltage range, and the width is 1-8 mu m.
6. An insulated gate bipolar transistor integrated with a bipolar junction transistor according to claim 5, wherein: the gate dielectric layer (2) is made of silicon dioxide or a high-K material, and the width of the gate dielectric layer is 0.05-2 mu m.
7. The insulated gate bipolar transistor integrated with a bipolar junction transistor of claim 6 wherein: the doping concentration of the N1 region (8) and the doping concentration of the drift region (9) are 1 multiplied by 10 14 cm -3 ～5×10 14 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the N+ region (10) is 5 multiplied by 10 19 cm -3 ～1×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the P1 region (6) and the P2 region (12) is 1 multiplied by 10 16 cm -3 ～5×10 16 cm -3 。
8. An insulated gate bipolar transistor integrated with a bipolar junction transistor according to claim 7, wherein: the doping concentration of the P-type base region (7) is 3 multiplied by 10 16 cm -3 ～8×10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The N-type buffer layer (1)1) Is 3×10 in doping concentration 17 cm -3 ～5×10 17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the P+ collector region (13) is 3×10 19 cm -3 ～8×10 19 cm -3 。
9. A method of fabricating an insulated gate bipolar transistor integrated with a bipolar junction transistor as in claim 1, comprising the steps of:
step 1, selecting a high-resistance silicon substrate with required doping concentration as a device drift region (9);
step 2, forming a P-type base region (7) on the upper part of a high-resistance silicon substrate through ion implantation, forming an emitter region on the upper part of the P-type base region (7), wherein the emitter region comprises an N+ emitter region (5) and a P+ emitter region (4), and forming a cathode (1) on the top surface of the emitter region through deposition of metal;
step 3, forming an N-type buffer layer (11) and a P+ collector region (13) on the lower part of the high-resistance silicon substrate in sequence through ion implantation, and forming an anode (14) on the bottom surface of the P+ collector region (13) through metal deposition;
step 4, forming a groove on the high-resistance silicon substrate on one side of the cathode (1) close to the N+ emission region (5) through etching, wherein the thickness of the groove is smaller than that of the high-resistance silicon substrate;
step 5, growing a gate dielectric layer (2) on the inner wall of one side of the groove close to the cathode (1), wherein the thickness of the gate dielectric layer (2) is equal to that of the groove, and the width of the gate dielectric layer (2) is smaller than that of the groove;
step 6, growing a P2 region (12), an N+ region (10), an N1 region (8) and a P1 region (6) in the groove from bottom to top in sequence;
step 7, forming a gate electrode (3) on the top surface of the P1 region (6) by depositing metal;
and 8, forming a passivation layer on the whole surface obtained in the step 7, and completing the preparation of the insulated gate bipolar transistor integrated with the bipolar junction transistor.
CN202211062521.0A 2022-08-31 2022-08-31 Insulated gate bipolar transistor integrated with bipolar junction transistor and preparation method Pending CN117673134A (en)

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