CN117673131A

CN117673131A - Insulated gate bipolar transistor with high short-circuit safe operating area SOA

Info

Publication number: CN117673131A
Application number: CN202211042746.XA
Authority: CN
Inventors: 陆界江; 吴磊; 李娇; 周明江
Original assignee: Shanghai Ruiqu Microelectronics Technology Co ltd
Current assignee: Shanghai Ruiqu Microelectronics Technology Co ltd
Priority date: 2022-08-29
Filing date: 2022-08-29
Publication date: 2024-03-08

Abstract

The invention discloses an insulated gate bipolar transistor with a high short-circuit safe operating area SOA, wherein the insulated gate bipolar transistor IGBT comprises: a body region, a drift region, and an N-field stop FS region; an emitter and a grid are arranged above the main body region; a P-type collector region is arranged below the N-type FS region, and a collector electrode is arranged below the P-type collector region; a gate pad is arranged above the gate region, and a non-active unit region, an active unit region, a gate runner and a hole flow contact region are arranged around the gate pad; hole flow paths are provided in the inactive cell region and around the gate runner. The invention may have a high short-circuited SOA.

Description

Insulated gate bipolar transistor with high short-circuit safe operating area SOA

Technical Field

The invention relates to the field of semiconductors, and in particular to an insulated gate bipolar transistor with a high short-circuit SOA.

Background

The insulated gate bipolar transistor IGBT (Insulated Gate Bipolar Transistor) is the most widely used power device in power electronics applications such as household appliances, industry, renewable energy sources, UPS, railways, motor drives, and EV and HEV applications, and has a very high current handling capability in its structure, on the order of hundreds of amps, with a blocking voltage of 6500V due to the presence of the bipolar transistor. These IGBTs can control loads of hundreds of kilowatts, and are suitable for many applications. The IGBT is particularly suitable for duty cycle, low frequency, high voltage and load variations, enabling it to be used in locomotive trains, electric vehicles and hybrid electric vehicles. Applications of IGBTs in Electric Vehicles (EVs) and Hybrid Electric Vehicles (HEVs) include their use in drivetrains and chargers for delivering and controlling electrical power to electric machines. The IGBT market for EV/HEVs is expected to increase by a factor of two over the prediction period, accounting for more than 50% of the total market.

However, IGBTs have an inherent disadvantage, such as that Vce (sat) increases rapidly with increasing blocking voltage, and thus the IEGT concept was developed to reduce the on-state voltage drop. The trench gate power device reduces channel resistance and eliminates JFET effects and can reduce on-state voltage drop. Furthermore, the IEGT (injection enhanced IGBT) concept increases the stored carriers on the upper side of the n drift region by using a floating p-region between trench gate cells, thus significantly reducing Vce (sat) for relatively high voltage IGBTs.

These power devices applied to hybrid vehicles and electric vehicles are forced to frequently face severe environments, and it is very useful to analyze failure mechanisms and innovate main measures for failure and destruction according to the failure mechanisms from the viewpoint of device failure and protection. One of the most important damage phenomena is damage under short circuit conditions in inverter applications. In general, it can be said that the most severe condition for the destructiveness is under high power switching. The IGBT structure must be able to operate over the entire area covering these tracks without damaging failure. In the course of the IGBT structure being subjected to both high currents and voltages, a phenomenon known as avalanche induced secondary breakdown occurs, resulting in destructive failure. This phenomenon can be triggered during both the on-transient and the off-transient. During an on transient, the Forward Biased Safe Operating Area (FBSOA) is said to be limited. During a shutdown transient, the Reverse Bias Safe Operating Area (RBSOA) is said to be limited. Very severe stresses, including FBSOA and RBSOA, occur under short circuit conditions, and the failure mechanism of the short circuit operation can be considered to be divided into four modes.

Mode a is a breakdown that occurs within a few microseconds after conduction due to the parasitic bipolar transistor turning on when the collector current is large. Mode B is thermal damage caused by excessive power consumption. Mode C is the disruption observed during shutdown, and shortly before Ic reaches zero current level, dic/dt is increasing and a higher peak voltage occurs. If the Rg off resistance is reduced to a very small value and the parasitic inductance is large, dynamic avalanche can occur, which is a destructive event due to current filarization, and SSCM (switched self-clamping mode) can occur, clamping the peak voltage to the breakdown voltage. Mode D is a failure observed on the order of hundreds of microseconds after shutdown, which may be described as thermal runaway caused by a large leakage current.

Short circuit endurance has been one of the most important issues for IGBTs and IGETs in EV, HEV and high power motor control applications. Many requirements in applications operating under hard switching conditions drive the trend of IGBT development for wide SOA limitations. Improved SOA performance will have a positive impact on manufacturability, reliability, power handling capability, better controllability, better system and gate device design, with the aim of reducing overall loss and employing more optimized protection schemes. To ensure that high voltage devices do not exceed their SOA limitations, many limitations are introduced to the operation of such devices. Thus, system designers have decided to set many circuit and gate drive parameters accordingly. Such modifications include increasing gate resistance and inclusion of protective active clamps or buffers.

This increased complexity typically negatively impacts the performance, cost, and size of the high power electronic system.

Disclosure of Invention

In view of this, the present invention aims to provide an insulated gate bipolar transistor IGBT with a high short-circuit safe operating area SOA.

Specifically, the present invention provides an insulated gate bipolar transistor with a high short-circuit SOA, the insulated gate bipolar transistor IGBT comprising: a body region, a drift region, and an N-field stop FS (Field Stop) region; an emitter and a grid are arranged above the main body region; a P-type collector region is arranged below the N-type FS region, and a collector electrode is arranged below the P-type collector region; a gate pad is arranged above the gate region, and a non-active unit region, an active unit region, a gate runner and a hole flow contact region are arranged around the gate pad; hole flow paths are provided in the inactive cell region and around the gate runner.

Further, the number of the hole flow contact areas is plural, and the plural hole flow contact areas are located at four corners of the insulated gate bipolar transistor chip.

Further, a gate pad is arranged above the gate region, a p+ well region is arranged below the gate pad, and a hole bypass for transmitting hole current is arranged in the p+ well region;

the hole bypass is communicated with the gate region;

the number of the hole bypasses is multiple, and the hole bypasses are symmetrically distributed below the grid electrode bonding pad.

Further, the ratio of the emitter region to the gate region below the gate pad is greater than 1:1 or greater than 2:1, the length of the emitter region below the gate pad is smaller than a preset value.

Further, the gate region comprises a trench gate and a planar gate; the planar gate is arranged on the surface of the gate region, a groove is formed in a preset position of the gate region, a groove gate is arranged in the groove, one end, far away from the bottom end of the groove, of the groove gate is connected with the insulating layer, and the insulating layer covers the outer surface of the planar gate.

Further, the emitter region is an N-type emitter region, the gate region is a P-type base region, the P-type base region is arranged around the trench gate, the N-type emitter region is arranged at one end, close to the insulating layer, of the trench gate, and a gate oxide layer is arranged on the outer surface of the trench gate.

Further, a trench is formed at a preset position of the gate region, a trench gate is arranged in the trench, a P-type annular structure is arranged at the periphery of the bottom end of the trench, the P-type annular structure is embedded, the center of the P-type annular structure is overlapped with the center of the trench, the inner circumference of the P-type annular structure is the outer circumference of the trench, and the distance between each point of the outer circumference of the P-type annular structure and the center of the trench is equal.

Further, a mixed diffusion layer is arranged between the N-type FS region and the P-type collector region, and the mixed diffusion layer is provided with a P+ region and an N+ region;

during a short-circuit shutdown transient state, the P+ region arranged by the mixed diffusion layer injects hole carriers into the space charge region; the hole carriers compensate for the effective net charge density in the space charge to eliminate peak electric fields; and the n+ region arranged in the mixed diffusion layer is used for removing injected hole carriers, and the P+ region and the N+ region in the mixed diffusion layer are alternately arranged and distributed.

The invention also provides power electronic equipment comprising the insulated gate bipolar transistor.

The invention also provides a power vehicle comprising the insulated gate bipolar transistor.

The IGBT with improved short circuit endurance of the present invention is achieved by having an inactive hole flow path around the edge termination and an inactive hole path in the cell along the periphery of the internal cell. In addition, since the region is easy to generate a higher electric field, a larger hole flow contact region is arranged around the four corners of the chip, namely, an inactive hole flow path is designed through a region between the edge termination region and the internal battery, and meanwhile, an inactive cell region exists around the gate pad as a hole flow path, so that concentration of electric field and current density around the region can be effectively avoided.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, illustrate some, but not all embodiments of the invention. Other figures can be derived from these figures by one of ordinary skill in the art without undue effort.

FIG. 1 is a schematic diagram of electric field and current distribution non-uniformity in an IGBT chip in different local areas provided by an embodiment of the invention;

fig. 2 is a schematic structural diagram of an insulated gate bipolar transistor with a high-short SOA according to an embodiment of the present invention;

FIG. 3 is a cross-sectional view taken along line X-X' of FIG. 2;

FIG. 4 is a cross-sectional view taken along Y-Y' in FIG. 2;

FIG. 5 is a cross-sectional view taken along line A-A' of FIG. 2;

FIG. 6 is a cross-sectional view taken along line B-B' of FIG. 2;

FIG. 7 is a cross-sectional view taken along line C-C' of FIG. 2;

FIG. 8 is a cross-sectional view taken along line D-D' of FIG. 2;

FIG. 9 is a cross-sectional view taken along E-E' in FIG. 2;

FIG. 10 is a cross-sectional view taken along line F-F' of FIG. 2;

FIG. 11 is a cross-sectional view taken along G-G' in FIG. 2;

FIG. 12 is a schematic view of the structure corresponding to circle No.1 in FIG. 5;

FIG. 13 is a schematic view of the structure corresponding to circle No.2 in FIG. 5;

FIG. 14 is a schematic view of the structure corresponding to circle No.3 in FIG. 7;

FIG. 15 is a schematic view of the structure corresponding to circle No.4 in FIG. 9;

FIG. 16 is a schematic view of the structure corresponding to circle No.5 in FIG. 11;

fig. 17 is another schematic structural diagram of an insulated gate bipolar transistor with a high-short SOA according to an embodiment of the present invention.

Detailed Description

The exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, however, the present invention may be embodied in many different forms and is not limited to the examples described herein, which are provided to fully and completely disclose the present invention and fully convey the scope of the invention to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the accompanying drawings is not intended to be limiting of the invention. In the drawings, like elements/components are referred to by like reference numerals.

Unless otherwise indicated, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. In addition, it will be understood that terms defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

The inventor of the application finds out through experimental tests and theoretical analysis that a plurality of fault points in a chip are caused by nonuniform electric fields and currents, wherein higher electric fields are concentrated at the bottom of a trench gate and four corners of the chip. Higher current densities concentrate around the gate pad and gate runner with higher lattice temperatures below the emitter pad region. As shown in particular in fig. 1, the circle No.1 indicates the point between the edge termination and the active cell region, no.2 indicates the point around the emitter pad region, no.3 indicates the point along the gate runner, and No.4 indicates the spot pad region around the gate. The higher electric field is concentrated at the trench gate bottom and at the four corners of the chip. Higher current densities concentrate around the gate pad and gate runner with higher lattice temperatures below the emitter pad region. These problems can be ameliorated by an additional hole flow path for over-current concentration.

As shown in fig. 2-17, a plan view around an edge termination includes an active cell, a non-active cell, a gate runner, and a gate pad region, and the latch-up improving IGBT includes: the device comprises a main body region, a drift region and an N-type FS region; an emitter and a grid are arranged above the main body region; a P-type collector region is arranged below the N-type FS region, and a collector electrode is arranged below the P-type collector region; a gate pad is arranged above the gate region, and a non-active unit region, an active unit region, a gate runner and a hole flow contact region are arranged around the gate pad; hole flow paths are provided in the inactive cell region and around the gate runner.

the hole bypass is communicated with the gate region;

The present embodiment has an IGBT that improves short circuit endurance, by having an inactive hole flow path around the edge termination, and an inactive hole path in the cell along the periphery of the internal cell. In addition, since the region is easy to generate a higher electric field, a larger hole flow contact region is arranged around the four corners of the chip, namely, an inactive hole flow path is designed through a region between the edge termination region and the internal battery, and meanwhile, an inactive cell region exists around the gate pad as a hole flow path, so that concentration of electric field and current density around the region can be effectively avoided.

The application also provides power electronic equipment comprising the insulated gate bipolar transistor. In particular, the power electronics device may comprise a current transformer.

The application also provides a power vehicle comprising the insulated gate bipolar transistor. Specifically, the power vehicle comprises a locomotive train, an electric vehicle or a hybrid electric vehicle.

The power electronics and the power vehicle include the technical effects of the insulated gate bipolar transistor described above that enable hole carriers to be injected from the extra p+ region into the space charge region during a short turn-off transient, thereby compensating for the effective net charge density in the space charge to eliminate peak electric fields. Eventually, dynamic avalanche leading to a current filament can be avoided. The injected carriers can be rapidly removed through the additional n+ region, thereby shortening the turn-off time.

The invention has been described with reference to a few embodiments. However, as is well known to those skilled in the art, other embodiments than the above disclosed invention are equally possible within the scope of the invention, as defined by the appended patent claims.

Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise therein. All references to "a/an/the [ means, component, etc. ]" are to be interpreted openly as referring to at least one instance of said means, component, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated.

Claims

1. An insulated gate bipolar transistor having a high short-circuit safe operating area SOA, the insulated gate bipolar transistor comprising: a body region, a drift region, and an N-field stop FS region;

an emitter and a grid are arranged above the main body region; a P-type collector region is arranged below the N-type FS region, and a collector electrode is arranged below the P-type collector region;

a gate pad is arranged above the gate region, and a non-active unit region, an active unit region, a gate runner and a hole flow contact region are arranged around the gate pad;

hole flow paths are provided in the inactive cell region and around the gate runner.

2. The insulated gate bipolar transistor of claim 1 wherein the number of said hole flow contact regions is a plurality, and wherein a plurality of said hole flow contact regions are located at four corners of the insulated gate bipolar transistor chip.

3. The insulated gate bipolar transistor of claim 2 wherein a gate pad is disposed above the gate region, a p+ well region is disposed below the gate pad, and a hole bypass for transporting hole current is disposed in the p+ well region;

the hole bypass is communicated with the gate region;

4. The insulated gate bipolar transistor of claim 3 wherein the ratio of emitter region to gate region below the gate pad is greater than 1:1 or greater than 2:1, the length of the emitter region below the gate pad is smaller than a preset value.

5. The insulated gate bipolar transistor of claim 4 wherein said gate region comprises a trench gate and a planar gate; the planar gate is arranged on the surface of the gate region, a groove is formed in a preset position of the gate region, a groove gate is arranged in the groove, one end, far away from the bottom end of the groove, of the groove gate is connected with the insulating layer, and the insulating layer covers the outer surface of the planar gate.

6. The insulated gate bipolar transistor of claim 5 wherein said emitter region is an N-type emitter region, and said gate region is a P-type base region, said trench gate is surrounded by a P-type base region, an N-type emitter region is disposed at an end of said trench gate adjacent to said insulating layer, and a gate oxide layer is disposed on an outer surface of said trench gate.

7. The insulated gate bipolar transistor of claim 5 wherein a trench is formed in a predetermined position of the gate region, a trench gate is disposed in the trench, a P-type ring structure is disposed at a bottom periphery of the trench, the P-type ring structure is buried, a center of the P-type ring structure overlaps with a center of the trench, an inner circumference of the P-type ring structure is an outer circumference of the trench, and a distance from each point of the outer circumference of the P-type ring structure to the center of the trench is equal.

8. The insulated gate bipolar transistor of claim 7 wherein a hybrid diffusion layer is disposed between the N-type FS region and the P-type collector region, the hybrid diffusion layer being disposed with a p+ region and an n+ region;

during a short-circuit shutdown transient state, the P+ region arranged by the mixed diffusion layer injects hole carriers into the space charge region; the hole carriers compensate for the effective net charge density in the space charge to eliminate peak electric fields; and the N+ regions arranged in the mixed diffusion layer remove injected hole carriers, and the P+ regions and the N+ regions in the mixed diffusion layer are alternately arranged and distributed.

9. A power electronic device comprising an insulated gate bipolar transistor according to any of claims 1-8.

10. A power vehicle comprising an insulated gate bipolar transistor according to any one of claims 1 to 8.