CN117673125A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDF

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Publication number
CN117673125A
CN117673125A CN202211067393.9A CN202211067393A CN117673125A CN 117673125 A CN117673125 A CN 117673125A CN 202211067393 A CN202211067393 A CN 202211067393A CN 117673125 A CN117673125 A CN 117673125A
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region
layer
epitaxial layer
conductive material
semiconductor device
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蒋光浩
陈彦儒
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Hongyang Semiconductor Co ltd
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Hongyang Semiconductor Co ltd
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Priority to CN202211067393.9A priority Critical patent/CN117673125A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/157—Doping structures, e.g. doping superlattices, nipi superlattices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H01L29/365—Planar doping, e.g. atomic-plane doping, delta-doping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor device includes a substrate, an epitaxial layer, a well region, a current diffusion layer, a source region, a base region, and a gate layer. The epitaxial layer is on the substrate. The well region is in the epitaxial layer. The current diffusion layer is arranged in the epitaxial layer and under the well region, wherein the current diffusion layer comprises a plurality of first doped regions and a plurality of second doped regions, the first doped regions comprise a plurality of dopants of a first semiconductor type, the second doped regions comprise a plurality of dopants of a second semiconductor type different from the first semiconductor type, and the first doped regions and the second doped regions are alternately arranged. The source region is in the well region. The base region is in the well region and adjacent to the source region. The gate layer is on the epitaxial layer. The current spreading layer may be used to relax the localized region of electron flow so that electron flow is not concentrated only in a specific region.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips
Technical Field
Some embodiments of the present disclosure relate to semiconductor devices.
Background
Power devices, such as power metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field-Effect Transistor, MOSFETs), may include a gate, a source, and a drain. When a voltage is applied to the gate, electrons can flow from the source through the channel to the drain. When the channel is horizontal, the path of electron flow is easily limited, so that the current of the power element is small and the conversion efficiency is not high.
Disclosure of Invention
The present disclosure provides a semiconductor device including a substrate, an epitaxial layer, a well region, a current diffusion layer, a source region, a base region, and a gate layer. The epitaxial layer is on the substrate. The well region is in the epitaxial layer. The current diffusion layer is arranged in the epitaxial layer and under the well region, wherein the current diffusion layer comprises a plurality of first doped regions and a plurality of second doped regions, the first doped regions comprise a plurality of dopants of a first semiconductor type, the second doped regions comprise a plurality of dopants of a second semiconductor type different from the first semiconductor type, and the first doped regions and the second doped regions are alternately arranged. The source region is in the well region. The base region is in the well region and adjacent to the source region. The gate layer is on the epitaxial layer.
In some embodiments, the second doped region has a distance from the well region.
In some embodiments, the top of the first doped region protrudes upward from the top of the second doped region.
In some embodiments, the width of the first doped region decreases as it gets closer to the well region.
In some embodiments, the bottom of the first doped region is flush with the bottom of the second doped region.
Some embodiments of the present disclosure provide a semiconductor device including a substrate, an epitaxial layer, a well region, a current diffusion layer, a source region, a base region, and a gate layer. The epitaxial layer is on the substrate, the epitaxial layer comprises a drift region, and the drift region is provided with a plurality of dopants of a first semiconductor type. The well region is in the epitaxial layer and is surrounded by the drift region. The current diffusion layer is in the epitaxial layer and is closer to the well region than the substrate, wherein the current diffusion layer comprises a doped region having a plurality of dopants of a second semiconductor type and a plurality of conductive materials arranged in the doped region. The source region is in the well region. The base region is in the source region. The gate layer is over the current spreading layer.
In some embodiments, the conductive material is a plurality of metals.
In some embodiments, the conductive material is a plurality of carbon nanotubes.
In some embodiments, there is a distance between adjacent conductive materials.
In some embodiments, a top of at least one of the conductive materials protrudes upward from a top of the doped region.
Some embodiments of the present disclosure relate to current spreading layers in semiconductor devices. In particular, the current spreading layer may be used to relax localized regions of electron flow so that electron flow is not concentrated only in specific regions.
Drawings
Fig. 1 illustrates a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
Fig. 2A is an enlarged view of a region M in fig. 1, and the region M shows the relative positions of the current diffusion layer, the well region and the drift region.
Fig. 2B-2F are cross-sectional views of a current spreading layer, a well region, and a drift region in other embodiments.
Fig. 3-16 are cross-sectional views illustrating fabrication of semiconductor devices according to some embodiments of the present disclosure.
Detailed Description
Some embodiments of the present disclosure relate to a current spreading layer (current spreading layer, CSL) in a semiconductor device. In particular, the current spreading layer may be used to relax localized regions of electron flow so that electron flow is not concentrated only in specific regions. Some embodiments of the present disclosure provide different kinds of current spreading layers.
Fig. 1 illustrates a cross-sectional view of a semiconductor device 100 in accordance with some embodiments of the present disclosure. The semiconductor device 100 includes a substrate 110, an epitaxial layer 120, a well region 122, a current diffusion layer 200, a source region 124, a base region 126, and a gate layer 140. An epitaxial layer 120 is on the substrate 110. Well region 122 is in epitaxial layer 120. The current spreading layer 200 is in the epitaxial layer 120 and under the well region 122. The current spreading layer 200 is closer to the well region 122 than the substrate 110. Source region 124 is in well region 122. The base region 126 is in the well region 122 and adjacent to the source region 124. The gate layer 140 is on the epitaxial layer 120 and on the current diffusion layer 200. Well region 122 includes a channel region 122C, and channel region 122C is adjacent source region 124.
The semiconductor device 100 may include regions having different semiconductor types. In some embodiments, the epitaxial layer 120 may include a drift region 121, a well region 122, a source region 124, and a base region 126. The substrate 110, the drift region 121, and the source region 124 may include a plurality of dopants having a first semiconductor type (e.g., N-type). The well region 122 and the base region 126 may include a plurality of dopants having a second semiconductor type (e.g., P-type). The first semiconductor type is different from the second semiconductor type. In some embodiments, the substrate 110 and the source region 124 may be heavily doped regions of a first semiconductor type, the drift region 121 may be lightly doped regions of a first semiconductor type, the well region 122 may be lightly doped regions of a second semiconductor type, and the base region 126 may be heavily doped regions of a second semiconductor type.
The semiconductor device 100 further includes a gate dielectric layer 130, the gate dielectric layer 130 underlying the gate layer 140 and on the epitaxial layer 120. In other words, the gate dielectric layer 130 is between the gate layer 140 and the epitaxial layer 120. The semiconductor device 100 also includes a source contact 150, a dielectric layer 160, an interconnect structure 170, and a drain electrode 190. A source contact 150 is on the source region 124 and the base region 126. Dielectric layer 160 covers epitaxial layer 120, gate dielectric layer 130, gate layer 140, and source contact 150. Interconnect structure 170 extends through dielectric layer 160 and contacts source contact 150. The drain electrode 190 is under the substrate 110.
The current spreading layer 200 may be used to widen the flow range of the electron flow of the semiconductor device 100. Specifically, after the gate layer 140 voltage is applied (i.e., the transistor is "on"), the electron current EC may flow from the source contact 150, through the source region 124, the channel region 122C, the drift region 121, the current spreading layer 200, and the substrate 110 to the drain electrode 190. Since electrons pass through the channel region 122C in the horizontal direction, the path of the electron flow EC is easily restricted. When the electron flow passes through the current diffusion layer 200, the current diffusion layer 200 can disperse the path of the electron flow so that the electron flow is not concentrated in the same region, for example, the electron flow is not concentrated in the drift region 121 under the gate layer 140. Thus, the electron flow of the semiconductor device 100 can be increased, and the power conversion efficiency of the semiconductor device 100 can be improved.
Fig. 2A shows an enlarged view of a region M in fig. 1, and the region M shows the relative positions of the current diffusion layer 200, the well region 122 and the drift region 121. The current diffusion layer 200 includes a plurality of first doped regions 210 and a plurality of second doped regions 220. The first doped region 210 includes a plurality of dopants of a first semiconductor type, and the second doped region 220 includes a plurality of dopants of a second semiconductor type different from the first semiconductor type. The first doped regions 210 are alternately arranged with the second doped regions 220. In other words, the first doped region 210 has the same semiconductor type dopant as the substrate 110, the drift region 121, and the source region 124, and the second doped region 220 has the same semiconductor type dopant as the well region 122 and the base region 126. In some embodiments, the first doped region 210 is a heavily doped region of a first semiconductor type and the second doped region 220 is a heavily doped region of a second semiconductor type.
The first doped region 210 has a top 210T and a bottom 210B, and the top 210T is narrower than the bottom 210B of the first doped region 210. The top 210T of the first doped region 210 protrudes upward from the top 220T of the second doped region 220. The second doped region 220 of the current diffusion layer 200 has a distance D1 from the well region 122, i.e., a portion of the drift region 121 is between the second doped region 220 of the current diffusion layer 200 and the well region 122. The first doped regions 210 have a width W1, and a distance D2 is between adjacent first doped regions 210. In some embodiments, the distance D1 is between 0.8 microns and 1.5 microns, the width W1 at the bottom 210B is between 1 micron and 2 microns, and the distance D2 is between 100 nanometers and 500 nanometers. When the electron flow EC flows through the drift region 121 and enters the current diffusion layer 200, the electron flow EC enters from the top 210T of the first doped region 210 and flows downward. Since the width W1 of the first doping region 210 decreases as it gets closer to the well region 122, the flow area of the electron flow EC becomes wider gradually to achieve an advantage of relaxing the flow area of the electron flow EC. The second doped regions 220 are disposed between adjacent first doped regions 210, and the top 220T of the second doped regions 220 is lower than the top 210T of the first doped regions 210. Thus, the electron flow EC may be directed into the first doped region 210. The second doped region 220 can be used to maintain the breakdown voltage (breakdown voltage) of the semiconductor device 100 (fig. 1) such that the semiconductor device can withstand a certain level of driving voltage.
Fig. 2B to 2F illustrate different embodiments of the current diffusion layer. Fig. 2B illustrates a cross-sectional view of the current spreading layer 200A, the well region 122, and the drift region 121 in other embodiments. The current diffusion layer 200A includes a doped region 230 having a dopant of a second semiconductor type and a conductive material 240. Conductive material 240 is arranged in doped region 230. The doped region 230 has a different semiconductor type than the drift region 121. In some embodiments, the conductive material 240 may be a metal, such as titanium, nickel, or silver. The top 240T of the conductive material 240 protrudes upward from the top 230T of the doped region 230. Thus, the top 240T of the conductive material 240 contacts the drift region 121. The conductive material 240 may be a structure with a narrow upper portion and a wide lower portion, for example, the conductive material 240 may be triangular. The bottom of the conductive material 240 may have a width W2. In some embodiments, the width W2 is between 5 microns and 10 microns. In some embodiments, the bottoms of adjacent conductive materials 240 may contact each other. When the electron flow EC flows through the drift region 121 and enters the current diffusion layer 200A, the electron flow EC enters from the top 240T of the conductive material 240 and flows downward. Since the conductive material 240 has a structure of being narrow at the top and wide at the bottom, the flow area of the electron flow EC is gradually widened to achieve the advantage of widening the flow area of the electron flow EC. The flow area of the electron flow EC may be further relaxed since the bottoms of adjacent conductive materials 240 are connected together. In this way, the power conversion efficiency of the semiconductor device 100 (fig. 1) can be further improved.
Fig. 2C shows a cross-sectional view of the current spreading layer 200B, the well region 122, and the drift region 121 in other embodiments. The current diffusion layer 200B includes a doped region 230 having a dopant of a second semiconductor type and a conductive material 250. The conductive material 250 is arranged in the doped region 230. The doped region 230 has a different semiconductor type than the drift region 121. In some embodiments, the conductive material 240 may be a metal, such as titanium, nickel, or silver. The top 250T of the conductive material 250 protrudes upward from the top 230T of the doped region 230. Thus, the top 250T of the conductive material 250 contacts the drift region 121. The width W3 of the conductive material 250 is uniform from top to bottom, for example, the conductive material 250 is rectangular. In some embodiments, the width W3 of the conductive material 250 is between 5 microns and 10 microns. With a distance D3 between adjacent conductive materials 250. In some embodiments, the distance D3 is between 1 micron and 3 microns. When the electron flow EC flows through the drift region 121 and enters the current diffusion layer 200B, the electron flow EC enters from the top 250T of the conductive material 250 and flows downward. The flow area of the electron flow EC into the conductive material 250 is wider to achieve the advantage of relaxing the flow area of the electron flow EC.
Fig. 2D illustrates a cross-sectional view of the current spreading layer 200C, the well region 122, and the drift region 121 in other embodiments. The current diffusion layer 200C includes a doped region 230 having a dopant of a second semiconductor type and a conductive material 260. Conductive material 260 is arranged in doped region 230. The doped region 230 has a different semiconductor type than the drift region 121. The conductive material 260 may be metal particles, such as nano-gold particles. In some embodiments, the particle size W4 of the conductive material 260 may be between a few nanometers and 100 nanometers. The conductive materials 260 may be arranged in a plurality of rows, with the top 260T of at least one of the conductive materials 260 protruding upward from the top 230T of the doped region 230. For example, the top 260T of the uppermost row of conductive material 260 contacts the drift region 121. When the electron flow EC flows through the drift region 121 and enters the current diffusion layer 200C, the electron flow EC flows along the surface of the conductive material 260 of the uppermost row to the surface of the conductive material 260 of the next row, and finally flows to the surface of the conductive material 260 of the lowermost row. Thus, the advantage of relaxing the flow area of the electron flow EC can be achieved. The conductive material 260, the conductive material 240 of fig. 2B, and the conductive material 250 of fig. 2C may be metal materials, and the conductive material 260 and the other two may be different in that the other two are larger in size, so that the electron current EC may flow into the conductive material 240 and the conductive material 250. The conductive material 260 is small in size, and thus the electron current EC flows along the surface of the conductive material 260 without flowing into the inside of the conductive material 260.
Fig. 2E shows a cross-sectional view of the current spreading layer 200D, the well region 122, and the drift region 121 in other embodiments. The current diffusion layer 200D includes a doped region 230 having a dopant of a second semiconductor type and a conductive material 270. Conductive material 270 is arranged in doped region 230. The doped region 230 has a different semiconductor type than the drift region 121. The conductive material 270 may be carbon nanotubes, and the conductive material 270 may be arranged in a plurality of rows at an oblique angle. The conductive materials 270 may contact each other, for example, a bottom 270B of the upper row of conductive materials 270 may contact a top 270T of the lower row of conductive materials 270. Alternatively, the top 270T or the bottom 270B of the same row of conductive material 270 may contact each other. A top 270T of at least one of the conductive materials 270 protrudes upward from the top 230T of the doped region 230. For example, the top 270T of the uppermost row of conductive material 270 contacts the drift region 121. Conductive material 270 has a width W5. In some embodiments, the width W5 is between 5 nanometers and 10 nanometers. When the electron flow EC flows through the drift region 121 and enters the current diffusion layer 200D, the electron flow EC flows along the inside of the conductive material 270 of the uppermost row to the inside of the conductive material 270 of the next row, and finally flows to the inside of the conductive material 270 of the lowermost row. Thus, the advantage of relaxing the flow area of the electron flow EC can be achieved.
Fig. 2F shows a cross-sectional view of the current spreading layer 200E, the well region 122, and the drift region 121 in other embodiments. The current diffusion layer 200E includes a doped region 230 having a dopant of a second semiconductor type and a conductive material 280. Conductive material 280 is disposed in doped region 230. The doped region 230 has a different semiconductor type than the drift region 121. The conductive material 280 may be carbon nanotubes, and the conductive material 280 may be arranged in a plurality of rows at a horizontal angle. The conductive materials 280 do not contact each other and there may be a distance D4 between adjacent conductive materials 280. In some embodiments, the distance D4 may be between 0.3 nanometers and 1.0 nanometers. Conductive material 280 has a width W6. In some embodiments, the width W6 is between 5 nanometers and 10 nanometers. A portion of the uppermost row of conductive material 280 contacts the drift region 121. When the electron flow EC flows through the drift region 121 and enters the current diffusion layer 200E, the electron flow EC flows along the surface of the conductive material 280 in the uppermost row to the surface of the conductive material 280 in the next row, and finally flows to the surface of the conductive material 280 in the lowermost row. Thus, the advantage of relaxing the flow area of the electron flow EC can be achieved. Conductive material 280 may be carbon nanotubes as compared to conductive material 270 of fig. 2E, except that the portions of both are more conductive. For example, the surface of the conductive material 280 is more conductive, so the electron flow EC is more likely to flow along the surface of the conductive material 280. The interior of the conductive material 280 is more conductive and thus the electron current EC flows more easily along the interior of the conductive material 280.
Fig. 3-16 illustrate cross-sectional views of fabrication of a semiconductor device 100 according to some embodiments of the present disclosure. Referring to fig. 3, a substrate 110' and an epitaxial layer 120 are provided. The substrate 110' is any suitable substrate. In some embodiments, the substrate 110' may be made of, for example, but not limited to, silicon carbide. The substrate 110' may be doped with a dopant of a first semiconductor type. For example, the substrate 110' may be an N-type heavily doped substrate, such as a heavily doped region comprising N-type dopants such as phosphorus, arsenic, and the like. Next, an epitaxial layer 120 may be formed on the substrate 110'. In some embodiments, epitaxial layer 120 may be made of, for example, but not limited to, silicon carbide. The epitaxial layer 120 may be doped with a dopant of a first semiconductor type. For example, the epitaxial layer 120 may be an N-type lightly doped substrate, such as a lightly doped region containing N-type dopants such as phosphorus, arsenic, and the like. That is, the doping concentration of epitaxial layer 120 may be lower than the doping concentration of substrate 110'.
Referring to fig. 4, a well region 122 is formed in the epitaxial layer 120. Specifically, a patterned masking layer may be formed over the epitaxial layer 120, and then ion implantation of dopants of the second semiconductor type may be performed from above the epitaxial layer 120 to form the well region 122 having dopants of the second semiconductor type. After the ion implantation process, the patterned masking layer may be removed. After forming the well region 122, the epitaxial layer 120 may be divided into a well region 122 doped with the second semiconductor type ions and a drift region 121 undoped with the second semiconductor type ions, and the well region 122 is covered with the drift region 121. Thus, the drift region 121 still contains dopants of the first semiconductor type. For example, the drift region 121 remains an N-type lightly doped region. In some embodiments, well region 122 may be a P-type lightly doped region, such as a lightly doped region containing P-type dopants of boron, gallium, and the like.
Referring to fig. 5, a source region 124 is formed in the well region 122. Specifically, another patterned masking layer may be formed over the epitaxial layer 120, followed by ion implantation of dopants of the first semiconductor type from above the well region 122 to form a source region 124 comprising dopants of the first semiconductor type. After the ion implantation process, the patterned masking layer may be removed. The sides and bottom of the source region 124 are covered by the well region 122. In some embodiments, source region 124 may be an N-type heavily doped region, such as a heavily doped region comprising N-type dopants of phosphorus, arsenic, and the like. That is, the doping concentration of the source region 124 may be higher than that of the drift region 121.
Referring to fig. 6, a base region 126 is formed in the source region 124. Specifically, ion implantation of dopants of the second semiconductor type may be performed in the source region 124 to form the base region 126 having dopants of the second semiconductor type. The bottom of the base region 126 may contact the well region 122, and the base region 126 does not extend toward the well region 122. In some embodiments, the base region 126 may be a P-type heavily doped region, such as a heavily doped region comprising P-type dopants of boron, gallium, or the like. That is, the doping concentration of the base region 126 may be higher than that of the well region 122.
It should be noted that the process sequence of fig. 4-6 may be adjusted. Therefore, the order of formation of the well region 122, the source region 124, and the base region 126 may also be adjusted. For example, the base region 126 may be formed in the epitaxial layer 120, followed by the source region 124, and finally the well region 122.
Referring to fig. 7, a gate dielectric layer 130 and a gate layer 140 are formed on the epitaxial layer 120. Specifically, in some embodiments, a dielectric layer may be formed on the epitaxial layer 120 first. Next, the dielectric layer is patterned to form a gate dielectric layer 130. Gate dielectric layer 130 covers a portion of well region 122. And, the gate dielectric layer 130 covers the drift region 121 between two adjacent well regions 122. Next, a semiconductor layer may be formed on the epitaxial layer 120 and the gate dielectric layer 130. Next, the semiconductor layer is patterned to form a gate layer 140. In some embodiments, gate layer 140 has a smaller width than gate dielectric layer 130, so that a portion of gate layer 140 exposes a portion of gate dielectric layer 130, as shown in fig. 7.
In other embodiments, a dielectric layer and a semiconductor layer may be sequentially formed on the epitaxial layer 120. Next, the semiconductor layer may be patterned to form the gate layer 140, and then the dielectric layer may be patterned to form the gate dielectric layer 130 using the gate layer 140 as a mask. Accordingly, the sidewalls of the gate layer 140 may be aligned with the sidewalls of the gate dielectric layer 130 (not shown). In some implementations, the gate dielectric layer 130 may be made of, for example, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. In some embodiments, the gate layer 140 may be made of, for example, but not limited to, polysilicon.
Referring to fig. 8, a source contact 150 is formed on the source region 124 and the base region 126. Specifically, a conductor layer may be formed over the structure of fig. 7, followed by patterning of the conductor layer to form source contacts 150 over the source region 124 and the base region 126. In some implementations, the source contact 150 may be made of a material such as, but not limited to, aluminum, titanium nitride, the like, or a combination thereof.
Referring to fig. 9, a dielectric layer 160 may be formed on the gate dielectric layer 130 and the gate layer 140. Next, an interconnect structure 170 is formed in the dielectric layer 160. Specifically, a dielectric layer 160 may be formed on the gate dielectric layer 130 and the gate layer 140, such that the dielectric layer 160 covers the gate dielectric layer 130, the gate layer 140 and the source contact 150. Next, an opening is formed in the dielectric layer 160, and an interconnect structure 170 is formed in the opening. Interconnect structure 170 contacts source contact 150. In some embodiments, the dielectric layer 160 may be made of a material such as, but not limited to, silicon oxide, silicon nitride, the like, or a combination thereof. The interconnect structure 170 may be made of a material such as, but not limited to, aluminum, titanium nitride, the like, or a combination thereof. Next, a carrier 180 is formed over the dielectric layer 160 and the interconnect structure 170. Carrier 180 may be used to provide support during a subsequent process of polishing semiconductor device 100.
Referring to fig. 10, the semiconductor device 100 is polished from below the semiconductor device 100 to remove the substrate 110' and a portion of the epitaxial layer 120. After removing the substrate 110' and a portion of the epitaxial layer 120, a distance is provided between the bottom of the epitaxial layer 120 and the well region 122. That is, in fig. 10, the removed epitaxial layer 120 is the drift region 121, and the well region 122, the source region 124 and the base region 126 are not removed. In some embodiments, the semiconductor device 100 may be flipped prior to polishing the semiconductor device 100. It should be noted that, in order to make the orientations of the elements consistent (e.g., bottom, top, etc.), fig. 10 and the following figures illustrate the semiconductor device 100 as it is not flipped, but do not represent embodiments of the present disclosure that merely disclose the semiconductor device 100 as it is, but rather, directly performs the subsequent processes.
Referring to fig. 11, a current diffusion layer 200 is formed at the bottom of the epitaxial layer 120. Fig. 12A to 12B illustrate a manner of forming the current diffusion layer 200 according to some embodiments, and fig. 12A to 12B are exemplified by a region M of fig. 11. Referring to fig. 12A, ion implantation of a dopant of a second semiconductor type may be performed from below the epitaxial layer 120 to form a second doped region 220 having a dopant of the second semiconductor type at the bottom of the epitaxial layer 120. In some embodiments, a P-type ion implantation may be performed from below the epitaxial layer 120 to form a P-type doped region 220 at the bottom of the epitaxial layer 120, and the P-type doped region 220 may be a heavily doped region, such as a heavily doped region including P-type dopants of boron, gallium, and the like. After the second doped region 220 is formed, a distance D1 is provided between the second doped region 220 and the well region 122. In some embodiments, the distance D1 is between 0.8 microns and 1.5 microns. Next, referring to fig. 12B, the first doped regions 210 arranged in the second doped regions 220 are formed. Specifically, a patterned masking layer may be formed under the epitaxial layer 120, ion implantation of dopants of the first semiconductor type is performed from below the epitaxial layer 120 to form a first doped region 210 having dopants of the first semiconductor type, and the first doped region 210 is arranged in the second doped region 220. In some embodiments, an N-type ion implantation may be performed from below the epitaxial layer 120 to form an N-type doped region 210, and the N-type doped region 210 may be a heavily doped region, such as a heavily doped region comprising N-type dopants such as phosphorus, arsenic, and the like. Since ions are implanted from below epitaxial layer 120, the width of first doped region 210 near well region 122 may be smaller than the width of first doped region 210 away from well region 122. The doping intensity of the first doped region 210 may be controlled such that the top 210T of the first doped region 210 protrudes from the top 220T of the second doped region 220, and the bottom 210B of the first doped region 210 is flush with the bottom 220B of the second doped region 220. That is, the first doped region 210 may contact the drift region 121. In some embodiments, the top 210T of the first doped region 210 may also be flush with the top 220T of the second doped region 220.
Fig. 13A to 13C illustrate a formation method of the current diffusion layer 200A according to other embodiments. Referring to fig. 13A, ion implantation of dopants of a second semiconductor type may be performed from below the epitaxial layer 120 to form a doped region 230 having dopants of the second semiconductor type. The detailed description of fig. 13A is as shown in fig. 12A, and thus, the description is not repeated here. Next, referring to fig. 13B, an etching process is performed to form an opening O in the doped region 230. The depth of the opening O may be controlled such that the opening O exposes a small amount of the drift region 121. Next, referring to fig. 13C, a conductive material 240 is formed in the opening O, and the conductive material 240 may contact the drift region 121. The shape of the conductive material 240 may be defined by the shape of the opening O. That is, the conductive material 240 of different shapes may be formed by forming the opening O of different shapes. In some embodiments, the bottoms of the openings O are connected, and thus the bottoms 240B of the formed conductive material 240 are also connected, as shown in fig. 2B and 13C. In other embodiments, the bottoms of the openings O are not connected, and thus the bottoms 240B of the conductive material 240 are not connected, as shown in fig. 2C. The current diffusion layer 200B of fig. 2C is formed in a similar manner to the current diffusion layer 200A, except that the shape of the opening O is different, and thus, the related details are not repeated here.
Fig. 14A to 14D illustrate a formation method of the current diffusion layer 200C according to other embodiments. Referring to fig. 14A, a metal nanoparticle solution may be first coated on the surface of the epitaxial layer 120. The metal nanoparticle solution includes a conductive material 260, and the conductive material 260 may be uniformly distributed on the surface of the epitaxial layer 120, and a portion of the conductive material 260 is exposed to the environment. Next, referring to fig. 14B, an epitaxial growth process is performed such that the conductive material 260 is encapsulated by the epitaxial layer 120. A material of the same semiconductor type as that of the epitaxial layer 120 may be deposited on the epitaxial layer 120 of fig. 14A so that the material of the epitaxial layer 120 is uniform from top to bottom. Next, referring to fig. 14C, the coating of the metal nanoparticle solution and the performing of the epitaxial growth process are repeated, so that the conductive material 260 is arranged in a plurality of rows in the epitaxial layer 120. Next, referring to fig. 14D, ion implantation of a dopant of the second semiconductor type is performed from below the epitaxial layer 120 to form a doped region 230 having a dopant of the second semiconductor type at the bottom of the epitaxial layer 120. In some embodiments, a P-type ion implantation may be performed from below the epitaxial layer 120 to form the P-type doped region 230, and the P-type doped region 230 may be a P-type heavily doped region, such as a heavily doped region including P-type dopants of boron, gallium, and the like. The doping intensity of the doped region 230 may be controlled such that the top 260T of the uppermost row of conductive material 260 protrudes from the top 230T of the doped region 230. After forming the doped region 230, the doped region 230 of the current diffusion layer 200 has a distance D1 from the well region 122. In some embodiments, the distance D1 is between 0.8 microns and 1.5 microns.
Fig. 15A to 15D illustrate a formation method of the current diffusion layer 200D according to other embodiments, respectively. Referring to fig. 15A, a conductive material 270 may be grown on the surface of the epitaxial layer 120, and the conductive material 270 may be a carbon nanotube. The growth direction of the carbon nanotubes can be determined according to the characteristics of the carbon nanotubes to be grown. The carbon nanotube characteristics may include portions of the carbon nanotubes that are more conductive. For example, when the portion of the grown carbon nanotubes that is more conductive is in the tube, the growth direction of the carbon nanotubes is inclined to the surface of the epitaxial layer 120, as shown in fig. 15A. Next, referring to fig. 15B, an epitaxial growth process is performed such that the conductive material 270 is encapsulated by the epitaxial layer 120. A material having the same semiconductor type as that of the epitaxial layer 120 may be deposited on the epitaxial layer 120 of fig. 15A so that the material of the epitaxial layer 120 is uniform from top to bottom. Next, referring to fig. 15C, the conductive material 270 is repeatedly grown and an epitaxial growth process is performed such that the conductive material 270 is arranged in a plurality of rows in the epitaxial layer 120. Next, referring to fig. 15D, ion implantation of the dopant of the second semiconductor type is performed from below the epitaxial layer 120 to form a doped region 230 having the dopant of the second semiconductor type at the bottom of the epitaxial layer 120. The doping intensity of the doped region 230 may be controlled such that the top 270T of the uppermost row of conductive material 270 protrudes from the top 230T of the doped region 230. Doped region 230 of fig. 15D is shown as doped region 230 of fig. 14D, and thus, the relevant details are not repeated here.
The current diffusion layer 200E of fig. 2F is formed in a similar manner to the current diffusion layer 200D. The difference is that the more conductive portion of the conductive material 280 of fig. 2F is the surface of the conductive material 280, so the growth direction of the carbon nanotubes may be horizontal to the surface of the epitaxial layer 120.
After the current spreading layer 200 is formed, referring to fig. 16, the carrier 180 is removed. Next, a substitute epitaxial layer and a substitute substrate are placed under the current diffusion layer 200. The substitute epitaxial layer may be a lightly doped region having dopants of the first semiconductor type, for example, the substitute epitaxial layer may serve as the drift region 121, and the substitute substrate may be the substrate 110 in fig. 1. In some embodiments, the substitute epitaxial layer and the substitute substrate may be formed in advance. After the formation of the current spreading layer 200, a substitute epitaxial layer and a substitute substrate are directly placed under the current spreading layer 200. Next, a drain electrode 190 is formed under the alternative substrate (i.e., substrate 110).
In summary, some embodiments of the present disclosure include a current spreading layer. The current spreading layer can be used to widen the flow range of the electron flow to increase the overall current. The flow range of the electron flow may be dispersed in various ways, for example, by ion-doped regions, metals, or carbon nanotubes. In this way, the power conversion efficiency of the semiconductor device can be improved.
The foregoing is only a few, but not all, of the embodiments of the present disclosure, and any equivalent modifications of the embodiments of the present disclosure will be apparent to those skilled in the art from a review of the present disclosure, are intended to be encompassed by the claims of the present disclosure.
[ symbolic description ]
100: semiconductor device with a semiconductor device having a plurality of semiconductor chips
110: substrate board
110': substrate board
120: epitaxial layer
121: drift region
122: well region
124: source region
126: base region
130: gate dielectric layer
140: gate layer
150: source contact
160: dielectric layer
170: interconnect structure
180: carrier plate
190: drain electrode
200: current diffusion layer
200A: current diffusion layer
200B: current diffusion layer
200C: current diffusion layer
200D: current diffusion layer
200E: current diffusion layer
210: first doped region/N-type doped region
210B: bottom part
210T: top part
220: second doped region/P-doped region
220B: bottom part
220T: top part
230: doped region
230T: top part
240: conductive material
240B: bottom part
240T: top part
250: conductive material
250T: top part
260: conductive material
260T: top part
270: conductive material
270B: bottom part
270T: top part
280: conductive material
D1: distance of
D2: distance of
D3: distance of
D4: distance of
EC: electron flow
M: region(s)
O: an opening
W1: width of (L)
W2: width of (L)
W3: width of (L)
W4: particle size
W5: width of (L)
W6: width of the material.

Claims (10)

1. A semiconductor device, comprising:
a substrate;
an epitaxial layer on the substrate;
a well region in the epitaxial layer;
a current diffusion layer in the epitaxial layer and under the well region, wherein the current diffusion layer comprises a plurality of first doped regions and a plurality of second doped regions, the plurality of first doped regions comprising a plurality of dopants of a first semiconductor type, and the plurality of second doped regions comprising a plurality of dopants of a second semiconductor type different from the first semiconductor type, the plurality of first doped regions alternating with the plurality of second doped regions;
a source region in the well region;
a base region in the well region and adjacent to the source region; and
a gate layer on the epitaxial layer.
2. The semiconductor device of claim 1, wherein the plurality of second doped regions have a distance from the well region.
3. The semiconductor device according to any one of claims 1 to 2, wherein a plurality of tops of the plurality of first doped regions protrude upward from a plurality of tops of the plurality of second doped regions.
4. The semiconductor device according to any one of claims 1 to 2, wherein a plurality of widths of the plurality of first doped regions decreases as approaching the well region.
5. The semiconductor device of any one of claims 1-2, wherein bottoms of the first plurality of doped regions are flush with bottoms of the second plurality of doped regions.
6. A semiconductor device, comprising:
a substrate;
an epitaxial layer on the substrate, the epitaxial layer comprising a drift region, the drift region having a plurality of dopants of a first semiconductor type;
a well region in the epitaxial layer and surrounded by the drift region;
a current diffusion layer in the epitaxial layer and closer to the well region than the substrate, wherein the current diffusion layer comprises a doped region having a plurality of dopants of a second semiconductor type and a plurality of conductive materials arranged in the doped region;
a source region in the well region;
a base region in the source region; and
and a gate layer over the current diffusion layer.
7. The semiconductor device according to claim 6, wherein the plurality of conductive materials are a plurality of metals.
8. The semiconductor device of claim 6, wherein the plurality of conductive materials are a plurality of carbon nanotubes.
9. The semiconductor device according to any one of claims 6 to 8, wherein a distance is provided between adjacent ones of the plurality of conductive materials.
10. The semiconductor device of any one of claims 6 to 8, wherein a top of at least one of the plurality of conductive materials protrudes upward from a top of the doped region.
CN202211067393.9A 2022-09-01 2022-09-01 Semiconductor device with a semiconductor device having a plurality of semiconductor chips Pending CN117673125A (en)

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CN202211067393.9A CN117673125A (en) 2022-09-01 2022-09-01 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211067393.9A CN117673125A (en) 2022-09-01 2022-09-01 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Publications (1)

Publication Number Publication Date
CN117673125A true CN117673125A (en) 2024-03-08

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Country Status (1)

Country Link
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