CN117672873A - Manufacturing method of chip packaging structure and chip packaging structure - Google Patents

Abstract

The embodiment of the application provides a manufacturing method of a chip packaging structure and the chip packaging structure, and relates to the technical field of chip packaging, and the method comprises the following steps: providing a substrate; setting a first positioning mark on the substrate; setting a second positioning mark on the substrate based on the first positioning mark; attaching a chip assembly to the substrate based on the second positioning mark, wherein the chip assembly comprises at least one chip, and the chip comprises pins; forming a plastic sealing layer covering the chip assembly on one side of the substrate; an insulating layer is arranged on one side of the chip assembly, which is opposite to the plastic sealing layer; and forming a rewiring layer on one side of the insulating layer, which is far away from the plastic sealing layer, based on the second positioning mark. The alignment precision between the pin of the rewiring block and the chip can be greatly improved, so that the precision of chip packaging can be greatly improved, and the quality of the chip packaging structure can be improved.

Description

Manufacturing method of chip packaging structure and chip packaging structure

Technical Field

The present disclosure relates to the field of chip packaging technologies, and in particular, to a method for manufacturing a chip packaging structure and a chip packaging structure.

Background

Chips are also known as microcircuits, microchips, integrated circuits, etc., which are in fact a collective term for semiconductor electronic component products. There are many kinds of chips, and the chips can be classified into analog chips and digital chips according to different processing signals. In order to protect the chip, the chip needs to be packaged, and a chip packaging structure is formed after the chip is packaged.

However, the alignment of the chip package in the related art is poor, thereby affecting the quality of the chip package structure.

Disclosure of Invention

In order to overcome the technical problems mentioned in the background of the technology, embodiments of the present application provide a method for manufacturing a chip package structure and a chip package structure.

The application provides a manufacturing method of a chip packaging structure, which comprises the following steps:

providing a substrate;

setting a first positioning mark on the substrate;

setting a second positioning mark on the substrate based on the first positioning mark;

attaching a chip assembly to the substrate based on the second positioning mark, wherein the chip assembly comprises at least one chip, and the chip comprises pins;

forming a plastic sealing layer covering the chip assembly on one side of the substrate;

an insulating layer is arranged on one side of the chip assembly, which is opposite to the plastic sealing layer;

and forming a rewiring layer on one side, far away from the plastic sealing layer, of the insulating layer based on the second positioning mark, wherein the rewiring layer comprises a rewiring unit, and the rewiring unit is electrically connected with a pin of the chip.

In one possible embodiment, the step of setting a second positioning mark on the substrate based on the first positioning mark includes:

forming a metal layer on one side of the substrate;

coating photoresist on one side of the metal layer far away from the substrate, and exposing and developing the photoresist to form patterned photoresist;

etching the metal layer based on the patterned photoresist to form a patterned metal block;

and removing part of the patterned metal block based on the first positioning mark, and forming a second positioning mark on the substrate by the rest of the patterned metal block.

In one possible embodiment, after the step of etching the metal layer based on the patterned photoresist to form a patterned metal block, the method further includes:

removing the photoresist;

coating a transparent protective layer covering the patterned metal block on one side of the substrate;

and grinding the transparent protective layer.

In one possible embodiment, before the step of attaching the chip assembly on the substrate based on the second positioning mark, the method further includes:

checking a first offset of the second positioning mark based on the first positioning mark; if the first offset exceeds the preset offset, resetting the second positioning mark or providing a substrate again.

In one possible embodiment, before the step of disposing an insulating layer on a side of the chip assembly opposite to the molding layer, the method further includes:

peeling the plastic sealing layer, the chip assembly and the second positioning mark from the substrate;

and detecting a second offset of the chip assembly based on the second positioning mark.

In one possible embodiment, the step of forming a rewiring layer on a side of the insulating layer away from the molding layer based on the second positioning mark includes:

and forming a rewiring layer on one side of the insulating layer, which is far away from the plastic sealing layer, based on the second positioning mark based on the second offset.

In one possible embodiment, the step of forming a rewiring layer on a side of the insulating layer away from the molding layer based on the second positioning mark includes:

forming a plurality of through holes on the insulating layer along the direction perpendicular to the insulating layer, wherein the through holes correspond to pins of the chip;

forming a rewiring layer on one side of the insulating layer, which is far away from the plastic sealing layer, based on the second positioning mark; and the rewiring unit is electrically connected with the pins of the chip through the through holes.

In one possible embodiment, the step of forming a molding layer on one side of the substrate to cover the chip assembly includes:

and forming a plastic sealing layer covering the chip assembly on one side of the substrate, and grinding the plastic sealing layer.

In one possible embodiment, after the step of forming a rewiring layer on a side of the insulating layer away from the molding layer based on the second positioning mark, the method further includes:

and cutting the plastic sealing layers among the packaged chips along the direction perpendicular to the substrate to separate the packaged chips from each other.

In one possible embodiment, the present application further provides a chip packaging structure, where the chip packaging structure is manufactured by the manufacturing method of the chip packaging structure described in the present application.

Compared with the prior art, the application has the following beneficial effects:

according to the manufacturing method of the chip packaging structure and the chip packaging structure, the second positioning mark is arranged on the substrate based on the first positioning mark, and the chip assembly and the rewiring layer are arranged based on the second positioning mark, so that the alignment precision between the rewiring block and the pins of the chip can be greatly improved, the precision of chip packaging can be greatly improved, and the quality of the chip packaging structure can be improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 illustrates a schematic top view of a die assembly attached to a substrate in accordance with the related art provided herein;

FIG. 2 illustrates a schematic top view of a related art molding layer covering a chip assembly provided herein;

FIG. 3 illustrates a schematic top view of a related art chip assembly peeled from a substrate provided in the present application;

FIG. 4 illustrates a top view of a related art redistribution layer disposed on a chip assembly provided by the present application;

FIG. 5 illustrates a top view of a chip offset in the related art provided herein;

FIG. 6 illustrates a top view of a related art rewiring layer offset provided herein;

fig. 7 illustrates a schematic cross-sectional view of a chip package structure fabricated by a related art method provided herein;

fig. 8 illustrates a flow chart of a method for manufacturing a chip package structure provided by the present application;

FIG. 9 illustrates a schematic top view of a first positioning mark provided on a substrate according to the present application;

FIG. 10 illustrates a schematic top view of a second positioning mark provided in the present application on a substrate;

FIG. 11 illustrates a schematic top view of a die assembly attached to a substrate based on a second registration mark provided herein;

FIG. 12 illustrates a schematic top view of a plastic layer provided herein over a substrate to cover a chip assembly;

FIG. 13 illustrates a schematic top view of the chip assembly and the second alignment mark provided herein after being peeled from the substrate;

FIG. 14 illustrates a schematic cross-sectional view of the chip assembly and the second alignment mark provided herein after being peeled from the substrate;

fig. 15 illustrates a schematic cross-sectional view of the chip assembly provided herein with an insulating layer on a side of the chip assembly remote from the molding layer;

FIG. 16 illustrates a schematic cross-sectional view of a via opening in an insulating layer provided herein;

FIG. 17 illustrates a schematic top view of a redistribution layer provided over insulation provided herein;

FIG. 18 illustrates a schematic cross-sectional view of a redistribution layer provided on an insulation;

FIG. 19 is a flowchart illustrating a specific implementation method of step S12 provided in the present application;

FIG. 20 illustrates a schematic cross-sectional view of a metal layer formed on one side of a substrate provided herein;

FIG. 21 illustrates a schematic cross-sectional view of the photoresist coated on a side of a metal layer remote from a substrate provided herein;

FIG. 22 illustrates a schematic cross-sectional view of etching a metal layer to form a patterned metal block provided herein;

FIG. 23 illustrates a flow chart of a method provided herein after the step of etching the metal layer to form a patterned metal block;

FIG. 24 illustrates a schematic cross-sectional view of photoresist removal provided herein on a side of a patterned metal block away from a substrate;

FIG. 25 illustrates a schematic cross-sectional view of a transparent protective layer coated on one side of a substrate to cover a patterned metal block provided herein;

FIG. 26 illustrates a schematic top view of a patterned metal block provided on one side of a substrate as provided herein;

fig. 27 illustrates a schematic cross-sectional view of a solder ball provided on a rewiring unit provided herein.

Reference numerals: 1. a substrate; 2. a chip assembly; 21. a chip; 211. pins; 3. positioning marks; 4. a plastic sealing layer; 5. a rewiring layer; 51. a rewiring block; 6. an insulating layer; 61. a via hole; 7. a first positioning mark; 8. a second positioning mark; 9. a metal layer; 91. patterning the metal block; 10. patterning the photoresist; 11. a transparent protective layer; 12. solder balls.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the present application, it should be noted that, the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship that is commonly put when the product of the application is used, are merely for convenience of describing the present application and simplifying the description, and are not indicative or implying that the apparatus or electronic component to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present application.

It should be noted that, in the case of no conflict, different features in the embodiments of the present application may be combined with each other.

The manufacturing method of the chip packaging structure in the related art comprises the following steps:

referring to fig. 1, a positioning mark 3 is disposed on a substrate 1, and a chip assembly 2 is attached to the substrate 1 based on the positioning mark 3, wherein the chip assembly 2 includes a chip 21, and the chip 21 includes pins.

Referring to fig. 2, a molding layer 4 is disposed on a substrate 1 to cover a chip assembly 2.

Referring to fig. 3, the chip assembly 2 and the molding layer 4 are peeled off from the substrate 1.

Referring to fig. 4, an insulating layer is formed on a side of the chip assembly 2 opposite to the plastic sealing layer 4, a via hole is formed on the insulating layer, and then a redistribution layer 5 is formed on a side of the insulating layer away from the substrate 1, wherein the redistribution layer 5 is electrically connected with a pin of the chip 21 through the via hole, so as to complete the manufacture of the package structure of the chip 21.

However, since the chip assembly 2 is disposed based on the positioning mark 3 on the substrate 1, the via hole 61 and the rewiring layer 5 on the insulating layer 6 can be disposed only with the chip 21 as the mark, and thus, the marks to which the chip assembly 2 and the rewiring layer 5 are disposed refer are different. Referring to fig. 5-7, if the chip 21 is offset, the via hole 61 and the redistribution layer 5 are offset when the offset chip 21 is used as a mark, so that the via hole 61 on the insulating layer 6 is offset from the pin 211 of the chip 21, so that the redistribution layer 5 is not easily electrically connected with the pin 211 of the chip 21 through the via hole 61 on the insulating layer 6, thereby affecting the packaging precision of the chip 21, and finally affecting the quality of the packaging structure of the chip 21.

In order to solve the above technical problems. The inventor innovatively designs the following technical schemes, and detailed description will be given below of specific implementation schemes of the present application with reference to the accompanying drawings.

Referring to fig. 8, the present application provides a method for manufacturing a chip 21 package structure, which includes:

s10: a substrate 1 is provided.

The substrate 1 may be a glass substrate 1 or the like.

S11: a first positioning mark 7 is provided on the substrate 1.

Referring to fig. 9, a first positioning mark 7 may be perforated on the substrate 1, or may be provided by laser perforation, and the first positioning mark 7 may be located at a top corner of the substrate 1.

S12: a second positioning mark 8 is provided on the substrate 1 based on the first positioning mark 7.

Referring to fig. 10, a plurality of second positioning marks 8 are disposed on the substrate 1 with the first positioning mark 7 as a reference, the second positioning marks 8 may also be disposed at the top corner of the substrate 1, and one second positioning mark 8 corresponds to one first positioning mark 7.

S13: based on the second positioning mark 8, the chip assembly 2 is attached to the substrate 1, the chip assembly 2 includes at least one chip 21, and the chip 21 includes a pin 211.

Referring to fig. 11, the chip assembly 2 is attached to the substrate 1 based on the second positioning mark 8, for example, an adhesive layer may be coated on the substrate 1, and then the chip assembly 2 is adhered to the substrate 1 by the adhesive layer. The chip assembly 2 may include a plurality of chips 21, and the chips 21 may include a plurality of pins 211, and signals of the chips 21 may be transmitted through the pins 211.

S14: a plastic layer 4 is formed on one side of the substrate 1 to cover the chip assembly 2.

Referring to fig. 12, a plastic layer 4 is disposed on one side of the substrate 1, the plastic layer 4 covers the chip 21, and protects the chip 21, and the plastic layer 4 may be made of epoxy resin.

S15: an insulating layer 6 is provided on the side of the chip assembly 2 opposite the plastic layer 4.

Referring to fig. 13-14, the plastic layer 4, the chip assembly 2 and the second positioning mark 8 are peeled off from the substrate 1.

Referring to fig. 15, an insulating layer 6 is disposed on a side of the chip assembly 2 opposite to the plastic sealing layer 4, the insulating layer 6 can protect and insulate the chip 21, and the insulating layer 6 can be made of polyimide.

S16: based on the second positioning mark 8, a rewiring layer 5 is formed on the side of the insulating layer 6 away from the plastic sealing layer 4, and the rewiring layer 5 comprises a rewiring unit, wherein the rewiring unit is electrically connected with the pins 211 of the chip 21.

Referring to fig. 16, a plurality of vias 61 are formed on the insulating layer 6 along a direction perpendicular to the insulating layer 6 based on the second positioning mark 8, and the vias 61 correspond to the pins 211 of the chip 21.

Referring to fig. 17-18, a redistribution layer 5 is formed on a side of the insulating layer 6 away from the plastic sealing layer 4 based on the second positioning mark 8; the rewiring unit is electrically connected to the pins 211 of the chip 21 through the vias 61.

Since the chip assembly 2 is provided on the substrate 1, the via hole 61 is provided on the insulating layer 6, and the rewiring layer 5 is provided on the insulating layer 6, the second positioning mark 8 is used as a reference. Accordingly, the via hole 61 formed in the insulating layer 6 can more easily correspond to the lead 211 of the chip 21, and the rewiring layer 5 can more easily be electrically connected to the lead 211 of the chip 21 through the via hole 61.

Based on the above design, the second positioning mark 8 is set on the substrate 1 based on the first positioning mark 7, and the chip assembly 2 and the redistribution layer 5 are both set based on the second positioning mark 8, so that the alignment precision between the redistribution block 51 and the pins 211 of the chip 21 can be greatly improved, the precision of packaging the chip 21 can be greatly improved, and the quality of the packaging structure of the chip 21 can be improved.

In a possible embodiment, referring to fig. 19, the step of setting the second positioning mark 8 on the substrate 1 based on the first positioning mark 7 includes:

s121: a metal layer 9 is formed on one side of the substrate 1.

Referring to fig. 20, a metal layer 9 is sputtered on one side of the substrate 1, and the material of the metal layer 9 may be a single layer structure of metal aluminum or a double layer structure of metal titanium and metal copper, and the thickness of the metal layer 9 may be in the range of 0.1 μm to 0.5 μm, for example, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, or 0.5 μm.

S122: a photoresist is coated on a side of the metal layer 9 remote from the substrate 1, and the photoresist is exposed and developed to form a patterned photoresist 10.

Referring to fig. 21, a photoresist is coated on a side of the metal layer 9 away from the substrate 1, and then the photoresist is exposed and developed according to the shape and position of the second positioning mark 8 to be formed, so as to finally form a patterned photoresist 10.

S123: the metal layer 9 is etched based on the patterned photoresist 10 to form a patterned metal block 91.

Referring to fig. 22, the metal layer 9 is etched based on the patterned photoresist 10, and finally a patterned metal block 91 is formed.

S124: based on the first positioning marks 7, part of the patterned metal blocks 91 is removed, and the remaining part of the patterned metal blocks 91 forms second positioning marks 8 on the substrate 1.

Referring to fig. 2 again, with reference to the first positioning mark 7, a part of the patterned metal block 91 is removed, and the remaining part of the patterned metal block 91 is used as the second positioning mark 8, for example, four patterned metal blocks 91 located at the top corners of the substrate 1 and respectively corresponding to the first positioning mark 7 are used as four second positioning marks 8.

The second positioning mark 8 can be more conveniently prepared by the method.

In a possible embodiment, referring to fig. 23, after the step of etching the metal layer 9 based on the patterned photoresist 10 to form the patterned metal block 91, the method further includes:

s01: the photoresist is removed.

Referring to fig. 24, the photoresist on the side of the patterned metal 91 away from the substrate 1 is removed.

S02: a transparent protective layer 11 covering the patterned metal block 91 is coated on one side of the substrate 1.

Referring to fig. 25, a transparent protective layer 11 covering the patterned metal block 91 is coated on one side of the substrate 1, and the transparent protective layer 11 is cured, wherein the transparent protective layer 11 may be polyimide.

Referring to fig. 26, the front projection shape of the patterned metal block 91 on the molding layer 4 may be cross-shaped, so that the center of the second positioning mark 8 may be detected more precisely, and the accuracy of using the second positioning mark 8 as a positioning reference may be improved.

S03: the transparent protective layer 11 is polished.

According to practical needs, the transparent protection layer 11 may be ground to thin the transparent protection layer 11, and the patterned metal blocks 91 may be ground into separate pieces, so that the second positioning mark 8 is more conveniently formed in step S124.

By the method, the transparent protective layer 11 is arranged on the second positioning mark 8, so that the oxidation of the second positioning mark 8 and the scratch risk of the second positioning mark 8 can be reduced, and the second positioning mark 8 can be protected.

In a possible embodiment, before the step of attaching the chip assembly 2 to the substrate 1 based on the second positioning mark 8, the method further comprises: checking a first offset of the second positioning mark 8 based on the first positioning mark 7; if the first offset exceeds the preset offset, the second positioning mark 8 is reset or a substrate 1 is provided again.

The preset offset is an offset preset in advance, the first offset is within the preset offset, the setting of the second positioning mark 8 meets the requirement, and the first offset exceeds the preset offset, so that the setting of the second positioning mark 8 does not meet the requirement.

The second positioning mark 8 set with the first positioning mark 7 as a reference may have a large offset, and therefore, the first offset amount of the second positioning mark 8 is checked based on the first positioning mark 7. If the first offset exceeds the preset offset, the second positioning mark 8 is set on the substrate 1 again, or the second positioning mark 8 is scrapped, the substrate 1 is provided again, and then the second positioning mark 8 is set on the substrate 1 again. Therefore, before the chip assembly 2 is attached to the substrate 1, whether the second positioning mark 8 deviates beyond the specification can be detected, and the process control treatment can be timely performed, so that the packaging precision of the chip 21 can be further improved.

In a possible embodiment, before the step of disposing the insulating layer 6 on the side of the chip assembly 2 opposite to the plastic layer 4, it further comprises: based on the second positioning mark 8, a second offset of the chip assembly 2 is detected.

The second offset of the chip assembly 2 is again detected based on the second positioning mark 8 before the step of providing the insulating layer 6 on the side of the chip assembly 2 opposite the plastic layer 4, i.e. before the step of forming the rewiring layer 5 on the side of the insulating layer 6 remote from the plastic layer 4. A re-wiring layer 5 is then formed on the side of the insulating layer 6 remote from the plastic layer 4 based on the second offset. In this way, the rewiring layer 5 can be provided with the second offset amount as compensation, so that the electrical connection between the rewiring layer 5 and the pins 211 of the chip 21 can be made more accurately through the vias 61.

In one possible embodiment, the step of forming a molding layer 4 covering the chip assembly 2 on one side of the substrate 1 includes: a molding layer 4 covering the chip assembly 2 is formed on one side of the substrate 1, and the molding layer 4 is polished.

The grinding process can be selectively added according to different requirements of clients, so that the plastic sealing layer 4 can be thinned, the plastic sealing layer 4 can be flatter, and further the requirements of the clients can be met more easily.

In a possible embodiment, after the step of forming the rewiring layer 5 on the side of the insulating layer 6 remote from the molding layer 4 based on the second positioning mark 8, the method further includes: the plastic layer 4 between the packaged chips 21 is cut in a direction perpendicular to the substrate 1 so that the packaged chips 21 are separated from each other. In this way, the packaged chip assembly 2 can be divided into individual chip 21 packages according to the needs of customers.

In a possible embodiment, referring to fig. 27, after the step of forming the redistribution layer 5 on the side of the insulating layer 6 away from the molding layer 4 based on the second positioning mark 8, the method further includes: solder balls 12 are provided on the rewiring unit. The signal of the chip 21 can be led out more conveniently through the solder balls 12.

In summary, the second positioning mark 8 is set on the substrate 1 based on the first positioning mark 7, and the chip assembly 2 and the redistribution layer 5 are both set based on the second positioning mark 8, so that the alignment precision between the redistribution block 51 and the pins 211 of the chip 21 can be greatly improved, the precision of packaging the chip 21 can be greatly improved, and the quality of the packaging structure of the chip 21 can be improved. Since the alignment accuracy of the package structure of the chip 21 is higher, the distance between the pins 211 of the chip 21 can be set smaller.

Based on the same inventive concept, the application also provides a chip packaging structure, which is manufactured by the manufacturing method of the chip packaging structure. The chip packaging structure has higher alignment precision and better quality.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method for manufacturing a chip package structure, the method comprising:

providing a substrate;

setting a first positioning mark on the substrate;

setting a second positioning mark on the substrate based on the first positioning mark;

attaching a chip assembly to the substrate based on the second positioning mark, wherein the chip assembly comprises at least one chip, and the chip comprises pins;

forming a plastic sealing layer covering the chip assembly on one side of the substrate;

an insulating layer is arranged on one side of the chip assembly, which is opposite to the plastic sealing layer;

and forming a rewiring layer on one side, far away from the plastic sealing layer, of the insulating layer based on the second positioning mark, wherein the rewiring layer comprises a rewiring unit, and the rewiring unit is electrically connected with a pin of the chip.

2. The method of manufacturing a chip package structure according to claim 1, wherein the step of disposing a second positioning mark on the substrate based on the first positioning mark comprises:

forming a metal layer on one side of the substrate;

coating photoresist on one side of the metal layer far away from the substrate, and exposing and developing the photoresist to form patterned photoresist;

etching the metal layer based on the patterned photoresist to form a patterned metal block;

and removing part of the patterned metal block based on the first positioning mark, and forming a second positioning mark on the substrate by the rest of the patterned metal block.

3. The method of manufacturing a chip package structure according to claim 2, further comprising, after the step of etching the metal layer based on the patterned photoresist to form a patterned metal block:

removing the photoresist;

coating a transparent protective layer covering the patterned metal block on one side of the substrate;

and grinding the transparent protective layer.

4. The method of manufacturing a chip package structure according to claim 1, further comprising, before the step of attaching the chip assembly to the substrate based on the second positioning mark:

checking a first offset of the second positioning mark based on the first positioning mark; if the first offset exceeds the preset offset, resetting the second positioning mark or providing a substrate again.

5. The method of manufacturing a chip package structure of claim 1, further comprising, prior to the step of disposing an insulating layer on a side of the chip assembly opposite the molding layer:

peeling the plastic sealing layer, the chip assembly and the second positioning mark from the substrate;

and detecting a second offset of the chip assembly based on the second positioning mark.

6. The method of manufacturing a chip package structure according to claim 5, wherein the step of forming a redistribution layer on a side of the insulating layer away from the molding layer based on the second positioning mark comprises:

and forming a rewiring layer on one side of the insulating layer, which is far away from the plastic sealing layer, based on the second positioning mark based on the second offset.

7. The method of manufacturing a chip package structure according to claim 1, wherein the step of forming a redistribution layer on a side of the insulating layer away from the molding layer based on the second positioning mark comprises:

forming a plurality of through holes on the insulating layer along the direction perpendicular to the insulating layer, wherein the through holes correspond to pins of the chip;

forming a rewiring layer on one side of the insulating layer, which is far away from the plastic sealing layer, based on the second positioning mark; and the rewiring unit is electrically connected with the pins of the chip through the through holes.

8. The method of manufacturing a chip package structure according to claim 7, wherein the step of forming a molding layer on one side of the substrate to cover the chip assembly comprises:

and forming a plastic sealing layer covering the chip assembly on one side of the substrate, and grinding the plastic sealing layer.

9. The method of manufacturing a chip package structure according to claim 8, further comprising, after the step of forming a redistribution layer on a side of the insulating layer away from the molding layer based on the second positioning mark:

and cutting the plastic sealing layers among the packaged chips along the direction perpendicular to the substrate to separate the packaged chips from each other.

10. A chip package structure, characterized in that the chip package structure is manufactured by the manufacturing method of the chip package structure according to any one of claims 1 to 9.