CN117672325A - Shift register unit, gate driving circuit, display panel and display device - Google Patents
Shift register unit, gate driving circuit, display panel and display device Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The application discloses a shift register unit and a driving method thereof, a gate driving circuit, a display panel and a display device, wherein the shift register unit comprises: the input circuit is connected with the input signal and the voltage of the first power supply signal end; the first control circuit is used for controlling the on-off of the second clock signal end and the fifth node and the on-off of the fifth node and the sixth node; a compensation circuit configured to switch the potential of the second power supply signal terminal to the sixth node in response to the signal of the second clock signal terminal; and an output circuit outputting an output signal, the compensation circuit including: the first electrode of the first transistor is electrically connected to the sixth node, the second electrode of the first transistor is electrically connected to the second power supply signal end, the control electrode of the first transistor is electrically connected to the second clock signal end, the first end of the first capacitor is electrically connected to the second clock signal end, and the second end of the first capacitor is electrically connected to the sixth node. According to the embodiment of the application, through compensation of the compensation unit, output abnormality caused by forward bias of the output unit is avoided.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a gate driving circuit, a display panel, a display device, and a driving method.
Background
Array substrate gate drive or shift register (Gate Driver on Array, GOA) circuits are widely used in display products. The GOA circuit is integrated on the array substrate and is prepared simultaneously with other display components on the array substrate, so that the cost of display products can be reduced.
In the related art, during the driving process of a row of gate lines in one frame period, after the GOA circuit outputs a scan signal, a non-operating voltage should be output to the gate line to which the GOA circuit is coupled to ensure that the sub-pixel to which the gate line is coupled is turned off, which is referred to as a hold phase. However, in practical situations, due to process deviation or usage conditions encountering high and low temperatures, the threshold voltage of the transistor will shift, and in the present circuit, the forward shift of the transistor in the output unit will cause abnormal output in the holding stage.
Disclosure of Invention
In order to solve at least one of the above problems, a first aspect of the present application provides a shift register unit, comprising:
an input circuit configured to switch a signal of the input terminal to a first node in response to a signal of the first clock signal terminal and to switch a potential of the first power signal terminal to a second node, and to switch the signal of the first clock signal terminal to the second node in response to the potential of the first node;
The first control circuit is configured to control the on-off of the second clock signal end and the fifth node in response to the signal of the second clock signal end and the signal received by the fourth node from the second node, and control the on-off of the fifth node and the sixth node in response to the potential of the first node;
a compensation circuit configured to switch the potential of the second power supply signal terminal to the sixth node in response to the signal of the second clock signal terminal; and
an output circuit configured to output an output signal in response to signals of the fifth node and the third node,
the compensation circuit includes: the first electrode of the first transistor is electrically connected to the sixth node, the second electrode of the first transistor is electrically connected to the second power supply signal end, the control electrode of the first transistor is electrically connected to the second clock signal end, the first end of the first capacitor is electrically connected to the second clock signal end, and the second end of the first capacitor is electrically connected to the sixth node.
In some alternative embodiments, the shift register unit further includes: and the second control circuit is configured to control the on-off of the second power supply signal end and the seventh node in response to the potential of the second node and control the on-off of the second clock signal end and the seventh node in response to the potential of the third node.
In some alternative embodiments, the shift register unit further includes: the voltage stabilizing circuit comprises a first voltage stabilizing circuit and a second voltage stabilizing circuit,
the first voltage stabilizing circuit is configured to respond to the voltage of the first power supply signal end and control the on-off of the second node and the fourth node according to the electric potential of the second node and the fourth node;
the second voltage stabilizing circuit is configured to respond to the voltage of the first power supply signal end and control the on-off of the first node and the third node according to the electric potential of the first node and the third node.
In some alternative embodiments, the input circuit further comprises: a second transistor, a third transistor, and a fourth transistor, wherein,
the first electrode of the second transistor is electrically connected to the input terminal, the second electrode is electrically connected to the first node, the control electrode is electrically connected to the first clock signal terminal,
the first electrode of the third transistor is electrically connected to the first clock signal terminal, the second electrode is electrically connected to the second node, the control electrode is electrically connected to the first node,
the first electrode of the fourth transistor is electrically connected to the first power signal terminal, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first clock signal terminal.
In some alternative embodiments, the first control circuit further comprises: a fifth transistor, a sixth transistor, a seventh transistor, and a second capacitor, wherein,
The first electrode of the fifth transistor is electrically connected to the second clock signal terminal, the second electrode is electrically connected to the eighth node, the control electrode is electrically connected to the fourth node,
the first electrode of the sixth transistor is electrically connected to the eighth node, the second electrode is electrically connected to the fifth node, the control electrode is electrically connected to the second clock signal terminal,
the seventh transistor has a first electrode electrically connected to the fifth node, a second electrode electrically connected to the sixth node, a control electrode electrically connected to the first node,
the first end of the second capacitor is electrically connected to the fourth node, and the second end is electrically connected to the eighth node.
In some alternative embodiments, the output circuit further comprises: an eighth transistor, a ninth transistor, and a third capacitor, wherein,
the first electrode of the eighth transistor is electrically connected to the second power signal terminal, the second electrode is electrically connected to the output terminal, the control electrode is electrically connected to the fifth node,
the ninth transistor has a first electrode electrically connected to the output terminal, a second electrode electrically connected to the first power signal terminal, a control electrode electrically connected to the third node,
the first end of the third capacitor is electrically connected to the fifth node, and the second end of the third capacitor is electrically connected to the second power signal end.
In some alternative embodiments, the second control circuit includes: a tenth transistor, an eleventh transistor, and a fourth capacitor, wherein,
The tenth transistor has a first electrode electrically connected to the second power signal terminal, a second electrode electrically connected to the seventh node, a control electrode electrically connected to the second node,
the eleventh transistor has a first electrode electrically connected to the second clock signal terminal, a second electrode electrically connected to the seventh node, a control electrode electrically connected to the third node,
the first end of the fourth capacitor is electrically connected to the third node, and the second end is electrically connected to the seventh node.
In some alternative embodiments, the first voltage stabilizing circuit includes: a twelfth transistor, the second voltage stabilizing circuit including a thirteenth transistor, wherein,
the twelfth transistor has a first electrode electrically connected to the second node, a second electrode electrically connected to the fourth node, a control electrode electrically connected to the first power signal terminal,
the thirteenth transistor has a first electrode electrically connected to the first node, a second electrode electrically connected to the third node, and a control electrode electrically connected to the first power signal terminal.
A second aspect of the present application provides a gate driving circuit, including N cascaded shift register units according to the foregoing, where an output end of an nth shift register unit is electrically connected to an input end of an n+1th shift register unit, and an input end of the 1 st shift register unit is connected to an initial input signal, where N is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 1.
A third aspect of the present application provides a display panel comprising the gate driving circuit described above.
A fourth aspect of the present application provides a display device comprising a display panel as described above.
A fifth aspect of the present application provides a method of driving the shift register unit described above, the driving method comprising: an output phase and a hold phase, wherein the hold phase comprises:
the compensation unit writes a signal of the second power supply signal terminal into the sixth node in response to the first level signal from the first clock signal terminal and the second level signal from the second clock signal terminal, and the first control terminal writes the potential of the sixth node into the fifth node in response to the potential of the first node so that the output circuit outputs the second level signal;
the compensation unit continuously increases the potential of the sixth node by using the first capacitor in response to the second clock signal terminal being changed from the second level signal to the first level signal, and the first control terminal writes the potential of the sixth node into the fifth node in response to the potential of the first node, so that the output circuit continuously outputs the second level signal.
The beneficial effects of this application are as follows:
aiming at the existing problems at present, the shift register unit, the grid driving circuit, the display panel, the display device and the driving method are formulated, the compensation unit is arranged to respond to the signal of the second clock signal end to enable the potential of the second power signal end to be connected to the sixth node, and the compensation unit comprises the first transistor and the first capacitor, so that the control electrode potential of the output transistor in the output circuit is raised through the cooperation of the first transistor and the first capacitor in the holding stage of the shift register unit, the output transistor Guan Wenpiao threshold voltage is positively biased in time, the turn-off can still be ensured, the output end is ensured not to be abnormal, the display effect is improved, and the shift register unit has wide application prospect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1a is a schematic circuit diagram of a shift register unit of the related art;
FIG. 1b is an output simulation diagram of the circuit structure of FIG. 1 a;
FIG. 2 is a schematic circuit block diagram of a shift register cell according to an embodiment of the present application;
FIG. 3 is a schematic circuit schematic of a shift register cell according to an embodiment of the present application;
FIG. 4 is a timing diagram of key signals of a shift register unit according to an embodiment of the present application;
FIG. 5 is a simulation diagram of the output of a shift register unit according to an embodiment of the present application; and
fig. 6 is a schematic diagram of a gate driving circuit according to an embodiment of the present application.
Detailed Description
For a clearer description of the present application, the present application is further described below with reference to preferred embodiments and the accompanying drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is intended to be illustrative, and not restrictive, and that this invention is not to be limited to the specific embodiments shown.
It should be noted that, ordinal terms such as "first," "second," "third," … … and the like in this document are not intended to limit the order of the respective units, nodes, elements, or components, but are merely intended to distinguish the respective units, nodes, elements, or components. The terms "comprises," "comprising," "includes," and "having" are intended to be inclusive and mean that there may be additional elements, nodes, elements, or components other than the elements, nodes, elements, or components.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and the source and drain of the transistors used herein are symmetrical, so that the source and drain may be interchanged. In the embodiment of the present application, the gate of the transistor is referred to as a control electrode, one of the source and the drain is referred to as a first electrode, and the other is referred to as a second electrode. In the embodiments of the present application, a first electrode of a transistor is referred to as a source electrode, and a second electrode is referred to as a drain electrode. In addition, the shift register unit in the embodiment of the present application adopts a P-type transistor, and improves the drive compensation architecture based on a PMOS transistor, so that the on condition of the transistor is that the control electrode is connected to a low-level signal, which will not be described in detail below.
In addition, the shift register unit of the present application may be used to output the gate signal (that is, the EM signal) of the light emission control transistor of the LPTS display panel, that is, the shift register unit in the EM GOA, and may also be used to output the gate signal of the N-tube in the LPTO display panel (the N-type TFT and the P-type TFT are simultaneously present in the pixel circuit), and the control signal needs to be output row by row regardless of the signals. Therefore, the following block diagrams or circuit schematic diagrams of the shift register units represent control signals corresponding to driving the pixels in the nth row, where n is a positive integer greater than or equal to 1 and less than or equal to the total number of pixels, and will not be described in detail.
Referring to fig. 1a, a schematic circuit diagram of a typical shift register unit in the related art is shown. The output circuit is composed of transistors T9 and T10 and a capacitor C3, and the high-level signal terminal VGH has a potential of 7V and the low-level signal terminal VGL has a potential of-7V. In the hold phase, when the clock signal terminal CB is connected to the low level, the clock signal terminal CK is connected to the high level, the node N1 is kept at the low level at the previous time, the transistor T8 is turned on, the potential of the node N4 is 7V, and the node N5 is a negative voltage with an absolute value smaller than 7, for example, -13V, when vgs=0v > tth of the transistor T9 is kept off, vgs= -6v < vth of the transistor T10 is turned on, and therefore the output terminal Out outputs the low level; when the level of the CB at the clock signal terminal becomes high, since the node N2 is still at a low level, the node N7 is at a high level, the transistor T4 is turned off, the potential at the node N5 is raised by the capacitor C2, the transistor T10 is turned off, the potential at the output terminal is mainly controlled by the transistor T9, and at this time, during operation or process deviation, the transistor T9 may be biased positively, i.e., vth is positive, typically less than 1V, and the node N1 is at a low level, vth > vgs=0v of the transistor T9 is turned on, and high level appears at the output, as can be seen with reference to the simulation diagram of fig. 1b, a spike at a high level will appear during the hold phase, resulting in display of an abnormality during the hold phase.
In order to solve the above problems, an embodiment of the present application provides a shift register unit, including:
an input circuit configured to switch a signal of the input terminal to a first node in response to a signal of the first clock signal terminal and to switch a potential of the first power signal terminal to a second node, and to switch the signal of the first clock signal terminal to the second node in response to the potential of the first node;
the first control circuit is configured to control the on-off of the second clock signal end and the fifth node in response to the signal of the second clock signal end and the signal received by the fourth node from the second node, and control the on-off of the fifth node and the sixth node in response to the potential of the first node;
a compensation circuit configured to switch the potential of the second power supply signal terminal to the sixth node in response to the signal of the second clock signal terminal; and
an output circuit configured to output an output signal in response to signals of the fifth node and the third node,
the compensation circuit includes: the first electrode of the first transistor is electrically connected to the sixth node, the second electrode of the first transistor is electrically connected to the second power supply signal end, the control electrode of the first transistor is electrically connected to the second clock signal end, the first end of the first capacitor is electrically connected to the second clock signal end, and the second end of the first capacitor is electrically connected to the sixth node.
In this embodiment, by providing the compensation unit, the setting compensation unit is configured to switch the potential of the second power supply signal terminal into the sixth node in response to the signal of the second clock signal terminal, and specifically the setting compensation unit includes the first transistor and the first capacitor, so that the potential of the control electrode of the output transistor in the output circuit can be raised by the cooperation of the first transistor and the first capacitor in the holding stage of the shift register unit, so that the threshold voltage of the output transistor Guan Wenpiao is forward biased in time, the turn-off can still be ensured, the output terminal is ensured not to be abnormal, and the display effect is improved.
In a specific embodiment, as shown in connection with fig. 2 and 3, the shift register unit includes: an input circuit 101, a first control circuit 102, and an output circuit 103.
The Input circuit 101 is configured to switch a signal of the Input terminal Input to the first node N1 and a voltage of the first power signal terminal VGL to the second node N2 in response to a signal of the first clock signal terminal CK, and switch a signal of the first clock signal terminal CK to the second node N2 in response to a potential of the first node N1. Specifically, the Input circuit 101 may be configured to Input the Input signal Input to the first node N1 and the voltage of the first power signal terminal VGL to the second node N2 in response to the first clock signal Input to the first clock signal terminal CK being active, and to write the first clock signal to the second node N2 in response to the first node N1 being at an active potential.
The first control circuit 102 is configured to control on-off of the second clock signal terminal CB and the fifth node N5 in response to a signal of the second clock signal terminal CB and a signal from the second node N2 received by the fourth node N4, and to control on-off of the fifth node N5 and the sixth node N6 in response to a potential of the first node N1. Specifically, the first control circuit may be configured to switch the second clock signal to the fifth node N5 in response to the second clock signal to which the second clock signal terminal CB is connected being active and the potential of the fourth node N4 being at an active potential, and to write the potential of the sixth node N6 to the fifth node N5 in response to the potential of the first node N1 being an active potential.
The output circuit 103 is configured to output an output signal in response to signals of the fifth node N5 and the third node N3.
In particular, referring to fig. 2, the shift register unit of the embodiment of the present application includes a compensation circuit 104, and the compensation circuit 104 is configured to switch the potential of the second power supply signal terminal VGH to the sixth node N6 in response to the signal of the second clock signal terminal CB. Specifically, referring to fig. 2, the compensation circuit 104 includes: the first transistor T1 and the first capacitor C1, the first pole of the first transistor T1 is electrically connected to the sixth node N6, the second pole is electrically connected to the second power signal terminal VGH, the control pole is electrically connected to the second clock signal terminal CB, the first end of the first capacitor C1 is electrically connected to the second clock signal terminal CB, and the second end is electrically connected to the sixth node N6.
Through the above arrangement, the compensation circuit 104 may be configured such that the second clock signal accessed by the second clock signal terminal CB is effective, the first transistor T1 is turned on to access the voltage of the second power signal terminal VGH to the sixth node, and simultaneously, the voltage of the second power signal terminal VGH is utilized to charge the first capacitor C1, and when the second clock signal is not effective, the bootstrap function of the first capacitor C1 is utilized to continuously raise the potential of the sixth node N6, so as to perform the compensation function on the sixth node N6. By compensating the potential of the sixth node N6, the potential of the fifth node N5 can be compensated and raised, so that when the transistor is forward biased in the output circuit 103, the output is ensured not to be abnormal by the compensated and raised potential.
With continued reference to fig. 2 and in combination with fig. 3, the shift register unit further includes a second control circuit 105 configured to control the on/off of the second power signal terminal VGH and the seventh node N7 in response to the potential of the second node N2, and to control the on/off of the second clock signal terminal CB and the seventh node N7 in response to the potential of the third node N3. Specifically, the second control unit 105 may be configured to switch the voltage of the second power signal terminal VGH to the seventh node N7 in response to the potential of the second node N2 being an effective potential, and switch the second clock signal of the second clock signal terminal CB to the seventh node N7 in response to the potential of the third node N3 being an effective potential.
In addition, with continued reference to FIG. 2, the shift register cell may also include a voltage regulator circuit including a first voltage regulator circuit 106-1 and a second voltage regulator circuit 106-2. The first voltage stabilizing circuit 106-1 is configured to respond to the voltage of the first power supply signal end VGL and control on-off between the second node N2 and the fourth node N4 according to the potentials of the second node N2 and the fourth node N4; the second voltage stabilizing circuit 106-2 is configured to respond to the voltage of the first power signal terminal VGL and to control on/off between the first node N1 and the third node N3 according to the potentials of the first node N1 and the third node N3.
Specifically, the first voltage stabilizing circuit 106-1 turns on the second node N2 and the fourth node N4 in response to the first power signal terminal VGL having a low level and the second node N2 having a high level; or the first voltage stabilizing circuit 106-1 is responsive to the voltage level of the first power signal terminal VGL being low, and the fourth node N4 being high, to turn on the second node N2 and the fourth node N4; or the first voltage stabilizing circuit 106-1 turns off the second node N2 and the fourth node N4 when the potential of the first power signal terminal VGL is at a low level and the second node N2 and the fourth node N4 are at a low level.
More specifically, the second voltage stabilizing circuit 106-2 turns on the first node N1 and the third node N3 when the potential of the first power signal terminal VGL is at a low level and the first node N1 is at a high level; or the second voltage stabilizing circuit 106-2 is responsive to the voltage level of the first power signal terminal VGL being low, and the third node N3 being high, to turn on the first node N1 and the third node N3; or the second voltage stabilizing circuit 106-2 turns off the first node N1 and the third node N3 in response to the potential of the first power signal terminal VGL being at a low level and the first node N1 and the third node N3 being at a low level.
Further specifically, in this example, referring to the specific circuit configuration shown in fig. 3, the input circuit 101 includes: a second transistor T2, a third transistor T3, and a fourth transistor T4. Wherein, the first electrode of the second transistor T2 is electrically connected to the Input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal terminal CK; the first electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the fourth transistor T4 has a first electrode electrically connected to the first power signal terminal VGL, a second electrode electrically connected to the second node N2, and a control electrode electrically connected to the first clock signal terminal CK.
The first control circuit 102 includes: a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a second capacitor C2. Wherein, the first pole of the fifth transistor T5 is electrically connected to the second clock signal terminal CB, the second pole is electrically connected to the eighth node N8, and the control pole is electrically connected to the fourth node N4; the first electrode of the sixth transistor T6 is electrically connected to the eighth node N8, the second electrode is electrically connected to the fifth node N5, the control electrode is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, the second electrode is electrically connected to the sixth node N6, the control electrode is electrically connected to the first node N1, the first end of the second capacitor C2 is electrically connected to the fourth node N4, and the second end is electrically connected to the eighth node N8.
The output circuit 103 includes: an eighth transistor T8, a ninth transistor T9, and a third capacitor C3. The first electrode of the eighth transistor T8 is electrically connected to the second power signal terminal VGH, the second electrode is electrically connected to the output terminal Out, the control electrode is electrically connected to the fifth node N5, the first electrode of the ninth transistor T9 is electrically connected to the output terminal Out, the second electrode is electrically connected to the first power signal terminal VGL, the control electrode is electrically connected to the third node N3, the first end of the third capacitor C3 is electrically connected to the fifth node N5, and the second end is electrically connected to the second power signal terminal VGH. The third capacitor C3 maintains the stability of the fifth node N5 by using the energy storage function thereof, so that the state of the eighth transistor T8 is stable, thereby ensuring the stability of the output waveform.
The second control circuit includes: a tenth transistor T10, an eleventh transistor T11, and a fourth capacitance C4. Wherein, the first pole of the tenth transistor T10 is electrically connected to the second power signal terminal VGH, the second pole is electrically connected to the seventh node N7, and the control pole is electrically connected to the second node N2; the eleventh transistor T11 has a first electrode electrically connected to the second clock signal terminal CB, a second electrode electrically connected to the seventh node N7, and a control electrode electrically connected to the third node N3; the first end of the fourth capacitor C4 is electrically connected to the third node N3, and the second end is electrically connected to the seventh node N7. The fourth capacitor C4 maintains the stability of the third node N3 by using the energy storage function thereof, so that the state of the ninth transistor T9 is stable, and the stability of the output waveform is ensured, where the energy storage function includes maintaining the stability of the third node N3 by using the bootstrap function of the capacitor with the written potential after the voltage of the second power supply signal terminal VGH or the second clock signal of the second clock signal terminal CB is connected to the seventh node N7.
The first voltage stabilizing circuit 106-1 includes: the twelfth transistor T12, the second voltage stabilizing circuit 106-2 includes a thirteenth transistor T13. Wherein, the first pole of the twelfth transistor T12 is electrically connected to the second node N2, the second pole is electrically connected to the fourth node N4, and the control pole is electrically connected to the first power signal terminal VGL; the thirteenth transistor has a first electrode electrically connected to the first node N1, a second electrode electrically connected to the third node N3, and a control electrode electrically connected to the first power signal terminal VGL.
Fig. 4 shows an exemplary timing diagram of the critical signal terminals of the schematic of the circuit of fig. 3. The function of the compensation circuit is described in detail below in connection with figures 4 and 3. The voltage of the first power signal terminal VGL is set to be a low level VGL, and the voltage of the second power signal terminal VGH is set to be a high level VGH. The low level and the high level of the first clock signal and the second clock signal are set to be consistent with the corresponding high level and low level of the power supply, and the high level and the low level of the Input signal connected to the Input end Input are also set to be consistent with the corresponding high level and low level of the power supply.
Wherein referring to fig. 4, in this example, the output terminal Out includes an output stage outputting a high level signal and a hold stage outputting a low level signal, wherein the output stage substantially represents a stage outputting an active level signal of a control electrode of a corresponding transistor in the driving pixel circuit, and the hold stage substantially represents a stage outputting an inactive level signal of a control electrode of a corresponding transistor in the driving pixel circuit. Since the function of the compensation circuit 103 of the embodiment of the present application is mainly embodied in the hold stage, the function thereof in the hold stage is described in detail below.
Referring to fig. 4, it can be seen that the hold phase includes alternating first phases T1 and second phases T2.
Specifically, in the first stage T1, as shown in fig. 3, the second clock signal connected to the second clock signal terminal CB is at a low level, and the first clock signal connected to the first clock signal terminal CK is at a high level.
At this time, the first transistor T1 in the compensation circuit 104 is turned on, the voltage connected to the second power signal terminal VGH is written into the eighth node N6, the first node N1 maintains the low level at the previous time, the seventh transistor T7 in the first control circuit 102 is turned on, the fifth node N5 and the sixth node N6 are turned on, the potential of the fifth node N5 is connected to the high level potential VGH of the second power signal terminal VGH, and therefore, the gate-source voltage vgs=0 > vth of the eighth transistor T7 in the output circuit 103, and the eighth transistor T8 is turned off. Meanwhile, since the seventh node N7 writes the high level VGH of the second power signal terminal VGH at the previous time, the potential at the second terminal of the fourth capacitor C4 is VGH at the previous time, the potential at the first terminal is low level vgl, the third node N3 is low level, the tenth transistor T10 is turned on, the potential at the seventh node N7 is low level vgl of the second clock signal, the potential at the second terminal of the fourth capacitor C4 is VGH-vgl, the first terminal should also change with the same value, and the potential is: 2vgl-vgh, so that the third node N3 is at a very negative low level by the holding action of the fourth capacitor C4, the ninth transistor T9 in the output circuit 103 is turned on.
In summary, in the first stage T1, the eighth transistor T8 is turned off, and the ninth transistor T9 is turned on, and the output terminal Out outputs the low level vgl.
In the second phase T2, the second clock signal of the second clock signal terminal CB goes high, and in this phase, sub-phases T1, T2, and T3 are included.
Specifically, in the sub-stage t1, both the first clock signal and the second clock signal are high.
At this time, in the first control circuit 102, since the second clock signal is at the high level, the fourth node N4 and the fifth node N5 are turned off, the first transistor T1 is turned off, and the fifth node N5 is mainly affected by the seventh transistor T7 and the compensation circuit 104.
Because of the holding action of the fourth capacitor C4, the fifth node N5 is at a low level, the tenth transistor T10 is turned on, the high level vgh is written to the seventh node T7, and simultaneously the fourth capacitor C4 is charged, the potential of the first end of the fourth capacitor C4 is raised accordingly, and thus the potential of the third node N3 is raised, and the ninth transistor T9 is turned off. At this time, the potential of the first node N1 is still at the low level, and the seventh transistor T7 is turned on, because the potential of the first end of the first capacitor C1 is at the low level vgl and at the high level vgh, the variation is vgl-vgh, and the potential of the second end, i.e., the sixth node, is at this time: 2vgh-vgl, since the seventh transistor T7 is turned on, the potential of the fifth node N5 is: 2vgh-ghl. At this time, the second terminal potential of the third capacitor C3 is at a high level vgh, and therefore, the gate-source voltage vgs= vgh-vgl of the eighth transistor T8 is at a positive value with a large absolute value due to the compensation capacitor, and therefore, even if the threshold voltage Vth of the eighth transistor T8 is biased positively due to process variation or temperature drift during actual use at this time, the value after being shifted at normal temperature is at a positive value close to or less than 1v, the eighth transistor T8 can be surely turned off, and the output terminal Out outputs a low level.
In sub-stage t2, the first clock signal is low and the second clock signal is high.
At this time, similarly, in the first control circuit 102, since the second clock signal is at the high level, the fourth node N4 and the fifth node N5 are turned off, the first transistor T1 is turned off, and the fifth node N5 is mainly affected by the seventh transistor T7 and the compensation circuit 104.
Because the first clock signal of the first clock signal terminal CK is at a low level, the second transistor T2, the third transistor T3 and the fourth transistor T4 in the input circuit 101 are all turned on, the first node N1 is connected to the low level vgl, the second node N2 is connected to the low level vgl, the fifth transistor T5 is turned on, the seventh node N7 is still connected to the high level vgh, and the third node N3 is unchanged in potential, so that the ninth transistor T9 in the output circuit 103 is turned off.
Since the potential of the first node N1 is at the low level vgl, the seventh transistor T7 is turned on, and since the first capacitor C1 has a memory function, the potential of the second node, i.e., the sixth node, is still: 2vgh-vgl, since the seventh transistor T7 is turned on, the potential of the fifth node N5 is: 2vgh-ghl. At this time, the second terminal potential of the third capacitor C3 is at a high level vgh, so the gate-source voltage vgs= vgh-vgl of the eighth transistor T8 is at a positive value with a large absolute value due to the compensation capacitor, and therefore, even if the threshold voltage Vth of the eighth transistor T8 is biased positively due to the process deviation or the temperature drift during the actual use, the eighth transistor T8 can be turned off and the output terminal Out outputs a low level.
In sub-stage t3, both the first clock signal and the second clock signal are high.
At this time, the second transistor T2 and the fourth transistor T4 in the input circuit 101 are turned off, the first node N1 is still at a low level, the third transistor T3 is turned on, the second node N2 is at a high level vgh, the tenth transistor T10 in the second control circuit 105 is turned on, the eleventh transistor T11 is turned off, the seventh node N7 is still at a high level vgh, and the ninth transistor T9 in the output circuit 103 is kept turned off. The first transistor in the compensation circuit 104 is turned off, the potential of the sixth node N6 is still 2vgh-ghl under the action of the first capacitor C1, the seventh transistor T7 is turned on, so that the sixth node N6 and the fifth node N5 are turned on, and the potential of the fifth node is still: 2vgh-ghl. At this time, the second terminal potential of the third capacitor C3 is at a high level vgh, so the gate-source voltage vgs= vgh-vgl of the eighth transistor T8 is at a positive value with a large absolute value due to the compensation capacitor, and therefore, even if the threshold voltage Vth of the eighth transistor T8 is biased positively due to the process deviation or the temperature drift during the actual use, the eighth transistor T8 can be turned off and the output terminal Out outputs a low level.
As can be seen from the above analysis, in the second stage T2, although the first clock signal connected to the first clock signal terminal CK changes between the high level and the low level, the second clock signal connected to the second clock signal terminal CB is at the high level, and the control electrode of the first transistor T1 in the compensation circuit 104 is only controlled by the second clock signal, and under the bootstrap and storage functions of the first capacitor, the potential of the sixth node N6 can be raised and maintained in the second stage T2, so that the ninth transistor T9 is turned off, and it is ensured that the output clock can correctly output the low level even if the threshold voltage of the eighth transistor T8 is forward biased.
In addition, it should be noted that, in the holding stage, the ninth transistor T9 in the output circuit 103 may also generate the positive bias of the threshold voltage Vth synchronously, and the transistor must be able to pull the output terminal Out to the low level VGL of the first power signal terminal VGL when turned on due to the positive bias, so that the compensation effect of the compensation circuit 104 is equivalent to that when the transistor in the output circuit generates the positive bias of the threshold voltage, the correct output of the output terminal Out is ensured, which is not described herein.
Referring to fig. 5, an output simulation diagram based on the schematic circuit diagram shown in fig. 3 is further shown, in which an output effect that a transistor generates 2.5V forward bias in an output circuit to be capable of covering a threshold voltage (for example, 0V or more and 1V or less) after conventional forward bias in a current display product is given, it can be seen that by the shift register unit according to the embodiment of the present application, even if the threshold voltage is positive due to the occurrence of 2.5V forward bias in the output circuit, the output circuit can still be ensured to normally output a low-level signal in a hold stage, and the display effect is improved.
Based on the same inventive concept, embodiments of the present application further provide a method of driving the shift register unit described above, the driving method including: an output phase and a hold phase, wherein the hold phase comprises:
The compensation unit writes a signal of the second power supply signal end into a sixth node in response to an invalid level signal from the first clock signal end and an valid level signal from the second clock signal end, and the first control end writes a potential of the sixth node into a fifth node in response to a potential of the first node so that the output circuit outputs a low level signal;
the compensation unit continues to raise the potential of the sixth node by using the first capacitor in response to the second clock signal terminal changing from the active level signal to the inactive level signal, and the first control terminal writes the potential of the sixth node into the fifth node in response to the potential of the first node, so that the output circuit continues to output the low level signal.
It should be appreciated by those skilled in the art that the specific process of the above method has been described in detail in connection with the respective timing diagrams when describing the specific circuit principles of the shift register unit, and will not be repeated herein.
In this embodiment, by using the compensation unit of the foregoing embodiment, the compensation unit is configured to switch the potential of the second power supply signal terminal into the sixth node in response to the signal of the second clock signal terminal, and specifically, use the cooperation of the first transistor and the first capacitor, so that the potential of the control electrode of the output transistor in the output circuit can be raised by the cooperation of the first transistor and the first capacitor in the holding stage of the shift register unit, so that the threshold voltage of the output transistor Guan Wenpiao is forward biased in time, and still can ensure that the output terminal is turned off, so that no abnormality occurs in the output terminal, thereby improving the display effect and having a wide application prospect.
Based on the same inventive concept, an embodiment of the present application further provides a gate driving circuit, including N cascaded shift register units according to the foregoing embodiment, where an output end of an nth shift register unit is electrically connected to an input end of an n+1th shift register unit, and an input end of the 1 st shift register unit is connected to an initial input signal, where N is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 1.
Referring to fig. 6, a shift register unit comprised of 4 cascades GOA-1, GOA-2, GOA-3 and GOA-4 is schematically illustrated. As can be seen, in the figure, the Input end Input of the 1 st stage shift register unit GOA-1 is connected to the initial Input signal STV, the Input end Input of the 2 nd stage shift register unit GOA-2 is electrically connected to the output end Out of the 1 st stage shift register unit GOA-1, the Input end Input of the 3 rd stage shift register unit GOA-3 is electrically connected to the output end Out of the 2 nd stage shift register unit GOA-2, and the Input end Input of the 4 th stage shift register unit GOA-4 is electrically connected to the output end Out of the 3 rd stage shift register unit GOA-3.
To ensure that each shift register unit can access the correct first and second clock signals, four clock signal lines ck1_1, ck2_1, ck1_2, and ck2_2 are introduced, and the first clock signal terminal CK of the 1 st stage shift register unit GOA-1 is electrically connected to the clock signal line ck1_2, and the second clock signal terminal CB is electrically connected to the clock signal line ck2_2; the first clock signal terminal CK of the 2 nd stage shift register unit GOA-2 is electrically connected to the clock signal line CK2_2, and the second clock signal terminal CB is electrically connected to the clock signal line CK1_2; the first clock signal terminal CK of the 3 rd stage shift register unit GOA-3 is electrically connected to the clock signal line CK1_1, and the second clock signal terminal CB is electrically connected to the clock signal line CK2_1; the first clock signal terminal CK of the 4 th stage shift register unit GOA-4 is electrically connected to the clock signal line ck2_1, and the second clock signal terminal CB is electrically connected to the clock signal line ck1_1.
It will be appreciated by those skilled in the art that this is not limitative, but that only two clock signal lines CK1 and CK2 may be provided, and that the first clock signal terminal CK and the second clock signal terminal CB of the n-th stage shift register unit are connected to CK1 and CK2, respectively, and the first clock signal terminal CK and the second clock signal terminal CB of the n+1th stage shift register unit are connected to CK2 and CK1, respectively, to achieve the effect of shifting the input clock signals of the adjacent shift registers.
In addition, it should be understood by those skilled in the art that the number of shift register units cascaded above is not limited, and any number of shift register units cascaded may be set according to the needs in practical applications, which is not described herein.
However, compared with two clock signal lines, the four clock signal lines shown in fig. 6 can reduce line load and improve accuracy of clock driving.
Based on the same inventive concept, embodiments of the present application also provide a display panel including the gate driving circuit described in the above embodiments.
Based on the same inventive concept, embodiments of the present application also provide a display device including the display panel described in the above embodiments.
In this embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a vehicle-mounted display, a digital photo frame, or a navigator, and by using the display panel with the gate driving circuit, normal display of a display screen can be ensured in the display process of the display device, and the display device has a wide application prospect.
Aiming at the existing problems at present, the shift register unit, the grid driving circuit, the display panel, the display device and the driving method are formulated, the compensation unit is arranged to respond to the signal of the second clock signal end to enable the potential of the second power signal end to be connected to the sixth node, and the compensation unit comprises the first transistor and the first capacitor, so that the control electrode potential of the output transistor in the output circuit is raised through the cooperation of the first transistor and the first capacitor in the holding stage of the shift register unit, the output transistor Guan Wenpiao threshold voltage is positively biased in time, the turn-off can still be ensured, the output end is ensured not to be abnormal, the display effect is improved, and the shift register unit has wide application prospect.
It should be apparent that the foregoing examples of the present application are merely illustrative of the present application and not limiting of the embodiments of the present application, and that various other changes and modifications may be made by one of ordinary skill in the art based on the foregoing description, and it is not intended to be exhaustive of all embodiments, and all obvious changes and modifications that come within the scope of the present application are intended to be embraced by the technical solution of the present application.
Claims (12)
1. A shift register unit, comprising:
the input circuit is configured to connect a signal of an input end to a first node in response to a signal of a first clock signal end, connect a potential of a first power supply signal end to a second node, and connect the signal of the first clock signal end to the second node in response to the potential of the first node;
the first control circuit is configured to control the on-off of the second clock signal end and the fifth node in response to the signal of the second clock signal end and the signal received by the fourth node from the second node, and control the on-off of the fifth node and the sixth node in response to the potential of the first node;
A compensation circuit configured to switch the potential of the second power supply signal terminal to the sixth node in response to the signal of the second clock signal terminal; and
an output circuit configured to output an output signal in response to signals of the fifth node and the third node,
the compensation circuit includes: the first electrode of the first transistor is electrically connected to the sixth node, the second electrode of the first transistor is electrically connected to the second power supply signal end, the control electrode of the first transistor is electrically connected to the second clock signal end, the first end of the first capacitor is electrically connected to the second clock signal end, and the second end of the first capacitor is electrically connected to the sixth node.
2. The shift register unit of claim 1, further comprising: and the second control circuit is configured to control the on-off of the second power supply signal end and the seventh node in response to the potential of the second node and control the on-off of the second clock signal end and the seventh node in response to the potential of the third node.
3. The shift register unit of claim 1, further comprising: the voltage stabilizing circuit comprises a first voltage stabilizing circuit and a second voltage stabilizing circuit,
The first voltage stabilizing circuit is configured to respond to the voltage of the first power supply signal end and control the on-off of the second node and the fourth node according to the potentials of the second node and the fourth node;
the second voltage stabilizing circuit is configured to respond to the voltage of the first power supply signal end and control the on-off of the first node and the third node according to the potentials of the first node and the third node.
4. The shift register unit of claim 1, wherein the input circuit further comprises: a second transistor, a third transistor, and a fourth transistor, wherein,
a first electrode of the second transistor is electrically connected to the input terminal, a second electrode is electrically connected to the first node, a control electrode is electrically connected to the first clock signal terminal,
a first electrode of the third transistor is electrically connected to the first clock signal terminal, a second electrode is electrically connected to the second node, a control electrode is electrically connected to the first node,
the first pole of the fourth transistor is electrically connected to the first power signal terminal, the second pole is electrically connected to the second node, and the control pole is electrically connected to the first clock signal terminal.
5. The shift register unit of claim 1, wherein the first control circuit further comprises: a fifth transistor, a sixth transistor, a seventh transistor, and a second capacitor, wherein,
the first pole of the fifth transistor is electrically connected to the second clock signal terminal, the second pole is electrically connected to the eighth node, the control pole is electrically connected to the fourth node,
a first electrode of the sixth transistor is electrically connected to the eighth node, a second electrode is electrically connected to the fifth node, a control electrode is electrically connected to the second clock signal terminal,
a first pole of the seventh transistor is electrically connected to the fifth node, a second pole is electrically connected to the sixth node, a control pole is electrically connected to the first node,
the first end of the second capacitor is electrically connected to the fourth node, and the second end is electrically connected to the eighth node.
6. The shift register unit of claim 1, wherein the output circuit further comprises: an eighth transistor, a ninth transistor, and a third capacitor, wherein,
the first electrode of the eighth transistor is electrically connected to the second power signal terminal, the second electrode is electrically connected to the output terminal, the control electrode is electrically connected to the fifth node,
A first pole of the ninth transistor is electrically connected to the output terminal, a second pole is electrically connected to the first power signal terminal, a control pole is electrically connected to the third node,
the first end of the third capacitor is electrically connected to the fifth node, and the second end of the third capacitor is electrically connected to the second power signal end.
7. The shift register unit according to claim 2, wherein the second control circuit includes: a tenth transistor, an eleventh transistor, and a fourth capacitor, wherein,
a first electrode of the tenth transistor is electrically connected to the second power signal terminal, a second electrode is electrically connected to the seventh node, a control electrode is electrically connected to the second node,
a first pole of the eleventh transistor is electrically connected to the second clock signal terminal, a second pole is electrically connected to the seventh node, a control pole is electrically connected to the third node,
the first end of the fourth capacitor is electrically connected to the third node, and the second end is electrically connected to the seventh node.
8. A shift register unit as claimed in claim 3, characterized in that the first voltage stabilizing circuit comprises: a twelfth transistor, the second voltage stabilizing circuit including a thirteenth transistor, wherein,
A first electrode of the twelfth transistor is electrically connected to the second node, a second electrode is electrically connected to the fourth node, a control electrode is electrically connected to the first power signal terminal,
the first pole of the thirteenth transistor is electrically connected to the first node, the second pole is electrically connected to the third node, and the control pole is electrically connected to the first power signal terminal.
9. A gate driving circuit according to any one of claims 1 to 8, comprising N cascaded shift register units, wherein the output terminal of the nth shift register unit is electrically connected to the input terminal of the n+1th shift register unit, the input terminal of the 1 st shift register unit is connected to the initial input signal, N is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 1.
10. A display panel comprising the gate driving circuit of claim 9.
11. A display device comprising the display panel of claim 10.
12. A method of driving a shift register unit according to any one of claims 1 to 8, characterized in that the driving method comprises: an output phase and a hold phase, wherein the hold phase comprises:
The compensation unit writes a signal of the second power supply signal terminal to the sixth node in response to a first level signal from the first clock signal terminal and a second level signal from the second clock signal terminal, and the first control terminal writes a potential of the sixth node to the fifth node in response to a potential of the first node to cause the output circuit to output a second level signal;
and the first control end responds to the potential of the first node to write the potential of the sixth node into the fifth node so that the output circuit continuously outputs the second level signal.
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