CN117672316A - EEPROM memory type device with "partial pressure" type architecture - Google Patents

Abstract

Embodiments of the present disclosure relate to EEPROM memory type devices having a "voltage division" type architecture. The non-volatile memory device has a "voltage division" architecture and includes columns of memory words formed on each row by groups of memory cells. All state transistors of the memory cells for a memory word are gated by a control element. All control elements of the same row are controlled by a first control signal, which is generated by a first row control circuit in response to a set-reset (SR) latch output signal for a selected row output. To write a data segment in a memory word, a first row control circuit applies an erase voltage corresponding to a first logic state of a first control signal to the first control signal and then applies a program voltage corresponding to a second logic state of the first control signal, but does not modify the state of the latch output signal for the selected row between erasing and programming the memory word.

Description

EEPROM memory type device with "partial pressure" type architecture

Cross Reference to Related Applications

The present application claims priority from french patent application number 2209003 filed at 9/8 2022, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law.

Technical Field

Implementations relate to non-volatile memories, such as Electrically Erasable Programmable (EEPROM) memories, particularly memories having a "voltage division" type architecture for their erase and program operations, and more particularly to controlling signals that control gates of state transistors of memory cells of memory words during a write cycle, which includes erasing the memory words and then programming the memory words, by means of inverter type control elements.

Background

In EEPROM memories, the logical value of a bit stored in a memory point is represented by a threshold voltage value of a floating gate transistor, which can be modified as needed by a program or erase operation. Programming or erasing a floating gate transistor includes injecting charge into or extracting charge from the gate of the transistor by means of high voltage, by tunneling (known in the art as the "fowler-nordheim effect").

During erase, the high voltage may be about 9 volts to 20 volts, for example 15 volts.

This high voltage is necessary for writing to EEPROM memories and is limited in terms of technology process and product reliability.

In practice, photolithographic reduction, i.e. an increase in the fineness of the etching, leads to a decrease in the operating voltage and this high voltage becomes more problematic in terms of leakage in the source/substrate and drain/substrate junctions or the channel between the drain and source of the transistor and stress on the gate oxide ("gate stress"), or even in terms of breakdown of these gate oxides of the transistor.

Thus, these risks of premature aging and/or transistor breakdown have a direct impact on the reliability of the product.

That is why the "partial pressure" solution mentioned above can be used. More precisely, the high voltage required for programming of the memory plane is divided between a positive voltage and a negative voltage such that the difference between the positive and negative voltages corresponds to a sufficiently high programming voltage.

Such a solution may relax the stress on the voltage resistance of the transistor.

The control in the X (row) direction in a voltage division type architecture is more complex than in a conventional architecture because each physical row of memory cells has to decode two different signals, namely, a signal for controlling the gates of the state transistors of the memory cells of a memory word and a signal for controlling the word lines controlling the gates of the access transistors (or select transistors) of the memory cells by means of the inverter control element.

Accordingly, there is a need for an improved row control circuit for a nonvolatile memory having a voltage dividing architecture, particularly in terms of current consumption and the number of transistors.

Disclosure of Invention

According to one aspect, a non-volatile memory device having a voltage division type architecture, such as an EEPROM type memory, is presented.

The memory device includes a matrix memory plane including columns of memory words.

These memory words are formed by groups of memory cells on each row of the memory plane (each memory cell forming 1 bit of the memory word).

Each memory cell includes a state transistor having a control gate and a floating gate, and a select or access transistor (access transistor, also referred to as an access transistor).

All state transistors of the memory cells of a memory word are controlled on the gate by a control element, typically an inverter.

All control elements of the same row are controlled by a first control signal from a SR type first latch device ("flip-flop") associated with the row.

The memory device further includes a row decoder configured to select a row containing a memory word for writing a data segment in the memory word.

The memory device further includes a first row control circuit associated with the selected row and configured to impart an erase voltage corresponding to a first logic state of the first control signal and then a program voltage corresponding to a second logic state of the first control signal to the first control signal in order to write the data segment in the memory word, but without modifying a state of an output terminal of the first latch device associated with the selected row between erasing and programming of the memory word.

In practice, therefore, the first latch device is supplied with a first supply voltage or high voltage and a second supply voltage or low voltage.

During an erase operation, the high voltage is typically about 15 volts, while the low voltage is typically about 3 volts.

During a programming operation, the high voltage is typically about 3 volts, while the low voltage is typically a negative voltage, e.g., equal to-5 volts.

Thus, for a selected row, during a write cycle including programming after erase, the first control signal sequentially goes from a low logic state (corresponding to a low voltage) to a high logic state (corresponding to a high voltage), even though the value of the high voltage is here equal to the value of the low voltage in the erase operation.

And, here, switching between the logic state of the first control signal in the erase operation and the logic state of the control signal in the program operation is performed, but the state of the output terminal of the first latch device associated with the selected row is not modified between erase and program, whereas in the related art, the logic state of the output terminal is modified between erase and program.

In the prior art this leads to a risk of breakdown of the power supply voltage of the latch device in relation to the control element to which the gate of the state transistor is connected, with a risk of erroneous switching of the output state of the latch device and a current peak in the middle of the write cycle.

This also results in reduced current consumption.

According to one implementation, the first row control circuit includes: a first control circuit having a first circuit input connected to the output terminal of the first latch device; a second circuit input configured to receive a first control signal; and a first circuit output configured to pass a first control signal, the logic state of the first control signal being dependent on the value of the first control signal; and a first control stage configured to communicate the first control signal.

Thus, here, the switching of the logic state of the first control signal is performed by a control circuit connected downstream of the latch device.

According to one implementation, the first control circuit includes: a dedicated NOR-type logic gate having a first gate input connected to the first circuit input, a second gate input connected to the second circuit input, and a gate output; and a first inverter connected between the gate output and the first circuit output.

Thus, in this implementation, the switching of the logic state of the first control signal is performed using a dedicated NOR logic gate connected downstream of the latch device.

The lines carrying the first respective control signals are quite capacitive and their switching results in a significant current draw. The most compact dedicated NOR gate uses six transistors, which has the disadvantage of delivering the output current to the input. Therefore, it is advantageous to avoid this situation.

The presence of an inverter at the output of the dedicated NOR gate achieves this object. In practice, the inverter behaves like an output buffer stage. Thus, the switching current on the line carrying the first control signal is not observed through the output of the dedicated NOR gate and therefore cannot be observed at the input of this gate either.

The dedicated NOR gate inverter assembly can be completed using eight transistors (six for gates and two for inverters) that are particularly compact.

In contrast, a dedicated OR gate (logically equivalent to a dedicated NOR gate-inverter component) completed using a scheme that does not pass output current to its input requires the use of several transistors greater than 8.

According to one implementation, a memory plane includes R rows, and a memory device includes: m first latch devices, each first latch device being associated with a block of N rows, R being equal to the product of N times M, and likewise, for each first latch device, N first row control means respectively associated with N rows of the block of rows are associated with the first latch device.

The row decoder thus comprises: a block decoding circuit configured to select a first latch device from the M first latch devices; and a first row decoding circuit configured to select a row associated with the selected first latch device from the N rows of the row block.

According to one implementation, a block decoding circuit is connected to the set input of each first latch device, and a first row decoding circuit comprises in each first control circuit a first logic gate connected on the one hand to a first circuit input at the input and on the other hand to a second input capable of first decoding the input and connected at the output to a dedicated NOR logic gate, the first decoding input being configured to receive the row code.

According to one implementation, all select transistors of memory cells of the same row are controlled by a second control signal from a second latch device of the SR type associated with the row.

The row decoder is then configured to select a row containing the memory word for programming the data segment in the memory word, and the memory device comprises a second row control circuit associated with the selected row and configured to apply a select voltage to the second control signal for programming the data segment in the memory word.

The second row control circuit advantageously comprises a second control circuit having a first circuit input coupled to the output terminal of the second latch device and a second circuit output configured to pass the second control signal.

Also, the second control circuit is connected downstream of the second latch device.

Also, the second control circuit here advantageously comprises a second inverter, the output of which is connected to the second circuit output.

According to one implementation, each pair formed by the first latch device and the second latch device is associated with the same block of N rows.

The memory device thus comprises, for each second latch device, N second row control circuits respectively associated with N rows of the row block with which the second latch device is associated, and the row decoder comprises, in addition to the block decoding circuits, a second row decoding circuit configured to select a pair of the first latch device and the second latch device from the M pairs, the second row decoding circuit configured to select a row associated with the selected second latch device from the N rows of the row block.

According to one implementation, a block decoding circuit is connected to the set input of each second latch device, and the second row decoding circuit comprises in each second control circuit a second logic gate connected at an input to the first circuit input on the one hand and to a second decoding input capable of receiving a row decoding signal, the second logic gate being connected at an output to the second inverter.

The first logic gate and the second logic gate are advantageously NAND gates.

Any type of conventional latch device known per se may be used, for example such as a latch device using a scheme with 6 volatile memory point (SRAM) type transistors.

Such a latch device is set or reset at the nominal supply voltage Vdd of the integrated circuit, which requires that the conductivity of the N-channel of the NMOS transistor is much greater than the conductivity of the P-channel of the PMOS transistor.

The conductivity condition is obtained by adjusting the width/length (W/L) ratio of the transistor.

However, it is suitable in the future to use low-consumption memories with a voltage Vdd of about 1.2 volts or even lower.

However, for a slow NMOS transistor and a fast PMOS transistor, the conductivity conditions described above require that the PMOS transistor have a larger channel length or that the NMOS transistor have a larger channel width.

Thus, in the case where some transistors that are efficiently produced are proven to be slow NMOS transistors and/or fast PMOS transistors, it is necessary to determine the transistor size as described above.

Thus, this results in an increase in transistor size and a significant increase in gate capacitance.

Furthermore, if some of the transistors that are effectively produced are proved to be fast NMOS transistors and/or slow PMOS transistors, slow switching of the latch device between high and low voltage transfer will be obtained, and vice versa, because the PMOS transistors will be too small in size and thus result in very low currents.

Thus, the SRAM type current latch device cannot operate at a voltage Vdd equal to the maximum value between the threshold voltage of the NMOS transistor and the absolute value of the threshold voltage of the PMOS transistor.

Furthermore, in the extreme configuration of the transistors (fast or slow of MOS transistors), they have a very unstable operation at low voltages Vdd, which leads to an increased gate surface and an increased risk of breakdown of the gate oxide and in some cases to long switching times.

Thus, in certain applications, it is preferred to use a compact latch device that is capable of operating at low voltage Vdd, has no current conflict between NMOS and PMOS transistors, and is configured to minimize stress ("gate stress") in the gate oxide of the PMOS transistor, such as the latch device described in french patent application No. 2205502, for example, the contents of which can be optionally referred to by those skilled in the art, and which is incorporated herein for all practical purposes.

It is therefore advantageously proposed to use a controllable full CMOS SR latch flip-flop, in combination with a control module configured to manage the setting and resetting of the flip-flop and the values and time sequences of the various voltages used by the flip-flop in its various operating phases.

According to one implementation, the latch device will pass and hold either a high voltage (e.g., 15 volts) or a low voltage (e.g., 3.5 volts) on its output terminal according to the command.

A latch device according to this implementation includes a latch flip-flop configured to be powered between a first supply voltage and a second supply voltage, the second supply voltage being lower than the first supply voltage.

The latch flip-flop has a first flip-flop input and a second flip-flop input and a flip-flop output connected to an output terminal of the latch device.

The latch device further includes a control module configured to: when the first supply voltage has a first value lower than the low voltage (e.g., a value Vdd equal to 1.2 volts or even lower), the latch flip-flop is positioned in a set state or a reset state; the latch flip-flops are then positioned to impart a high voltage to the first supply voltage and a low voltage to the second supply voltage, and at the same time, starting from the transfer time, two input voltages theoretically corresponding to the disabled logic state are transferred to the two flip-flop inputs under transfer conditions such that the two input voltages do not actually transition the flip-flop to the disabled logic state, thereby transferring and maintaining either the high voltage or the low voltage on the flip-flop output (depending on the initial "set" or "reset" positioning of the flip-flop).

Those skilled in the art will appreciate that the inhibited logic state of the SR flip-flop transitions to simultaneously apply set and reset conditions to both flip-flop inputs.

When the SR flip-flop comprises a NOR logic gate, the inhibit logic state translates into the application of two voltages to the two flip-flop inputs as seen through the NMOS transistor of the flip-flop, the gate of which is connected to the two flip-flop inputs as a "1" logic state.

But the transfer conditions of the two input voltages are such that they allow to practically avoid the inhibit logic state.

For example, these transfer conditions include satisfying the relationship between the values of the two input voltages, the value of the second power supply voltage, and the threshold voltages of the NMOS transistors of the flip-flops at and after the transfer time, the gates of the NMOS transistors being connected to the two flip-flop inputs.

The values of the high voltage and the low voltage correspond to values used in the phase of erasing or programming the nonvolatile memory cell.

The first value of the first supply voltage is at least equal to the maximum value of the threshold voltage of the NMOS transistor and the absolute value of the threshold voltage of the PMOS transistor of the latch device.

Furthermore, it is advantageously less than or equal to 1.2 volts.

According to one implementation, the latch flip-flop comprises a first logic gate and a second logic gate, advantageously a NOR gate.

According to one implementation, a first logic gate has a first gate input coupled to a first flip-flop input, a second gate input, and a first gate output.

The second logic gate has a first gate input coupled to the first gate output, a second gate input coupled to the second flip-flop input, and a second gate output coupled to the second gate input of the first logic gate and the flip-flop output.

The first and second logic gates comprise NMOS transistors having gates connected to the first or second flip-flop input, and the control module is advantageously configured to transfer said corresponding input voltage on each flip-flop input from said transfer time when the flip-flop is positioned (in its set or reset state), the value of the input voltage being lower than the value of the second supply voltage increasing the threshold voltage of the NMOS transistor.

This allows to obtain a gate-source voltage of these transistors, which is lower than its threshold voltage, thus preventing and thus avoiding the forbidden logic state of the flip-flop, while avoiding leakage of these NMOS transistors.

The input voltage may be transferred at the transfer time and at least temporarily on each flip-flop input, the value of the input voltage being equal to the value of the second supply voltage, increasing the threshold voltage of the NMOS transistor. Since such an input voltage is not considered to be representative of a 1 "logic state, a disabled logic state is still not obtained, but this may result in current leakage at the NMOS transistor.

According to one implementation, the control module includes a first NAND logic gate capable of being powered between a first auxiliary voltage and a second auxiliary voltage.

The first logic gate has a first gate input configured to receive a logic signal for setting the latch flip-flop, a second gate input configured to receive a control signal, and a first gate output coupled to the first flip-flop input.

The control module also includes a second NAND logic gate configured to be powered between the first auxiliary voltage and the second auxiliary voltage.

The second NAND logic gate has a first gate input configured to receive a control signal, a second gate input configured to receive a logic signal for setting a latch flip-flop, and a second gate output coupled to the second flip-flop input.

The control module further includes control circuitry configured to assign logic values to the control signals, to pass set signals in their active or inactive logic states, to pass reset signals in their inactive or active logic states, and to manage the values of the first supply voltage, the second supply voltage, the first auxiliary supply voltage, and the second auxiliary supply voltage, in accordance with various phases of operation of the flip-flop (e.g., the flip-flop being in an inactive state, the flip-flop being set, the flip-flop being reset, and to pass and hold at the output a high voltage or a low voltage latching the flip-flop once the flip-flop is set or reset).

Drawings

Other advantages and features of the invention will appear upon examination of the detailed description of embodiments and implementations not in any way limited and the accompanying drawings, in which:

FIG. 1 illustrates a block diagram of a non-volatile memory device;

FIG. 2 is a schematic diagram of a non-volatile memory device;

FIG. 3 is a schematic diagram of the association of a first latch device with multiple rows of a non-volatile memory device;

FIG. 4 is a schematic diagram of a first control stage of a nonvolatile memory device;

FIGS. 5 and 6 are schematic diagrams of a row decoder including block decoding circuitry of a nonvolatile memory device;

FIG. 7 is a schematic diagram of a latch device; and

fig. 8 illustrates the use of the latch device of fig. 7 in the circuit shown in fig. 6.

Detailed Description

In fig. 1, reference numeral DM denotes a nonvolatile memory device having a voltage division type architecture, which includes a matrix memory plane PM including rows and columns of memory cells CEL.

A row decoder RDEC and a column decoder CDEC of conventional construction are associated with this memory plane PM.

The row decoder (examples of which structures will be described in more detail below) is configured to select rows of the memory plane.

As schematically shown in fig. 2, each memory cell includes an access or select transistor TA and a state transistor TR having a floating gate and a control gate.

All access transistors TA of the same cell row j are connected to a word line WLj by their respective gates and are controlled on their gates by a signal WLj (for simplicity the word line and the signals passed on this word line will be indicated by the same reference sign WLj).

The source of the state transistor TR is connected to a controlled source line SL, the potential of which is typically grounded during the operational phase of data erasing or data reading of the memory cell, but which is a positive voltage of the order of a few volts during the operational phase of programming the memory cell.

As shown in fig. 2, the memory plane PM typically includes memory words MTMi in each row. Each memory word MTMi comprises a number of memory cells, here p memory cells.

These are therefore referred to as memory word columns.

Thus, the memory words MTMi in each row belong to a memory word column i, and the access transistors TA of the p memory cells of these memory words MTMi are connected to bit lines blp.i, blp.i+1, respectively.

As described above, the source line SL dedicated to column i and thus dedicated to the corresponding memory word MTMi connects the source of the state transistor TR of the memory word MTMi.

All state transistors TR of the memory cells of the memory word MTMi are controlled on their gates by a control element CGSWij, which here comprises an inverter comprising an NMOS transistor TN and a PMOS transistor TP.

And, all control elements CGSWij of the same row j are controlled by a first control signal CLj conveyed on line CLj (here, for simplicity, reference numeral CLj of a line corresponds to the reference numeral of a control signal carried on that line).

As will be shown in more detail below, this first control signal CLj comes from a first latch device of the SR type, labeled dist 1, associated with row j via a first row control circuit MPLR 1.

Likewise, the second control signal WLj comes from a second latch device of SR type, labeled dist 2, via a second row control circuit MPLR 2.

If the inverter CGSWij is now considered again, it is apparent that the input of this inverter is controlled by the first control signal CLj.

The substrate of transistor TP is biased by voltage BP and the substrate of transistor TN is biased by voltage BN.

Further, the source of the transistor TP is biased by the voltage DPi, and the source of the transistor TN is biased by the voltage DNi.

As will be seen in more detail below, in order to write a data fragment in a memory word MTMi: the row decoder RDEC is configured to select a row j containing the memory word and the first row control circuit MPLR1 associated with the selected row j is configured to apply an erase voltage corresponding to the first logic state of the first control signal CLj to the first control signal CLj and then to apply a program voltage corresponding to the second logic state of the first control signal CLj, but without modifying the state of the output terminal OUT of the first latch device dist 1 associated with the selected row j between erasing and programming the memory word MTMi.

The various voltage values of the control signal CLj corresponding to their respective logic states will be returned in more detail below.

Although the first latch device and the first row control circuit may be provided for each row j, it is particularly advantageous to provide the first latch device dist 1 associated with N rows (e.g. 8 rows) as illustrated very schematically in fig. 3.

Thus, if the memory plane PM comprises R rows, where R is equal to the product of M times N, there are M blocks of N rows and M first latch devices dist 1 associated with M blocks of N rows, respectively.

The first row control circuit MPLR1 thus comprises N identical first control circuits CPLT0-CPLT7 (where N is equal to 8), each having a first circuit input ECR1, the first circuit input ECR1 being connected to the output terminal OUT of the corresponding first latch device dist 1. Further, each first control circuit has a circuit output SCR1, the circuit output SCR1 delivering a corresponding first control signal CLj (j=0 to 7).

Each first control circuit CLPTi further comprises a second circuit input ECR2, the second circuit input ECR2 being configured to receive a first control signal control v delivered by the first control stage ETCM 1.

Also, as will be seen in more detail below, the logic state of the first control signal CLj depends on the value of the first control signal control v.

The first latch device dist 1 comprises a Set input Set and a Reset input Reset.

The latch device dist 1 is also powered between a first supply voltage Vplus and a second supply voltage Vminus, which is lower than the supply voltage Vplus.

Upon erasing, once the latch device dist 1 is set, the first power supply voltage Vplus rises to a high voltage value, for example 15 volts, and the second power supply voltage Vminus rises to a low voltage, for example 3 volts.

For the selected row j, the voltage of the first control signal CLj associated with the selected row is equal to the low voltage or 3 volts in this example. Thus, this corresponds to a low logic state.

During a programming operation following an erase operation in a write cycle of the memory word under consideration, the first supply voltage Vplus is equal to, for example, 3 volts, while the second supply voltage Vminus is a negative voltage, for example, equal to-5 volts.

And, for the selected row j, the voltage value of the signal CLj passed on that selected row is equal to 3 volts in the programming step, which corresponds to programming with a high voltage Vplus. The first control signal CLj now therefore has a high logic state.

It is therefore apparent that the logic state of the first control signal is changed between the erasing step and the programming step.

It changes from a low logic state to a high logic state.

However, as will be seen in more detail below, this is performed without a change in the logic state of the output signal passed on the output terminal OUT of the first latch device dist 1.

In practice, this logic state change of the first control signal CLj is performed via the value of the first control signal control v.

During an erase operation, the selection of column i containing the memory word MTMi is performed using the value of the voltage Dpi.

More precisely, for a selected column, the value Dpi is equal to a high voltage, for example 15 volts, while for unselected columns and selected rows, the value of this voltage is equal to 3 volts.

For a programming operation, the selection of column i containing the word MTMi located in the selected row is performed via the value of voltage DNi.

More precisely, this voltage is equal to-5 volts to select column i of the selected row j, and this voltage is equal to 3 volts to not select column i of the selected row.

Regarding the values of the substrate voltages BN and BP, they are equal to 3 volts and 15 volts, respectively, for an erase operation, whether or not this is for the selected column and/or row.

For a programming operation, the values of voltages BN and BP are equal to-5 volts and 3 volts, respectively, whether this is for selecting or not selecting a column and/or row.

An exemplary embodiment of the first control stage CPLT0 will now be described with more specific reference to fig. 4.

The latter comprises a dedicated NOR type logic gate PL2, the dedicated NOR type logic gate PL2 having: a first gate input ENP1 connected to a first circuit input ECR1 via a NAND logic gate PL 1; a second gate input ENP2 connected to the second circuit input ECR2; and a gate output connected to an input of the first inverter INV1, an output of the first inverter INV1 being connected to the first circuit output SCR1.

The logic gate PL1 also receives on its other input the first decoding signal P0HVCL0 connected to the first decoding input EDC1, allowing to select or not select the row associated with this first control circuit CPLT 0.

The logic gate PL1 thus forms a first row decoding circuit and allows the row to be selected or not selected in combination with the first row decoding signal P0HVCL 0.

More precisely, if the logical value of the first decoding signal P0HVCL0 is equal to 1, a row is selected. However, if the logical value is equal to 0, then the row is not selected.

If now referring more specifically to fig. 5, it is evident that the row decoder comprises a block decoding circuit CDCBLC, here comprising an AND logic gate connected at the output to the Set input Set of the first latch device dist 1.

In this example, a first input of the AND gate CDCBLC receives conductor P1 of the eight conductors. The second input receives conductor P2 of the eight conductors which allows selecting the latch device dist 1 from M (here m=64) devices.

Thus, the combination of this gate CDCBLC and the NAND gate PL1 of the control circuit CPLT1 allows selecting a row from 512 rows.

The Reset input Reset of the first latch device dist 1 is capable of receiving a Reset signal RstCL.

As described above, the write cycle of a memory word begins with a phase of erasing the memory word.

In this respect, for erasure, after the first latch device is set, it passes the voltage Vplus (15 volts) on its output terminal OUT. The logic output of the output terminal OUT is thus in a high state.

The corresponding row has been selected (signal pohvcl0=1), and the output of NAND gate PL1 is equal to 0.

The first control signal control also has a low logic state. Thus, the output of the dedicated NOR gate PL2 has a high logic state (the delivered voltage is a voltage Vplus equal to 15 volts).

Therefore, the output of the inverter INV1 is in a low state (voltage equal to 3 volts). Thus, first control signal CL0 has a low logic state and a voltage equal to Vminus (3 volts).

For the programming phase, the first latch device DISV1 is now powered between voltage Vplus (3 volts) and voltage Vminus (-5 volts). The output of the first latch device passes a voltage Vplus (3 volts), which here again corresponds to the high logic state of the output signal.

The output of the NAND logic gate PL1 is thus still equal to 0. At this time, however, the first control signal control has a voltage equal to Vplus, which corresponds to its high logic state. Thus, the output of logic gate PL2 is in a low logic state. Accordingly, the output of the first inverter INV1 is in a high logic state (which has a voltage Vplus equal to 3 volts).

The same is true for the first control signal CL0, which has a voltage Vplus corresponding to the high state of the signal.

Thus, there is indeed a modification of the logic state of the first control signal CL0 between the erasing and programming of the memory word, but not of the output terminal OUT of the first latch device dist 1.

Reference is now made more specifically to fig. 6.

All select transistors of the memory cells of the same row are controlled by a second control signal WL0 (for row 0). The second control signal is from a second latch device DISV2 of SR type, which may have a structure similar to that of the first device DISV 1.

To program a data fragment in a memory word, the row decoder is configured to select a row containing the memory word, and as shown in fig. 2, the second row control circuit MPLR2 associated with the selected row is configured to apply a selection voltage, typically a high voltage, for example 13 volts, to the second control signal WLj.

As shown in fig. 6, the second row control circuit MPLR2 includes a second control circuit CPTL20, and the second control circuit CPTL20 has a structure similar to that of the first control circuit CPTL0, except for a dedicated NOR logic gate.

More precisely, the NAND logic gate PL12 forms a second row decoding circuit, the NAND logic gate PL12 receiving the second decoding signal P0HVWL0 on an input connected to the second decoding input EDC2, being connected on its other input to the first circuit input ECR12, the first circuit input ECR12 itself being connected to the output of the corresponding second latch device DISV 2.

The output of gate PL12 is connected to the input of second inverter INV2, the output of second inverter INV2 is connected to circuit output SCR12, and circuit output SCR12 passes second control signal WL0 (for row 0).

Although any type of latch device (e.g., SRAM type latch device) may be used for latch devices dist 1 and dist 2, it is particularly advantageous to use a latch device of the type described in the aforementioned french patent application No. 2205502 and an exemplary embodiment thereof is shown in fig. 7.

The latch device DISV comprises a latch flip-flop of SR type, denoted BSV, which is supplied between a first supply voltage Vplus and a second supply voltage Vminus and has a first flip-flop input a, a second flip-flop input B and a flip-flop output OUTN2 connected to an output terminal OUT.

Here, the flip-flop output OUTN2 forms the output terminal OUT of the device dist.

The latch flip-flop BSV comprises a first logic gate NOR1 and a second logic gate NOR2, which are here NOR gates.

The first logic gate NOR1 has a first gate input ENR10, a second gate input ENR11 and a first gate output OUTN1 coupled to the first flip-flop input a.

The second logic gate NOR2 has a first gate input ENR20 coupled to the first gate output OUTN1, a second gate input ENR21 coupled to the second flip-flop input B, a second gate input ENR11 coupled to the first logic gate NOR1, and a second gate output OUTN2 coupled to the flip-flop output OUT.

The device DISV further comprises a control module MCM configured to position the latch flip-flop BSV in a set state or a reset state when the first supply voltage Vplus has a first value Vdd that is smaller than the low voltage LV and may be as low as a maximum value (e.g. about 0.9 volt) between the absolute value of the threshold voltage of the NMOS transistor of the device and the threshold voltage of the PMOS transistor of the device.

When the flip-flop BSV is in its "set" or "reset" state, the control module is configured to assign a high voltage HV to the first supply voltage Vplus and a low voltage LV to the second supply voltage Vminus, depending on the initial positioning state of the flip-flop, and cause the high voltage HV or the low voltage LV to be transferred and held on the flip-flop output OUTN2.

In this aspect, the control module is configured to simultaneously deliver two input voltages to the two flip-flop inputs a and B at and after the delivery time, which theoretically correspond to the inhibit logic state, but under delivery conditions such that the two input voltages do not actually transition the flip-flop to the inhibit logic state.

The inhibit logic state is a state that transitions to a state that applies a Set and reset condition to both flip-flop inputs a and B simultaneously.

In the described example, the flip-flop BSV includes a NOR gate.

Therefore, for such flip-flops, the logic state is disabled from theoretically transitioning to apply two voltages to the two flip-flop inputs observed through the NMOS transistor of the flip-flop, the gate of which is connected to the two flip-flop inputs a and B, denoted as a "1" logic state.

For example, the above-described transfer condition (causing the theoretical inhibit logic state to not actually switch the flip-flop to the inhibit logic state) includes satisfying the relationship between the values of the two input voltages (the value of the second power supply voltage and the threshold voltage of the NMOS transistor of the flip-flop) at and after the transfer time, the gate of the NMOS transistor being connected to the two flip-flop inputs.

More precisely, the first and second logic gates NOR1 and NOR2 comprise NMOS transistors, the gates of which are connected to the first flip-flop input a or the second flip-flop input B, and the control module is advantageously configured to, starting from said transfer time, transfer said corresponding input voltage on each flip-flop input, the value of the corresponding input voltage being lower than the value of the second supply voltage, increasing the threshold voltage of the NMOS transistor, when the flip-flop is positioned (in its set or reset state).

These pass conditions allow the gate-source voltage of these transistors to be obtained, which is lower than its threshold voltage, thus preventing and avoiding the forbidden logic states of the flip-flops, while avoiding leakage of these NMOS transistors.

Physically, the control module comprises a first NAND logic gate, for example labeled NAND1, powered between a first auxiliary voltage VdVp and a second auxiliary voltage VgVm, and coupled at an output to a first flip-flop input a.

The control module further comprises a second NAND logic gate, labeled NAND2, which is powered between the first auxiliary voltage VdVp and the second auxiliary voltage VgVm and is coupled at an output to the second flip-flop input B.

The first NAND logic gate NAND1 has a first gate input END10 capable of receiving a logic signal SetN for setting the latch flip-flop, a second gate input END11 capable of receiving a control signal NoGsN, and a first gate output out 1 coupled to the first flip-flop input a.

The second NAND logic gate NAND2 has a first gate input END20 configured to receive a control signal NoGsN; a second gate input END21 configured to receive a logic signal ResetN for resetting the latch flip-flop and a second gate output OUTD2 coupled to the second flip-flop input B.

The control module MCM further comprises a control circuit MCTRL configured to assign logic values to the control signal NoGsN, to pass the set signal SetN in its active or inactive logic state, to pass the reset signal ResetN in its inactive or active logic state, and to manage the values of the first supply voltage Vplus, the second supply voltage Vminus, the first auxiliary supply voltage VdVp and the second auxiliary supply voltage VgVm, according to the respective operating phases of the latch flip-flop.

This management is performed, for example, in particular by a state machine, comprising a time ordering of these different voltage values.

Fig. 8 illustrates an example of the use of these latch devices of fig. 7 in a configuration of the type shown in fig. 6.

More precisely, each first latch device dist 1 is controlled by a control signal CLnoGsN, and each second latch device dist 2 is controlled by a control signal WLnoGsN.

These inputs END10 and END21 of the two NAND gates NAND1 and NAND2 respectively receive the reset signal PCRN. The output of the NAND logic gate CDCBLC, which allows here to select the block of two devices dist 1 and dist 2 from the 64 blocks, is connected to the gate inputs END22 and END13 of the two NAND gates NAND12 and NAND11 of the two latch devices to set these devices.

The NOR gate of the latch device DISV2 and the gates of the control circuits CPLT20-CPLT27 are supplied between the voltage VWLdec and the voltage sw_gnd2.

Claims (19)

1. A non-volatile memory device having a "partial pressure" type architecture, comprising:

a matrix memory plane including memory word columns formed on each row of the memory plane by groups of memory cells, respectively;

wherein each memory cell includes a state transistor having a control gate and a floating gate, and a select transistor;

wherein the state transistors of the memory cells for a memory word are controlled on the control gate by control elements, wherein all control elements of a same row are controlled by a first control signal generated by a first row control element;

A first latch device of a set-reset SR type, associated with the row, and having an output terminal generating a latch signal, the latch signal being input to the first row control element;

a row decoder configured to, when writing a data fragment in the memory word:

selecting a row for storing the memory word and selecting the first row control element associated with the selected row; and

applying an erase voltage corresponding to a first logic state of the first control signal to the first control signal; and

a programming voltage corresponding to a second logic state of the first control signal is then applied to the first control signal, but the logic state of the latch signal generated at the output terminal of the first latch device associated with the selected row is not modified between erasing and programming of the memory word.

2. The memory device of claim 1, further comprising a first control stage configured to pass a voltage control signal, and wherein the first row control circuit comprises a first control circuit having a first circuit input connected to the output terminal of the first latch device, a second circuit input configured to receive the voltage control signal, and a first circuit output configured to pass the first control signal, wherein the logic state of the first control signal depends on a voltage value of the voltage control signal.

3. The memory device of claim 2, wherein the first control circuit comprises:

a dedicated NOR-type logic gate having a first gate input connected to the first circuit input, a second gate input connected to the second circuit input, and a gate output; and

a first inverter is connected between the gate output and the first circuit output.

4. The memory device of claim 2, wherein all select transistors of the memory cells of a same row are controlled by a second control signal generated by a second latch device of a set-reset SR type associated with the row, wherein the row decoder is further configured to select a row containing a memory word when programming a data segment in the memory word, and wherein the memory device comprises a second row control circuit associated with the selected row and configured to: to program the data segment in the memory word, a select voltage is applied to the second control signal.

5. The apparatus of claim 4, wherein the second row control circuit comprises: a second control circuit having a first circuit input connected to the output terminal of the second latch device and a second circuit output configured to pass the second control signal.

6. The memory device of claim 5, wherein the second control circuit comprises: a second inverter having an output connected to the second circuit output.

7. The memory device of claim 4,

wherein the memory plane includes R rows and the memory device includes:

m first latch devices, each first latch device associated with a block of N rows, R being equal to the product of N times M;

likewise, for each first latch device, N first row control circuits are associated with N rows, respectively, in a row block with which the first latch device is associated; and

wherein the row decoder comprises a block decoding circuit configured to select a first latch device from M of the first latch devices and a first row decoding circuit configured to select a row associated with the first latch device from N rows of a row block; and

wherein each pair formed by the first latch device and the second latch device is associated with a block of the same N rows, and the memory device comprises, for each second latch device, N second row control means associated with N rows of the block of rows with which the second latch device is associated, respectively; and

In addition to the block decoding circuitry configured to select a pair of first and second latch devices from M pairs, the row decoder further comprises second row decoding circuitry configured to select a row associated with the selected second latch device from N rows of the row block.

8. The memory device of claim 7, wherein the block decoding circuit is connected to the set input of each second latch device and the second row decoding circuit includes a second logic gate in each second control circuit, the second logic gate having a first input connected to the first circuit input and a second input connected to a second decoding input, and having an output connected to the second inverter, the second decoding input configured to receive a row decoding signal.

9. The memory device of claim 8,

wherein the block decoding circuit is connected to a set input of each first latch device and the first row decoding circuit comprises in each first control circuit a first logic gate connected at a first input to the first circuit input and at a second input to a first decoding input configured to receive a row decoding signal and at an output to the second gate input of the dedicated NOR logic gate; and

Wherein the first logic gate and the second logic gate are NAND gates.

10. The memory device of claim 1, wherein the memory plane comprises R rows, and the memory device comprises:

m first latch devices, each first latch device associated with a block of N rows, R being equal to the product of N times M; and

likewise, for each first latch device, N first row control circuits are associated with N rows, respectively, in a row block with which the first latch device is associated; and

wherein the row decoder comprises a block decoding circuit configured to select a first latch device from the M first latch devices and a first row decoding circuit configured to select a row associated with the selected first latch device from the N rows of the row block.

11. The memory device of claim 10, wherein the block decoding circuit is connected to a set input of each first latch device and the first row decoding circuit includes a first logic gate in each first control circuit connected to the first circuit input at a first input and to a first decoding input at a second input and to the second gate input of the dedicated NOR logic gate at an output, the first decoding input configured to receive a row decoding signal.

12. The memory device of claim 1, wherein the first latch device is configured to pass and hold a high or low voltage on the output terminal according to a command, and comprises:

a first latch flip-flop of the SR type being supplied between a first supply voltage and a second supply voltage lower than the first supply voltage and having a first flip-flop input and a second flip-flop input and a flip-flop output connected to the output terminal; and

a control module configured to:

positioning the first latch flip-flop in a set state or a reset state when the first power supply voltage has a first value lower than the low voltage; and

the latch flip-flop is then positioned to impart the high voltage to the first supply voltage and the low voltage to the second supply voltage, and from a transfer time, two input voltages are simultaneously transferred to the two flip-flop inputs under transfer conditions, the two input voltages theoretically corresponding to a disabled logic state, such that the two input voltages do not actually transition the first flip-flop to the disabled logic state to transfer and hold the high voltage or the low voltage on the flip-flop output.

13. The memory device of claim 12, wherein the control module comprises:

a first NAND logic gate powered between a first auxiliary voltage and a second auxiliary voltage and having a first gate input connected to the output of the block decoding circuit, a second gate input configured to receive a third control signal, and a first gate output coupled to the first flip-flop input;

a second NAND logic gate powered between the first auxiliary voltage and the second auxiliary voltage and having a first gate input configured to receive the third control signal, a second gate input configured to receive a logic signal for resetting the first latch flip-flop, and a second gate output coupled to the second flip-flop input;

a control circuit configured to assign a logic value to the third control signal, pass the reset signal in an inactive logic state or an active logic state of the third control signal, and manage the value of the first power supply voltage, the value of the second power supply voltage, the value of the first auxiliary power supply voltage, and the value of the second auxiliary power supply voltage according to respective operation phases of the first latch flip-flop.

14. The memory device of claim 12, wherein all select transistors of the memory cells of a same row are controlled by a second control signal generated by a second latch device of a set-reset SR type associated with the row, and wherein the second latch device has an architecture similar to that of the first latch device.

15. The memory device of claim 1, wherein the memory device is an EEPROM type.

16. A non-volatile memory device, comprising:

a matrix memory plane including memory cells;

wherein each memory cell includes a state transistor having a control gate and a floating gate, and a select transistor;

latch circuitry for each row of the matrix memory plane;

a control element having an input and an output, wherein the input is configured to receive a first control signal, and wherein the output is connected to a control gate of the status transistor associated with a memory word location in a row of the matrix memory plane;

a first row control element coupled to an output of the latch circuit and configured to generate the first control signal;

Wherein, in a write mode, the first control signal has an erase voltage corresponding to a first logic state of the first control signal during an erase operation on the memory word location and then has a program voltage corresponding to a second logic state of the first control signal during a program operation on the memory word location; and

wherein the output of the latch circuit does not change state between the erase operation and the program operation.

17. The memory device of claim 16, wherein the output of the latch circuit is set in response to address decoding that selects the row of the matrix memory plane.

18. The memory device of claim 17, wherein the first row of control elements comprises:

a dedicated NOR-type logic gate having a first gate input coupled to receive a signal derived from the output of the latch circuit and a second gate input coupled to receive a signal derived from the address; and

a first inverter has an input coupled to the output of the logic gate and an output that generates the first control signal.

19. The memory device of claim 16, further comprising:

another latch circuit for each row of the matrix memory plane;

a second row control element coupled to an output of the other latch circuit and configured to generate a second control signal applied to a control gate of the select transistor of the memory cell of the row.