CN117672096A - Driving circuit for display device - Google Patents

Abstract

The invention provides a driving circuit for a display device. The driving circuit comprises an enabling unit, a driving unit and a mode selecting unit. The enabling unit sets the voltage value at the bias node to a first voltage value according to the clock signal and the initial signal during the enabling period. The driving unit generates a light-emitting enabling signal according to a first voltage value at the bias node during driving, and generates a test signal according to the first voltage value at the bias node and an auxiliary clock signal. The pulse width of the test signal is smaller than the pulse width of the light emission enabling signal. The mode selection unit outputs a light-emitting enabling signal according to the first selection signal and outputs a test signal according to the second selection signal.

Description

Driving circuit for display device

Technical Field

The present invention relates to a driving circuit, and more particularly, to a driving circuit for a display device.

Background

The light emitting diode display device includes a plurality of pixel circuits. The plurality of pixel circuits may be organic light emitting diodes (organic light emitting diode, OLEDs), sub-millimeter light emitting diodes (mini LEDs), micro light emitting diodes (micro LEDs), or quantum dot light emitting diodes (quantum dot LEDs), respectively. The plurality of pixel circuits are driven by a light emission enable signal.

Referring to fig. 1, fig. 1 is a signal timing diagram of a light emitting enable signal in the prior art. Fig. 1 shows light emission enable signals EM1, EM2, EM3. In order to enable the pixel circuit to provide sufficient brightness, the minimum pulse widths of the light emission enable signals EM1, EM2, EM3 are respectively limited. The minimum pulse width of the light emission enable signals EM1, EM2, EM3 is designed to be equal to 2a times the pulse width of the data signal. "a" is a positive integer. The first pixel circuit emits light according to the negative pulse width of the light emission enable signal EM 1. The second pixel circuit emits light according to the negative pulse width of the light emission enable signal EM 2. The third pixel circuit emits light according to the negative pulse width of the light emission enable signal EM3.

At the time of detection (e.g., array test), the pixel circuit detects based on the light emission enable signal. It should be noted that the minimum pulse width of the light emission enable signals EM1, EM2, EM3 is designed to be equal to 2a times the pulse width of the data signal. Therefore, when an abnormality occurs in response to the detection of the light emission enable signal EM2, the detection result cannot determine which of the first pixel circuit and the second pixel circuit is abnormal. When an abnormality occurs in response to the detection of the light emission enable signal EM3, the detection result cannot determine which of the second pixel circuit and the third pixel circuit is abnormal.

Therefore, the current detection cannot accurately indicate the abnormal pixel circuit based on the light emitting enable signal.

Disclosure of Invention

The invention provides a driving circuit for a display device, which can enable the display device to provide accurate detection results during detection.

The driving circuit is used for a display device. The driving circuit comprises an enabling unit, a driving unit and a mode selecting unit. The enabling unit is coupled to the bias node. The enabling unit sets the voltage value at the bias node to a first voltage value according to the clock signal and the initial signal during the enabling period. The driving unit is coupled to the bias node. The driving unit generates a light-emitting enabling signal according to a first voltage value at the bias node during driving, and generates a test signal according to the first voltage value at the bias node and an auxiliary clock signal. The pulse width of the test signal is smaller than the pulse width of the light emission enabling signal. The mode selection unit is coupled to the driving unit. The mode selection unit outputs a light-emitting enabling signal according to the first selection signal and outputs a test signal according to the second selection signal.

Based on the above, the driving unit generates the light emission enable signal and the test signal during the driving period. In addition, the mode selection unit outputs a test signal according to the second selection signal. The pulse width of the test signal is smaller than the pulse width of the light emission enabling signal. Therefore, the driving circuit can make the display device provide a precise detection result at the time of detection based on the test signal having a small pulse width.

Drawings

FIG. 1 is a signal timing diagram of a prior art light-emitting enable signal.

Fig. 2 is a schematic diagram of a driving circuit according to an embodiment of the invention.

Fig. 3 is a schematic diagram of a driving circuit according to another embodiment of the invention.

Fig. 4 is a circuit diagram of a driving circuit according to a first embodiment of the present invention.

FIG. 5 is a timing diagram of signals according to the diagram of FIG. 4.

Fig. 6 is a circuit diagram of a driving circuit according to a second embodiment of the present invention.

FIG. 7 is a timing diagram of signals according to the embodiment shown in FIG. 6.

Reference numerals illustrate:

100. 200, 300, 400: driving circuit

110. 310: enabling unit

120. 320, 420: driving unit

130. 330: mode selection unit

240. 340, 440: discharge circuit

341. 441: control circuit

342. 442: reset circuit

A (n): node

C1, C2: capacitor with a capacitor body

CK: clock signal

EM1, EM2, EM3, em_t (n): luminescence enable signal

Em_at (n): test signal

Em_t (n-1): initial signal

P (n): control node

PW1, PW2: pulse width

Q (n): bias node

RST: reset signal

SM1: first selection signal

SM2: second selection signal

t1, t2, t3, t4, t5: time point

TC1, TC2, TC3, TC4, TR1, TR2, TR3: transistor with a high-voltage power supply

TD: during driving

TD1, TD2, TD3: driving transistor

TE: during the enabling period

TE1: enable transistor

TR: during discharge period

TS1, TS2: switch

VGH, VGL: reference voltage

XCK: auxiliary clock signal

Detailed Description

Some embodiments of the invention will be described in detail below with reference to the drawings, wherein reference to the following description refers to the same or similar elements appearing in different drawings. These examples are only a part of the present invention and do not disclose all possible embodiments of the invention. Rather, these embodiments are merely examples of the invention in the claims.

Referring to fig. 2, fig. 2 is a schematic diagram of a driving circuit according to an embodiment of the invention. In the present embodiment, the driving circuit 100 is used for a display device. Further, the driving circuit 100 may be used to drive and test corresponding pixel circuits in a display device. For example, the pixel circuits may be organic light emitting diodes (organic light emitting diode, OLEDs), sub-millimeter light emitting diodes (mini LEDs), micro light emitting diodes (micro LEDs), or quantum dot light emitting diodes (quantum dot LEDs), respectively.

In the present embodiment, the driving circuit 100 includes an enabling unit 110, a driving unit 120, and a mode selecting unit 130. The enabling unit 110 is coupled to the bias node Q (n). The enabling unit 110 sets the voltage value at the bias node Q (n) to a first voltage value according to the clock signal CK and the initial signal em_t (n-1) during the enabling period. The driving unit 120 is coupled to the bias node Q (n). The driving unit 120 generates the light emitting enable signal em_t (n) according to the first voltage value AT the bias node Q (n) during driving, and generates the test signal em_at (n) according to the first voltage value AT the bias node Q (n) and the auxiliary clock signal XCK. In the present embodiment, the initial signal em_t (n-1) is a light emission enable signal of a previous stage of the light emission enable signal em_t (n).

Taking this embodiment as an example, the light emission enable signal em_t (n) has a pulse. The test signal em_at (n) also has pulses. The light emission enable signal em_t (n) has a pulse width PW1. The test signal em_at (n) has a pulse width PW2. It should be noted that the pulse width PW2 is smaller than the pulse width PW1. The first voltage is, for example, a low voltage (e.g., 0 v) or a negative voltage, but the invention is not limited thereto. The pulses of the present embodiment are exemplified by negative pulses. However, the invention is not limited thereto. In some embodiments, the light-emitting enable signal em_t (n) and the test signal em_at (n) have positive pulses, respectively.

In the present embodiment, the light emission enable signal em_t (n) is used to drive the corresponding pixel circuit in the normal use state. The test signal em_at (n) is used to detect the corresponding pixel circuit in the detection phase. For example, the corresponding pixel circuit may output a detection signal generated based on detection (e.g., array test) based on the test signal em_at (n).

In the present embodiment, the mode selection unit 130 is coupled to the driving unit 120. The mode selection unit 130 receives the light emitting enable signal em_t (n) and the test signal em_at (n) generated by the driving unit 120. The mode selection unit 130 outputs a light emitting enable signal em_t (n) according to the first selection signal SM1, and outputs a test signal em_at (n) according to the second selection signal SM2. In other words, in the normal use state, the mode selection unit 130 outputs the light emission enable signal em_t (n) to drive the corresponding pixel circuit. In the detection phase, the mode selection unit 130 outputs the test signal em_at (n) to detect the corresponding pixel circuit.

It should be noted that the driving unit 120 generates the light emitting enable signal em_t (n) and the test signal em_at (n) during the driving period. In addition, the mode selection unit 130 outputs the test signal em_at (n) according to the second selection signal SM2. The pulse width PW2 of the test signal em_at (n) is smaller than the pulse width PW1 of the light emission enable signal em_t (n). In this way, the pulse width PW2 of the test signal em_at (n) corresponds to a single pixel circuit. In the detection, the driving circuit 100 can enable the display device to provide accurate detection results.

Referring to fig. 3, fig. 3 is a schematic diagram of a driving circuit according to another embodiment of the invention. In the present embodiment, the driving circuit 200 includes an enabling unit 110, a driving unit 120, a mode selecting unit 130, and a discharging circuit 240. The implementation of the enabling unit 110, the driving unit 120 and the mode selection unit 130 is already described in the embodiment of fig. 2, and is not repeated here.

In the present embodiment, the discharging circuit 240 is coupled to the bias node Q (n) and the driving unit 120. The discharging circuit 240 resets the voltage value at the bias node to the second voltage value during the discharging period other than the enabling period and the driving period, and resets the voltage value of the light emitting enable signal em_t (n) to the second voltage value during the discharging period. The second voltage value is different from the first voltage value. The second voltage is, for example, a high voltage, but the invention is not limited thereto. In addition, the discharging circuit 240 also resets the voltage value of the emission test signal em_at (n) to the second voltage value during the discharging.

Referring to fig. 4, fig. 4 is a circuit diagram of a driving circuit according to a first embodiment of the present invention. In the present embodiment, the driving circuit 300 includes an enabling unit 310, a driving unit 320, a mode selecting unit 330, and a discharging circuit 340. The enabling unit 310 includes an enabling transistor TE1. The first terminal of the enable transistor TE1 receives the initial signal em_t (n-1). The second terminal of the enable transistor TE1 is coupled to the bias node Q (n). The control terminal of the enable transistor TE1 receives the clock signal CK. The enable transistor TE1 is turned on in response to the pulse of the clock signal CK, thereby providing the initial signal em_t (n-1) to the bias node Q (n). Taking this embodiment as an example, the enabling transistor TE1 is implemented by a field-effect transistor (FET) (but the invention is not limited thereto). Accordingly, the enable transistor TE1 is turned on in response to the negative pulse of the clock signal CK.

In the present embodiment, the driving unit 320 includes a capacitor C1 and driving transistors TD1, TD2. A first terminal of the capacitor C1 receives the auxiliary clock signal XCK. The second terminal of the capacitor C1 is coupled to the bias node Q (n). The first terminal of the driving transistor TD1 receives the reference voltage VGL. The second terminal of the driving transistor TD1 is configured to output a light-emitting enable signal em_t (n). The control terminal of the driving transistor TD1 is coupled to the bias node Q (n). The first terminal of the driving transistor TD2 receives the auxiliary clock signal XCK. The second terminal of the driving transistor TD2 is used for outputting the test signal em_at (n). The control terminal of the driving transistor TD2 is coupled to the bias node Q (n). In the present embodiment, the voltage value of the reference voltage VGL is substantially equal to the first voltage value.

In the present embodiment, the capacitor C1 adjusts the voltage value at the bias node Q (n) in response to the pulse of the auxiliary clock signal XCK during driving. The driving transistor TD1 is turned on according to the first voltage value at the bias node Q (n). Therefore, the turned-on driving transistor TD1 uses the received reference voltage VGL as the light emission enabling signal em_t (n). The driving transistor TD2 is turned on according to the first voltage value at the bias node Q (n). Accordingly, the turned-on driving transistor TD2 takes the received auxiliary clock signal XCK as the test signal em_at (n).

Taking the embodiment as an example, the driving transistors TD1 and TD2 are respectively implemented by P-type FETs (but the invention is not limited thereto). The first voltage value is a negative voltage value or a low voltage value. Accordingly, the driving transistors TD1 and TD2 are turned on in response to the negative voltage value or the low voltage value at the bias node Q (n), respectively. The driving transistors TD1 and TD2 are turned off in response to the high voltage value at the bias node Q (n), respectively.

In the present embodiment, the mode selection unit 330 includes switches TS1, TS2. The first end of the switch TS1 is coupled to the driving unit 320 for receiving the light-emitting enable signal EM_T (n). The second terminal of the switch TS1 is coupled to the output terminal of the driving unit 320. The control terminal of the switch TS1 receives the first selection signal SM1. The first terminal of the switch TS2 is coupled to the driving unit 320 for receiving the test signal EM_AT (n). A second terminal of the switch TS2 is coupled to the output terminal of the driving unit 320. The control terminal of the switch TS2 receives the second selection signal SM2.

When the first selection signal SM1 has a first value, the switch TS1 is turned on. When the first selection signal SM1 has the second value, the switch TS1 is turned off. When the second selection signal SM2 has the first value, the switch TS2 is turned on. When the second selection signal SM2 has the second value, the switch TS2 is turned off. Taking this embodiment as an example, the switches TS1, TS2 are implemented by P-type FETs, respectively. The first value is a negative voltage value or a low voltage value. The second value is a high voltage value. When the first selection signal SM1 has a first value and the second selection signal SM2 has a second value, the mode selection unit 330 outputs the light emission enable signal em_t (n) through the output terminal. When the first selection signal SM1 has the second value and the second selection signal SM2 has the first value, the mode selection unit 330 outputs the test signal em_at (n) through the output terminal.

In some embodiments, the first selection signal SM1 and the second selection signal SM2 are complementary to each other. That is, when the first selection signal SM1 has a first value, the second selection signal SM2 has a second value. When the first selection signal SM1 has the second value, the second selection signal SM2 has the first value.

In some embodiments, the switches TS1, TS2 may each be implemented by a transmission gate (transmission gate). In some embodiments, the mode selection unit 330 may be implemented by a Multiplexer (MUX).

In the present embodiment, the discharging circuit 340 includes a control circuit 341 and a reset circuit 342. The control circuit 341 includes a capacitor C2 and transistors TC1 to TC4. The first terminal of the capacitor C2 receives the clock signal CK. The second terminal of the capacitor C2 is coupled to the node a (n). The first terminal of the transistor TC1 is coupled to the node A (n). The second terminal of the transistor TC1 receives the reference voltage VGH. The control terminal of the transistor TC1 receives the initial signal EM_T (n-1). The first terminal of the transistor TC2 receives the reference voltage VGL. A second terminal of the transistor TC2 is coupled to the control node P (n). The control terminal of the transistor TC2 is coupled to the node a (n). The first terminal of the transistor TC3 is coupled to the control node P (n). The second end of the transistor TC3 receives the reference voltage VGH. The control terminal of the transistor TC3 is coupled to the bias node Q (n). The first terminal of the transistor TC4 receives the reference voltage VGL. A second terminal of the transistor TC4 is coupled to the control node P (n). The control terminal of the transistor TC4 receives the reset signal RST. In the present embodiment, the voltage value of the reference voltage VGH is substantially equal to the second voltage value.

In the present embodiment, the reset circuit 342 is coupled to the control circuit 341 through the control node P (n). The reset circuit 342 includes transistors TR1, TR2. The first terminal of the transistor TR1 is coupled to the bias node Q (n). The second terminal of the transistor TR1 receives the reference voltage VGH. The control terminal of the transistor TR1 is coupled to the control node P (n). The first terminal of the transistor TR2 is coupled to the second terminal of the driving transistor TD 1. The second terminal of the transistor TR2 receives the reference voltage VGH. The control terminal of the transistor TR2 is coupled to the control node P (n).

In the present embodiment, the control circuit 341 may adjust the voltage value at the control node P (n) and control the transistors TR1 and TR2 according to the voltage value at the control node P (n). In the present embodiment, the transistors TC1 to TC4, TR1 and TR2 are implemented by P-type FETs, respectively (but the invention is not limited thereto).

The specific generation of the light emission enable signal em_t (n) and the test signal em_at (n) in the present embodiment will be described below.

Referring to fig. 4 and fig. 5, fig. 5 is a signal timing diagram according to fig. 4. During the discharge period TR before the time point T1, the initial signal em_t (n-1) has a high voltage value. Thus, the transistor TC1 is turned off. During the discharge period TR, the enable transistor TE1 is turned on or not. The voltage value at the bias node Q (n) is a high voltage value. Thus, the transistor TC3 is turned off. In the present embodiment, the voltage value at the node A (n) is pulled down based on the negative pulse of the clock signal CK. Therefore, the transistor TC2 pulls down the voltage value at the control node P (n) to the voltage value (e.g., negative voltage value or low voltage value) of the reference voltage VGL based on the negative pulse of the clock signal CK. Therefore, in the discharging period TR before the time point t1, the voltage timing at the control node P (n) follows the timing of the clock signal CK. When the voltage value at the control node P (n) is a low voltage value, the transistors TR1, TR2 are turned on. Accordingly, the reset circuit 342 resets the voltage value at the bias node Q (n) to the second voltage value, and resets the voltage value of the light emitting enable signal em_t (n) to the second voltage value. The second voltage value is substantially equal to the high voltage value of the reference voltage VGH.

Between the time point t1 and the time point t3, the driving circuit 300 enters the operation of the enabling period TE. During the enable period TE, the initial signal EM_T (n-1) has a negative pulse. During the enable period TE, the enable transistor TE1 is turned on in response to the negative pulse of the clock signal CK at the time point t 2. Accordingly, the driving circuit 300 enters the operation of the driving period TD. The driving period TD is between the time point t2 and the time point t 5. In other words, the enable period TE and the driving period TD partially overlap.

At time T2, the enable transistor TE1 pulls down the voltage value at the bias node Q (n) to the first voltage value by the negative pulse of the initial signal EM_T (n-1). Accordingly, the driving transistor TD1 is turned on to provide the light emission enable signal em_t (n). In addition, the driving transistor TD2 is also turned on to provide the test signal em_at (n). It should be noted that between time point t2 and time point t3, the auxiliary clock signal XCK is not undershoot. Therefore, between the time point t2 and the time point t3, the test signal em_at (n) has the second voltage value.

During the driving period TD, the enabling transistor TE1 is turned off in response to the clock signal CK between the time point t3 and the time point t 5. This causes the bias node Q (n) to be in a floating state. Therefore, the voltage of the bias node Q (n) is maintained at the first voltage. The driving transistors TD1, TD2 are still turned on.

During the driving period TD, the auxiliary clock signal XCK has a negative pulse between the time point t3 and the time point t 4. Based on the capacitive coupling effect of the capacitor C1 itself, the capacitor C1 adjusts the voltage value at the bias node Q (n) in response to the negative pulse of the auxiliary clock signal XCK during the driving period TD. Accordingly, the voltage value of the bias node Q (n) can be lower than the first voltage value, thereby ensuring the conduction of the driving transistors TD1, TD2.

In addition, the test signal em_at (n) has a negative pulse between the time point t3 and the time point t 4. It should be noted that the pulse width of the auxiliary clock signal XCK is smaller than the pulse width of the light emission enable signal em_t (n). Therefore, the pulse width of the test signal em_at (n) is smaller than that of the light emission enable signal em_t (n).

Between time t4 and time t5, auxiliary clock signal XCK has no negative pulse. Therefore, the pulse width of the test signal em_at (n) is substantially equal to the time length between the time point t3 and the time point t 4.

At least one of the initial signal em_t (n-1) and the voltage value at the bias node Q (n) has a first voltage value during the enable period TE and the driving period TD. Thus, both transistors TC1, TC3 are turned on. The voltage values at node a (n) and control node P (n) are both high voltage values (e.g., a second voltage value). Thus, both transistors TR1, TR2 are turned off.

At time point t5, the driving period TD ends. During the discharge period TR after the time point T5, the initial signal em_t (n-1) has a high voltage value. Similar to the discharging period TR before the time point t1, the voltage timing at the control node P (n) follows the timing of the clock signal CK. When the voltage value at the control node P (n) is a low voltage value, the transistors TR1, TR2 are turned on. Accordingly, the reset circuit 342 resets the voltage value at the bias node Q (n) to the second voltage value, and resets the voltage value of the light emitting enable signal em_t (n) to the second voltage value.

In the present embodiment, during the reset period, the transistor TC4 is turned on in response to the reset signal RST to make the voltage value of the control node P (n) be a low voltage value. Thus, both transistors TR1, TR2 are turned on during reset. The reset period is a period other than the driving period TD, the enabling period TE, and the discharging period TR. For example, the reset period may be a portion of a period during which the display device is in a sleep state, a power-on operation, or a power-off operation. During the driving period TD, the enabling period TE and the discharging period TR, the transistor TC4 is turned off.

Referring to fig. 6, fig. 6 is a circuit diagram of a driving circuit according to a second embodiment of the invention. In the present embodiment, the driving circuit 400 includes an enabling unit 310, a driving unit 420, a mode selecting unit 330 and a discharging circuit 440. The embodiments of the enabling unit 310 and the mode selecting unit 330 are clearly described in the examples of fig. 4 and 5, and are not repeated here.

In the present embodiment, the driving unit 420 includes a capacitor C1 and driving transistors TD1, TD2, TD3. A first terminal of the capacitor C1 receives the auxiliary clock signal XCK. The second terminal of the capacitor C1 is coupled to the bias node Q (n). The first terminal of the driving transistor TD1 receives the reference voltage VGL. The second terminal of the driving transistor TD1 is configured to output a light-emitting enable signal em_t (n). The control terminal of the driving transistor TD1 is coupled to the bias node Q (n). The first terminal of the driving transistor TD2 receives the reference voltage VGL. The control terminal of the driving transistor TD2 receives the auxiliary clock signal XCK. The first terminal of the driving transistor TD3 is coupled to the second terminal of the driving transistor TD2. The second terminal of the driving transistor TD3 is used for outputting the test signal em_at (n). The control terminal of the driving transistor TD3 is coupled to the bias node Q (n).

In the present embodiment, the driving transistor TD1 is turned on according to the first voltage value at the bias node Q (n). Therefore, the turned-on driving transistor TD1 uses the received reference voltage VGL as the light emission enabling signal em_t (n).

The driving transistor TD2 is turned on according to the negative pulse of the auxiliary clock signal XCK. Accordingly, the turned-on driving transistor TD2 supplies the received reference voltage VGL to the first terminal of the driving transistor TD3. The driving transistor TD3 is turned on according to the first voltage value at the bias node Q (n). Accordingly, the turned-on driving transistor TD3 takes the signal AT the first terminal of the driving transistor TD3 as the test signal em_at (n). The driving transistors TD1, TD2, and TD3 are implemented by P-type FETs, respectively (but the invention is not limited thereto).

In the present embodiment, the discharging circuit 440 includes a control circuit 441 and a reset circuit 442. The implementation of the control circuit 441 is similar to the implementation of the control circuit 341 in fig. 4 and is not repeated here. The reset circuit 442 is coupled to the control circuit 441 via a control node P (n). The reset circuit 442 includes transistors TR1, TR2, TR3. The first terminal of the transistor TR1 is coupled to the bias node Q (n). The second terminal of the transistor TR1 receives the reference voltage VGH. The control terminal of the transistor TR1 is coupled to the control node P (n). The first terminal of the transistor TR2 is coupled to the second terminal of the driving transistor TD 1. The second terminal of the transistor TR2 receives the reference voltage VGH. The control terminal of the transistor TR2 is coupled to the control node P (n). The first terminal of the transistor TR3 is coupled to the second terminal of the driving transistor TD3. The second terminal of the transistor TR3 receives the reference voltage VGH. The control terminal of the transistor TR3 is coupled to the control node P (n). The transistors TR1, TR2, TR3 are implemented by P-type FETs, respectively (although the invention is not limited thereto).

The specific generation of the light emission enable signal em_t (n) and the test signal em_at (n) in the present embodiment will be described below.

Referring to fig. 6 and fig. 7, fig. 7 is a timing diagram of signals shown in fig. 6. During the discharging period TR before the time point T1, the initial signal EM_T (n-1) and the voltage value of the bias node Q (n) both have high voltage values. Thus, the transistors TC1, TC3 are turned off. The voltage value at node a (n) is pulled down based on the negative pulse of the clock signal CK. Therefore, the transistor TC2 pulls down the voltage value at the control node P (n) to the voltage value (e.g., negative voltage value or low voltage value) of the reference voltage VGL based on the negative pulse of the clock signal CK. When the voltage value at the control node P (n) is a low voltage value, the transistors TR1, TR2, TR3 are turned on. Accordingly, the reset circuit 442 resets the voltage value AT the bias node Q (n) to the second voltage value, resets the voltage value of the light emitting enable signal em_t (n) to the second voltage value, and resets the voltage value of the test signal em_at (n) to the second voltage value.

Between the time point t1 and the time point t3, the driving circuit 400 enters the operation of the enable period TE. During the enable period TE, the initial signal EM_T (n-1) has a negative pulse. During the enable period TE, the enable transistor TE1 is turned on in response to the negative pulse of the clock signal CK at the time point t 2. Accordingly, the driving circuit 300 enters the operation of the driving period TD.

At time T2, the enable transistor TE1 pulls down the voltage value at the bias node Q (n) to the first voltage value by the negative pulse of the initial signal EM_T (n-1). Accordingly, the driving transistor TD1 is turned on to provide the light emission enable signal em_t (n). Further, the transistor TD3 is driven. It should be noted that between time point t2 and time point t3, the auxiliary clock signal XCK is not undershoot. The driving transistor TD2 is still turned off. Therefore, between the time point t2 and the time point t3, the test signal em_at (n) has the second voltage value.

During the driving period TD, the enabling transistor TE1 is turned off in response to the clock signal CK between the time point t3 and the time point t 5. This causes the bias node Q (n) to float. Therefore, the voltage of the bias node Q (n) is maintained at the first voltage. The drive transistors TD1, TD3 are still turned on.

During the driving period TD, the auxiliary clock signal XCK has a negative pulse between the time point t3 and the time point t 4. Based on the capacitive coupling effect of the capacitor C1 itself, the capacitor C1 adjusts the voltage value at the bias node Q (n) in response to the negative pulse of the auxiliary clock signal XCK during the driving period TD. Accordingly, the voltage value of the bias node Q (n) can be lower than the first voltage value, thereby ensuring the conduction of the driving transistors TD1, TD3. It should be noted that the driving transistor TD2 is turned on in response to the negative pulse of the auxiliary clock signal XCK. Therefore, the test signal em_at (n) has a first voltage value between the time point t3 and the time point t 4.

Between time t4 and time t5, auxiliary clock signal XCK has no negative pulse. The driving transistor TD2 is turned off after the time point t 4. The first terminal of the driving transistor TD3 is in a floating state. Therefore, between the time point t4 and the time point t5, the test signal em_at (n) still has the first voltage value.

At least one of the initial signal em_t (n-1) and the voltage value at the bias node Q (n) has a first voltage value during the enable period TE and the driving period TD. Thus, both transistors TC1, TC3 are turned on. The voltage values at node a (n) and control node P (n) are both high voltage values. Accordingly, the transistors TR1 to TR3 are all turned off.

At time point t5, the driving period TD ends. During the discharge period TR after the time point T5, the initial signal em_t (n-1) has a high voltage value. Similar to the discharging period TR before the time point t1, the voltage timing at the control node P (n) follows the timing of the clock signal CK. When the voltage value at the control node P (n) is a low voltage value, the transistors TR1 to TR3 are turned on. Therefore, the reset circuit 442 resets the voltage value AT the bias node Q (n), the voltage value of the light-emitting enable signal em_t (n), and the voltage value of the test signal em_at (n) to the second voltage value.

In summary, the driving unit of the present invention generates the light-emitting enable signal and the test signal during the driving period. In addition, the mode selection unit outputs a test signal according to the second selection signal. The pulse width of the test signal is smaller than the pulse width of the light emission enabling signal. In this way, the pulse width of the test signal corresponds to a single pixel circuit. When in detection, the driving circuit can enable the display device to provide accurate detection results.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.

Claims (12)

1. A driving circuit for a display device, comprising:

an enabling unit coupled to a bias node and configured to set a voltage value at the bias node to a first voltage value according to a clock signal and an initial signal during an enabling period;

a driving unit, coupled to the bias node, configured to generate a light-emitting enable signal according to the first voltage value at the bias node during a driving period, and generate a test signal according to the first voltage value at the bias node and an auxiliary clock signal, wherein a pulse width of the test signal is smaller than a pulse width of the light-emitting enable signal; and

the mode selection unit is coupled to the driving unit and configured to output the light-emitting enabling signal according to a first selection signal and output the test signal according to a second selection signal.

2. The driving circuit of claim 1, wherein a pulse width of the auxiliary clock signal is smaller than a pulse width of the light-emitting enable signal.

3. The driving circuit of claim 1, wherein the enabling unit comprises:

and the first end of the enabling transistor receives the initial signal, the second end of the enabling transistor is coupled with the bias node, and the control end of the enabling transistor receives the clock signal.

4. The driving circuit of claim 3, wherein the enable transistor is turned on in response to a pulse of the clock signal to provide the initial signal to the bias node.

5. The driving circuit of claim 1, wherein the driving unit comprises:

a capacitor having a first end receiving the auxiliary clock signal and a second end coupled to the bias node;

a first driving transistor, a first end of which receives a reference voltage, a second end of which is used for outputting the light-emitting enabling signal, and a control end of which is coupled with the bias node; and

the first end of the second driving transistor receives the auxiliary clock signal, the second end of the second driving transistor is used for outputting the test signal, and the control end of the second driving transistor is coupled with the bias node.

6. The driving circuit of claim 5, wherein the capacitor adjusts the voltage value at the bias node in response to pulses of the auxiliary clock signal during the driving.

7. The drive circuit of claim 5, wherein during the driving:

the first driving transistor is turned on according to the first voltage value at the bias node, thereby using the received reference voltage as the light-emitting enable signal, and

the second driving transistor is turned on according to the first voltage value at the bias node, so that the received auxiliary clock signal is used as the test signal.

8. The driving circuit of claim 1, wherein the driving unit comprises:

a capacitor having a first end receiving the auxiliary clock signal and a second end coupled to the bias node;

a first driving transistor, a first end of which receives a reference voltage, a second end of which is used for outputting the light-emitting enabling signal, and a control end of which is coupled with the bias node; and

a second driving transistor, a first end of which receives the reference voltage, and a control end of which receives the auxiliary clock signal; and

the first end of the third driving transistor is coupled to the second end of the second driving transistor, the second end of the third driving transistor is used for outputting the test signal, and the control end of the third driving transistor is coupled to the bias node.

9. The drive circuit of claim 8, wherein during the driving:

the first driving transistor is turned on according to the first voltage value at the bias node, so that the received reference voltage is used as the light emitting enabling signal,

the second driving transistor is turned on according to the auxiliary clock signal to provide the received reference voltage to the first terminal of the third driving transistor, and

the third driving transistor is turned on according to the first voltage value at the bias node, so that a signal at the first end of the third driving transistor is used as the test signal.

10. The driving circuit of claim 1, wherein the mode selection unit comprises:

the first end of the first switch is coupled with the driving unit to receive the light-emitting enabling signal, the second end of the first switch is coupled with the output end of the driving circuit, and the control end of the first switch receives the first selection signal; and

the first end of the second switch is coupled to the driving unit to receive the test signal, the second end of the second switch is coupled to the output end of the driving circuit, and the control end of the second switch receives the second selection signal.

11. The drive circuit of claim 1, wherein:

when the first selection signal has a first value, the first switch is turned on,

when the first selection signal has a second value, the first switch is turned off,

when the second selection signal has the first value, the second switch is turned on and

when the second selection signal has a second value, the second switch is turned off.

12. The drive circuit of claim 1, further comprising:

and a discharging circuit coupled to the bias node and the driving unit, configured to reset the voltage value of the bias node to a second voltage value during a discharging period other than the enabling period and the driving period, and reset the voltage value of the light emitting enabling signal to the second voltage value.