CN117668929A - Identification circuit, implantable device and identification system - Google Patents
Identification circuit, implantable device and identification system Download PDFInfo
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Abstract
The application relates to an identification circuit, an implantable device and an identification system, which belong to the field of device identification and comprise a driving module, a switching module and a plurality of groups of identity information generating circuits; each group of identity information generating circuits is used for outputting a level signal according to an external signal; the driving module is respectively connected with the plurality of groups of identity information generating circuits and is used for transmitting the level signals output by each group of identity information generating circuits to the switching module; the switching module is connected with the driving module, and the switching module obtains the identity information according to the level signal output by each group of identity information generating circuits. The unique sequence code is generated by using the multiple groups of identity information generating circuits, and then the unique sequence code is output through the driving module and the switching module, so that the confidentiality of the unique sequence code of the implantable device is improved.
Description
Technical Field
The application relates to the technical field of equipment identification, in particular to an identification circuit, implantable equipment and an identification system.
Background
Implantable devices, i.e., implantable medical devices, include implantable neurostimulation systems, implantable cardiac electrical stimulation systems (i.e., cardiac pacemakers), implantable drug infusion systems, and the like. In the above systems, the corresponding stimulator is implanted in the patient to achieve treatment of the patient site.
For high-risk medical instruments such as implantable medical instruments, in order to ensure safe and effective use of the medical instruments, health and life safety of patients are guaranteed, and history of the medical instruments can be traced back in time when adverse events occur to the medical instruments, unique serial codes are required to be assigned to each implantable medical instrument so as to trace the implantable medical instruments. However, if the unique sequence code is in a public or easily available state, the disclosure of the unique sequence code is easy to cause, and the use risk of the implantable medical device is increased, so how to increase the confidentiality of the unique sequence code of the implantable medical device is a problem to be solved at present.
Disclosure of Invention
In order to improve confidentiality of unique serial codes of implantable devices, the application provides an identification circuit, implantable devices and an identification system.
In a first aspect of the present application, an identification circuit is provided. The identification circuit comprises a driving module, a switching module and a plurality of groups of identity information generating circuits;
each group of identity information generating circuits is used for outputting a level signal according to an external signal;
the driving module is respectively connected with the plurality of groups of identity information generating circuits and is used for transmitting the level signals output by each group of identity information generating circuits to the switching module;
the switching module is connected with the driving module, and the switching module obtains the identity information according to the level signal output by each group of identity information generating circuits.
According to the technical scheme, the identity information is generated by using the multiple groups of identity information generating circuits, the combination of different level signals is realized by different combinations of the multiple groups of identity information generating circuits, the confidentiality of the unique serial code of the implanted device is guaranteed to a certain extent, and then the output of the identity information is realized by using the combination of the driving module and the switching module, and compared with the unique serial code which is directly readable, the confidentiality of the unique serial code of the implanted device is further improved.
In one possible implementation manner, the external signal is a radio frequency signal, the identity information generating circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a zener voltage regulator D1 and a comparator, the first resistor R1 and the second resistor R2 are connected in series, the third resistor R3 and the zener voltage regulator D1 are connected in series, the other end of the third resistor R3 is connected with the first resistor R1, the other end of the zener voltage regulator D1 is connected with the other end of the second resistor, the common end of the first resistor R1 and the third resistor is connected with a power supply end, and the common end of the second resistor R2 and the zener voltage regulator D1 is grounded;
the common end of the first resistor R1 and the second resistor R2 is connected with the inverting input end of the comparator, and the common end of the third resistor R3 and the zener voltage stabilizing tube D1 is connected with the non-inverting input end of the comparator; the output of the comparator outputs a level signal.
According to the technical scheme, the conducting state of the zener voltage stabilizing tube is affected under the condition that an external signal changes, the relative magnitudes of the potentials of the two input ends of the comparator can be changed due to the fact that the conducting state of the zener voltage stabilizing tube is different, and then output of a high-level signal and a low-level signal is achieved, namely output of each bit in the unique serial code of the implantable device is achieved.
In one possible implementation manner, the external signal is a radio frequency signal, the identity information generating circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a zener voltage regulator D1 and a comparator, the first resistor R1 and the second resistor R2 are connected in series, the third resistor R3 and the zener voltage regulator D1 are connected in series, the other end of the third resistor R3 is connected with the first resistor R1, the other end of the zener voltage regulator D1 is connected with the other end of the second resistor, the common end of the first resistor R1 and the third resistor is connected with a power supply end, and the common end of the second resistor R2 and the zener voltage regulator D1 is grounded;
the common end of the first resistor R1 and the second resistor R2 is connected with the non-inverting input end of the comparator, and the common end of the third resistor R3 and the zener voltage stabilizing tube D1 is connected with the inverting input end of the comparator; the output of the comparator outputs a level signal.
According to the technical scheme, the conducting state of the zener voltage stabilizing tube is affected under the condition that an external signal changes, the relative magnitudes of the potentials of the two input ends of the comparator can be changed due to the fact that the conducting state of the zener voltage stabilizing tube is different, and then output of a high-level signal and a low-level signal is achieved, namely output of each bit in the unique serial code of the implantable device is achieved.
In one possible implementation, the output voltage of the power supply terminal varies according to the difference in received radio frequency power.
According to the technical scheme, the change of the level signal output by the identity information generating circuit is caused by the change of the output voltage of the power supply end, so that the difference of the level signal output by the identity information generating circuit in different scenes is realized, and the confidentiality of the unique sequence code of the implantable device is further improved.
In a possible implementation manner, the external signal is a radio frequency signal, the identity information generating circuit comprises a first resistor R1, a second resistor R2, a third resistor R3 and a comparator, the first resistor R1 and the second resistor R2 are connected in series and then connected in parallel with the third resistor R3, a common end of the first resistor R1 and the third resistor is connected with a power supply end, and a common end of the second resistor R2 and the third resistor is grounded;
the common end of the first resistor R1 and the second resistor R2 is connected with the input end of the comparator, and the common end of the third resistor R3 and the second resistor R2 is connected with the other input end of the comparator; the output of the comparator outputs a level signal.
According to the technical scheme, through setting the fixed resistor, under the condition that an external signal changes, the relative sizes of the potentials of the two input ends of the comparator are fixed, the comparator can only realize fixed output, and the confidentiality of the identity information of the implantable device can be improved by adding the output of the fixed level signal as the verification bit in the identity information.
In one possible implementation, the driving module is a cyclic shifter.
In a second aspect of the present application, an implantable device is provided. The apparatus comprises an identification circuit as in the first aspect of the present application.
In a third aspect of the present application, an identification system is provided. The system comprises a reading device for generating a radio frequency field and an implantable device as according to the second aspect of the present application;
the implantable device is used for outputting identity information according to the radio frequency field;
and the reading device is used for reading the identity information.
According to the technical scheme, the implantable device is activated through the radio frequency field generated by the reading device, the implantable device can output identity information, the reading device receives the identity information output by the implantable device, and the identity information between the implantable device and the reading device is read.
In one possible implementation manner, the reading device comprises a radio frequency signal generating module, a directional coupling module and a detection demodulation module, wherein the detection demodulation module and the radio frequency signal generating module are connected with the directional coupling module;
the radio frequency signal generation module is used for generating a radio frequency field;
the directional coupling module is used for reading the identity information output by the implantable device;
and the detection demodulation module is used for carrying out detection demodulation on the identity information to obtain target identity information.
In one possible implementation manner, the reading device further includes a radio frequency power amplification module and a demodulation display module, the radio frequency power amplification module is connected with the radio frequency signal generation module, the radio frequency power amplification module is used for enhancing output power of the radio frequency field, the demodulation display module is connected with the demodulation detection and demodulation module, and the demodulation display module is used for displaying the identity information of the target.
In summary, the present application includes at least one of the following beneficial technical effects:
the method has the advantages that the generation of the identity information is realized by using a plurality of groups of identity information generation circuits, the combination of different level signals is realized by different combinations of the plurality of groups of identity information generation circuits, the confidentiality of the unique serial code of the implantable device is ensured to a certain extent, and then the output of the identity information is realized by using the combination of the driving module and the switching module, so that the confidentiality of the unique serial code of the implantable device is further improved compared with the direct readable unique serial code.
Drawings
Fig. 1 is a schematic structural diagram of an identification system according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of an identification circuit according to an embodiment of the present application.
Fig. 3 is a schematic circuit diagram of an identity information generating circuit according to an embodiment of the present application.
Fig. 4 is a schematic circuit diagram of an identity information generating circuit according to an embodiment of the present application.
Fig. 5 is a schematic circuit diagram of an identity information generating circuit according to an embodiment of the present application.
Fig. 6 is a schematic circuit diagram of an identity information generating circuit according to an embodiment of the present application.
Fig. 7 is a schematic diagram of a connection structure of an identity information generating circuit according to an embodiment of the present application.
Fig. 8 is a schematic diagram of a connection structure of an identity information generating circuit according to an embodiment of the present application.
In the figure, 1, an identification system; 2. a reading device; 21. a radio frequency signal generation module; 22. a directional coupling module; 23. a demodulation module; 24. a radio frequency power amplification module; 25. a demodulation display module; 3. an implantable device; 31. a switching module; 32. a driving module; 33. an identity information generating circuit.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In addition, the term "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, unless otherwise specified, the term "/" generally indicates that the associated object is an "or" relationship.
At present, in the field of nerve treatment, a spinal cord nerve stimulation system is used for treating a patient, the spinal cord nerve stimulation system comprises a nerve stimulator and an external energy controller, the nerve stimulator is implanted into the patient, the external energy controller and the nerve stimulator adopt wireless communication, and a user adjusts the stimulation parameters of the external energy controller and sends the stimulation parameters to the nerve stimulator through the wireless communication so as to control the working state of the nerve stimulator. Therefore, it has been a common treatment modality to achieve treatment of patients with the implantable device 3.
Because of the particularities of the implantable device 3, it is necessary to implant inside the body of the patient, the use of the implantable device 3 is risky. In order to improve the use safety of the implantable device 3, it is necessary to trace back the history of the implantable device 3 in time when an adverse event occurs in the implantable device 3, so that each implantable device 3 needs to be given a unique sequence code in order to trace back the source of the implantable device 3. The method of obtaining the unique serial code of the implantable device 3 directly affects the security of the implantable device 3, so how to ensure the confidentiality of the unique serial code of the implantable device 3 is a problem to be solved at present.
At present, an X-ray developing method is generally used for reading, X-rays are used for realizing the reading of the implantable device 3, on one hand, the X-ray reading device 2 is not easy to carry, on the other hand, the X-rays can also radiate the human body, and the long-term use is not beneficial to the health of users. The embodiment of the application provides an identification system 1, which adopts a radio frequency technology to realize the identification of an implantable device 3. Because electromagnetic waves have volatility, reflection and refraction can occur at a medium interface, the identification of the implantable device 3 is realized according to the reflectivity of the electromagnetic waves of the implantable device 3 in different frequency bands by utilizing the volatility of the electromagnetic waves.
Embodiments of the present application are described in further detail below with reference to the drawings attached hereto.
Referring to fig. 1, an embodiment of the present application provides an identification system 1, a reading device 2 and an implantable device 3, the reading device 2 being adapted to generate a radio frequency field; the implantable device 3 is configured to output identity information according to a radio frequency field generated by the reading device 2; the reading device 2 is configured to read the identity information output by the implantable device 3.
Specifically, the reading device 2 includes a radio frequency signal generating module 21, a directional coupling module 22, and a detection demodulation module 23, where the detection demodulation module 23 and the radio frequency signal generating module 21 are connected to the directional coupling module 22; the rf signal generating module 21 is configured to generate the rf field; the directional coupling module 22 is configured to read identity information output by the implantable device 3; the demodulation module 23 is configured to perform demodulation on the identity information to obtain target identity information.
Further, the reading device 2 further includes a radio frequency power amplifying module 24 and a demodulation display module 25, where the radio frequency power amplifying module 24 is connected to the radio frequency signal generating module 21, the radio frequency power amplifying module 24 is used for enhancing the output power of the radio frequency field, the demodulation display module 25 is connected to the demodulation module 23, and the demodulation display module 25 is used for displaying the target identity information.
When the implantable device 3 enters the rf field of the specific frequency band sent by the reading device 2, the implantable device 3 is activated, the identification system 1 is powered on, after a specific interval, the implantable device 3 sends out a reflected signal, and the reading device 2 detects and demodulates the reflected signal sent by the implantable device to obtain a cyclic sequence, for example: 10010011 10010011 10010011 …, a unique sequence code representing the identity information of the implanted device 3.
Meanwhile, the antenna of the implanted device 3 and the circuit thereof have the band-pass frequency selecting function, so that the implanted device 3 only responds to the radio frequency field of a specific frequency band, and can prevent random reading to a certain extent.
The implantable device 3 in the above-mentioned identification system 1 includes an identification circuit, referring to fig. 2, the embodiment of the present application provides an identification circuit, including a driving module 32, a switching module 31, and a plurality of sets of identity information generating circuits 33, where each set of identity information generating circuits 33 is configured to output a level signal according to an external signal; the driving module 32 is respectively connected with the multiple groups of identity information generating circuits 33, and the driving module 32 is used for transmitting the level signal output by each group of identity information generating circuits 33 to the switching module 31; the switching module 31 is connected to the driving module 32, and the switching module 31 obtains identity information according to the level signal output from each group of the identity information generating circuits 33. The external signal is a radio frequency signal. In a specific example, the driving module 32 is a cyclic shifter.
In a specific embodiment, the switching module 31 is a radio frequency switch, and the state of the antenna is switched by the radio frequency switch, where the state of the antenna includes a mismatch state and a matching state, and when the state of the antenna is the mismatch state, the reflection of the antenna is large, and when the state of the antenna is the matching state, the reflection of the antenna is small. When the antenna reflection is large, the signal read by the external device through directional coupling is strong, corresponding to logic 1, and when the antenna reflection is small, the signal read by the external device through directional coupling is weak, corresponding to logic 0.
It will be appreciated that when the level signal is output by the identity information output circuit, the level signal is recorded in the driving module 32, the driving module 32 receives a pulse every time a period of time, then the recorded signal is circularly shifted, and one level signal is shifted to the switching module 31 each time, for example, when the switching module 31 receives a high level signal or logic 1, the antenna state is switched to a mismatch state, when the switching module 31 receives a low level signal or logic 0, the antenna state is switched to a matching state, and the output of the identity information is completed.
Referring to fig. 3, in a first specific example, the identity information generating circuit 33 includes a first resistor R1, a second resistor R2, a third resistor R3, a zener diode D1, and a comparator N1, the first resistor R1 and the second resistor R2 are connected in series, the third resistor R3 and the zener diode D1 are connected in series, the other end of the third resistor R3 is connected to the first resistor R1, the other end of the zener diode D1 is connected to the other end of the second resistor, a common terminal of the first resistor R1 and the third resistor is connected to a power supply terminal, and a common terminal of the second resistor R2 and the zener diode D1 is grounded; the common terminal of the first resistor R1 and the second resistor R2 is connected to the inverting input terminal of the comparator N1, and the common terminal of the third resistor R3 and the zener diode D1 is connected to the non-inverting input terminal of the comparator N1; the output terminal of the comparator N1 outputs the level signal.
The level signal output by the group of identity information generating circuits 33 is a bit unit, wherein the VCC power supply terminal is the output from the rectifying circuit which is not stabilized by the voltage source, and the size of the power supply terminal changes along with the change of the received radio frequency power. VDD is a regulated power supply output, and is a logic circuit power supply with a fixed size. The comparator outputs BITn as VDD or 0, and VDD as logic 1 and 0 as logic 0.
When the output voltage of VCC is smaller, the zener diode D1 is not conducted, the potential of the non-inverting input end of the comparator N1 is higher than that of the inverting input end, and the output level signal BITn is in a high level, namely logic 1; when the output voltage of VCC increases to a certain threshold, the zener diode D1 is turned on, clamps and fixes the potential, the potential of the non-inverting input terminal of the comparator N1 will be lower than the potential of the inverting input terminal, and the output level signal BITn is at a low level, i.e. logic 0.
Each set of the identity information generating circuits 33 may output 0 or 1, and when a plurality of sets of the identity information generating circuits 33 are used, unique serial codes, that is, identity information, may be output. In a first specific example, the identity information composing circuit outputs a logic 1 when the output voltage of VCC is small; when the output voltage of VCC is high, a logic 0 is output. In other embodiments, it may be implemented to output a logic 0 when the output voltage of VCC is small; when the output voltage of VCC is high, a logic 1 is output.
Referring to fig. 4, in a second specific example, the identity information generating circuit 33 includes a first resistor R1, a second resistor R2, a third resistor R3, a zener diode D1, and a comparator N1, the first resistor R1 and the second resistor R2 are connected in series, the third resistor R3 and the zener diode D1 are connected in series, the other end of the third resistor R3 is connected to the first resistor R1, the other end of the zener diode D1 is connected to the other end of the second resistor, a common terminal of the first resistor R1 and the third resistor is connected to a power supply terminal, and a common terminal of the second resistor R2 and the zener diode D1 is grounded; the common terminal of the first resistor R1 and the second resistor R2 is connected to the non-inverting input terminal of the comparator N1, and the common terminal of the third resistor R3 and the zener diode D1 is connected to the inverting input terminal of the comparator N1; the output terminal of the comparator N1 outputs the level signal.
When the output voltage of VCC is smaller, the zener diode D1 is not conducted, the potential of the non-inverting input end of the comparator N1 is lower than that of the inverting input end, and the output level signal BITn is low level, namely logic 0; when the output voltage of VCC increases to a certain threshold, zener diode D1 is turned on, and clamps and fixes the potential, the potential of the non-inverting input terminal of comparator N1 will be higher than the potential of the inverting input terminal, and the output level signal BITn is at a high level, i.e. logic 1.
In order to improve confidentiality of the identity information, when a plurality of sets of the identity information generating circuits 33 are used, the identity information generating circuits 33 which are not affected by external signals may be added thereto.
Referring to fig. 5, in a third specific example, the identity information generating circuit 33 includes a first resistor R1, a second resistor R2, a third resistor R3, and a comparator N1, wherein the first resistor R1 and the second resistor R2 are connected in series and then connected in parallel to the third resistor R3, a common terminal of the first resistor R1 and the third resistor is connected to a power supply terminal, and a common terminal of the second resistor R2 and the third resistor is grounded; the common terminal of the first resistor R1 and the second resistor R2 is connected to the inverting input terminal of the comparator N1, and the common terminal of the third resistor R3 and the second resistor R2 is connected to the non-inverting input terminal of the comparator N1; the output terminal of the comparator N1 outputs the level signal.
It will be appreciated that the potential at the non-inverting input of the comparator N1 must be higher than the potential at the inverting input, regardless of the change in VCC, so the level signal output by the comparator N1 is a high level signal. Referring to fig. 6, when the common terminal of the first resistor R1 and the second resistor R2 is connected to the non-inverting input terminal of the comparator N1 and the common terminal of the third resistor R3 and the second resistor R2 is connected to the inverting input terminal of the comparator N1, the potential of the non-inverting input terminal of the comparator N1 is necessarily lower than the potential of the inverting input terminal, so that the level signal output by the comparator N1 is a low level signal.
Referring to fig. 7, in a specific example, three sets of identity information generating circuits 33 are used to obtain a unique sequence code [ BIT0, BIT1, BIT2], and when the output voltage of VCC is low, the obtained unique sequence code is 001; when the output voltage of VCC is high, the unique sequence code is obtained as 110. The unique sequence code obtained when the output voltage of VCC is high may be used as the identity information for determining the implanted device 3. If the sequence code is obtained when the output voltage of VCC is low, the obtained sequence code may be subjected to a negation operation to obtain the identity information of the implantable device 3. For example, when the output voltage of VCC is low, a sequence code 1010 is obtained, and then the sequence code is inverted to obtain 0101, and then the unique sequence code of the implantable device 3 is 0101.
It can be understood that the sequence codes of the two conditions of higher VCC output voltage and lower VCC output voltage can be obtained at the same time, and it is determined whether the sequence codes in the two conditions are the opposite codes, if so, the obtained sequence code is correct, and if not, the obtained sequence code is problematic and needs to be obtained again.
Referring to fig. 8, in a specific example, three sets of identity information generating circuits 33 are used to obtain a unique sequence code [ BIT0, BIT1, BIT2], where the identity information generating circuit 33 corresponding to BIT1 does not include a zener diode, so BIT1 is a constant value, i.e., BIT 1=0. BIT0 and BIT2 will change according to the change of the VCC output voltage, when the VCC output voltage is low, the unique sequence code obtained is 001; when the output voltage of VCC is high, the unique sequence code obtained is 100.
Since BIT1 is a constant value, BIT1 may be used as a check BIT, indicating that the read sequence code is correct when BIT1 is 0, and indicating that the read sequence code is incorrect when BIT1 is 1. When there are check bits in the sequence code, the check bits should be removed to obtain the unique sequence code of the implantable device 3, the unique sequence code obtained when the output voltage of VCC is high is 10, and the unique sequence code obtained when the output voltage of VCC is low is 01.
In other embodiments, there may be multiple check bits of the implantable device 3 and multiple sets of identity information generating circuits 33 may be randomly combined.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
In addition, the functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The foregoing description is only of the preferred embodiments of the present application and is presented as a description of the principles of the technology being utilized. It will be appreciated by persons skilled in the art that the scope of the application referred to in this application is not limited to the specific combinations of features described above, but it is intended to cover other embodiments in which any combination of features described above or their equivalents is possible without departing from the spirit of the application. Such as the above-mentioned features and the technical features having similar functions (but not limited to) applied for in this application are replaced with each other.
Claims (10)
1. An identification circuit is characterized by comprising a driving module (32), a switching module (31) and a plurality of groups of identity information generating circuits (33);
each group of the identity information generating circuits (33) is used for outputting a level signal according to an external signal;
the driving module (32) is respectively connected with the plurality of groups of identity information generating circuits (33), and the driving module (32) is used for transmitting the level signal output by each group of identity information generating circuits (33) to the switching module (31);
the switching module (31) is connected with the driving module (32), and the switching module (31) obtains identity information according to the level signals output by each group of identity information generating circuits (33).
2. The identification circuit according to claim 1, wherein the external signal is a radio frequency signal, the identity information generating circuit (33) includes a first resistor R1, a second resistor R2, a third resistor R3, a zener diode D1, and a comparator, the first resistor R1 and the second resistor R2 are connected in series, the third resistor R3 and the zener diode D1 are connected in series, the other end of the third resistor R3 is connected to the first resistor R1, the other end of the zener diode D1 is connected to the other end of the second resistor, a common terminal of the first resistor R1 and the third resistor is connected to a power supply terminal, and a common terminal of the second resistor R2 and the zener diode D1 is grounded;
the common end of the first resistor R1 and the second resistor R2 is connected with the inverting input end of the comparator, and the common end of the third resistor R3 and the zener voltage stabilizing tube D1 is connected with the non-inverting input end of the comparator; the output end of the comparator outputs the level signal.
3. The identification circuit according to claim 1, wherein the external signal is a radio frequency signal, the identity information generating circuit (33) includes a first resistor R1, a second resistor R2, a third resistor R3, a zener diode D1, and a comparator, the first resistor R1 and the second resistor R2 are connected in series, the third resistor R3 and the zener diode D1 are connected in series, the other end of the third resistor R3 is connected to the first resistor R1, the other end of the zener diode D1 is connected to the other end of the second resistor, a common terminal of the first resistor R1 and the third resistor is connected to a power supply terminal, and a common terminal of the second resistor R2 and the zener diode D1 is grounded;
the common end of the first resistor R1 and the second resistor R2 is connected with the non-inverting input end of the comparator, and the common end of the third resistor R3 and the zener voltage stabilizing tube D1 is connected with the inverting input end of the comparator; the output end of the comparator outputs the level signal.
4. A recognition circuit according to claim 2 or 3, wherein the output voltage of the supply terminal varies according to the received radio frequency power.
5. The identification circuit according to claim 1, wherein the external signal is a radio frequency signal, the identity information generating circuit (33) comprises a first resistor R1, a second resistor R2, a third resistor R3 and a comparator, the first resistor R1 and the second resistor R2 are connected in series and then connected in parallel with the third resistor R3, a common terminal of the first resistor R1 and the third resistor is connected with a power supply terminal, and a common terminal of the second resistor R2 and the third resistor is grounded;
the common end of the first resistor R1 and the second resistor R2 is connected with the input end of the comparator, and the common end of the third resistor R3 and the second resistor R2 is connected with the other input end of the comparator; the output end of the comparator outputs the level signal.
6. The identification circuit according to any of the claims 1-5, characterized in that the driving module (32) is a cyclic shifter.
7. An implantable device (3) comprising an identification circuit as claimed in any one of claims 1-6.
8. An identification system (1), characterized by comprising: a reading device (2) and an implantable device (3) as claimed in claim 1, the reading device (2) being adapted to generate a radio frequency field;
the implantable device (3) is used for outputting identity information according to the radio frequency field;
the reading device (2) is used for reading the identity information.
9. The identification system (1) according to claim 8, wherein the reading device (2) comprises a radio frequency signal generation module (21), a directional coupling module (22) and a detection demodulation module (23), the detection demodulation module (23) and the radio frequency signal generation module (21) being both connected to the directional coupling module (22);
-said radio frequency signal generating module (21) for generating said radio frequency field;
the directional coupling module (22) is used for reading identity information output by the implantable device (3);
and the detection demodulation module (23) is used for carrying out detection demodulation on the identity information to obtain target identity information.
10. The identification system (1) according to claim 9, wherein the reading device (2) further comprises a radio frequency power amplification module (24) and a demodulation display module (25), the radio frequency power amplification module (24) being connected to the radio frequency signal generation module (21), the radio frequency power amplification module (24) being configured to enhance the output power of the radio frequency field, the demodulation display module (25) being connected to the detection demodulation module (23), the demodulation display module (25) being configured to display the target identity information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311695541.6A CN117668929A (en) | 2023-12-11 | 2023-12-11 | Identification circuit, implantable device and identification system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311695541.6A CN117668929A (en) | 2023-12-11 | 2023-12-11 | Identification circuit, implantable device and identification system |
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| Publication Number | Publication Date |
|---|---|
| CN117668929A true CN117668929A (en) | 2024-03-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311695541.6A Pending CN117668929A (en) | 2023-12-11 | 2023-12-11 | Identification circuit, implantable device and identification system |
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| Country | Link |
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| CN (1) | CN117668929A (en) |
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2023
- 2023-12-11 CN CN202311695541.6A patent/CN117668929A/en active Pending
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