CN117667828B

CN117667828B - Network-on-chip integration method, device and storage medium

Info

Publication number: CN117667828B
Application number: CN202410135854.4A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2024-01-31
Filing date: 2024-01-31
Publication date: 2024-05-03
Anticipated expiration: 2044-01-31
Also published as: CN117667828A

Abstract

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a network on chip integration method, apparatus, and storage medium. The method comprises the following steps: acquiring a configuration file, wherein the configuration file comprises configuration information of a network on chip to be integrated in a system on chip, and the network on chip to be integrated comprises a plurality of networks on sub-chips to be integrated; based on the configuration file, determining a first connection relation between the networks on the sub-chips to be integrated and a second connection relation between the networks on the sub-chips to be integrated and target elements in the system on chip, wherein the first connection relation is used for binding the networks on the sub-chips to be integrated, and the second connection relation is used for binding the networks on the sub-chips to be integrated and the target elements in the system on chip, and based on the binding, the integration of the networks on chip is realized. According to the embodiment of the application, the workload in the network-on-chip integration process can be greatly reduced, the integration efficiency is improved, and the integration process is flexible, concise and easy to implement.

Description

Network-on-chip integration method, device and storage medium

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a network on chip integration method, apparatus, and storage medium.

Background

Network On Chip (NoC) is mainly responsible for information interaction between different components in the system, and thus NoC is an essential part of modern multi-core processor chips. For complex chip systems, the element instances to which nocs are connected are too large, and if a complete NoC topology is used, including all the element instances can cause the back-end engineer to be overly cumbersome to place and route. At this time, a complete NoC is often divided into a plurality of sub-nocs, so that a back-end engineer can independently perform layout and wiring on each sub-NoC, and the working efficiency of the back-end is improved.

The scheme of dividing a complete NoC into multiple sub-nocs for place and route may improve the efficiency of complex system backend engineers, but would be a challenge for system integration engineers. Because each sub-NoC has its own independent input and output ports, in the current solution, system integration engineers need to manually integrate each port of each sub-NoC in a one-to-one and binding manner. This would be a very time consuming iterative process, considering that nocs are likely to undergo large topology adjustments throughout the chip development cycle, with each adjustment requiring re-integration of nocs and underlying sub-nocs. Therefore, a new network-on-chip integration method is needed to improve the efficiency of NoC integration process, so that the integration process is flexible, simple, highly versatile and easy to implement.

Disclosure of Invention

In view of this, the present disclosure proposes a network-on-chip integration method, apparatus, and storage medium.

According to an aspect of the present disclosure, a network-on-chip integration method is provided. The method comprises the following steps:

Acquiring a configuration file, wherein the configuration file comprises configuration information of a network on chip to be integrated in a system on chip, the network on chip to be integrated comprises a plurality of networks on sub-chips to be integrated, and the configuration information comprises an output transmission path of each output port and/or an input transmission path of each input port on the network on sub-chips to be integrated;

based on the configuration file, determining a first connection relation between the networks on the sub-chips to be integrated and a second connection relation between the networks on the sub-chips to be integrated and target elements in the system on chip, wherein the first connection relation is used for binding the networks on the sub-chips to be integrated, and the second connection relation is used for binding the networks on the sub-chips to be integrated and the target elements in the system on chip, and based on the binding, the integration of the networks on chip is realized.

In one possible implementation, the target elements include a master element in the system-on-chip and a slave element in the system-on-chip, the output transmission path of each output port on the network-on-chip to be integrated terminating at one input port on the other network-on-chip to be integrated or at one slave element in the system-on-chip, wherein the slave element is to receive data from the output transmission path, the input transmission path of each input port on the network-on-chip to be integrated starting from one output port on the other network-on-chip to be integrated or one master element in the system-on-chip, wherein the master element is to provide data to the input transmission path.

In one possible implementation, the configuration file includes a configuration file of the network on chip to be integrated, each row in the configuration file of the network on chip to be integrated indicates one input transmission path or one output transmission path, and based on the configuration file, determining a first connection relationship between the networks on chip to be integrated and a second connection relationship between the network on chip to be integrated and a target element in the system on chip to be integrated, including:

Reading a row from a configuration file of a network on chip to be integrated;

analyzing the row, and judging whether the row meets a first constraint condition, wherein the first constraint condition comprises that an input port or an output port described in the row does not repeatedly appear in a configuration file of a network on chip to be integrated;

And under the condition that each row in the configuration file of the network on chip to be integrated meets the first constraint condition, determining a first connection relation between the networks on chip to be integrated and a second connection relation between the networks on chip to be integrated and target elements in the system on chip according to the input transmission path or the output transmission path indicated by each row in the configuration file of the network on chip to be integrated.

In one possible implementation manner, determining, based on the configuration file, a first connection relationship between the networks on the sub-chips to be integrated and a second connection relationship between the networks on the sub-chips to be integrated and a target element in the system on chip, includes:

determining a first connection relation according to output transmission paths of input ports ending on other sub-chip networks to be integrated in the configuration file of the network to be integrated and input transmission paths of output ports starting on other sub-chip networks to be integrated;

And determining a second connection relation according to an output transmission path of a slave element ending in the system-on-chip and an input transmission path of a master element starting in the system-on-chip in the configuration file of the network-on-chip to be integrated.

In one possible implementation, the input port or the output port is indicated in the configuration file of the network on chip to be integrated by a first identification, the first identification being associated with an order in which the master element or the slave element appears in the system on chip in the configuration file of the network on chip to be integrated.

In one possible implementation, the configuration file includes a configuration file of each network on a sub-chip to be integrated, and ports of the network on a sub-chip to be integrated on the same output transmission path or the same input transmission path in the configuration file of each network on a sub-chip to be integrated have the same keyword number.

analyzing the configuration files of the networks on the sub-chips to be integrated, and judging whether the configuration files of the networks on the sub-chips to be integrated meet a second constraint condition;

determining a global table based on the output transmission path/input transmission path with the keyword number under the condition that the configuration file of the network on chip to be integrated meets the second constraint condition;

Based on the global table, a first connection relation between the networks on the sub-chips to be integrated and a second connection relation between the networks on the sub-chips to be integrated and target elements in the system on chip are determined.

In one possible implementation manner, the global table includes a key number of a port, a second identifier indicating that the port is an input port or an output port, an output/input object corresponding to the port, and determining, based on the global table, a first connection relationship between each network on a sub-chip to be integrated, and a second connection relationship between the network on a sub-chip to be integrated and a target element in the system on a chip, including:

Binding an input port and an output port with the same keyword number, and determining a first connection relation;

and binding the port and the slave element/master element under the condition that the output/input object corresponding to the port is the slave element or the master element in the system on chip, and determining a second connection relation.

In one possible implementation, the second constraint includes:

The keyword numbers described in the configuration file of each sub-network-on-chip to be integrated do not appear repeatedly in the configuration file;

The target elements in the system on chip described in the configuration files of the sub-networks to be integrated do not repeatedly appear in the configuration files of all the sub-networks to be integrated; and the keyword numbers described in the configuration files of the networks on the sub-chips to be integrated appear twice in the configuration files of the networks on the sub-chips to be integrated.

In one possible implementation manner, the ports include floating ports that do not need to be bound to other ports, the target element further includes virtual elements corresponding to the floating ports one to one, and determining, based on the configuration file, a first connection relationship between each of the networks on the sub-chip to be integrated, and a second connection relationship between the network on the sub-chip to be integrated and the target element in the system on the chip, including:

analyzing the configuration file, and determining the number of virtual elements corresponding to the suspension ports, wherein the virtual elements comprise virtual master elements and virtual slave elements;

the virtual master element and the virtual slave element are instantiated to determine a second connection relationship.

In one possible implementation, the ports on the network on the sub-chip to be integrated are in one-to-one correspondence with the ports of the elements instantiated on the network on the sub-chip to be integrated.

In a possible implementation manner, the configuration information of the network on chip to be integrated includes information of elements in each sub-network on chip to be integrated, and the method further includes:

And determining the connection relation among the elements in the sub-chip network to be integrated according to the information of the elements in the sub-chip network to be integrated aiming at each sub-chip network to be integrated so as to carry out interface binding among the elements in the sub-chip network to be integrated.

In one possible implementation, the master element in the system on chip includes at least one of a graphics processor GPU, a neural network processor NPU, and a virtual master element, and the slave element in the system on chip includes at least one of a double rate synchronous dynamic random memory DDR, a cache memory, and a virtual slave element.

According to another aspect of the present disclosure, a network-on-chip integrated device is provided. The device comprises:

The system comprises an acquisition module, a configuration module and a control module, wherein the acquisition module is used for acquiring a configuration file, the configuration file comprises configuration information of a network on chip to be integrated in a system on chip, the network on chip to be integrated comprises a plurality of networks on a sub-chip to be integrated, and the configuration information comprises an output transmission path of each output port and/or an input transmission path of each input port on the network on the sub-chip to be integrated;

the first determining module is used for determining a first connection relation between the networks on the sub-chips to be integrated based on the configuration file and a second connection relation between the networks on the sub-chips to be integrated and target elements in the system on the chip, wherein the first connection relation is used for binding the networks on the sub-chips to be integrated, and the second connection relation is used for binding the networks on the sub-chips to be integrated and the target elements in the system on the chip, and the integration of the networks on the chip is realized based on the binding.

In one possible implementation, the configuration file includes a configuration file to be integrated into the network on chip, each row in the configuration file to be integrated into the network on chip indicates one input transmission path or one output transmission path, and the first determining module is configured to:

Reading a row from a configuration file of a network on chip to be integrated;

In one possible implementation manner, the first determining module is configured to:

In one possible implementation, the second constraint includes:

In one possible implementation manner, the ports include suspended ports that do not need to be bound to other ports, the target element further includes virtual elements corresponding to the suspended ports one to one, and the first determining module is configured to:

In a possible implementation manner, the configuration information of the network on chip to be integrated includes information of elements in each sub-network on chip to be integrated, and the apparatus further includes:

The second determining module is used for determining connection relations among the elements in the network on the sub-chip to be integrated according to the information of the elements in the network on the sub-chip to be integrated aiming at each network on the sub-chip to be integrated so as to perform interface binding among the elements in the network on the sub-chip to be integrated.

According to another aspect of the present disclosure, there is provided a network-on-chip integrated apparatus including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing the instructions stored by the memory.

According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement the above-described method.

According to another aspect of the present disclosure, there is provided a computer program product comprising a computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.

According to the embodiment of the application, the network on chip can be integrated by acquiring the configuration file comprising the configuration information of the network on chip to be integrated. According to the embodiment of the application, the first connection relation between each network on a chip to be integrated and the second connection relation between each network on a chip to be integrated and target elements in the system on a chip can be determined based on the configuration file, so that binding between each sub NoC (i.e. network on a chip to be integrated) can be automatically performed based on the first connection relation, binding between the sub NoC and the target elements in the system on a chip can be automatically performed based on the second connection relation, binding is performed in the form of the configuration file, network on a chip is integrated based on the binding, workload in the network on a chip integrating process can be greatly reduced, the integrating efficiency is improved, and the integration from single NoC topology integration to multi-level NoC integration is more flexible, simple and easy to implement.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of an application scenario according to an embodiment of the application.

Fig. 2 shows a flow chart of a network on chip integration method according to an embodiment of the application.

Fig. 3 shows a flow chart of a network on chip integration method according to an embodiment of the application.

Fig. 4 shows a schematic diagram of the topology of a network on chip to be integrated according to an embodiment of the application.

Fig. 5 shows a flow chart of a network on chip integration method according to an embodiment of the application.

Fig. 6 shows a schematic diagram of the topology of a network on chip to be integrated according to an embodiment of the application.

Fig. 7 illustrates a block diagram of a network-on-chip integrated device according to an embodiment of the present application.

Fig. 8 is a block diagram illustrating an apparatus 1900 for integrating a network on chip, according to an example embodiment.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

Nocs are mainly responsible for information interaction between the different components in the system, and are therefore an essential part of modern multi-core processor chips. For complex chip systems, the element instances to which nocs are connected are too large, and if a complete NoC topology is used, including all the element instances can cause the back-end engineer to be overly cumbersome to place and route. At this time, a complete NoC is often divided into a plurality of sub-nocs, so that a back-end engineer can independently perform layout and wiring on each sub-NoC, and the working efficiency of the back-end is improved. The scheme of dividing a complete NoC into multiple sub-nocs for place and route may improve the efficiency of complex system backend engineers, but would be a challenge for system integration engineers. Because each sub-NoC has its own independent input and output ports, in the current solution, system integration engineers need to manually integrate each port of each sub-NoC in a one-to-one and binding manner. This would be a very time consuming iterative process, considering that nocs are likely to undergo large topology adjustments throughout the chip development cycle, with each adjustment requiring re-integration of nocs and underlying sub-nocs. Therefore, a new network-on-chip integration method is needed to improve the efficiency of NoC integration process, so that the integration process is flexible, simple, highly versatile and easy to implement.

In view of the above, the present application proposes a network-on-chip integration method. The method of the embodiment of the application can be used for integrating the network on chip by acquiring the configuration file comprising the configuration information of the network on chip to be integrated. The method according to the embodiment of the application can determine the first connection relation between the networks on the sub-chip to be integrated and the second connection relation between the networks on the sub-chip to be integrated and the target elements in the system on the chip based on the configuration file, so that the binding between the sub-NoCs (i.e. the networks on the sub-chip to be integrated) can be automatically performed based on the first connection relation, the binding between the sub-NoCs and the target elements in the system on the chip can be automatically performed based on the second connection relation, the binding is performed in the form of the configuration file, the integration of the network on the chip is performed based on the binding, the workload in the integration process of the network on the chip can be greatly reduced, the integration efficiency is improved, and the scheme is more flexible, simple and easy to implement from a single NoC topology integration method to a multi-level NoC integration method.

Fig. 1 shows a schematic diagram of an application scenario according to an embodiment of the application. The method of the embodiment of the application can be applied to a scene of integrating nocs with a hierarchical structure of a plurality of sub-nocs, as shown in fig. 1, and a System On Chip (SoC) can include nocs to be integrated (which can be called top nocs, as top-nocs in the figure) and target elements. the top-NoC may be composed of a plurality of sub-nocs to be integrated (may be referred to as sub-nocs, such as sub-NoC 0-sub-NoC 3 in the figure). The target elements may include master elements (may be referred to as masters, such as GM0, NM0, virtual master element 1 in the figure) and slave elements (may be referred to as slave, such as S0, S1, virtual slave element 0, virtual slave element 1 in the figure).

Each sub-noc can be composed of independent element examples (input unit, output unit, switch, bit width converter and the like), in the integration stage, each sub-noc can be integrated internally, interface binding and integration are carried out on the element examples through a certain topological connection relation, after internal integration, a group of input ports and output ports can be displayed externally, in general, one input port can correspond to one input unit element, and one output port can correspond to one output unit element. In the process of integrating the top noc, all the sub nocs can be used as members of the top noc, the input ports and the output ports of the sub nocs in the top noc are connected according to a certain topology, binding is carried out, and finally a group of input ports and output ports of the whole top noc can be formed. The input port of the top noc (i.e., the input port of the sub noc) may be connected to a master element in the system-on-chip, and the output port of the top noc (i.e., the output port of the sub noc) may be connected to a slave element in the system-on-chip, for binding.

For each sub-noc, the identification ids of the input port and the output port of the sub-noc can be called sub-noc input id/sub noc output id; for top noc, the identification ids of the input port and the output port of the top noc may be called as top noc input id/top noc output id, so that the connection relationship between the sub noc input id/sub noc output id and the top noc input id/top noc output id, that is, the connection relationship between the sub noc and the target element in the system on chip (that is, the connection relationship between the top noc and the target element in the system on chip) needs to be clarified.

The method of the embodiment of the application can be applied to the process of integrating the top noc, and in the example shown in the figure, the method of the embodiment of the application can be utilized to firstly determine the connection relation between sub-noc 0-sub-noc 3 and then determine the connection relation between each sub-noc and target elements (GM 0, NM0, virtual master element 0, virtual master elements 1, S0, S1, virtual slave element 0 and virtual slave element 1) in the system on chip. The connection relation between sub-noc 0-sub-noc 3 can be represented by the corresponding relation between an input port and an output port on the sub-noc 0-sub-noc 3, and the connection relation between each sub-noc and a target element in the system on chip can be represented by the corresponding relation between the input port and the output port on the sub-noc 0-noc 3 and the target element in the system on chip.

The network-on-chip integration method of the embodiment of the application can be applied to terminal equipment or a server. The terminal device may be any one or more of a mobile phone, a foldable electronic device, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a Personal Digital Assistant (PDA), and a vehicle-mounted device. The embodiment of the application does not limit the specific type of the terminal equipment, and can have a wired or wireless communication function.

The server may be located at a local or cloud end, may be a physical device, may also be a virtual device, such as a virtual machine, a container, or the like, and has a wireless communication function, where the wireless communication function may be provided on a chip (system) or other parts or components of the server. The wireless communication function may be realized by mobile communication technologies such as 2G/3G/4G/5G, wi-Fi, bluetooth, frequency modulation (frequency modulation, FM), digital radio, satellite communication, and the like. Communication may also be via a wired connection to enable interaction with other devices.

The network-on-chip integration method according to the embodiment of the present application is described below with reference to fig. 2 to 6.

Fig. 2 shows a flow chart of a network on chip integration method according to an embodiment of the application. The method may be used for the terminal device or the server, as shown in fig. 2, and the method may include:

Step S201, a configuration file is acquired.

The configuration file may be pre-generated, for example, may be written by the user according to the desired network topology. Configuration information of a network on chip to be integrated in the system on chip may be included in the configuration file, an example of the network on chip to be integrated may be referred to as top-noc in fig. 1, the network on chip to be integrated may include a plurality of networks on sub chip to be integrated, and an example of the network on sub chip to be integrated may be referred to as sub-noc0 to sub-noc3 in fig. 1.

The configuration information includes an output transmission path for each output port and/or an input transmission path for each input port on the network on a sub-chip to be integrated.

The ports on the network on the sub-chip to be integrated, which appear in the configuration file, are guaranteed to be in one-to-one correspondence with the ports of the elements instantiated on the network on the sub-chip to be integrated. The element may be a network component of a node in the network topology of the sub-NoC to be integrated, which may be instantiated as a corresponding device used in the NoC, such as a display device, router, chip core, shifter, memory, etc. The element on the sub-NoC to be integrated has at least one input port and/or at least one output port, and the configuration information of the network on chip to be integrated may include information of each element in each sub-network on chip to be integrated, and for the process of internal integration of the sub-NoC to be integrated, the method may include:

After the integration is performed inside the sub-NoC to be integrated, the input ports and the output ports which are not connected on each element of the sub-NoC to be integrated can be used as a group of input ports and output ports which are presented externally, namely, the input ports and the output ports on the network on the sub-chip to be integrated in the embodiment of the application.

The target elements on the system-on-chip may include a master element in the system-on-chip and a slave element in the system-on-chip, and the output transmission path of each output port on the sub-network-on-chip to be integrated may terminate at one input port on the other sub-network-on-chip to be integrated or one slave element in the system-on-chip, and the input transmission path of each input port on the sub-network-on-chip to be integrated may start at one output port on the other sub-network-on-chip to be integrated or one master element in the system-on-chip.

Examples of master elements in a system-on-chip may be referred to as masters in fig. 1, for providing data to an input transmission path, e.g., master elements may include GPUs, NPUs, virtual master elements (described below); examples of slave elements in a system on chip may be seen in slave in fig. 1 for receiving data from an output transmission path, e.g. the slave elements may comprise DDR, cache, virtual slave elements (described below).

Alternatively, the ports of the network on chip to be integrated may include suspended ports that do not need to be bound to other ports. This is because in some scenarios (e.g. in the scenario of testing the network on chip to be integrated), the debug signal of some network on chip to be integrated is less concerned, i.e. the input/output signal of the input port and/or the output port on some network on chip to be integrated is less concerned, at this time, the input port and/or the output port may be suspended, i.e. the ports corresponding to these ports are not bound, but in general, unbound interfaces are not allowed to exist in the network on chip to be integrated, so that the virtual master element and the virtual slave element corresponding to these ports may be instantiated one by one, so that the target element in the system on chip further includes the virtual element corresponding to the suspended ports one by one. A virtual master element (may be referred to as a dummy master) may be used to bind with a dangling input port, and a virtual slave element (may be referred to as a dummy slave) may be used to bind with a dangling output port. Examples of virtual master elements may be seen in virtual master element 0 and virtual master element 1 in fig. 1, and examples of virtual slave elements may be seen in virtual slave element 0 and virtual slave element 1 in fig. 1.

By using the dummy master and dummy slave, the support for the suspended interface is increased, so that NoC integration and testing can be automatically performed in more scenes (such as test scenes of top NoC) by using a configuration file.

Step S202, based on the configuration file, determining a first connection relation between the networks on the sub-chips to be integrated and a second connection relation between the networks on the sub-chips to be integrated and target elements in the system on chip.

Binding can be performed between the networks on the sub-chips to be integrated by determining the first connection relation, and binding can be performed between the networks on the sub-chips to be integrated and target elements in the system on chip by determining the second connection relation.

The first connection relation between the networks on the sub-chips to be integrated can be determined through the output transmission paths ending at the input ports on the networks on the other sub-chips to be integrated in the configuration file and the input transmission paths starting at the output ports on the networks on the other sub-chips to be integrated; the second connection relationship between the network on chip to be integrated and the target element in the system on chip may be determined by an output transmission path in the configuration file ending in a slave element in the system on chip and an input transmission path starting in a master element in the system on chip.

According to the embodiment of the application, the network on chip can be integrated by acquiring the configuration file comprising the configuration information of the network on chip to be integrated. The method according to the embodiment of the application can determine the first connection relation between the networks on the sub-chip to be integrated and the second connection relation between the networks on the sub-chip to be integrated and the target elements in the system on the chip based on the configuration file, so that the binding between the sub-NoCs (i.e. the networks on the sub-chip to be integrated) can be automatically performed based on the first connection relation, the binding between the sub-NoCs and the target elements in the system on the chip can be automatically performed based on the second connection relation, the binding is performed in the form of the configuration file, the integration of the network on the chip is performed based on the binding, the workload in the integration process of the network on the chip can be greatly reduced, the integration efficiency is improved, and the scheme is more flexible, simple and easy to implement from a single NoC topology integration method to a multi-level NoC integration method.

The implementation of step S202 will be described in detail below.

In one example, a configuration file of the network on chip to be integrated may be given based on determining the configuration file of the network on chip to be integrated, so that the configuration file includes the configuration file of the network on chip to be integrated. Before that, internal integration may be performed with respect to the configuration file of each network on a sub-chip to be integrated, so as to determine the connection relationship between each element in each network on a sub-chip to be integrated (see the description above). Step S202 may then be implemented based on the configuration file to be integrated into the network on chip.

Referring to fig. 3, a flow chart of a network-on-chip integration method according to an embodiment of the application is shown. As shown in fig. 3, step S202 may include:

step S301, a row is read from a configuration file to be integrated into the network on chip.

Fig. 4 shows a schematic diagram of the topology of a network on chip to be integrated according to an embodiment of the application. As shown in fig. 4, the network on chip to be integrated top-noc may include networks on chip sub-noc0 to sub-noc3 to be integrated, where GM0, NM0, S1, virtual master element 0, virtual master element 1, virtual slave element 0, and virtual slave element 1 may respectively represent target elements in the system on chip. Based on the topological relation as shown in fig. 4, one example of a configuration file to be integrated into a network on chip is as follows:

GM0 : sub-noc0 input0

NM0 : sub-noc1 input0

sub-noc0 output0 : sub-noc1 input1

sub-noc1 output0 : sub-noc2 input0

sub-noc2 output1 : sub-noc3 input0

sub-noc3 output1 : sub-noc0 input1

sub-noc3 output0 : S0

sub-noc2 output0 : S1

dummy M0 : sub-noc1 input2

dummy M1 : sub-noc0 input2

sub-noc2 output2 : dummy S0

sub-noc3 output2 : dummy S1

Input0 to input2 may respectively represent input ports corresponding to the network on the sub-chip to be integrated (see In0 to In2 In the top-noc box In fig. 4), and output0 to output2 may respectively represent output ports corresponding to the network on the sub-chip to be integrated (see out0 to out2 In the top-noc box In fig. 4). The input id/output id of the sub-noc (i.e., in 0-In 2, out 0-out 2 In the top-noc box) can be determined according to the order In which the corresponding ports appear In the configuration file.

Each row in the configuration file to be integrated into the network on chip may indicate one input transmission path or one output transmission path, each transmission path may be used to represent a pair of connection relationships, and the total number of rows of the configuration file may represent the total number of connections. For example, in the above configuration file, ": the left side of "may represent a side outputting signal data, and the right side may represent a side receiving signal data. "GM0 sub-noc0 input0" may represent a transmission path from a target element GM0 in the network on chip to the sub-noc0 network on chip to be integrated, i.e. data is output from GM0 to input port input0 of sub-noc 0; "sub-noc0 output 0: sub-noc1 input1" may represent a transmission path of the network sub-noc0 to sub-noc1 on the sub-chip to be integrated, i.e. data is output from the output port output0 of sub-noc0 to the input port input1 of sub-noc 1.

Step S302, the line is analyzed, and whether the line meets a first constraint condition is judged.

The port described in the line and/or the target element in the system-on-chip may be obtained by parsing the read line. Based on the acquired ports, it may be determined whether the line satisfies a first constraint.

The first constraint may include that the input port or output port described in the row does not appear repeatedly in the configuration file to be integrated into the network-on-chip.

The newly emerging input/output ports may be stored in a predefined one of the containers, which may refer to ports not stored in the container, upon parsing each row of the network on a sub-chip to be integrated. Based on the predefined container, it may be determined whether the parsed line satisfies a first constraint.

For example, for "GM0 sub-noc0 input0", input port input0 on network sub-noc0 on a sub-chip to be integrated is described, when determining whether the line satisfies the first constraint, it may be determined whether sub-noc0 input0 is already stored in the container based on the container, if sub-noc0 input0 is already stored in the container, sub-noc0 input0 may be considered to occur in other lines, so that it may be determined that the line does not satisfy the first constraint, parsing may be terminated, and a corresponding error code (error) may be returned to prompt the user. Otherwise, if sub-noc0 input0 is not stored in the container, it can be considered that sub-noc0 input0 appears only once in the line, so that it can be determined that the line meets the first constraint condition, and meanwhile, sub-noc0 input0 can be stored in the container, so that judgment of subsequent lines is convenient. Rows may be traversed to determine whether each row of the configuration file satisfies a first constraint.

Because there may be a dangling interface, and the virtual elements corresponding to the dangling interface are generally instantiated in the process of integration, when the configuration file is parsed, the number of virtual elements corresponding to the dangling port can be determined, wherein the virtual elements can include a virtual master element and a virtual slave element; the virtual master element and the virtual slave element are instantiated to determine a second connection relationship. For example, it may appear in the configuration file as ": "the number of dummy elements on the left side (e.g., dummy M0, dummy M1 described above), as the number of virtual master elements, and appear in the configuration file": "the number of dummy elements on the right side (dummy S0, dummy S1 described above) is taken as the number of virtual slave elements, and these virtual master elements and virtual slave elements are instantiated by numbers, respectively.

Step S303, determining a first connection relationship between the integrated sub-networks and a second connection relationship between the integrated sub-networks and the target element in the system on chip according to the input transmission path or the output transmission path indicated by each line in the configuration file of the integrated network on chip, if each line in the configuration file of the integrated network on chip satisfies the first constraint condition.

The first connection relationship may be determined according to an output transmission path of an input port ending on the other network on a sub-chip to be integrated in the configuration file of the network on a chip to be integrated and an input transmission path of an output port starting on the other network on a sub-chip to be integrated; the second connection relationship may be determined according to an output transmission path ending in a slave element in the system-on-chip and an input transmission path starting from a master element in the system-on-chip in a configuration file to be integrated into the network-on-chip.

For example, since "GM 0: sub-noc0 input0" may represent a transmission path from a target element GM0 in the system on chip to the sub-noc0 network on chip to be integrated, GM0 and input port input0 of sub-noc0 may be bound based on this, and a connection relationship (belonging to one of the second connection relationships) between GM0 and sub-noc0 may be determined; similarly, based on the sub-noc0 output 0: sub-noc1 input1", the output port ouput of sub-noc0 and the input port input1 of sub-noc1 can be bound, and the connection relationship (belonging to one of the first connection relationships) between sub-noc0 and sub-noc1 can be determined, so that the method is applicable to other rows in the configuration file by analogy.

Optionally, for convenience of subsequent test scenarios, for the configuration file of the network on chip to be integrated, the input port or the output port may be indicated by a first identifier (input id/output id), where the first identifier may be associated with a sequence in which a master element or a slave element appears in the system on chip in the configuration file of the network on chip to be integrated, and is used to determine a connection relationship between the input port/output port indicated by the first identifier and a target element in the system on chip.

Referring to the identifiers outside the top-noc box In fig. 4, based on the sequence of occurrence of the master element or the slave element In the system on chip In the configuration file, a first identifier In0 may be allocated to the sub-noc0 input0, a first identifier In1 may be allocated to the sub-noc1 input0, a first identifier In2 may be allocated to the sub-noc1 input2, and a first identifier In3 may be allocated to the sub-noc0 input 2; the method comprises the steps of distributing a first identifier out0 for sub-noc3 output0, distributing a first identifier out1 for sub-noc2 output0, distributing a first identifier out2 for sub-noc2 output2, and distributing a first identifier out3 for sub-noc3 output 2. Thus, by uniquely identifying the input/output ports of the network on chip to be integrated based on the first identification determined in the order of appearance, subsequent test work can be facilitated.

In the above example, a configuration file of the network on chip to be integrated is given, however, because a configuration file is added, when the user writes the configuration file of the network on chip to be integrated, if a first identifier is allocated to an input port/output port of each network sub-noc on chip to be integrated, the first identifier needs to be in one-to-one correspondence with an element instantiated in the sub-noc, which is troublesome and easy to make mistakes.

In this example, the configuration file may include a configuration file of each network on a sub-chip to be integrated, that is, the configuration file of each existing sub-noc may be optimized, so that a connection relationship between each sub-noc and a target element in the system on a chip may be reflected. So that step S202 can be implemented based on the configuration file of each network on chip to be integrated.

Referring to fig. 5, a flow chart of a network-on-chip integration method according to an embodiment of the application is shown. As shown in fig. 5, step S202 may include:

Step S501, analyzing the configuration file of each network on a sub-chip to be integrated, and judging whether the configuration file of the network on the sub-chip to be integrated meets the second constraint condition.

Fig. 6 shows a schematic diagram of the topology of a network on chip to be integrated according to an embodiment of the application. The topological relation shown in fig. 6 is the same as that shown in fig. 4, except that the ports of the networks on the sub-chips to be integrated on the same output transmission path or the same input transmission path in the configuration file of each network on the sub-chips to be integrated have the same key number. For example, the ports sub-noc0 output0 and sub-noc1 input1 on the sub-chip network sub-noc0 and sub-noc1 to be integrated are replaced with the same keyword number, external 0; ports sub-noc1 output0 and sub-noc2 input0 on sub-noc1 and sub-noc2 are replaced by the same keyword number, external 1; ports sub-noc2 output1 and sub-noc3 input0 on sub-noc2 and sub-noc3 are replaced by the same keyword number, external 2; ports sub-noc3 output1 and sub-noc0 input1 on sub-noc3 and sub-noc0 are replaced with the same keyword number, external 3. By adding the keyword numbers, the connection relation among the sub nocs can be directly embodied in the configuration file of the sub noc, so that the configuration file of the top noc can be omitted. Based on the topological relation as shown in fig. 6, one example of the configuration file of each network on a sub-chip to be integrated is as follows:

configuration file of network sub-noc0 on sub-chip to be integrated:

GM0 : xxx

external3 : xxx

dummy M1 :xxx

xxx : external0

configuration file of network sub-noc1 on sub-chip to be integrated:

NM0 : xxx

external0 : xxx

dummy M0 : xxx

xxx : external1

Configuration file of network sub-noc2 on sub-chip to be integrated:

external1 : xxx

xxx : S1

xxx : external2

xxx : dummy S0

configuration file of network sub-noc3 on sub-chip to be integrated:

external2 : xxx

xxx : S0

xxx : external3

xxx : dummy S1

Wherein xxx may represent any input port/output port on the sub-noc to be integrated, for example, xxx in the configuration file of sub-noc0 may represent a corresponding input port/output port on sub-noc0, and the representation manner of the input port/output port is not concerned in the embodiment of the present application, so that the representation is replaced by xxx to make the example more concise.

The term 0 to term 3 are the keyword numbers, and 'term' is only an example of the keyword numbers.

The network on a sub-chip to be integrated may be parsed to determine whether the network on a sub-chip to be integrated meets a second constraint, where the second constraint may include:

The keyword numbers described in the configuration file of each sub-network-on-chip to be integrated do not appear repeatedly in the configuration file; the target elements in the system on chip described in the configuration files of the sub-networks to be integrated do not repeatedly appear in the configuration files of all the sub-networks to be integrated; and the keyword numbers described in the configuration files of the networks on the sub-chips to be integrated appear twice in the configuration files of the networks on the sub-chips to be integrated.

In the process of analysis, the network on each sub-chip to be integrated can be analyzed first, and constraint inspection can be performed. For example, for the sub-noc0 profile, it is possible to check whether the keyword number extra 3 described therein appears only once in the profile, and check whether the keyword number extra 0 described therein appears only once in the profile, respectively. If the extra 3/extra 0 occurs more than once, it may be determined that the sub-noc0 profile does not satisfy the second constraint, parsing may be terminated, and a corresponding error code (error) may be returned to prompt the user. Otherwise, if both external3 and external0 occur only once, respectively, it may be determined that the sub-noc0 profile satisfies the second constraint condition. The method is applicable to other configuration files of the network on the sub-chip to be integrated by analogy.

Then, the configuration files of all the sub-network-on-chip to be integrated can be analyzed, and constraint checking can be performed. For example, for element GM0 on other network-on-chips described in the sub-noc0 profile, all of the networks-on-chips to be integrated may be checked to determine if the element's number GM0 has only occurred once; and for the keyword number extra 3/extra 0 described therein, all the sub-networks to be integrated may be checked, and it may be determined whether the keyword number extra 3/extra 0 appears twice in the configuration file of all the sub-networks to be integrated, respectively. If GM0 does not appear only once in all the profiles, or extra 3/extra 0 appears only once or more than twice in all the profiles, it may be determined that the profiles do not satisfy the second constraint, parsing may be terminated, and a corresponding error code (error) may be returned to prompt the user. All of the configuration files may be parsed to determine whether the second constraint is satisfied.

In step S502, in the case that the configuration file of the network on a sub-chip to be integrated satisfies the second constraint condition, the global table is determined based on the output transmission path/input transmission path having the key number.

Similar to the above embodiment, since there may be a suspension interface, and the virtual elements corresponding to the suspension interface are generally instantiated in the process of integration, when analyzing the configuration files of all the network on a sub-chip to be integrated, the number of virtual elements corresponding to the suspension port may be determined, where the virtual elements may include a virtual master element and a virtual slave element; the virtual master element and the virtual slave element are instantiated to determine a second connection relationship. For example, it may appear in the overall configuration file as ": "the number of dummy elements on the left side (e.g., dummy M0, dummy M1 described above), as the number of virtual master elements, and appear in the overall configuration file": "the number of dummy elements on the right side (dummy S0, dummy S1 described above) is taken as the number of virtual slave elements, and these virtual master elements and virtual slave elements are instantiated, respectively.

The configuration file of each network on a sub-chip to be integrated is newly added in the original configuration file of the network on the sub-chip to be integrated according to the embodiment of the application, and each network on the sub-chip to be integrated can also be internally integrated according to the original configuration file to determine the connection relationship between each element in the network on the sub-chip to be integrated, and then determine the first connection relationship and the second connection relationship.

The global table may include a key number of the port, a second identification indicating that the port is an input port or an output port, and an output/input object to which the port corresponds. The global table may be denoted as table1, taking example of external0 in the configuration file of sub-noc0, one record in table1 may be [ external0, input, xxx ], where external0 may represent a key number, input may be a second identifier, indicating that the port is an input port on sub-noc0 (i.e., global input id), and xxx may represent an output object of the port. For each key number that appears in each configuration file, a record may be saved in table1 in this manner.

The input id/output id of a sub-noc or top noc may be determined in the order in which the elements appear. Wherein the second identifier (input id/output id representing top noc) may be associated with a sequence of parsing (parameter) the configuration file of each network on chip to be integrated.

The configuration file of each network-on-chip to be integrated includes a third identifier (i.e. the above mentioned 'xxx') indicating that the port is an input port or an output port, and the third identifier may be associated with the order in which the input port or the output port appears in the configuration file of each network-on-chip to be integrated.

The elements with key numbers may not have to be assigned input id/output id of top noc.

Optionally, a global table may also be created for target elements of the system-on-chip that appear in the configuration file. The global table may be an element type number, a fourth identifier indicating that the element is a master element or a slave element, and an output/input object corresponding to the element. The global table may be denoted as table2, taking GM0 in the configuration file of sub-noc0 as an example, one record in table2 may be [ GM0, master, xxx ], where GM0 may represent a type number of a target element, master may be a fourth identifier, indicating that the target element is a master element (corresponding to a slave element may be slave), and xxx may represent an output object of the target element. A record may be saved in table2 for each target element in the system-on-chip that appears in each configuration file and so on.

The table1 and the table2 may be combined into one global table.

Step S503, determining a first connection relationship between the networks on the sub-chips to be integrated and a second connection relationship between the networks on the sub-chips to be integrated and the target element in the system on chip based on the global table.

The input port and the output port with the same keyword number can be bound based on the global table, and a first connection relation is determined; the second connection relationship may be determined by binding the port with the slave element/master element in the case where the output/input object corresponding to the port is the slave element or the master element in the system on chip.

For example, for the keyword number extra 0, a global table may be traversed, where two of [ extra 0, output, xxx (e.g. sub-noc1 input 1) ], [ extra 0, input, xxx (e.g. sub-noc0 output 0) ] indicate output objects sub-noc1 input1 and sub-noc0 output0 of the ports to be bound to determine a first connection relationship between the networks sub-noc1 and sub-noc0 on the sub-chip to be integrated. The same applies for the first connection relations between other sub-networks to be integrated.

The global table may also be traversed, and for a record in which a target element in the system-on-chip occurs, for example, a record [ GM0, master, xxx (e.g., sub-noc0 input 0) ] for GM0, the target element GM0 in the system-on-chip indicated in the record is bound to the output port input0 on the corresponding sub-noc0, so as to determine a second connection relationship between the target element GM0 in the system-on-chip and the sub-noc0 of the network-on-chip to be integrated. The same applies for the second connection relationship between other sub-networks to be integrated and the target element in the system-on-chip.

Therefore, the binding between the sub-networks to be integrated and the target elements in the system on chip can be automatically performed based on the global table, and the efficiency is higher.

In the embodiment of the application, the identification of the input port/output port of the network on chip to be integrated and the identification of the input port/output port of the network on the sub-chip to be integrated can be determined according to the occurrence sequence of the input port/output port. For example, the identification of input/output ports of the network on a sub-chip to be integrated may be determined based on the order of the ports in their configuration files. The global identification of the input/output ports of the network-on-chip to be integrated may be determined based on the parsing order of the network-on-chip to be integrated included therein, wherein the ports with the key numbers may not be assigned global identification.

Fig. 7 illustrates a block diagram of a network-on-chip integrated device according to an embodiment of the present application. As shown in fig. 7, the apparatus includes:

An obtaining module 701, configured to obtain a configuration file, where the configuration file includes configuration information of a network on chip to be integrated in a system on chip, the network on chip to be integrated includes a plurality of networks on a sub-chip to be integrated, and the configuration information includes an output transmission path of each output port and/or an input transmission path of each input port on the network on the sub-chip to be integrated;

The first determining module 702 is configured to determine, based on the configuration file, a first connection relationship between the networks on the sub-chip to be integrated, and a second connection relationship between the networks on the sub-chip to be integrated and a target element in the system on the chip, where the first connection relationship is used to bind between the networks on the sub-chip to be integrated, and the second connection relationship is used to bind between the networks on the sub-chip to be integrated and the target element in the system on the chip, and implement integration of the networks on the chip based on the binding.

In one possible implementation, the configuration file includes a configuration file to be integrated into the network on chip, and each row in the configuration file to be integrated into the network on chip indicates one input transmission path or one output transmission path, and the first determining module 702 is configured to:

Reading a row from a configuration file of a network on chip to be integrated;

In one possible implementation, the first determining module 702 is configured to:

In one possible implementation, the second constraint includes:

In one possible implementation manner, the ports include suspended ports that do not need to be bound to other ports, the target element further includes virtual elements corresponding to the suspended ports one to one, and the first determining module 702 is configured to:

In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.

The disclosed embodiments also provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method. The computer readable storage medium may be a volatile or nonvolatile computer readable storage medium.

The embodiment of the disclosure also provides a network-on-chip integration device, which comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing the instructions stored by the memory.

Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above method.

Fig. 8 is a block diagram illustrating an apparatus 1900 for integrating a network on chip, according to an example embodiment. For example, the apparatus 1900 may be provided as a server or terminal device. Referring to fig. 8, the apparatus 1900 includes a processing component 1922 that further includes one or more processors and memory resources represented by memory 1932 for storing instructions, such as application programs, that are executable by the processing component 1922. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. Further, processing component 1922 is configured to execute instructions to perform the methods described above.

The apparatus 1900 may further comprise a power component 1926 configured to perform power management of the apparatus 1900, a wired or wireless network interface 1950 configured to connect the apparatus 1900 to a network, and an input/output interface 1958 (I/O interface). The device 1900 may operate based on an operating system stored in memory 1932, such as Windows Server ^TM,Mac OS X^TM,Unix^TM, Linux^TM,FreeBSD^TM or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 1932, including computer program instructions executable by processing component 1922 of apparatus 1900 to perform the above-described methods.

The present disclosure may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.

The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as SMALLTALK, C ++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method of network-on-chip integration, the method comprising:

Acquiring a configuration file, wherein the configuration file comprises configuration information of a network on chip to be integrated in a system on chip, the network on chip to be integrated comprises a plurality of networks on sub chip to be integrated, the configuration information comprises an output transmission path of each output port and/or an input transmission path of each input port on the network on sub chip to be integrated, the configuration file comprises configuration files of the networks on sub chip to be integrated, the ports of the same output transmission path or the network on sub chip to be integrated on the same input transmission path in the configuration files of the networks on sub chip to be integrated have the same keyword number, and the ports with the keyword numbers are not distributed with global identifiers;

And determining a first connection relation between each sub-network to be integrated and a second connection relation between the sub-network to be integrated and a target element in the system-on-chip based on the configuration file, wherein the first connection relation is used for binding each sub-network to be integrated, and the second connection relation is used for binding the sub-network to be integrated and the target element in the system-on-chip based on the binding so as to realize the integration of the network-on-chip.

2. The method of claim 1, wherein the target elements comprise a master element in the system-on-chip and a slave element in the system-on-chip, the output transmission path of each output port on the sub-network to be integrated terminating at one input port on the other sub-network to be integrated or at one slave element in the system-on-chip, wherein the slave element is to receive data from the output transmission path, the input transmission path of each input port on the sub-network to be integrated starting from one output port on the other sub-network to be integrated or one master element in the system-on-chip, wherein the master element is to provide data to the input transmission path.

3. The method of claim 1, wherein the configuration file includes a configuration file of a network on chip to be integrated, each row in the configuration file of the network on chip to be integrated indicates one input transmission path or one output transmission path, and the determining a first connection relationship between the networks on chips to be integrated and a second connection relationship between the network on chip to be integrated and a target element in the system on chip based on the configuration file includes:

reading a row from the configuration file of the network on chip to be integrated;

And under the condition that each row in the configuration file of the network on chip to be integrated meets the first constraint condition, determining a first connection relation between the network on chip to be integrated and a second connection relation between the network on chip to be integrated and target elements in the system on chip according to the input transmission path or the output transmission path indicated by each row in the configuration file of the network on chip to be integrated.

4. The method of claim 3, wherein determining a first connection relationship between the networks on the sub-chips to be integrated and a second connection relationship between the networks on the sub-chips to be integrated and the target element in the system on the chip based on the configuration file comprises:

Determining the first connection relation according to the output transmission paths of the configuration files of the network on chip to be integrated, which are terminated on the input ports of the networks on other sub-chips to be integrated, and the input transmission paths of the output ports of the networks on other sub-chips to be integrated;

And determining the second connection relation according to the output transmission path of the slave element ending in the system-on-chip and the input transmission path of the master element starting in the system-on-chip in the configuration file of the network-on-chip to be integrated.

5. A method according to claim 3, characterized in that the input port or output port is indicated in the configuration file of the network on chip to be integrated by a first identification, which is associated with the order in which the master or slave elements in the system on chip appear in the configuration file of the network on chip to be integrated.

6. The method of claim 1, wherein determining a first connection relationship between the networks on the sub-chips to be integrated and a second connection relationship between the networks on the sub-chips to be integrated and the target element in the system on the chip based on the configuration file comprises:

Analyzing configuration files of each network on a sub-chip to be integrated, and judging whether the configuration files of the network on the sub-chip to be integrated meet a second constraint condition;

Determining a global table based on an output transmission path/input transmission path with a keyword number under the condition that the configuration file of the network on a sub-chip to be integrated meets the second constraint condition;

and determining a first connection relation between the networks on the sub-chips to be integrated and a second connection relation between the networks on the sub-chips to be integrated and target elements in the system on chip based on the global table.

7. The method of claim 6, wherein the global table includes a key number of a port, a second identifier indicating that the port is an input port or an output port, an output/input object corresponding to the port, wherein the determining, based on the global table, a first connection relationship between the networks on the sub-chips to be integrated and a second connection relationship between the networks on the sub-chips to be integrated and a target element in the system on the chip includes:

Binding an input port and an output port with the same keyword number, and determining the first connection relation;

And binding the port with the slave element/master element under the condition that the output/input object corresponding to the port is the slave element or the master element in the system on chip, and determining the second connection relation.

8. The method of claim 7, wherein the second identifier is associated with a sequence of parsing configuration files for each network-on-chip to be integrated; the configuration file of each network on a sub-chip to be integrated comprises a third identifier indicating that the port is an input port or an output port, and the third identifier is associated with the sequence of the occurrence of the input port or the output port in the configuration file of each network on a sub-chip to be integrated.

9. The method of claim 6, wherein the second constraint comprises:

The target elements in the system on chip described in the configuration files of the sub-networks to be integrated do not repeatedly appear in the configuration files of all the sub-networks to be integrated; and is also provided with

The key numbers described in the configuration files of each network-on-chip to be integrated appear twice in the configuration files of all the networks-on-chip to be integrated.

10. The method according to any one of claims 1 to 9, wherein the ports include a dangling port that does not need to be bound to other ports, the target element further includes a virtual element that corresponds to the dangling port one to one, and the determining, based on the configuration file, a first connection relationship between the networks on the sub-chips to be integrated and a second connection relationship between the networks on the sub-chips to be integrated and the target element in the system on the chip includes:

analyzing the configuration file, and determining the number of the virtual elements corresponding to the floating ports, wherein the virtual elements comprise virtual master elements and virtual slave elements;

Instantiating the virtual master element and the virtual slave element to determine the second connection relationship.

11. The method of claim 1, wherein the ports on the network on a sub-chip to be integrated are in one-to-one correspondence with ports of elements instantiated on the network on a sub-chip to be integrated.

12. The method of claim 1, wherein the configuration information of the network on chip to be integrated includes information of elements in each network on chip to be integrated, the method further comprising:

13. The method of claim 2, wherein the master elements in the system on chip comprise at least one of graphics processor GPU, neural network processor NPU, and virtual master elements, and the slave elements in the system on chip comprise at least one of double rate synchronous dynamic random memory DDR, cache memory, and virtual slave elements.

14. A network-on-chip integrated device, the device comprising:

The system comprises an acquisition module, a configuration file and a processing module, wherein the configuration file comprises configuration information of a network on chip to be integrated in a system on chip, the network on chip to be integrated comprises a plurality of networks on sub chip to be integrated, the configuration information comprises an output transmission path of each output port and/or an input transmission path of each input port on the network on sub chip to be integrated, the configuration file comprises configuration files of the networks on sub chip to be integrated, the ports of the same output transmission path or the same input transmission path of the network on sub chip to be integrated in the configuration files of the networks on sub chip to be integrated have the same keyword number, and the ports with the keyword numbers are not distributed with global identifiers;

The first determining module is configured to determine, based on the configuration file, a first connection relationship between the networks on the sub-chip to be integrated, and a second connection relationship between the networks on the sub-chip to be integrated and a target element in the system on the chip, where the first connection relationship is used to bind the networks on the sub-chip to be integrated, and the second connection relationship is used to bind the networks on the sub-chip to be integrated and the target element in the system on the chip, and implement integration of the network on the chip based on the binding.

15. A network-on-chip integrated device, comprising:

A processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to implement the method of any one of claims 1 to 13 when executing the instructions stored by the memory.

16. A non-transitory computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of any of claims 1 to 13.