CN117667817A - Serdes interface high-speed industrial bus - Google Patents
Serdes interface high-speed industrial bus Download PDFInfo
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- CN117667817A CN117667817A CN202311851633.9A CN202311851633A CN117667817A CN 117667817 A CN117667817 A CN 117667817A CN 202311851633 A CN202311851633 A CN 202311851633A CN 117667817 A CN117667817 A CN 117667817A
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Abstract
The invention discloses a high-speed industrial bus of a Serdes interface, which comprises a micro control unit; a bus chip; the Serdes comprises a serializer, a deserializer and a Serdes framework, and the Serdes framework is matched with the serializer and the deserializer to carry out Serdes stable high-speed communication; the Serdes, the micro control unit and the bus chip are communicated through sync, and the bus chip is communicated with the Serdes through optical fibers, so that the industrial bus field of the Serdes interface is related. The serializer processing unit and the deserializer processing unit in the Serdes interface are designed based on the Serdes universal architecture, the Serdes interface can be realized by using the architecture, the speed is generally higher than 28GHz, the highest speed can reach 112Ghz, the communication speed is higher than the communication speed of a common hundred megalevel PHY chip by more than two orders of magnitude, the data synchronization period can easily realize 1us level, and the response speed of the interface is effectively improved; the Serdes interface is based on optical communication, is hardly interfered, and is stable in communication.
Description
Technical Field
The invention relates to the field of industrial buses of Serdes interfaces, in particular to a high-speed industrial bus of Serdes interfaces.
Background
SerDes is an abbreviation for Serializer/Deserializer, i.e., serializer and Deserializer, and as the name implies, is a "physical device" that converts parallel data into serial data for transmission, and received serial data into parallel data. In other words, serDes is an "advanced" serial-to-parallel conversion device that requires digital-to-analog hardware implementation for high-speed transmission, which is a mainstream Time Division Multiplexing (TDM), point-to-point (P2P) serial communication technology. The multi-path low-speed parallel signals are converted into high-speed serial signals at the transmitting end, and finally the high-speed serial signals are converted into low-speed parallel signals at the receiving end through a transmission medium (an optical cable or a copper wire). The point-to-point serial communication technology fully utilizes the channel capacity of a transmission medium, reduces the number of required transmission channels and device pins, and improves the transmission speed of signals, thereby greatly reducing the communication cost.
Serdes basic architecture and composition
A common SerDes architecture is an 8b/10b coding based architecture with a clock embedded in the data stream, consisting mainly of a physical medium dependent sub-layer (PMD), a physical medium adaptation layer (Physical Media Attachment, PMA) and a physical coding sub-layer (physical coder sublayer, PCS). The PCS layer is responsible for encoding/decoding data flow, is standard comprehensive CMOS digital logic, can be realized by hard logic, and can also be realized by FPGA soft logic. The PMA layer is a digital-analog hybrid CML/CMOS circuit responsible for serialization/deserialization, which is the key to understand the distinction of SerDes from parallel interfaces. PMD is the electrical block responsible for serial signal transmission.
The high-speed industrial bus chip is connected with the network through the conventional PHY physical layer chip, and the communication speed can be generally only in the level of hundred megabytes. As the data volume of the high-speed industrial network is larger and larger, the real-time requirement is higher and higher, the communication rate of the industrial bus reaches kilomega or ten kilomega, and the conventional network cable interface cannot meet the requirement. We propose a high-speed industrial bus based on SerDes interface to replace the physical layer interface of common PHY chip.
Disclosure of Invention
The present invention is directed to a Serdes interface high-speed industrial bus to solve the above-mentioned problems.
In order to achieve the above purpose, the present invention provides the following technical solutions: a high-speed industrial bus of Serdes interface includes a micro control unit;
a bus chip; and
the Serdes comprises a serializer, a deserializer and a Serdes framework, and the Serdes framework is matched with the serializer and the deserializer to carry out Serdes stable high-speed communication;
the Serdes, the micro control unit and the bus chip are communicated through sync, and the bus chip is communicated with the Serdes through optical fibers.
As still further aspects of the invention: a high-speed industrial bus of a Serdes interface comprises a serializer processing unit and a deserializer processing unit in the Serdes framework, wherein the serializer processing unit and the deserializer processing unit perform open source processing through clock management.
As still further aspects of the invention: a high-speed industrial bus of a Serdes interface, the serializer processing unit includes a transmission line, a linear encoder, and a transmission channel that blends with the transmission line and performs transmission processing on the serializer.
As still further aspects of the invention: the high-speed industrial bus of Serdes interface, the said decoder processing unit includes receiving line, linear encoder and RX elastic buffer, said RX elastic buffer and linear encoder are fused with receiving line and receive the processing to the deserializer.
As still further aspects of the invention: the high-speed industrial bus of Serdes interface is characterized in that a topology system is arranged in the clock manager, the topology system comprises a topology conversion module, a logic processing module and a representation module, the topology system performs topology conversion on a serializer processing unit/decoder processing unit through the topology conversion module, the logic processing module processes a topology conversion result and generates a logic signal, and the representation module outputs the logic signal.
As still further aspects of the invention: a high-speed industrial bus of a Serdes interface, the topology conversion module comprising a topology addition block that adds a topology factor to a serializer or deserializer, a topology identification block that identifies a serializer/deserializer signal according to the topology factor, and an analog-to-digital conversion block that performs serial/decoding classification of the signal by the serializer/deserializer signal.
As still further aspects of the invention: the high-speed industrial bus of Serdes interface, the logic processing module includes AND gate block, OR gate block and NOT gate block, AND gate block, OR gate block and NOT gate block all connect with module brick block signal.
As still further aspects of the invention: a high-speed industrial bus of a Serdes interface is arranged in a performance module, and the performance module is provided with a performance block which is identical to an open source read-write signal.
As still further aspects of the invention: a Serdes interface high speed industrial bus, in which the linear encoder and RX elastic buffer cooperate to present outputs to a channel bundle.
As still further aspects of the invention: a high-speed industrial bus of Serdes interfaces, the channel bundle presents a redundancy mechanism whose output is the Serdes interface.
Compared with the prior art, the invention has the beneficial effects that:
the serializer processing unit and the deserializer processing unit in the Serdes interface are designed based on the Serdes universal architecture, and can be realized by using the architecture
1. The Serdes interface has high speed, generally more than 28GHz, the fastest speed can reach 112Ghz, the communication speed is higher than that of a common hundred megalevel PHY chip by more than two orders of magnitude, the data synchronization period can easily realize 1us level, and the response speed of the interface is effectively improved;
2. the Serdes interface is based on optical communication, is hardly interfered, and is stable in communication;
3. in the process of constructing information between the clock manager and the open source, the constructed information is subjected to topological treatment (namely, ordered position arrangement is carried out on unordered clock manager processing elements by topological treatment), the arrangement mode is determined by a read-write protocol between the clock manager and the open source (such as arrangement classification of pre-treatment time and post-treatment time of low-flow-rate information or high-flow-rate information), and therefore the problem that the working efficiency of the clock manager is affected due to the disorder of information arrangement in the clock manager is solved;
4. the load of the Serdes interface can be balanced and simplified through a backup mechanism that the linear encoder and the RX elastic buffer are matched to the channel bundling performance output, and the channel bundling performance output is the Serdes interface, so that the transmission speed of the Serdes interface is improved.
Drawings
FIG. 1 is a general block diagram of Serdes in a high-speed industrial bus of Serdes interface of the present invention;
FIG. 2 is a block diagram of a conventional high-speed industrial bus chip in a Serdes interface high-speed industrial bus of the present invention;
FIG. 3 is a block diagram of a Serdes interface high speed industrial bus chip in a Serdes interface high speed industrial bus according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In describing the present invention, it should be noted that the specific meaning of the above terms in the present invention can be understood in detail to those skilled in the art. Hereinafter, an embodiment of the present invention will be described in accordance with its entire structure.
A Serdes interface high-speed industrial bus comprises a micro control unit, wherein the bus chip comprises an SPI and a parallel port;
the bus chip comprises an SPI and a parallel port; and
the Serdes comprises a serializer, a deserializer and a Serdes framework, and the Serdes framework is matched with the serializer and the deserializer to carry out Serdes stable high-speed communication;
the Serdes, the micro control unit and the bus chip are communicated through sync, and the bus chip is communicated with the Serdes through optical fibers.
Example 1
Referring to fig. 2, when the micro control unit communicates with the high-speed industrial bus chip as the bus chip, the SPI and the parallel port disposed therein are bridged with each other and communicate through the sync communication protocol, and the conventional PHY physical layer chip (i.e. the Φ1 and Φ2 marks in fig. 1) is connected to the network, so that the communication speed is generally only hundred megabits, and the real-time requirement is higher and higher due to the increasing data volume of the high-speed industrial network, the communication speed of the industrial bus reaches gigabit or ten gigabit, and the conventional network interface cannot meet the requirement, so that the conventional network interface cannot be suitable for the gigabit or ten gigabit communication requirement, and the Serdes interface is improved for the communication architecture.
As still further aspects of the invention: a Serdes interface high-speed industrial bus, in the Serdes framework, comprising a serializer processing unit and a deserializer processing unit, wherein the serializer processing unit and the deserializer processing unit perform open source processing through clock management, the serializer processing unit comprises a transmission line, a linear encoder and a transmission channel, the transmission channel and the linear encoder are fused with the transmission line and perform transmission processing on the serializer, and the decoder processing unit comprises a receiving line, a linear encoder and an RX elastic buffer, and the RX elastic buffer and the linear encoder are fused with the receiving line and perform reception processing on the deserializer.
Example two
Referring to FIG. 1, the serializer and deserializer processing units in the Serdes interface are designed based on the Serdes general architecture with which implementation can be achieved
The Serdes interface has high speed, generally more than 28GHz, and the highest speed can reach 112Ghz, which is more than two orders of magnitude higher than the communication speed of a common hundred megalevel PHY chip, and the data synchronization period can easily realize 1us level, so that the response speed of the interface is effectively improved.
B. The Serdes interface is based on optical communication, is hardly interfered, and is stable in communication.
As still further aspects of the invention: the high-speed industrial bus with the Serdes interface is characterized in that a topology system is arranged in the clock manager and comprises a topology conversion module, a logic processing module and a representation module, the topology system performs topology conversion on a serializer processing unit/decoder processing unit through the topology conversion module, the logic processing module processes a topology conversion result and generates a logic signal, the representation module outputs the logic signal, the topology conversion module comprises a topology adding block, a topology identification block and an analog-to-digital conversion block, the topology adding block adds a topology factor to the serializer or the deserializer, the topology identification block identifies a serializer/deserializer signal according to the topology factor, the analog-to-digital conversion block performs serial/decoding classification of the signal through the serializer/deserializer signal, the logic processing module comprises an AND gate block, an OR gate block and an NOT gate block, the AND gate block are connected with the analog-to-digital block signal, and the representation block is arranged in the representation module and is identical with the open source read-write signal.
Example III
In the process of constructing information between the clock manager and the open source, the constructed information is subjected to topological treatment (namely, ordered position arrangement is carried out on unordered clock manager processing elements by topological treatment), the arrangement mode is determined by a read-write protocol between the clock manager and the open source (such as arrangement classification of pre-treatment time and post-treatment time of low-flow-rate information or high-flow-rate information), so that the problem that the working efficiency of the clock manager is influenced by the disorder of the arrangement of the information in the clock manager is solved, and the method is characterized by comprehensively configuring through a topology conversion module, a logic processing module and a representation module;
specifically, the topology adding block adds topology factors to the serializer or the deserializer, the topology identifying block identifies the signals of the serializer/deserializer according to the topology factors, the analog-to-digital conversion block performs serial/decoding classification of the signals through the signals of the serializer/deserializer, and the AND gate block, the OR gate block and the NOT gate block in the logic processing module are connected with the analog-to-digital brick block through signals, and then the AND gate block and the NOT gate block are identical to the open source read-write signals through the expression block.
As still further aspects of the invention: a high-speed industrial bus of Serdes interfaces, in which the linear encoder and RX elastic buffer cooperate to present outputs to a channel bundle, which is the redundancy mechanism of the Serdes interface.
Example IV
The load of the Serdes interface can be balanced and simplified through a backup mechanism that the linear encoder and the RX elastic buffer are matched to the channel bundling performance output, and the channel bundling performance output is the Serdes interface, so that the transmission speed of the Serdes interface is improved.
The working principle of the invention is as follows: in the process of the operation of the Serdes interface and the process of constructing information between the clock manager and the open source, the constructed information is subjected to topological treatment (namely, ordered position arrangement is carried out on unordered clock manager processing elements by topological treatment), the arrangement mode is determined by a read-write protocol of the clock manager and the open source (such as arrangement classification of pre-treatment time and post-treatment time of low-flow-rate information or high-flow-rate information), and thus the problem that the working efficiency of the clock manager is influenced by the disorder of the arrangement of the internal information of the clock manager is solved, and the method is comprehensively configured through a topology conversion module, a logic processing module and a presentation module;
specifically, the topology adding block adds topology factors to the serializer or the deserializer, the topology identifying block identifies the signals of the serializer/deserializer according to the topology factors, the analog-to-digital conversion block performs serial/decoding classification of the signals through the signals of the serializer/deserializer, and the AND gate block, the OR gate block and the NOT gate block in the logic processing module are connected with the analog-to-digital brick block through signals, and then the AND gate block and the NOT gate block are identical to the open source read-write signals through the expression block.
The foregoing description is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical solution of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.
Claims (10)
1. A high-speed industrial bus of Serdes interface, characterized by comprising a micro control unit;
a bus chip; and
the Serdes comprises a serializer, a deserializer and a Serdes framework, and the Serdes framework is matched with the serializer and the deserializer to carry out Serdes stable high-speed communication;
the Serdes, the micro control unit and the bus chip are communicated through sync, and the bus chip is communicated with the Serdes through optical fibers.
2. The Serdes interface high-speed industrial bus of claim 1, wherein the Serdes framework comprises a serializer processing unit and a deserializer processing unit, and wherein the serializer processing unit and the deserializer processing unit perform open source processing through clock management.
3. The Serdes interface high speed industrial bus of claim 2, wherein the serializer processing unit includes a transmit line, a linear encoder, and a transmit channel that blends with the transmit line and transmits the serializer.
4. The Serdes interface high-speed industrial bus of claim 2, wherein the decoder processing unit comprises a receive line, a linear encoder, and an RX elastic buffer, the RX elastic buffer and linear encoder being fused to the receive line and receiving the deserializer.
5. The Serdes interface high-speed industrial bus according to claim 2, wherein a topology system is arranged in the clock manager, the topology system comprises a topology conversion module, a logic processing module and a representation module, the topology system performs topology conversion on a serializer processing unit/decoder processing unit through the topology conversion module, the logic processing module processes a topology conversion result and generates a logic signal, and the representation module outputs the logic signal.
6. The Serdes interface high-speed industrial bus of claim 5, wherein the topology conversion module comprises a topology addition block that adds a topology factor to the serializer or deserializer, a topology identification block that identifies the serializer/deserializer signal based on the topology factor, and an analog-to-digital conversion block that performs serial/decoding classification of the signal by the serializer/deserializer signal.
7. The Serdes interface high-speed industrial bus of claim 5, wherein the logic processing module comprises an AND gate block, an OR gate block, and a NOT gate block, each in signal connection with a modular brick block.
8. The Serdes interface high-speed industrial bus according to claim 5, wherein the performance module is provided with a performance block, and the performance block is identical to an open source read-write signal.
9. The Serdes interface high-speed industrial bus of claim 4, wherein the linear encoder and RX elastic buffer cooperate to present outputs to the channel bundle in the decoder processing unit.
10. The Serdes interface high-speed industrial bus of claim 9, wherein the lane bundle exhibits a redundant mechanism of the Serdes interface as output.
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| CN202311851633.9A CN117667817A (en) | 2023-12-29 | 2023-12-29 | Serdes interface high-speed industrial bus |
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