CN117667156A

CN117667156A - Remote upgrading equipment and method based on FPGA chip

Info

Publication number: CN117667156A
Application number: CN202311826772.6A
Authority: CN
Inventors: 王克立; 何龙飞; 程本涛
Original assignee: Shenzhen Feisi Communication Technology Co ltd
Current assignee: Shenzhen Feisi Communication Technology Co ltd
Priority date: 2023-12-27
Filing date: 2023-12-27
Publication date: 2024-03-08

Abstract

The application relates to a remote upgrading device and a method based on an FPGA chip. The remote upgrading method based on the FPGA chip comprises the following steps: s1, sending a configuration upgrading file data packet to a first FPGA chip through a network chip; s2, judging whether a data preamble, a destination address and a source address of the configuration upgrade file data packet are correct or not through a network receiving module; s3, sending an instruction to a network sending module, so that the network sending module sends the state of the received data to an upper computer according to the format of an Ethernet upgrading data response packet; s4, analyzing address bits of data configuring the upgrade file data packet through a network analysis module, and judging which chip the upgrade file data packet is used for upgrading through the address bits of the data; s5, storing the analyzed data into a first nonvolatile memory through a first nonvolatile memory module; s6, storing the whole configuration upgrade file data packet, and enabling the first nonvolatile memory to be in a readable state after the data integrity check and the cyclic redundancy check are correct.

Description

Remote upgrading equipment and method based on FPGA chip

Technical Field

The application relates to the technical field of FPGA (field programmable gate array), in particular to remote upgrading equipment and method based on an FPGA chip.

Background

The deployment architecture of the universal FPGA (Field Programmable Gate Array ) intelligent network card mainly comprises an FPGA chip and a CPU chip. Because the FPGA chip is responsible for the main network processing forwarding work, the FPGA is connected with high-speed network interfaces, such as a high-speed network interface, a host golden finger PCIe interface 1, an on-board CPU PCIe interface 2, and DDR, FLASH memory, and general control I/O peripherals.

In a device having a plurality of FPGAs and a single-chip microcomputer, if a corresponding board card program is to be updated, a general use is to disassemble the device, and a downloading device special for the FPGAs and the single-chip microcomputer is used for burning each board card. If the equipment is installed, the equipment is in a complex working environment, such as an airborne or carrier-borne environment, the disassembly and assembly become time-consuming and labor-consuming, and the disassembly and the burning of the equipment are inconvenient.

In some current schemes, an FPGA is typically upgraded remotely through a portal. When facing devices with a plurality of FPGAs and singlechips, the schemes can not perfectly solve the related problems of upgrading all boards in the devices.

Disclosure of Invention

In order to overcome the problems in the related art, the application provides a remote upgrading device and a method based on an FPGA chip, which can remotely complete the data upgrading requirements of all boards through a network card chip of one FPGA chip, so that when each board needs to be upgraded, a plurality of different downloaders are not required to be prepared, and the upgrading process can be completed without disassembling the machine.

The application provides a remote upgrading device based on an FPGA chip, which comprises: the device comprises an upper computer, a first board card, a second board card and a third board card; the first board card is provided with a network card chip, a first non-volatile memory, a first FPGA chip, a second non-volatile memory, a first serial port and a second serial port; the first board card is communicated with the upper computer through the network card chip; the first FPGA chip comprises a network receiving module, a network analyzing module, a network sending module, a first nonvolatile storage module, a second nonvolatile storage module, a first serial port receiving and transmitting module and a second serial port receiving and transmitting module; the network receiving module is used for carrying out network communication between the first FPGA chip and the upper computer, receiving a configuration upgrade file sent by the upper computer and analyzing an MAC layer protocol of the configuration upgrade file; the network analysis module is used for receiving the configuration upgrade file sent by the network receiving module and analyzing the UDP layer protocol of the configuration upgrade file; the network sending module is used for sending the state of the configuration upgrade file received by the network receiving module to the upper computer; the first nonvolatile storage module is used for receiving the configuration upgrade file analyzed by the network analysis module and storing the configuration upgrade file into the first nonvolatile memory; the second nonvolatile memory module is used for reading the configuration file used for upgrading the first FPGA chip in the first nonvolatile memory and storing the configuration upgrading file of the first FPGA chip into the second nonvolatile memory; the first serial port transceiver module is configured to read a configuration file for upgrading the second board card in the first nonvolatile memory, and send the configuration upgrade file of the second board card to the second board card through a first serial port; the second serial port transceiver module is used for reading the configuration file for upgrading the third board card in the first nonvolatile memory and sending the configuration upgrading file of the third board card to the third board card through the second serial port.

Preferably, the network receiving module is configured to parse the MAC layer protocol of the configuration upgrade file according to the network protocol, and is configured to verify whether the frame header of the data packet received by the configuration upgrade file is consistent with the agreed frame header, and is configured to verify whether the last check bit of the data packet of the configuration upgrade file is correct.

Preferably, the UDP layer protocol of the configuration upgrade file includes: the network analysis module is used for sending the content of the upgrade file to the first nonvolatile storage module.

Preferably, it is characterized in that: the second board card comprises a second FPGA chip, and the third board card comprises a singlechip chip.

The application also provides a remote upgrading method based on the FPGA chip, which comprises the following steps: s1, sending a configuration upgrading file data packet to a first FPGA chip through a network chip; s2, judging whether a data preamble, a destination address and a source address of the configuration upgrade file data packet are correct or not through a network receiving module; s3, sending an instruction to a network sending module, so that the network sending module sends the state of the received data to an upper computer according to the format of an Ethernet upgrading data response packet; s4, analyzing address bits of data configuring the upgrade file data packet through a network analysis module, and judging which chip the upgrade file data packet is used for upgrading through the address bits of the data; s5, storing the analyzed data into a first nonvolatile memory through a first nonvolatile memory module; s6, storing the whole configuration upgrade file data packet, and enabling the first nonvolatile memory to be in a readable state after the data integrity check and the cyclic redundancy check are correct.

Preferably, the analyzing, by the network analyzing module, the address bits of the data configuring the upgrade file data packet, and determining, by the address bits of the data, which chip the upgrade configuring the upgrade file data packet is used for further includes: if the received configuration upgrade file data packet is used for upgrading the first FPGA chip, the second nonvolatile memory module reads upgrade data in the first nonvolatile memory through the first nonvolatile memory module, and then sends the upgrade data of the first FPGA chip to the second nonvolatile memory; if the received configuration upgrade file data packet is used for upgrading the second FPGA chip, the first serial port transceiver module reads upgrade data in the first nonvolatile memory through the first nonvolatile memory module, and the second FPGA chip receives the upgrade data sent by the first serial port transceiver module through the first serial port; if the received configuration upgrade file data packet is used for upgrading the singlechip chip, the second serial port transceiver module reads upgrade data in the first nonvolatile memory through the first nonvolatile memory module, and the singlechip chip receives the upgrade data sent by the second serial port transceiver module through the second serial port.

Preferably, the determining, by the network receiving module, whether the data preamble, the destination address, and the source address of the configuration upgrade file packet are correct further includes: s21, analyzing an MAC layer protocol of the configuration upgrade file through a network receiving module; s22, judging whether the 8Byte preamble, the destination MAC address and the source MAC address of the configuration upgrade file data packet are correct; s23, if the result of the step S22 is correct, the data length information of the configuration upgrade file data packet is sent to the first nonvolatile storage module, and the data information of the configuration upgrade file data packet is stored in the FIFO of the network receiving module; s24, verifying whether the last CRC check bit of the configuration upgrade file data packet is correct or not; s25, if the last CRC check bit is correct, reading out the data of the FIFO of the network receiving module, sending the data to the network analyzing module, and sending the information of the completion of data receiving to the network sending module; and if the last CRC check bit is in error, transmitting information of the received data error to a network transmitting module, and emptying the content in the FIFO.

Preferably, the sending instruction is sent to the network sending module, so that the network sending module sends the state of the received data to the upper computer according to the format of the ethernet upgrade data response packet further includes: s31, forming a packet of data according to the format of the Ethernet upgrading data response packet; s32, adding the state of the configuration upgrade file received by the receiving network receiving module; s33, adding CRC (cyclic redundancy check) of data configuring an upgrade file data packet, and sending the CRC to an upper computer through a network card chip; s34, receiving the data through the upper computer, and judging whether to send the next packet of data or resend the last packet of data.

Preferably, the analyzing, by the network analyzing module, the address bits of the data configuring the upgrade file data packet, and determining, by the address bits of the data, which chip the upgrade configuring the upgrade file data packet is used for further includes: s41, after receiving the configuration upgrade file data packet through a network analysis module, analyzing the configuration upgrade file data packet according to the format of an Ethernet upgrade data transmission frame; s42, obtaining address bits of data configuring an upgrade file data packet, wherein the value of the address bits is 0X01 and represents upgrade data of a first FPGA chip, the value of the address bits is 0X02 and represents upgrade data of a second FPGA chip, and the value of the address bits is 0X03 and represents upgrade data of a single chip microcomputer chip; s43, obtaining information of total length, total number of segments, data length of the configuration upgrade file data packet and data number of the configuration upgrade file data packet, judging whether the data number of the configuration upgrade file data packet is equal to the total number of segments of the data, and if not, obtaining UDP layer data of the configuration upgrade file data packet; s44, the obtained upgrade data are sent to the first nonvolatile storage module; s45, when the number of data segments of the configuration upgrade file data packet is equal to the total number of data segments, the configuration upgrade file data packet is the last packet of data of the configuration upgrade file; s46, verifying check bits of upgrade data of the configuration upgrade file.

Preferably, the storing the parsed data into the first nonvolatile memory through the first nonvolatile memory module further includes: s51, the first nonvolatile storage module stores each section of received upgrade data into the first nonvolatile storage; s52, after receiving all upgrade data in one configuration upgrade file, judging whether check bits of upgrade data of the configuration upgrade file of the network analysis module are correct; s53, if the check bit in the step S52 is correct, enabling the first nonvolatile memory to be in a readable state, and outputting a readable signal; s54, if the check bit in the step S52 is wrong, the first nonvolatile memory is in a reset state, the first nonvolatile memory is reset, and the upgrade data is cleared.

The technical scheme that this application provided can include following beneficial effect: the method can realize remote updating of a plurality of FPGA chips and singlechip chips, avoids the process of disassembling the device in special environment when the device is inconvenient to disassemble, reduces the process of burning the chips by using a special downloading device, and can complete upgrading by connecting the device with a computer through a network cable, thereby being more convenient and quick.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.

FIG. 1 is a schematic diagram of a remote upgrade apparatus based on an FPGA chip according to an embodiment of the present application;

FIG. 2 is a flow chart of a remote upgrade method based on an FPGA chip according to an embodiment of the present application;

FIG. 3 is a general workflow diagram of a remote upgrade method based on an FPGA chip, as shown in an embodiment of the present application;

FIG. 4 is a flow chart of a network receiving module according to an embodiment of the present application;

FIG. 5 is a flow chart of a network transmission module according to an embodiment of the present application;

FIG. 6 is a flow chart of a network resolution module according to an embodiment of the present application;

FIG. 7 is a flowchart illustrating operation of a first non-volatile memory module according to one embodiment of the present application;

FIG. 8 is an Ethernet upgrade data transport packet format as shown in one embodiment of the present application;

fig. 9 is an ethernet upgrade data reply packet format shown in an embodiment of the present application.

Detailed Description

Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first message may also be referred to as a second message, and similarly, a second message may also be referred to as a first message, without departing from the scope of the present application. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The following describes the technical scheme of the embodiments of the present application in detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a remote upgrade device based on an FPGA chip according to an embodiment of the present application.

Referring to fig. 1, a remote upgrade apparatus based on an FPGA chip, comprising: the device comprises an upper computer, a first board card, a second board card and a third board card.

The first board card is provided with a network card chip, a first non-volatile memory, a first FPGA chip, a second non-volatile memory, a first serial port and a second serial port. And the first board card is communicated with the upper computer through the network card chip. The second board comprises a second FPGA chip, and the third board card comprises a singlechip chip. The first board card and the second board card are communicated through a serial port, and the first board card and the third board card are communicated through the serial port.

The first FPGA chip comprises a network receiving module, a network analyzing module, a network sending module, a first nonvolatile storage module, a second nonvolatile storage module, a first serial port receiving and transmitting module and a second serial port receiving and transmitting module.

The network receiving module is used for carrying out network communication between the first FPGA chip and the upper computer, receiving a configuration upgrade file sent by the upper computer and analyzing an MAC layer protocol of the configuration upgrade file. The module is mainly used for carrying out network communication functions between a first FPGA chip and an upper computer, the upper computer sends configuration upgrade files of the first FPGA chip, a second FPGA chip and a single chip microcomputer chip to the first FPGA chip through a network card chip, the network receiving module analyzes an MAC layer protocol according to a agreed network protocol after receiving the configuration upgrade files, verifies whether received data frame heads are consistent with frame heads agreed by both sides, verifies whether final check bits of data are correct, and when the received configuration upgrade file frame heads are inconsistent or check bits are not checked, the configuration upgrade files are deleted, and when the received configuration upgrade file frame heads are consistent, the check codes are checked correctly, the configuration upgrade files are sent to the network analyzing module.

The network analysis module is used for receiving the configuration upgrade file sent by the network receiving module and analyzing the UDP layer protocol of the configuration upgrade file.

In one embodiment, the network receiving module is configured to parse the MAC layer protocol of the configuration upgrade file according to the network protocol, and is configured to verify whether the frame header of the data packet received by the configuration upgrade file is consistent with the agreed frame header, and is configured to verify whether the last check bit of the data packet of the configuration upgrade file is correct. That is, the module is mainly used for receiving and analyzing the UDP layer protocol of the configuration upgrade file sent by the network receiving module, and the network analyzing module analyzes the configuration upgrade file from the received configuration upgrade file, where the configuration upgrade file corresponds to one upgrade file of the first FPGA chip, the second FPGA chip or the single chip microcomputer chip.

In one embodiment, the UDP layer protocol of the configuration upgrade file includes: the network analysis module is used for sending the content of the upgrade file to the first nonvolatile storage module.

The network sending module is used for sending the state of the configuration upgrade file received by the network receiving module to the upper computer. The module is mainly used for network communication functions of the first FPGA chip and the upper computer, when the network receiving module encounters the condition that the frame heads of the received configuration upgrade files are inconsistent or check codes are not checked, the network receiving module sends a signal to the network sending module, and after receiving the signal, the network sending module sends the signal to the upper computer through the network card chip to tell the upper computer that the configuration upgrade files received by the first FPGA chip are wrong at the moment. When the network receiving module receives the configuration upgrade file correctly, the network receiving module also sends a signal to the network sending module, and after receiving the signal, the network sending module sends the signal to the upper computer through the network card chip to tell the upper computer that the configuration upgrade file received by the first FPGA chip is correct at the moment.

The first nonvolatile storage module is used for receiving the configuration upgrade file analyzed by the network analysis module and storing the configuration upgrade file into the first nonvolatile memory. The module is mainly used for storing the received upgrade file analyzed by the network analysis module into the first nonvolatile memory through the first nonvolatile memory module, so that when the subsequent first FPGA chip, second FPGA chip and single chip need to be upgraded, the corresponding upgrade file can be directly read from the first nonvolatile memory.

The second nonvolatile memory module is used for reading the configuration file used for upgrading the first FPGA chip in the first nonvolatile memory and storing the configuration upgrading file of the first FPGA chip into the second nonvolatile memory. The module is mainly used for upgrading a first FPGA chip, and when the first FPGA chip needs to be upgraded, the second nonvolatile memory module reads a configuration file for upgrading the first FPGA chip from the first nonvolatile memory through the first nonvolatile memory module. And the configuration file of the upgrade of the first FPGA chip is stored into a second nonvolatile memory through the second nonvolatile memory module, so that the upgrade of the first FPGA chip is completed.

The first serial port transceiver module is configured to read a configuration file for upgrading the second board card in the first nonvolatile memory, and send the configuration upgrade file of the second board card to the second board card through the first serial port. The module is mainly used for upgrading a second FPGA chip, and when the second FPGA chip needs to be upgraded, the first serial port receiving-transmitting module reads a configuration file for upgrading the second FPGA chip in the first nonvolatile memory through the first nonvolatile memory module. And the configuration file of the second FPGA chip upgrade is sent to the second board card through the first serial port transceiver module, so that the upgrade of the second FPGA chip is completed.

The second serial port transceiver module is used for reading the configuration file for upgrading the third board card in the first nonvolatile memory and sending the configuration upgrading file of the third board card to the third board card through the second serial port. The module is mainly used for upgrading the singlechip chip, and when the singlechip chip needs to be upgraded, the second serial port transceiver module reads the configuration file for upgrading the singlechip chip in the first nonvolatile memory through the first nonvolatile memory module. And the configuration file of the single chip microcomputer chip upgrade is sent to the third board card through the second serial port transceiver module, so that the upgrade of the single chip microcomputer chip is completed.

The device can realize remote updating of a plurality of FPGA chips and singlechip chips, avoids the process of disassembling the device in special environment when the device is inconvenient to disassemble, reduces the process of burning the chips by using a special downloader, and can complete upgrading by connecting the device with a computer through a network cable, thereby being more convenient and quick.

Fig. 2 is a flow chart of a remote upgrade method based on an FPGA chip. Fig. 3 is a general workflow diagram of a remote upgrade method based on an FPGA chip. Fig. 4 is a flow chart of a network receiving module. Fig. 5 is a flow chart of a network transmission module. Fig. 6 is a flow chart of the network resolution module. FIG. 7 is a flowchart of the operation of the first nonvolatile memory module. Fig. 8 is an ethernet upgrade data transport packet format. Fig. 9 is an ethernet upgrade data response packet format.

Referring to fig. 2, 8 and 9, a remote upgrade method based on FPGA chips includes:

s1, sending the configuration upgrading file data packet to a first FPGA chip through a network chip. Before this step, the method further comprises: firstly, a configuration upgrade file of equipment is put into upper computer software of a computer end, then the configuration upgrade file is transmitted in a subpacket mode according to a protocol of a MAC layer frame format in an Ethernet upgrade data transmission frame format, each frame of data comprises an 8Byte preamble, a 6Byte destination MAC address, a 6Byte source MAC address, a 2Byte data length bit, a 47-2047 Byte data information bit and a 4 ByteRC check bit, and the data information bit can be of any length when the last frame of data is transmitted. After the upgrade data of the configuration upgrade file is sent, check bits of the upgrade data in the upgrade configuration file are sent. And then the remote equipment network port receives the data packet of the configuration upgrade file.

Referring to fig. 4, S2, the network receiving module determines whether the data preamble, the destination address, and the source address of the configuration upgrade file packet are correct.

In one embodiment, the determining, by the network receiving module, whether the data preamble, the destination address, and the source address of the configuration upgrade file packet are correct further includes:

s21, analyzing the MAC layer protocol of the configuration upgrade file through the network receiving module.

S22, judging whether the 8Byte preamble, the destination MAC address and the source MAC address of the configuration upgrade file data packet are correct.

S23, if the result of the step S22 is correct, the data length information of the configuration upgrade file data packet is sent to the first nonvolatile storage module, and the data information of the configuration upgrade file data packet is stored in the FIFO of the network receiving module.

S24, verifying whether the last CRC check bit of the configuration upgrade file data packet is correct.

S25, if the last CRC check bit is correct, reading out the data of the FIFO of the network receiving module, sending the data to the network analyzing module, and sending the information of the completion of data receiving to the network sending module; and if the last CRC check bit is in error, transmitting information of the received data error to a network transmitting module, and emptying the content in the FIFO.

Referring to fig. 5, S3, a sending instruction is sent to the network sending module, so that the network sending module sends the state of the received data to the upper computer according to the format of the ethernet upgrade data response packet.

In one embodiment, the sending the instruction to the network sending module, causing the network sending module to send the status of the received data to the upper computer according to the format of the ethernet upgrade data response packet further includes:

s31, forming a packet of data according to the format of the Ethernet upgrading data response packet.

S32, adding the state of the configuration upgrade file received by the receiving network receiving module.

S33, adding CRC of data configuring the upgrade file data packet, and sending the CRC to the upper computer through the network card chip.

S34, receiving the data through the upper computer, and judging whether to send the next packet of data or resend the last packet of data.

Referring to fig. 6, S4, address bits of data configuring the upgrade file data packet are parsed by the network parsing module, and which chip the upgrade file data packet is used for is determined by the address bits of the data.

In one embodiment, the analyzing, by the network analyzing module, the address bits of the data configuring the upgrade file data packet, and determining, by the address bits of the data, which chip the upgrade configuring the upgrade file data packet is used for further includes: if the received configuration upgrade file data packet is used for upgrading the first FPGA chip, the second nonvolatile memory module reads upgrade data in the first nonvolatile memory through the first nonvolatile memory module, and then sends the upgrade data of the first FPGA chip to the second nonvolatile memory. If the received configuration upgrade file data packet is used for upgrading the second FPGA chip, the first serial port transceiver module reads upgrade data in the first nonvolatile memory through the first nonvolatile memory module, and the second FPGA chip receives the upgrade data sent by the first serial port transceiver module through the first serial port. If the received configuration upgrade file data packet is used for upgrading the singlechip chip, the second serial port transceiver module reads upgrade data in the first nonvolatile memory through the first nonvolatile memory module, and the singlechip chip receives the upgrade data sent by the second serial port transceiver module through the second serial port. That is, the corresponding chip completes the upgrade inside itself after receiving the upgrade data.

In one embodiment, the analyzing, by the network analyzing module, the address bits of the data configuring the upgrade file data packet, and determining, by the address bits of the data, which chip the upgrade configuring the upgrade file data packet is used for further includes:

s41, after receiving the configuration upgrade file data packet through the network analysis module, analyzing the configuration upgrade file data packet according to the format of the Ethernet upgrade data transmission frame.

S42, obtaining address bits of data configuring an upgrade file data packet, wherein the value of the address bits is 0X01 and represents upgrade data of the first FPGA chip, the value of the address bits is 0X02 and represents upgrade data of the second FPGA chip, and the value of the address bits is 0X03 and represents upgrade data of the single chip microcomputer chip.

S43, obtaining information of total length, total number of segments, data length of the configuration upgrade file data packet and data number of the configuration upgrade file data packet, judging whether the data number of the configuration upgrade file data packet is equal to the total number of segments of the data, and if not, obtaining UDP layer data of the configuration upgrade file data packet;

s44, the obtained upgrade data are sent to the first nonvolatile storage module;

s45, when the number of data segments of the configuration upgrade file data packet is equal to the total number of data segments, the configuration upgrade file data packet is the last packet of data of the configuration upgrade file;

s46, verifying check bits of upgrade data of the configuration upgrade file.

Referring to fig. 7, S5, the parsed data is stored in the first nonvolatile memory through the first nonvolatile memory module.

In one embodiment, storing the parsed data into the first nonvolatile memory through the first nonvolatile memory module further includes:

s51, the first nonvolatile storage module stores each section of received upgrade data into the first nonvolatile storage;

s52, after receiving all upgrade data in one configuration upgrade file, judging whether check bits of upgrade data of the configuration upgrade file of the network analysis module are correct;

s53, if the check bit in the step S52 is correct, enabling the first nonvolatile memory to be in a readable state, and outputting a readable signal;

s54, if the check bit in the step S52 is wrong, the first nonvolatile memory is in a reset state, the first nonvolatile memory is reset, and the upgrade data is cleared.

S6, storing the whole configuration upgrade file data packet, and enabling the first nonvolatile memory to be in a readable state after the data integrity check and the cyclic redundancy check are correct.

In one embodiment, after step S6, the method further includes:

s71, judging whether the address bit of the data analyzed by the network analysis module is 0x01;

s72, if the address bit of the data is 0x01, the second nonvolatile memory module reads the upgrade data in the first nonvolatile memory through the first nonvolatile memory module;

and S73, writing the read upgrade data into the second nonvolatile memory.

In one embodiment, after step S6, the method further includes:

s81, judging whether address bits of data analyzed by the network analysis module are 0x02;

s82, if the address bit of the data is 0x02, the first serial port transceiver module reads the upgrade data in the first nonvolatile memory through the first nonvolatile memory module;

s83, the read upgrade data are sent to the first serial port, and the upgrade data are sent to the second FPGA chip through the first serial port.

In one embodiment, after step S6, the method further includes:

s91, judging whether address bits of data analyzed by the network analysis module are 0x03;

s92, if the address bit of the data is 0x03, the second serial port transceiver module reads the upgrade data in the first nonvolatile memory through the first nonvolatile memory module;

s93, the read upgrade data are sent to the second serial port, and the upgrade data are sent to the singlechip chip through the second serial port.

The technical scheme that this application provided can include following beneficial effect: the upgrade data in the first nonvolatile memory is read through the second nonvolatile memory module, and then the upgrade data of the first FPGA chip is sent to the second nonvolatile memory; setting a first serial port transceiver module, reading upgrade data in a first nonvolatile memory through a first nonvolatile memory module, and then sending the upgrade data to a second FPGA chip through a first serial port; and setting a second serial port receiving and transmitting module, reading the upgrade data in the first nonvolatile memory through the first nonvolatile memory module, and sending the upgrade data to the singlechip chip through the second serial port. Namely, the corresponding chip finishes upgrading in the chip after receiving the upgrading data, so that a plurality of FPGA chips and singlechip chips can be updated remotely, the process that the equipment in a special environment needs to be disassembled when the equipment is inconvenient to disassemble is avoided in an implementation manner, the process of burning the chip by using a special downloading device is reduced, and the equipment and a computer are connected by using a network cable, so that the upgrading can be finished through an upper computer, and the method is more convenient and quicker. According to the remote upgrading method based on the FPGA, the equipment chip is upgraded in a network cable mode, equipment can be upgraded in an environment in which the equipment is not easy to disassemble, and meanwhile, the upgrading function of multiple chips in the equipment is guaranteed.

The embodiments of the present application have been described above, the foregoing description is exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A remote upgrade apparatus based on an FPGA chip, comprising:

the device comprises an upper computer, a first board card, a second board card and a third board card;

the first board card is provided with a network card chip, a first non-volatile memory, a first FPGA chip, a second non-volatile memory, a first serial port and a second serial port;

the first board card is communicated with the upper computer through the network card chip;

the first FPGA chip comprises a network receiving module, a network analyzing module, a network sending module, a first nonvolatile storage module, a second nonvolatile storage module, a first serial port receiving and transmitting module and a second serial port receiving and transmitting module;

the network receiving module is used for carrying out network communication between the first FPGA chip and the upper computer, receiving a configuration upgrade file sent by the upper computer and analyzing an MAC layer protocol of the configuration upgrade file;

the network analysis module is used for receiving the configuration upgrade file sent by the network receiving module and analyzing the UDP layer protocol of the configuration upgrade file;

the network sending module is used for sending the state of the configuration upgrade file received by the network receiving module to the upper computer;

the first nonvolatile storage module is used for receiving the configuration upgrade file analyzed by the network analysis module and storing the configuration upgrade file into the first nonvolatile memory;

the second nonvolatile memory module is used for reading the configuration file used for upgrading the first FPGA chip in the first nonvolatile memory and storing the configuration upgrading file of the first FPGA chip into the second nonvolatile memory;

the first serial port transceiver module is configured to read a configuration file for upgrading the second board card in the first nonvolatile memory, and send the configuration upgrade file of the second board card to the second board card through a first serial port;

the second serial port transceiver module is used for reading the configuration file for upgrading the third board card in the first nonvolatile memory and sending the configuration upgrading file of the third board card to the third board card through the second serial port.

2. The FPGA chip-based remote upgrade apparatus according to claim 1, wherein: the network receiving module is used for analyzing the MAC layer protocol of the configuration upgrade file according to the network protocol, verifying whether the frame header of the data packet of the received configuration upgrade file is consistent with the agreed frame header, and verifying whether the last check bit of the data packet of the configuration upgrade file is correct.

3. The FPGA chip-based remote upgrade apparatus according to claim 2, wherein: the UDP layer protocol for configuring the upgrade file comprises the following steps: the network analysis module is used for sending the content of the upgrade file to the first nonvolatile storage module.

4. The FPGA chip-based remote upgrade apparatus of claim 3, wherein: the second board card comprises a second FPGA chip, and the third board card comprises a singlechip chip.

5. The remote upgrading method based on the FPGA chip is characterized by comprising the following steps of:

s1, sending a configuration upgrading file data packet to a first FPGA chip through a network chip;

s2, judging whether a data preamble, a destination address and a source address of the configuration upgrade file data packet are correct or not through a network receiving module;

s3, sending an instruction to a network sending module, so that the network sending module sends the state of the received data to an upper computer according to the format of an Ethernet upgrading data response packet;

s4, analyzing address bits of data configuring the upgrade file data packet through a network analysis module, and judging which chip the upgrade file data packet is used for upgrading through the address bits of the data;

s5, storing the analyzed data into a first nonvolatile memory through a first nonvolatile memory module;

6. The remote upgrade method based on the FPGA chip according to claim 5, wherein: the analyzing, by the network analyzing module, address bits of data configuring the upgrade file data packet, and determining, by the address bits of the data, which chip the upgrade file data packet is used for, further includes:

if the received configuration upgrade file data packet is used for upgrading the first FPGA chip, the second nonvolatile memory module reads upgrade data in the first nonvolatile memory through the first nonvolatile memory module, and then sends the upgrade data of the first FPGA chip to the second nonvolatile memory;

if the received configuration upgrade file data packet is used for upgrading the second FPGA chip, the first serial port transceiver module reads upgrade data in the first nonvolatile memory through the first nonvolatile memory module, and the second FPGA chip receives the upgrade data sent by the first serial port transceiver module through the first serial port;

if the received configuration upgrade file data packet is used for upgrading the singlechip chip, the second serial port transceiver module reads upgrade data in the first nonvolatile memory through the first nonvolatile memory module, and the singlechip chip receives the upgrade data sent by the second serial port transceiver module through the second serial port.

7. The remote upgrade method based on the FPGA chip according to claim 6, wherein: the step of judging whether the data preamble, the destination address and the source address of the configuration upgrade file data packet are correct through the network receiving module further comprises the following steps:

s21, analyzing an MAC layer protocol of the configuration upgrade file through a network receiving module;

s22, judging whether the 8Byte preamble, the destination MAC address and the source MAC address of the configuration upgrade file data packet are correct;

s23, if the result of the step S22 is correct, the data length information of the configuration upgrade file data packet is sent to the first nonvolatile storage module, and the data information of the configuration upgrade file data packet is stored in the FIFO of the network receiving module;

s24, verifying whether the last CRC check bit of the configuration upgrade file data packet is correct or not;

8. The remote upgrade method based on FPGA chips of claim 7, wherein: the sending instruction is sent to the network sending module, so that the network sending module sends the state of the received data to the upper computer according to the format of the Ethernet upgrading data response packet, and the method further comprises the following steps:

s31, forming a packet of data according to the format of the Ethernet upgrading data response packet;

s32, adding the state of the configuration upgrade file received by the receiving network receiving module;

s33, adding CRC (cyclic redundancy check) of data configuring an upgrade file data packet, and sending the CRC to an upper computer through a network card chip;

9. The remote upgrade method based on FPGA chips of claim 8, wherein: the analyzing, by the network analyzing module, address bits of data configuring the upgrade file data packet, and determining, by the address bits of the data, which chip the upgrade file data packet is used for, further includes:

s41, after receiving the configuration upgrade file data packet through a network analysis module, analyzing the configuration upgrade file data packet according to the format of an Ethernet upgrade data transmission frame;

s42, obtaining address bits of data configuring an upgrade file data packet, wherein the value of the address bits is 0X01 and represents upgrade data of a first FPGA chip, the value of the address bits is 0X02 and represents upgrade data of a second FPGA chip, and the value of the address bits is 0X03 and represents upgrade data of a single chip microcomputer chip;

s46, verifying check bits of upgrade data of the configuration upgrade file.

10. The FPGA chip-based remote upgrade method according to claim 9, wherein: the storing the parsed data into the first nonvolatile memory through the first nonvolatile memory module further includes: