CN117666748A - Power-down time delay circuit, system and controller - Google Patents
Power-down time delay circuit, system and controller Download PDFInfo
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- CN117666748A CN117666748A CN202311709979.5A CN202311709979A CN117666748A CN 117666748 A CN117666748 A CN 117666748A CN 202311709979 A CN202311709979 A CN 202311709979A CN 117666748 A CN117666748 A CN 117666748A
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- 238000004146 energy storage Methods 0.000 claims abstract description 140
- 238000013500 data storage Methods 0.000 claims abstract description 13
- 238000007599 discharging Methods 0.000 claims description 22
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 15
- 238000012544 monitoring process Methods 0.000 description 8
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- General Engineering & Computer Science (AREA)
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Abstract
The invention provides a power-down delay circuit, a power-down delay system and a controller, wherein the power-down delay circuit comprises a control module and an energy storage module; the input end of the control module is connected with a power supply and used for detecting power failure; one input end of the energy storage module is connected with the power supply, the other input end of the energy storage module is connected with the output end of the control module, and the output end of the energy storage module is connected with a rear-stage circuit; when the power supply is powered off, the control module controls the energy storage module to supply power to the rear-stage circuit, and when data storage is completed, the control module controls the energy storage module to stop supplying power. The invention can supply power for the post-stage circuit when power is off, and can stop supplying power after the post-stage circuit finishes data storage, thereby avoiding the impact on the post-stage circuit caused by low voltage.
Description
Technical Field
The invention relates to the technical field of power supplies, in particular to a power-down delay circuit, a power-down delay system and a controller.
Background
In order to prevent data information loss caused by abnormal power failure, most controllers currently have a power failure delay function, and normal power supply can be kept for a period of time after an input power supply is disconnected, so that the controllers can continue to work to store data information.
Most of the current power-down maintaining circuits can maintain the normal work of the controller in a certain time when the input power supply is powered off, so that some important data can be stored conveniently, however, after the storage of the data information is finished by the controller, the capacitor in the circuit still continuously discharges the subsequent circuit, so that the voltage of the capacitor is reduced to cause voltage fluctuation, and the chip is impacted.
Disclosure of Invention
The invention provides a power-down delay circuit, a power-down delay system and a controller, and aims to solve the problem of voltage reduction caused by continuous discharge of the current power-down delay circuit after the controller finishes storing data information.
In a first aspect, the invention provides a power-down delay circuit, which comprises a control module and an energy storage module; the input end of the control module is connected with a power supply and used for detecting power failure; one input end of the energy storage module is connected with the power supply, the other input end of the energy storage module is connected with the output end of the control module, and the output end of the energy storage module is connected with a rear-stage circuit; when the power supply is powered off, the control module controls the energy storage module to supply power to the rear-stage circuit, and when data storage is completed, the control module controls the energy storage module to stop supplying power.
Further, the energy storage module comprises a charging switch, an energy storage piece, a discharging switch and a boosting circuit; the input end of the charging switch is connected with the power supply, the output end of the charging switch is connected with the input end of the energy storage part, the output end of the energy storage part is connected with the input end of the discharging switch, the output end of the discharging switch is connected with the input end of the boosting circuit, the discharging switch is also connected with the control module, and the output end of the boosting circuit is connected with the rear-stage circuit.
Further, the energy storage element is a super capacitor.
Further, the battery module is connected with the energy storage module and the control module respectively.
Further, the battery module includes a charge control circuit and a rechargeable battery; the input end of the charging control circuit is respectively connected with the energy storage module and the control module, the output end of the charging control circuit is connected with the input end of the rechargeable battery, and the output end of the rechargeable battery is connected with the rear-stage circuit.
Further, the power supply system also comprises a monitoring module, wherein the input end of the monitoring module is connected with the power supply, and the output end of the monitoring module is connected with the rear-stage circuit.
In a second aspect, the invention further provides a power-down delay system, which comprises a power supply, a post-stage circuit and the power-down delay circuit.
Further, the power supply is connected with the control module of the power-down delay circuit and the energy storage module, and the energy storage module is connected with the rear-stage circuit.
Further, the rear-stage circuit comprises a plurality of functional circuits, each functional circuit comprises a sub power supply, and each sub power supply is respectively connected with the power supply and the energy storage module.
In a third aspect, the present invention further provides a controller, where the controller includes the power-down delay system described in any one of the above.
The power-down time-delay circuit, the power-down time-delay system and the controller disclosed by the invention comprise a control module and an energy storage module, wherein the control module is connected with a power supply source and can perform power-down detection, the energy storage module is connected with the power supply source and can perform charging, when the control module detects that the power supply source is powered down, the control module controls the energy storage module to supply power to a rear-stage circuit, so that the rear-stage circuit can perform data storage when the power supply source is powered down, and when the control module detects that all data are stored, the control module stops supplying power, and the impact of voltage fluctuation caused by the fact that the voltage of the energy storage module is too low on chips in the rear-stage circuit is avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit block diagram of a power down delay circuit provided by a first embodiment of the present invention;
FIG. 2 is a timing diagram of a power down delay circuit according to an embodiment of the present invention;
FIG. 3 is a circuit block diagram of a power down delay circuit provided by a second embodiment of the present invention;
FIG. 4 is a circuit block diagram of a power down delay circuit provided by a third embodiment of the present invention;
FIG. 5 is a circuit block diagram of a power down delay circuit provided by a fourth embodiment of the present invention;
FIG. 6 is a circuit block diagram of a power down delay system provided by a fifth embodiment of the present invention; and
fig. 7 is a circuit block diagram of a power down delay system according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In addition, directional terms such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc. as used herein refer only to the attached drawings and the direction of the product in use. Accordingly, directional terminology is used to describe and understand the invention and is not limiting of the invention. In addition, in the drawings, structures similar or identical to those of the drawings are denoted by the same reference numerals.
Referring to fig. 1 to 6, fig. 1 is a circuit block diagram of a power-down delay circuit 100 according to a first embodiment of the present invention; FIG. 2 is a timing diagram of a power down delay circuit 100 according to an embodiment of the present invention; fig. 3 is a circuit block diagram of a power down delay circuit 100 according to a second embodiment of the present invention; fig. 4 is a circuit block diagram of a power-down delay circuit 100 according to a third embodiment of the present invention; fig. 5 is a circuit block diagram of a power-down delay circuit 100 according to a fourth embodiment of the present invention; fig. 6 is a circuit block diagram of a power-down delay system according to a fifth embodiment of the present invention. As shown in fig. 1, the power-down delay circuit 100 includes a control module 20 and an energy storage module 10; the input end of the control module 20 is connected with the power supply 200 and is used for power failure detection; an input end of the energy storage module 10 is connected with the power supply 200, another input end of the energy storage module 10 is connected with an output end of the control module 20, and an output end of the energy storage module 10 is connected with a rear-stage circuit 300; when the power supply 200 is powered down, the control module 20 controls the energy storage module 10 to supply power to the post-stage circuit 300, and when data storage is completed, the control module 20 controls the energy storage module 10 to stop supplying power.
Specifically, the power-down delay circuit 100 may include a control module 20 and an energy storage module 10, where the control module 20 may be a control circuit of the controller, and may include a control chip, and the control module 20 may also be a separately configured chip for controlling the power-down delay, where the chip is connected to the control circuit of the controller. Preferably, the control module 20 is a control circuit of a controller. The input end of the control module 20 is connected to the power supply 200, and is used for detecting whether the power supply 200 is powered down. The power down signal may be a low level when the power supply 200 is normally powered, a high level when the power supply 200 is powered down, or a high level when the power supply 200 is normally powered, and a low level when the power supply 200 is powered down. The energy storage module 10 may include an energy storage capacitor, which may store energy through the power supply 200, and discharge to supply power to the back-end circuit 300 when the power supply 200 is powered down. The input end of the energy storage module 10 is connected with the power supply 200, the output end of the energy storage module 10 is connected with the back-stage circuit 300, meanwhile, the energy storage module 10 is also connected with the control module 20, and the control module 20 controls whether to supply power for the back-stage circuit 300.
When normal power is supplied, the power-down signal is at a low level, the control module 20 and the energy storage module 10 detect the power-down signal at the low level, at this time, the energy storage module 10 is communicated with the power supply 200, the power supply 200 charges the energy storage module 10, and meanwhile, the control module 20 outputs an enabling signal to the energy storage module 10 to control the energy storage module 10 to stop discharging, and the power supply 200 supplies power to all circuits. When the power supply 200 is powered down, the power-down signal is changed from low level to high level, the control module 20 and the energy storage module 10 detect that the power-down signal is high level, the energy storage module 10 is disconnected from the power supply 200, the power supply 200 stops supplying power to the energy storage module 10, meanwhile, the control module 20 outputs an enabling signal to the energy storage module 10, the energy storage module 10 is controlled to discharge for the subsequent circuit 300, and the energy storage module 10 supplies power for all circuits. While the energy storage module 10 is powered, the control module 20 will detect all the subsequent circuits 300, and determine whether the devices in the subsequent circuits 300 that need to perform data storage complete data storage, for example, EEPROM (Electrically Erasable Programmable read onlymemory), EMMC (Embedded Multi Media Card), etc. When the control module 20 detects that all the devices needing to store data complete data storage, the control module 20 stops sending the enabling signal, and the energy storage module 10 does not supply power to the later-stage circuit 300 any more, so that the energy storage module 10 is in a discharge state all the time, and voltage fluctuation caused by voltage reduction of the energy storage module 10 is avoided.
As shown in fig. 2, fig. 2 is a timing diagram of the power-down delay circuit 100, ENA and ENB are enable signals, the energy storage module 10 is charged when the enable signal ENA is at a low level, and the energy storage module 10 is discharged when the enable signal ENA is at a high level. That is, when the control module 20 outputs the enable signal ENA to be at a high level, the energy storage module 10 supplies power to the post-stage circuit 300, and when the control module 20 stops outputting the enable signal ENA, the energy storage module 10 stops discharging. In fig. 2 a is a time when the power supply 200 is powered down, the power down signal is changed from low level to high level, and when the control module 20 detects that the power down signal is high level, the energy storage module 10 is output an enable signal ENA, the energy storage module 10 starts to discharge, and the subsequent power supply is kept unchanged. In fig. 2 b, when the control module 20 detects that all data are stored, the control module 20 stops outputting the enable signal ENA, the energy storage module 10 stops supplying power, the subsequent power supply starts to drop, and the post-stage circuit 300 stops working.
Referring to fig. 3, as a further embodiment, the energy storage module 10 includes a charge switch 11, an energy storage member 12, a discharge switch 13, and a boost circuit 14; the input end of the charging switch 11 is connected with the power supply 200, the output end of the charging switch 11 is connected with the input end of the energy storage element 12, the output end of the energy storage element 12 is connected with the input end of the discharging switch 13, the output end of the discharging switch 13 is connected with the input end of the boost circuit 14, the discharging switch 13 is also connected with the control module 20, and the output end of the boost circuit 14 is connected with the rear-stage circuit 300.
Further, the energy storage element 12 is a super capacitor.
The energy storage module 10 includes a charge switch 11, an energy storage element 12, a discharge switch 13, and a boost circuit 14. The charging switch 11 may be connected when receiving a low level signal, and disconnected when receiving a high level signal, and then when the power supply 200 is normal, the power-down signal is low level, the charging switch 11 receives the low level signal, the charging switch 11 is turned on, the power supply 200 supplies power to the energy storage element 12 through the charging switch 11, when the power supply 200 is powered down, the power-down signal is high level, the charging switch 11 receives the high level signal, the charging switch 11 is disconnected, and the power supply 200 stops supplying power to the energy storage element 12. The discharging switch 13 is connected with the control module 20, when receiving the enable signal ENA output by the control module 20, the discharging switch 13 is turned on, the energy storage 12 starts discharging, and the booster circuit 14 supplies power to the subsequent circuit 300, when the discharging switch 13 does not receive the enable signal ENA, the discharging switch 13 is turned off, and the energy storage 12 stops discharging. Preferably, the energy storage element 12 may be a super capacitor.
Referring to fig. 4, as a further embodiment, a battery module 30 is further included, and the battery module 30 is connected to the energy storage module 10 and the control module 20, respectively.
The input end of the battery module 30 is connected to the energy storage module 10 and the control module 20, respectively, on one hand, the energy storage module 10 can charge the battery module 30, and on the other hand, the battery module 30 receives the control of the control module 20. When the power supply 200 is normal, the energy storage module 10 charges, when the power supply 200 is powered down, the energy storage module 10 supplies power to the post-stage circuit 300, when all data are stored, the energy storage module 10 stops supplying power to the post-stage circuit 300, meanwhile, the control module 20 controls the battery module 30 to be conducted, and the energy storage module 10 charges the battery module 30, so that electric energy can be saved. In addition, when the power supply 200 is normal, the control module 20 is powered by the internal power supply until the control module 20 is completely powered down, and when the control module 20 is completely powered down, the battery module 30 continues to supply power to the clock circuit to maintain the timing function. The battery module 30 can also be used as a battery of the encoder, and is charged by the energy storage module 10 after power failure, and after power failure, the battery module 30 supplies power to the encoder to consume the electric quantity of the battery module 30, so that the energy storage module 10 can supply power to the battery module 30 when power failure occurs.
As shown in fig. 2, ENB in fig. 2 is an enable signal for the control module 20 to control the battery module 30, and when the enable signal ENB is at a high level, the battery module 30 is turned off, and when the enable signal ENB is at a low level, the battery module 30 is turned on. As shown in fig. 2, on the basis of providing the battery module 30, the control logic of the power-down delay circuit 100 provided by the invention is as follows: the control module 20 detects whether the power supply 200 is powered down, if the power supply 200 is powered down at the time a, the control module 20 and the energy storage module 10 detect that the power down signal is at a high level, the energy storage module 10 is disconnected from the power supply 300, and meanwhile, the control module 20 outputs an enable signal ENA to the energy storage module 10 to control the energy storage module 10 to discharge. During the time from time a to time b, the related circuits in the circuit store data, and during time b, all the circuits finish storing the data, the control module 20 stops outputting the enable signal ENA and outputs the enable signal ENB to the battery module 30, so that the battery module 30 is turned on, and at this time, the enable signal ENB is at a low level, and the energy storage module 10 charges the battery module 30. After time b, if the enable signal ENA is low and the enable signal ENB is high, the energy storage module 10 stops discharging and is charged by the power supply 300.
Referring to fig. 5, further, the battery module 30 includes a charge control circuit 31 and a rechargeable battery 32; the input end of the charging control circuit 31 is respectively connected with the energy storage module 10 and the control module 20, the output end of the charging control circuit 31 is connected with the input end of the rechargeable battery 32, and the output end of the rechargeable battery 32 is connected with the back-stage circuit 300.
The charging control circuit 31 is connected to the control module 20, and is configured to receive an enable signal of the control module 20, when the enable signal ENB received by the charging control circuit 31 is at a high level, the charging control circuit 31 is turned off, and when the enable signal ENB received by the charging control circuit 31 is at a low level, the charging control circuit 31 is turned on, and the energy storage module 10 charges the rechargeable battery 32. Meanwhile, the rechargeable battery 32 is also connected to a part of the circuits in the post-stage circuit 300, and is used for supplying power to the part of the circuits in the post-stage circuit 300 when the power supply 200 is powered up normally.
Referring to fig. 6, further, the device further comprises a monitoring module 40, an input end of the monitoring module 40 is connected with the power supply 200, and an output end of the monitoring module 40 is connected with the back-end circuit 300.
The monitoring module 40 is connected between the power supply 200 and the post-stage circuit 300, and is used for ensuring the safety of the post-stage circuit 300, and when the power supply 200 is abnormal, for example, over-temperature, over-voltage, over-current and under-current, the monitoring module 40 is disconnected, so as to avoid the damage of the power supply 200 to the post-stage circuit 300.
The present invention also provides a power-down delay system, which includes the power supply 200, the post-stage circuit 300, and the power-down delay circuit 100 according to any one of the above embodiments.
As a further embodiment, the power supply 200 is connected to the control module 20 of the power-down delay circuit 100 and the energy storage module 10, and the energy storage module 10 is connected to the post-stage circuit 300.
The power-down delay circuit 100 may include a control module 20 and an energy storage module 10, where the control module 20 may be a control circuit of a controller, and may include a control chip, and the control module 20 may also be a separately configured chip for controlling the power-down delay, where the chip is connected to the control circuit of the controller. Preferably, the control module 20 is a control circuit of a controller. The input end of the control module 20 is connected to the power supply 200, and is used for detecting whether the power supply 200 is powered down. The power down signal may be low when the power supply 200 is normally powered, high when the power supply 200 is powered down, or high when the power supply 200 is normally powered down, and low when the power supply 200 is powered down. The energy storage module 10 may include an energy storage capacitor, which may store energy through the power supply 200, and discharge to supply power to the back-end circuit 300 when the power supply 200 is powered down. The input end of the energy storage module 10 is connected with the power supply 200, the output end of the energy storage module 10 is connected with the back-stage circuit 300, meanwhile, the energy storage module 10 is also connected with the control module 20, and the control module 20 controls whether to supply power for the back-stage circuit 300.
When normal power is supplied, the power-down signal is at a low level, the control module 20 and the energy storage module 10 detect the power-down signal at the low level, at this time, the energy storage module 10 is communicated with the power supply 200, the power supply 200 charges the energy storage module 10, and meanwhile, the control module 20 outputs an enabling signal to the energy storage module 10 to control the energy storage module 10 to stop discharging, and the power supply 200 supplies power to all circuits. When the power supply 200 is powered down, the power-down signal is changed from low level to high level, the control module 20 and the energy storage module 10 detect that the power-down signal is high level, the energy storage module 10 is disconnected from the power supply 200, the power supply 200 stops supplying power to the energy storage module 10, meanwhile, the control module 20 outputs an enabling signal to the energy storage module 10, the energy storage module 10 is controlled to discharge for the subsequent circuit 300, and the energy storage module 10 supplies power for all circuits. While the energy storage module 10 is powered, the control module 20 will detect all the post-stage circuits 300, and confirm whether the devices in the post-stage circuits 300 that need to store data, such as EEPROM, EMMC, etc., complete data storage. When the control module 20 detects that all the devices needing to store data complete data storage, the control module 20 stops sending the enabling signal, and the energy storage module 10 does not supply power to the later-stage circuit 300 any more, so that the energy storage module 10 is in a discharge state all the time, and voltage fluctuation caused by voltage reduction of the energy storage module 10 is avoided.
As shown in fig. 2, fig. 2 is a timing diagram of the power-down delay circuit 100, ENA and ENB are enable signals, the energy storage module 10 is charged when the enable signal ENA is at a low level, and the energy storage module 10 is discharged when the enable signal ENA is at a high level. That is, when the control module 20 outputs the enable signal ENA to be at a high level, the energy storage module 10 supplies power to the post-stage circuit 300, and when the control module 20 stops outputting the enable signal ENA, the energy storage module 10 stops discharging. In fig. 2 a is a time when the power supply 200 is powered down, the power down signal is changed from low level to high level, and when the control module 20 detects that the power down signal is high level, the energy storage module 10 is output an enable signal ENA, the energy storage module 10 starts to discharge, and the subsequent power supply is kept unchanged. In fig. 2 b, when the control module 20 detects that all data are stored, the control module 20 stops outputting the enable signal ENA, the energy storage module 10 stops supplying power, the subsequent power supply starts to drop, and the post-stage circuit 300 stops working.
Referring to fig. 7, as a further embodiment, the post-stage circuit 300 includes a plurality of functional circuits 310, each of the functional circuits 310 includes a sub-power supply, and each of the sub-power supplies is connected to the power supply 200 and the energy storage module 10, respectively.
The post-stage circuit 300 may include a plurality of functional circuits 310 for implementing different functions, where each functional circuit 310 includes a sub-power supply, which may be a power chip for supplying power to the circuit where it is located, and all the sub-power supplies are connected to the power supply 200 and the energy storage module 10.
The invention also provides a controller comprising the power down delay system of any of the above embodiments.
The power-down time-delay circuit, the power-down time-delay system and the controller can supply power to the rear-stage circuit through the energy storage module when the power supply is powered down, so that the rear-stage circuit can finish data storage, and after the rear-stage circuit finishes data storage, the energy storage module stops discharging, so that voltage fluctuation caused by too low voltage of the energy storage module is avoided, and impact on the rear-stage circuit is avoided.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. A power down delay circuit, comprising:
the input end of the control module is connected with a power supply and used for detecting power failure;
the power supply device comprises an energy storage module, a control module and a power supply, wherein one input end of the energy storage module is connected with the power supply, the other input end of the energy storage module is connected with the output end of the control module, and the output end of the energy storage module is connected with a rear-stage circuit;
when the power supply is powered off, the control module controls the energy storage module to supply power to the rear-stage circuit, and when data storage is completed, the control module controls the energy storage module to stop supplying power.
2. The power down delay circuit of claim 1 wherein the energy storage module comprises a charge switch, an energy storage, a discharge switch, and a boost circuit;
the input end of the charging switch is connected with the power supply, the output end of the charging switch is connected with the input end of the energy storage part, the output end of the energy storage part is connected with the input end of the discharging switch, the output end of the discharging switch is connected with the input end of the boosting circuit, the discharging switch is also connected with the control module, and the output end of the boosting circuit is connected with the rear-stage circuit.
3. The power down delay circuit of claim 2 wherein the energy storage element is a super capacitor.
4. The power down delay circuit of claim 1 further comprising a battery module connected to the energy storage module and the control module, respectively.
5. The power down delay circuit of claim 4 wherein the battery module comprises a charge control circuit and a rechargeable battery;
the input end of the charging control circuit is respectively connected with the energy storage module and the control module, the output end of the charging control circuit is connected with the input end of the rechargeable battery, and the output end of the rechargeable battery is connected with the rear-stage circuit.
6. The power down delay circuit of claim 1 further comprising a monitor module, wherein an input of the monitor module is connected to the power supply, and an output of the monitor module is connected to the back-end circuit.
7. A power-down delay system comprising a power supply, a post-stage circuit, and a power-down delay circuit as claimed in any one of claims 1 to 6.
8. The power down delay system of claim 7 wherein the power supply is connected to a control module of the power down delay circuit and an energy storage module, the energy storage module being connected to the back-end circuit.
9. The power down delay system of claim 7 wherein said back-end circuit comprises a plurality of functional circuits, each of said functional circuits comprising a sub-power supply, each of said sub-power supplies being respectively connected to said power supply and said energy storage module.
10. A controller comprising a power down delay system as claimed in any one of claims 7 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311709979.5A CN117666748A (en) | 2023-12-13 | 2023-12-13 | Power-down time delay circuit, system and controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311709979.5A CN117666748A (en) | 2023-12-13 | 2023-12-13 | Power-down time delay circuit, system and controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117666748A true CN117666748A (en) | 2024-03-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311709979.5A Pending CN117666748A (en) | 2023-12-13 | 2023-12-13 | Power-down time delay circuit, system and controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117666748A (en) |
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2023
- 2023-12-13 CN CN202311709979.5A patent/CN117666748A/en active Pending
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