CN117666704A - Clock management circuit and clock management method - Google Patents

Abstract

The invention discloses a clock management circuit and a clock management method, which are used for managing an operation clock of a computing circuit, wherein the computing circuit changes the level of a state signal according to an interrupt signal. The clock management circuit includes: a delay circuit for delaying a wake-up interrupt signal to generate a delayed wake-up interrupt signal; and a clock control circuit coupled to the delay circuit for generating the operation clock according to a reference clock, generating the wake-up interrupt signal according to the status signal, and adjusting the frequency of the operation clock according to the delayed wake-up interrupt signal.

Description

Clock management circuit and clock management method

Technical Field

The present invention relates to clock management, and more particularly to a clock management circuit and clock management method for a high-speed circuit.

Background

Generally, a computing circuit consumes less power in an idle state (idle state) than in an active state (active state) due to a clock gating (clock gating) relationship. When the computing circuit is switched from an idle state to an active state, i.e., when the computing circuit is awakened (wake up), a momentary current peak (i.e., current surge) is often generated due to the clock gating, resulting in a drop (IR drop) in the supply voltage on the printed circuit board in which the computing circuit is located. When the reduction of the supply voltage on the printed circuit board exceeds the tolerance value, unexpected behavior of the calculation circuit can occur, so that the function of the circuit is disabled. Although capacitors can be added to the printed circuit board to stabilize the supply voltage, the addition of capacitors also results in increased costs. The present disclosure thus proposes a circuit design to mitigate current spikes (i.e., mitigate supply voltage drops).

The computing circuit is, for example, a central processing unit, a core (core) of the central processing unit, a microcontroller, a microprocessor, or other high-speed circuit. The operating state may also be referred to as a full speed state (full speed state). The idle state may also be referred to as a stationary state or an idle state.

Disclosure of Invention

In view of the shortcomings of the prior art, an object of the present invention is to provide a clock management circuit and a clock management method, so as to improve the shortcomings of the prior art.

An embodiment of the present invention provides a clock management circuit for managing an operation clock of a computing circuit, the computing circuit changing a level of a status signal according to an interrupt signal, the clock management circuit comprising: a delay circuit for delaying a wake-up interrupt signal to generate a delayed wake-up interrupt signal; and a clock control circuit coupled to the delay circuit for generating the operation clock according to a reference clock, generating the wake-up interrupt signal according to the status signal, and adjusting the frequency of the operation clock according to the delayed wake-up interrupt signal.

Another embodiment of the present invention provides a clock management method for managing an operation clock of a computing circuit, the computing circuit changing a level of a status signal according to an interrupt signal, the clock management method comprising: generating the operation clock according to a reference clock; generating a wake-up interrupt signal according to the status signal; delaying the wake-up interrupt signal to generate a delayed wake-up interrupt signal; and adjusting the frequency of the operation clock according to the delayed wake-up interrupt signal.

The technical means embodied by the embodiments of the present invention may improve at least one of the drawbacks of the prior art, and thus the present invention may mitigate current spikes compared to the prior art.

The features, operations and technical effects of the present invention will be described in detail below with reference to examples of embodiments shown in the accompanying drawings.

Drawings

FIG. 1 is a functional block diagram of one embodiment of a clock management circuit of the present invention;

FIG. 2 shows a functional block diagram of an embodiment of a clock control circuit;

FIG. 3 is a flow chart of one embodiment of a clock management method of the present invention;

FIG. 4 is an example of the timing of multiple clocks and signals;

FIG. 5 is a circuit diagram of one embodiment of a divide and wake-up control circuit and a gating pulse generator;

FIG. 6 shows an example of a frequency-divided finite state machine of the present invention;

FIG. 7 shows an example of the invention waking up a finite state machine; and

fig. 8A-8C are flowcharts illustrating an embodiment of a clock management method according to the present invention.

Symbol description

110: computing circuit

120: clock management circuit

122: delay circuit

124: clock control circuit

130: interrupt control circuit

Cpu_clk_src: reference clock

Cpu_clk: operating clock

Cpu_inr, inr 0, inr 1: interrupt signal

Cpu_sleep: status signal

Cpu_w_inr: wake-up interrupt signal

dly_cpu_w_inr: delayed wake-up interrupt signal

210: synchronizer

220: frequency-dividing and awakening control circuit

230: gate pulse generator

240: clock gating circuit

div_sel: divisor selection signal

div_st: frequency-divided signal

icg _en: gating signal

STG1, STG2, STG3, STG4, STGM: stage(s)

PI1, PI2, PI3: latency time

510: frequency-dividing finite state machine

520: waking up a finite state machine

sleep_ps, inter_ps, event_ps, wakeup_ps, div_st_nxt, wakeup_st, wakeup_st_nxt, st_chg_ps: signal signal

S610, S620, S630, S640, S710, S720, S730, S740, S750: status of

S310, S320, S330, S340, S350, S360, S370, S810, S820, S830, S840, S850, S860, S870, S875, S880, S890: step (a)

Detailed Description

Technical terms used in the following description refer to terms commonly used in the art, and as used in the specification, some terms are described or defined, and the explanation of the some terms is based on the description or the definition of the specification.

The present disclosure includes a clock management circuit and a clock management method. Since some of the components included in the clock management circuit of the present invention may be known components alone, details of the known components will be omitted from the following description without affecting the full disclosure and operability of the device invention. Furthermore, some or all of the flow of the clock management method of the present invention may be in the form of software and/or firmware, and may be performed by the clock management circuit of the present invention or an equivalent thereof, the following description of the method invention will focus on the contents of the steps rather than the hardware without affecting the full disclosure and operability of the method invention.

In the following description, a signal is active or active at a high level, inactive or inactive at a low level, and an enable/disable (de-enable) signal represents the level of the signal to be pulled high/low. However, this is merely an example and is not intended to limit the present invention. In other words, in various embodiments, a signal may be inactive at a high level (e.g., logic 1), active at a low level (e.g., logic 0), and enable/disable a signal may be indicative of a pull-down/pull-up level of the signal. Level shifting (changing) or logic level shifting (changing) represents a signal being enabled (i.e., active) to disabled (i.e., inactive) or vice versa.

FIG. 1 is a functional block diagram of one embodiment of a clock management circuit 120 of the present invention. Clock management circuit 120 includes delay circuit 122 and clock control circuit 124. The clock management circuit 120 receives the reference clock cpu_clk_src and provides the operating clock cpu_clk to the computation circuit 110. The computing circuit 110 operates in an idle state or an active state according to an operation clock cpu_clk and an interrupt signal cpu_inr. The calculation circuit 110 enters itself from the operating state into the idle state or from the idle state into the operating state by enabling the state signal cpu_sleep. The calculation circuit 110 may change the level of the state signal cpu_sleep according to the interrupt signal cpu_inr. The interrupt control circuit 130 is used to control the interrupt signal. As shown, the interrupt control circuit 130 receives the interrupt signal inr 0, the interrupt signal inr 1, and the wake-up interrupt signal cpu_w_inr, and transmits the interrupt signal cpu_inr to the computing circuit 110 and the wake-up interrupt signal cpu_w_inr to the clock management circuit 120. The delay circuit 122 generates a delayed wake-up interrupt signal dly_cpu_w_inr by delaying the wake-up interrupt signal cpu_w_inr. The clock control circuit 124 also adjusts the operation clock cpu_clk according to the delayed wake-up interrupt signal dly_cpu_w_inr.

FIG. 2 shows a functional block diagram of an embodiment of clock control circuit 124. The clock control circuit 124 includes a plurality of synchronizers 210, a frequency dividing and wake-up control circuit 220, a gating pulse generator 230, and a clock gating circuit 240.

The synchronizer 210 is for synchronizing the divisor selection signal div_sel, the status signal cpu_sleep, and the delayed wake-up interrupt signal dly_cpu_w_inr to prevent the shortage of the timing margin (timing margin); however, if the three belong to the same clock domain (clock domain), synchronizer 210 may be omitted.

The divide-by-frequency and wake-up control circuit 220 receives a reference clock CPU_clk_src, a divisor selection signal div_sel, a status signal CPU_sleep, and a delayed wake-up interrupt signal dly_CPU_w_inr. The divide-by-frequency and wake-up control circuit 220 generates or changes the divide-by-frequency signal div_st according to the state signal cpu_sleep and the delayed wake-up interrupt signal dly_cpu_w_inr, and generates or enables the wake-up interrupt signal cpu_w_inr according to the state signal cpu_sleep and the delayed wake-up interrupt signal dly_cpu_w_inr.

The gate pulse generator 230 generates a gate signal icg _en according to the frequency-divided signal div_st. More specifically, the gating pulse generator 230 adjusts the frequency of the gating signal icg _en according to the frequency dividing signal div_st.

The clock gating circuit 240 gates the reference clock cpu_clk_src according to the gating signal icg _en to generate the operation clock cpu_clk. The clock gating circuit 240 is well known to those skilled in the art and will not be described in detail.

Fig. 3 is a flowchart of an embodiment of the clock management method of the present invention, and fig. 4 is an example of the timing of the reference clock cpu_clk_src, the status signal cpu_sleep, the operation clock cpu_clk, the gate signal icg _en, the wake-up interrupt signal cpu_w_inr, and the delayed wake-up interrupt signal dly_cpu_w_inr. The principle of operation of the clock control circuit 124 is described below in conjunction with fig. 3 and 4. The flow of fig. 3 includes the following steps.

Step S310: the calculation circuit 110 is in an operating state, and represents that the frequency of the operation clock cpu_clk is the complete clock frequency (full clock frequency). For example, prior to symbol "1" of fig. 4.

Step S320: the computing circuit 110 is in an idle state. In this step, the clock control circuit 124 decreases the clock frequency of the operation clock cpu_clk. For example, at symbol "1" of fig. 4, the status signal cpu_sleep becomes active, and the calculation circuit 110 operates at a lower (lower than the full clock frequency of stage STG 4) clock frequency at stages STG1, STG2 and STG 3.

Step S330: the calculation circuit 110 wakes up, i.e. the status signal cpu_sleep becomes inactive, and the clock control circuit 124 enables the wake-up interrupt signal cpu_w_inr. For example, the status signal cpu_sleep becomes inactive at symbol "2" of fig. 4, and the wake-up interrupt signal cpu_w_intr becomes active at symbol "3".

Step S340: the clock control circuit 124 waits for the delayed wake-up interrupt signal dly_cpu_w_inr, i.e., the clock control circuit 124 waits for the delayed wake-up interrupt signal dly_cpu_w_inr to become active (equivalent to receiving the delayed wake-up interrupt signal dly_cpu_w_inr). For example, this step may correspond to the latency PI1 between symbol "3" and symbol "4", the latency PI2 between symbol "5" and symbol "6", and the latency PI3 between symbol "7" and symbol "8" of fig. 4.

Step S350: the clock control circuit 124 determines whether the calculation circuit returns to an idle state, i.e., whether the status signal cpu_sleep becomes valid (equivalent to receiving the status signal cpu_sleep). If the result of step S350 is Yes, go back to step S320; if not, step S360 is performed.

Step S360: the clock control circuit 124 determines whether the divide-by-finite state machine (finite state machine, FSM) is in the last stage (or state). The frequency division finite state machine is part of the frequency division and wake-up control circuit 220, which will be described in detail below. In some embodiments, the divide-by-frequency finite state machine indicates its next state with a signal div_st_nxt. This step may be determined based on the signal div_st_nxt. If the result of step S360 is yes, step S370 is performed; if not, go back to step S320. In the example of fig. 4, stage STG3 is the last stage (or state); therefore, at the symbols "4" and "6", the judgment result of step S360 is no, and at the symbol "8", the judgment result of step S360 is yes.

Step S370: the clock control circuit 124 adjusts the frequency of the operation clock cpu_clk to the full clock frequency (i.e., causes the calculation circuit 110 to operate in an operating state), and the flow returns to step S310. As shown in fig. 4, the clock control circuit 124 adjusts the frequency of the operation clock cpu_clk to the full clock frequency after the symbol "8" so that the calculation circuit 110 operates in the operation state (i.e., stage STG 4).

As shown in fig. 3 and 4, after the calculation circuit 110 wakes up (step S330), the clock control circuit 124 does not immediately adjust the operation clock cpu_clk from the lowest clock frequency (e.g., stage STG1 in fig. 4) to the full clock frequency (e.g., stage STG4 in fig. 4), but keeps the operation clock cpu_clk at a lower clock frequency (i.e., lower than the full clock frequency (e.g., stages STG2 and STG3 in fig. 4) for a period of time (which is proportional to the waiting time PI2 and the waiting time PI 3) according to the state of the divide-by-frequency finite state machine (step S360).

Furthermore, if the status signal cpu_sleep becomes active at stage STG2 or stage STG3 (i.e., yes in step S350), the frequency-divided finite state machine of the clock control circuit 124 returns to stage STG1 instead of proceeding to the next stage (stage STG3 or stage STG 4) to operate the calculation circuit 110 in the idle state again.

Latency PI1, latency PI2, latency PI3 in fig. 4 are adjustable; for example, the delay circuit 122 may be set by software.

Note that the number of states of the clock control circuit 124 (more specifically, the divide-by-frequency finite state machine) may be M (M is an integer greater than 2). In the example of fig. 4, m=4 (i.e., stage STG1, stage STG2, stage STG3, and stage STG 4). M may be set by the aforementioned divisor selection signal div_sel. Each state corresponds to a different operating clock cpu_clk frequency.

As described above, the clock management circuit 120 may gradually boost the clock frequency of the operating clock cpu_clk (rather than jumping from the lowest frequency (e.g., stage STG 1) to the highest frequency (e.g., stage STGM)) to mitigate current spikes (i.e., avoid large voltage drops).

Fig. 5 is a circuit diagram of one embodiment of the divide and wake-up control circuit 220 and the gate pulse generator 230. The divide-by-frequency and wake-up control circuit 220 comprises circuitry other than the gating pulse generator 230, i.e., the divide-by-frequency and wake-up control circuit 220 comprises a divide-by-frequency finite state machine 510, a wake-up finite state machine 520, a plurality of logic gates, and a plurality of flip-flops.

The signal sleep ps is related to the state of the state signal CPU sleep. More specifically, sleep_ps is a logic 1 representing the state signal CPU_sleep going from inactive to active.

The signal intr_ps is related to the state of the delayed wake-up interrupt signal dly_cpu_w_intr. More specifically, the fact that inr_ps is a logic 1 represents that the delayed wakeup interrupt signal dly_cpu_w_inr is changed from inactive to active.

The signal event_ps is related to the state of the signal sleep_ps and the state of the signal inr_ps. More specifically, the signal event_ps is logic 1 when the state signal cpu_sleep changes from inactive to active or the delayed wake-up interrupt signal dly_cpu_w_inr changes from inactive to active.

The signal wakeup_ps is related to the state of the state signal cpu_sleep. More specifically, a signal wakeup_ps of logic 1 represents a state signal CPU_sleep changing from inactive to inactive.

The signal div_st_nxt is used to indicate the next state of the divide-by-finite state machine 510. For example, in the example of fig. 4, the signal div_st_nxt indicates a stage STG1, a stage STG2, a stage STG3, or a stage STG4. The state of the frequency division finite state machine 510 will be described in detail below in conjunction with fig. 6.

The wakeup_st and wakeup_st_nxt signals are used to indicate the current state and the next state of the wake-up finite state machine 520, respectively. Wherein when either signal event_ps or signal wakeup_ps or signal st_chg_ps is logic 1, signal wakeup_st will jump to the next state according to the conditions of fig. 7. The state of wake-up finite state machine 520 will be described in detail below in conjunction with fig. 7.

The signal st chg ps is used to indicate a state change to wake up the finite state machine 520.

The circuit of the gate pulse generator 230 is well known to those skilled in the art, and will not be described again. In the example of fig. 5, the circuit of the gating pulse generator 230 corresponds to the divided finite state machine 510 having four states (stage STG1, stage STG2, stage STG3, and stage STG4, as shown in the example of fig. 6).

Fig. 6 shows an example of the divide-by-frequency finite state machine 510 of the present invention. In this example, the divide finite state machine 510 includes four states: the state S610 corresponds to the stage STG4 of fig. 4 (the frequency-divided signal div_st indicates that the frequency of the gating signal icg _en (i.e., the frequency of the operating clock cpu_clk) is the full clock frequency); state S620 corresponds to stage STG1 of fig. 4 (the frequency divided signal div_st indicates that the frequency of gating signal icg _en is one-fourth of the full clock frequency); the state S630 corresponds to the stage STG2 of fig. 4 (the frequency-divided signal div_st indicates that the frequency of the gating signal icg _en is two-fourth of the full clock frequency); and state S640 corresponds to stage STG3 of fig. 4 (the frequency of the divide-by-frequency signal div_st indicates that the frequency of the gating signal icg _en is three-fourths of the full clock frequency).

As shown in fig. 6, when the frequency-divided finite state machine 510 is in the state S610 and the signal sleep_ps is logic 1, the frequency-divided finite state machine 510 enters the state S620. When the frequency-divided finite state machine 510 is in the state S620, the signal event_ps is logic 1, and the state signal cpu_sleep is logic 0, the frequency-divided finite state machine 510 enters the state S630. When the frequency-divided finite state machine 510 is in the state S630, the signal event_ps is logic 1, and the state signal cpu_sleep is logic 0, the frequency-divided finite state machine 510 proceeds to the state S640. When the frequency-divided finite state machine 510 is in the state S640, the signal event_ps is logic 1, and the state signal cpu_sleep is logic 0, the frequency-divided finite state machine 510 proceeds to the state S610. When the frequency-divided finite state machine 510 is in the state S630, the signal event_ps is logic 1, and the state signal cpu_sleep is logic 1, the frequency-divided finite state machine 510 proceeds to the state S620. When the frequency-divided finite state machine 510 is in the state S640, the signal event_ps is logic 1, and the state signal cpu_sleep is logic 1, the frequency-divided finite state machine 510 proceeds to the state S620.

Fig. 7 shows an example of the invention waking up the finite state machine 520. The wake-up finite state machine 520 comprises the following five states.

State S710: and (5) an idle state. This state corresponds to the computing circuit 110 being in an operational state (i.e., operating at a full clock frequency). When the wake-up finite state machine 520 is in state S710 and the signal sleep_ps is logic 1 (e.g., corresponding to symbol "1" of fig. 4), the wake-up finite state machine 520 proceeds to state S720.

State S720: sleep state. This state corresponds to the computing circuit 110 being in an idle state (i.e., operating at one-M times the full clock frequency). When the wake-up finite state machine 520 is in state S720 and the signal wakeup_ps is logic 1 (e.g., corresponding to symbol "2" of fig. 4), the wake-up finite state machine 520 proceeds to state S730.

State S730: and (5) an awake state. In this state, the wake-up finite state machine 520 enables the wake-up interrupt signal cpu_w_inr (e.g., corresponding to the symbols "3", "5", or "7" of fig. 4) by the control signal wakeup_st and the signal wakeup_st_nxt. When the wake-up finite state machine 520 is in state S730 and the signal inr_ps is logic 1 (e.g., corresponding to the symbols "4", "6", or "8" of fig. 4), the wake-up finite state machine 520 enters state S740; when the finite state machine 520 is awakened in state S730 and the signal sleep_ps is logic 1 (representing the transition of the frequency-divided finite state machine 510 from state S640 to state S620 or from state S630 to state S620), the finite state machine 520 is awakened to state S720.

State S740: and judging the state. The wake-up finite state machine 520 determines whether the next state of the divide finite state machine 510 is a state that provides the full clock frequency (e.g., state S610 of fig. 6). If yes (i.e., corresponding to the computing circuit 110 being about to return to an operational state operating at the full clock frequency), then waking up the finite state machine 520 back to state S710 (e.g., corresponding to symbol "8" of fig. 4); if not (e.g., corresponding to the symbols "4" or "6" of FIG. 4), the wake-up finite state machine 520 enters state S750.

State S750: waiting state. The wake-up finite state machine 520 waits for the divided finite state machine 510 to change state (i.e., change the divided signals div_st and div_st_nxt). When the wake-up finite state machine 520 goes to the state S750, the signal st_chg_ps is logic 1, and the following operations are performed according to the signal sleep_ps. If sleep_ps is a logic 1, it represents that the computing circuit 110 is to enter the idle state again, and the frequency-dividing finite state machine 510 transitions from the state S640 to the state S620 or from the state S630 to the state S620; if the sleep ps signal is logic 0, the divide-by-frequency finite state machine 510 transitions from state S620 to state S630 or from state S630 to state S640, which represents that the computing circuit 110 is continuously awake. The signal st_chg_ps being a logic 1 may correspond to a falling edge between symbols "4" and "5" or between symbols "6" and "7" of fig. 4.

Those skilled in the art can implement the frequency-divided finite state machine 510 and the wake-up finite state machine 520 using logic gates and/or transistors according to the descriptions of fig. 6 and 7.

In summary, the present invention provides a plurality of stages for the operation clock cpu_clk, each stage generates a different clock frequency, so that the operation clock cpu_clk gradually returns to the complete clock frequency from the lowest clock frequency in the process of returning the computing circuit 110 from the idle state to the working state, so as to mitigate the current surge.

In addition to the clock management circuit, the invention also correspondingly discloses a clock management method. The method is performed by the aforementioned clock management circuit 120 or its equivalent. Fig. 8A-8C are flowcharts of one embodiment of the method, including the following steps.

Step S810: the operation clock cpu_clk is generated from the reference clock cpu_clk_src. In some embodiments, this step may be performed by clock control circuit 124; more specifically, it may be performed by clock gating circuit 240.

Step S820: the wake-up interrupt signal cpu_w_inr is generated from the status signal cpu_sleep. In some embodiments, this step may be performed by clock control circuit 124; more specifically, it may be performed by the divide-by-frequency and wake-up control circuit 220. This step may correspond to the state transition from state S720 to state S730 of fig. 7.

Step S830: the wake-up interrupt signal cpu_w_inr is delayed to generate a delayed wake-up interrupt signal dly_cpu_w_inr. In some embodiments, this step may be performed by delay circuit 122.

Step S840: the frequency of the operation clock CPU_clk is adjusted according to the delayed wake-up interrupt signal dly_CPU_w_inr. In some embodiments, this step may be performed by clock control circuit 124. This step may correspond to the state transition from state S620 to state S640 of fig. 6.

Step S850: when the level of the state signal cpu_sleep changes, the frequency of the operation clock cpu_clk is controlled to be the first frequency. In some embodiments, this step may be performed by clock control circuit 124. This step may correspond to states S610 through S620 of fig. 6, states S710 through S720 of fig. 7, and symbol "1" of fig. 4. The first frequency is, for example, the frequency of stage STG 1.

Step S860: when the level of the delayed wake-up interrupt signal dly_cpu_w_inr changes, the frequency of the operation clock cpu_clk is controlled to be the second frequency. The second frequency is greater than the first frequency. In some embodiments, this step may be performed by clock control circuit 124. This step may correspond to states S620 through S630 of fig. 6 and the symbols "4", "6" or "8" of fig. 4. The second frequency is, for example, the frequency of stage STG2 or stage STG 3.

Step S870: the frequency division signal div_st is generated or changed according to the divisor selection signal div_sel and the delayed wake-up interrupt signal dly_cpu_w_inr. In some embodiments, this step may be performed by clock control circuit 124; more specifically, it may be performed by the divide-by-frequency and wake-up control circuit 220. This step may correspond to the state S620 to state S640 state transition of fig. 6, wherein the divisor selection signal div_sel may determine M (m=4 in the example of fig. 6).

Step S875: the divided frequency signal div_st is changed in response to a level change of the delayed wake-up interrupt signal dly_cpu_w_inr. This step is a substep of step S870, and the frequency-dividing finite state machine 510 determines the state of fig. 6 (i.e. the control frequency-dividing signal div_st corresponds to 1/M, 2/M, … …) according to the delayed wake-up interrupt signal dly_cpu_w_inr.

Step S880: generating a gating signal icg _en according to the frequency division signal div_st. In some embodiments, this step may be performed by the gating pulse generator 230, one implementation of which gating pulse generator 230 is shown in FIG. 5.

Step S890: the reference clock CPU_clk_src is gated according to the gating signal to generate the operating clock CPU_clk. In some embodiments, this step may be performed by clock gating circuit 240.

Since those skilled in the art can understand the implementation details and variations of the disclosed method according to the disclosure of the disclosed device, repeated descriptions are omitted herein to avoid redundancy without affecting the disclosure requirement and the implementation of the disclosed method. It should be noted that the shapes, sizes and proportions of the elements in the foregoing figures are merely illustrative, and are used for the understanding of the present invention by those skilled in the art, and are not meant to limit the present invention. In addition, in some embodiments, the steps mentioned in the foregoing flowcharts may be adjusted in order according to actual operations, and may even be performed simultaneously or partially simultaneously.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto, and those skilled in the art can apply the present invention with respect to the technical features of the present invention according to the explicit or implicit disclosure, and all such variations are possible within the scope of the present invention, that is, the scope of the present invention is defined by the claims of the present specification.

Claims (10)

1. A clock management circuit for managing an operating clock of a computing circuit that changes a level of a status signal according to an interrupt signal, the clock management circuit comprising:

a delay circuit for delaying a wake-up interrupt signal to generate a delayed wake-up interrupt signal; and

the clock control circuit is coupled to the delay circuit and is used for generating the operation clock according to a reference clock, generating the wake-up interrupt signal according to the state signal and adjusting the frequency of the operation clock according to the delayed wake-up interrupt signal.

2. The clock management circuit of claim 1, wherein the clock management circuit is capable of controlling the frequency of the operation clock to be a first frequency, a second frequency or a third frequency, the first frequency is a lowest operation frequency of the computing circuit, the third frequency is a highest operation frequency of the computing circuit, the second frequency is between the first frequency and the third frequency, the clock control circuit is responsive to the level change of the status signal to control the frequency of the operation clock to be the first frequency, and the clock control circuit is responsive to the level change of the delayed wake-up interrupt signal to control the frequency of the operation clock to be the second frequency.

3. The clock management circuit of claim 2, wherein the delay circuit delays the wake-up interrupt signal according to a latency time, which is adjustable by means of a software setting, to generate the delayed wake-up interrupt signal.

4. A clock management circuit as claimed in claim 3, wherein the clock control circuit comprises:

a frequency dividing and waking control circuit for generating the waking interrupt signal according to the state signal and generating a frequency dividing signal according to a divisor selection signal and the delayed waking interrupt signal;

a gating pulse generator coupled to the frequency-dividing and wake-up control circuit for generating a gating signal according to the frequency-dividing signal; and

a clock gating circuit coupled to the gating pulse generator for gating the reference clock according to the gating signal to generate the operation clock.

5. The clock management circuit of claim 4, wherein the divide-by-frequency and wake-up control circuit varies the divide-by-frequency signal in response to a level change of the delayed wake-up interrupt signal.

6. A clock management method for managing an operation clock of a computing circuit, the computing circuit changing a level of a status signal according to an interrupt signal, the clock management method comprising:

generating the operation clock according to a reference clock;

generating a wake-up interrupt signal according to the status signal;

delaying the wake-up interrupt signal to generate a delayed wake-up interrupt signal; and

and adjusting the frequency of the operation clock according to the delayed wake-up interrupt signal.

7. The method of claim 6, wherein the clock management method controls the frequency of the operation clock to be a first frequency, a second frequency or a third frequency, the first frequency being a lowest operation frequency of the computing circuit, the third frequency being a highest operation frequency of the computing circuit, the second frequency being between the first frequency and the third frequency, the method further comprising:

when the level of the state signal changes, controlling the frequency of the operation clock to be the first frequency; and

when the level of the delayed wake-up interrupt signal changes, the frequency of the operation clock is controlled to be the second frequency.

8. The method of claim 7, wherein the step of delaying the wake-up interrupt signal to generate the delayed wake-up interrupt signal delays the wake-up interrupt signal by a waiting time, the waiting time being adjustable by a software setting.

9. The clock management method of claim 7, further comprising:

generating a frequency-dividing signal according to a divisor selection signal and the delayed wake-up interrupt signal;

generating a gate control signal according to the frequency-divided signal; and

the reference clock is gated according to the gating signal to generate the operating clock.

10. The clock management method as claimed in claim 9, wherein the step of generating the frequency-divided signal according to the divisor selection signal and the delayed wakeup interrupt signal comprises:

the frequency-divided signal is changed in response to a level change of the delayed wakeup interrupt signal.