CN117665535A - Test system, test signal transmission method, electronic device, and storage medium - Google Patents
Test system, test signal transmission method, electronic device, and storage medium Download PDFInfo
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Abstract
The embodiment of the application relates to the technical field of testing and discloses a testing system, a testing signal sending method, electronic equipment and a storage medium. The test system comprises an upper computer, at least two test signal sources, a control bus, a chip to be tested and a signal transmission medium; the upper computer is connected with each test signal source through a control bus, and each test signal source is connected with the chip to be tested through a signal transmission medium in a communication way; and sending test instructions to at least two test signal sources through a control bus by utilizing the upper computer according to the test signal receiving requirements so as to instruct at least one of the test signal sources to send test signals to the chip to be tested, wherein the total test signals received by the chip to be tested meet the test signal receiving requirements. According to the scheme, the upper computer can start different test signal sources through the control bus according to different test items, so that the test signals generated by the test signal sources support a high power dynamic range, and the receiving requirements of the chip to be tested on the test signals are met.
Description
Technical Field
The embodiment of the application relates to the technical field of testing, in particular to a testing system, a testing signal sending method, electronic equipment and a storage medium.
Background
Along with the update iteration of the radar electronic product, the chip mass production needs more comprehensive test parameter coverage rate, but the signal dynamic range of the test signal which can be provided in the conventional radio frequency test scheme at present is small, so that some test limitations can be caused.
For example, in millimeter wave chip on chip (SOC) mass production test, there is a very severe power dynamic range requirement on the signal source quality with respect to transceiver gain test, sensitivity test, gain compression point test, linearity test:
first: a signal source is required to support a high power dynamic range (> 80 dB);
second,: the required signal source can generate a multi-tone signal without clutter;
third,: the signal source is required to have a stable millimeter wave band frequency response.
Currently, based on cost and environmental considerations, all Radio Frequency (RF) test items are currently completed by using test signals sent by a single test chip. However, based on the use scenario of the test chip, many test chips need to perform different test items in different temperature environments (such as an automobile radar), and in addition, the hardware factors on the device to be tested are added, the test signal provided by a single test chip cannot meet the high dynamic range of the test signal gain condition, so that the test requirement cannot be met.
Disclosure of Invention
An object of the embodiment of the present application is to provide a test system, a test signal sending method, an electronic device, and a storage medium, which can start different test signal sources according to different test items through a control bus, so that a test signal generated by the test signal sources supports a high power dynamic range, so as to meet a receiving requirement of a chip to be tested on the test signal.
In order to solve the above technical problems, an aspect of an embodiment of the present application provides a test system, including:
the system comprises an upper computer, at least two test signal sources, a control bus, a chip to be tested and a signal transmission medium, wherein the upper computer is connected with the test signal sources through the control bus, and the test signal sources are in communication connection with the chip to be tested through the signal transmission medium;
the upper computer is used for sending test instructions to the at least two test signal sources through the control bus according to the test signal receiving requirements so as to instruct at least one of the test signal sources to send test signals to the chip to be tested, and the total test signals received by the chip to be tested meet the test signal receiving requirements.
In the above test system, the upper computer is further configured to perform adjustment and calibration on the test signals sent by the test signal sources for multiple times, so as to determine the number of the test signal sources used for sending the test signals to the chip to be tested, and the frequency and the power of the sent test signals.
In the test system as described above, the test signal source is a test chip.
In the test system, the test signals sent by the at least two test signal sources are collected to the same position through the signal transmission medium and then sent to the chip to be tested.
In the test system, the dynamic power range of the test signals sent by the at least two test signal sources when the test signals are received by the chip to be tested is more than or equal to 80db.
In the test system, the chip to be tested is a millimeter wave radar chip.
In the test system as described above, the signal transmission medium is a waveguide structure or an antenna.
In the test system as described above, the at least two test signal sources include: the first test signal source, the second test signal source and the third test signal source;
the first test signal source is used for sending a test signal to the chip to be tested in CG test;
the second test signal source is used for sending test signals to the chip to be tested in the 2tone test together with the first test signal source; and the signal test module is used for sending a signal test to the chip to be tested which is in an RX blocker test;
And the third test signal source is used for sending a signal test to the chip to be tested which is in the RX blocker test.
In the test system as described above, the output power of each of the at least two test signal sources is [ -20, 10] dbm;
when in CG test, the maximum output power of the first test signal source is-70 dBm, and the power loss when the test signal sent by the first test signal source reaches the chip to be tested through the signal transmission medium is [ -80, -50] dBm;
when in CG test, the minimum output power of the first test signal source is-50 dBm, and the power loss when the test signal sent by the first test signal source reaches the chip to be tested through the signal transmission medium is [ -60, -30] dBm.
In another aspect, an embodiment of the present application provides a method for sending a test signal, which is applied to the test system as described above, where the method includes:
the upper computer sends a test instruction to at least one test signal source through a control bus according to the test signal receiving requirement;
and the at least one test signal source sends test signals to the chip to be tested according to the received test instruction, and the total test signals received by the chip to be tested meet the test signal receiving requirement.
In the above test signal transmitting method, the upper computer transmits a test instruction to at least one test signal source through a control bus according to a test signal receiving requirement, including: the upper computer sends a test instruction to each test signal source through the control bus according to the test signal receiving requirement, wherein the test instruction comprises a signal source identifier of the test signal source instructed to send the test signal and the frequency and power requirements of the sent test signal;
the at least one test signal source sends test signals to the chip to be tested according to the received test instruction, and the method comprises the following steps: and the test signal source corresponding to the signal source identifier sends a test signal meeting the frequency and power requirements indicated by the test signal source in the test instruction to the chip to be tested.
In the above test signal transmitting method, the upper computer transmits a test instruction to at least one test signal source through a control bus according to a test signal receiving requirement, including: the upper computer respectively sends test instructions to the appointed test signal sources through a control bus according to the test signal receiving requirement, wherein the test instructions comprise frequency and power requirements for indicating the test signals sent by the appointed test signal sources;
The at least one test signal source sends test signals to the chip to be tested according to the received test instruction, and the method comprises the following steps: and the test signal source receives the test instruction and sends a test signal with frequency and power requirements indicated in the received test instruction to the chip to be tested.
The test signal transmitting method as described above further includes: and the upper computer adjusts and calibrates the test signals sent by the test signal sources for a plurality of times to determine the number of the test signal sources used for sending the test signals to the chip to be tested and the frequency and the power of the sent test signals.
In the above test signal transmitting method, the upper computer adjusts and calibrates the test signal sent by each test signal source for a plurality of times, including:
the upper computer sends a reference signal instruction to at least one test signal source through a control bus according to the test signal receiving requirement, wherein the reference signal instruction comprises the frequency and the power of the test signal source for sending a reference signal and the reference signal;
the upper computer adjusts and indicates the frequency and the power of the test signal source for sending the calibration signal and the frequency and the power of the calibration signal for many times according to the frequency and the power of the reference signal received by the chip to be tested until the calibration signal received by the chip to be tested meets the receiving requirement of the test signal when being used as the received test signal;
The calibration signal sent by the test signal source each time is a signal obtained by adjusting the reference signal sent last time or the calibration signal sent last time.
The test signal transmitting method as described above further includes:
the upper computer selects the test signal sources for transmitting the reference signals and determines the frequency and the power of the transmitted reference signals according to the output power range of each test signal source, the power loss when the test signals transmitted by the test signal sources reach the chip to be tested through a signal transmission medium and the test signal receiving requirement.
Another aspect of an embodiment of the present application provides an electronic device, including:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the test signaling method as described above.
Another aspect of the embodiments of the present application provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the test signal transmission method as described above.
Compared with the related art, the test system in the embodiment of the application comprises an upper computer, at least two test signal sources, a control bus, a chip to be tested and a signal transmission medium; the upper computer is connected with each test signal source through a control bus, and each test signal source is connected with the chip to be tested through a signal transmission medium in a communication way; and sending test instructions to at least two test signal sources through a control bus by utilizing the upper computer according to the test signal receiving requirements so as to instruct at least one of the test signal sources to send test signals to the chip to be tested, wherein the total test signals received by the chip to be tested meet the test signal receiving requirements. According to the scheme, the upper computer can start different test signal sources through the control bus according to different test items, so that the test signals generated by the test signal sources support a high power dynamic range, and the receiving requirements of the chip to be tested on the test signals are met.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
FIG. 1 is a schematic diagram of a test system provided in accordance with one embodiment of the present application;
FIG. 2 is a flow chart of a test signaling method provided in accordance with one embodiment of the present application;
fig. 3 is a schematic diagram of an electronic device provided according to one embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of each embodiment of the present application will be given with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present application, numerous technical details have been set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not be construed as limiting the specific implementation of the present application, and the embodiments may be mutually combined and referred to without contradiction.
One embodiment of the present application relates to a test system, as shown in fig. 1, comprising: the upper computer 11, at least two test signal sources 12, a control bus 13, a chip 14 to be tested and a signal transmission medium 15, wherein the upper computer 11 is connected with each test signal source 12 through the control bus 13, and each test signal source 12 is in communication connection with the chip 14 to be tested through the signal transmission medium 15; the upper computer 11 is configured to send a test instruction to at least two test signal sources 12 through the control bus 13 according to a test signal receiving requirement, so as to instruct at least one of the test signal sources 12 to send a test signal to the chip to be tested 14, and the total test signal received by the chip to be tested 14 meets the test signal receiving requirement.
The upper computer 11 may be a control device, such as a computer, a mobile terminal, a server, etc., and is in information interaction with the test signal source 12 through the control bus 13, and sends a test instruction to the test signal source 12, so that the test signal source 12 is instructed to send a test signal to the chip 14 to be tested through the test instruction.
The control bus 13 may include, but is not limited to, an I2C bus, SCI bus, VESA bus, PCI bus, etc. The host computer 11 may send a test instruction to a certain test signal source 12 alone or may send the same test instruction to a plurality of test signal sources 12 at the same time through the control bus 13. The manner of transmitting data by the control bus 13 is not limited in this embodiment.
The test signal sources 12 may transmit test signals of a specified frequency and power range, such as in a test scenario for a radar chip, each test signal source 12 may transmit a 77Ghz high frequency test signal, which may have a power dynamic range of 30db. In addition, the number of the test signal sources 12 is not limited in the present embodiment, and a preferable settable number is 3 in view of cost and effect of transmitting the test signal.
In some embodiments, the test signal source may be embodied as a test chip.
The test signal source 12 sends test signals to the chip 14 to be tested through the signal transmission medium 15, and in this embodiment, the specific structural form and materials of the signal transmission medium 15 are not limited, so that the test signal transmission can be realized. For example, the signal transmission medium 15 may be a waveguide structure or an antenna.
Because the structure of the signal transmission medium 15 directly affects the power loss of the test signals sent by the test signal sources 12 before reaching the chip 14 to be tested, when there are multiple test signal sources 12, in order to better manage the power loss of the test signals sent by the test signal sources 12, as shown in fig. 1, the test signals sent by the test signal sources 12 in the test system including at least two test signal sources are collected to the same position (e.g. point a in the figure) through the signal transmission medium 15 before being sent to the chip 14 to be tested. In this way, each time the chip 14 to be tested is replaced, the power loss difference between each test signal source 12 and the chip 14 to be tested does not need to be considered again, but the power loss difference between the same position (point a) and the chip 14 to be tested is directly considered.
In this embodiment, the total test signal emitted from all the test signal sources 12 in the test system should have a larger power dynamic range, compared with the existing test signal with a power dynamic range of 30db emitted from a single test signal source, the power dynamic range of the test signal emitted from the at least two test signal sources 12 provided in the test system when received by the chip 14 to be tested is greater than or equal to 80db. In the test system, the requirement of high power dynamic range can be well met by starting at least two test signal sources 12 to send out test signals simultaneously.
The chip 14 to be tested may be a chip structure of any function to be tested based on a radio frequency test signal, for example, but not limited to, a millimeter wave radar chip. The power range of the test signal required for millimeter wave radar chips is often critical, such as:
first: the signal source is required to support a high power dynamic range (> 80 dB).
Second,: the desired signal source may produce a multi-tone signal without noise.
Third,: the signal source is required to have a stable millimeter wave band frequency response.
In the test system of the present embodiment, the upper computer 11 may instruct one or more test signal sources 12 to simultaneously send test signals by sending test instructions to the test signal sources 12, and instruct the frequency and power of the test signals sent by each test signal source 12 at the same time, so as to implement that the test signals received by the millimeter wave radar chip can meet the above-mentioned severe requirements.
For example, multiple test signal sources 12 may be instructed to transmit test signals simultaneously, and since the power dynamic range of a single test signal source 12 is typically 30dB, the emitted test signal is brought to a high power dynamic range (e.g., >80 dB) by instructing, for example, 3 test signal sources 12 to transmit test signals simultaneously. For another example, a plurality of test signal sources 12 with small clutter signals can be selected to emit test signals simultaneously, so as to meet the requirement of emitting multi-tone signals without clutter. For another example, for the test signal with the same band frequency response (such as millimeter wave of 77 GHz), the test signal source 12 with a better single band frequency response effect can be selected to send out the test signal, and the test signals with the band frequency response (such as millimeter wave of 77 GHz) can be sent out by multiple test signal sources 12 at the same time, so that the power requirement under the stable target band frequency response can be achieved by the power superposition of the test signals.
In summary, the core idea of the test system in this embodiment is to flexibly select the test signal sources 12 that need to send test signals and instruct the frequency and power of the sent test signals to flexibly adjust the combination by setting a plurality of test signal sources 12, so as to meet the receiving requirement of the chip 14 to be tested on receiving the test signals.
The frequency and power of which test signal sources 12 transmit test signals to the chip 14 under test in the test scene can be adjusted and calibrated in advance by the upper computer 11.
In some embodiments, the upper computer 11 is further configured to determine the number of test signal sources for sending test signals to the chip under test, and the frequency and power of the sent test signals by performing adjustment and calibration on the test signals sent by each test signal source 12 multiple times.
For example, the upper computer 11 may flexibly select the test signal source 12 for transmitting the test signal and determine the frequency and power of the test signal transmitted by the selected test signal source 12 according to the output power range of each test signal source 12, the power loss of the test signal transmitted by each test signal source 12 to the chip 14 to be tested, and the receiving requirement of the chip 14 to be tested for the test signal in the test scenario.
It should be noted that, in practice, the total power of the test signals emitted by each test signal source 12 is not necessarily equal in value to the sum of the powers of the individual test signals emitted by each test signal source 12, which involves many factors that affect the total power, such as the size of each test signal source 12, the relative position to each other, the difference in the frequencies and powers of the emitted test signals, and the size, position, distance length from each test signal source 12, relative position, etc. of the chip under test 14. Thus, merely increasing the number of test signal sources in existing test signal output schemes does not scale up the power dynamic range of the test signal.
Thus, the process of selecting the test signal source 12 and determining the frequency and power of the transmitted test signal may need to be performed multiple times: the test signals are emitted by the selected test signal source 12 and are verified and then adjusted for the selected emitted test signals to be finally determined. In each adjustment process, the test system in this embodiment may not only adjust the test signal source 12 that emits the test signal, but also adjust the frequency and power of the transmitted test signal, which is not limited in this embodiment, and may be controlled by an adjustment algorithm preset in the host computer 11.
In some embodiments, the test environment corresponding to each test signal source 12 may be pre-specified, so that the structure and the position of each test signal source 12 may be better designed, and the frequency and the power of the test signal source 12 and the transmitted test signal suitable for the test scene may be selected more quickly for different test environments.
For example, the at least two test signal sources included in the test system in this embodiment include: the first test signal source, the second test signal source and the third test signal source; wherein:
the first test signal source is used for sending test signals to the chip to be tested in the CG test;
the second test signal source is used for transmitting test signals to the chip to be tested in the 2tone test together with the first test signal source; and transmitting a signal test to the chip under test under the RX blocker test;
and the third test signal source is used for sending a signal test to the chip to be tested which is in the RX blocker test.
Specifically, when designing the test scenario corresponding to each test signal source 12, the combination of the corresponding test signal sources 12, and the frequency and power of the test signal emitted by each test signal source 12 under the combination may be specified in advance according to the receiving requirement, especially the power dynamic range requirement, of the chip 14 to be tested for the received test signal in the test scenario. Therefore, the whole test system can more flexibly meet the test signal receiving requirements of different test scenes.
For example, in some embodiments, the output power of each of the at least two test signal sources included on the test system may be set to [ -20, 10] dBm; the power range basically meets the requirement of the existing single test signal source for transmitting test signals, and can realize multiplexing of the existing test signal source and reduce the transformation cost.
For the CG test scenario described above, the setting of the test signal sent by the corresponding first test signal source may be:
when in CG test, the maximum output power of the first test signal source is-70 dBm, and the power loss when the test signal sent by the first test signal source reaches the chip 14 to be tested through the signal transmission medium 15 is [ -80, -50] dBm;
when in CG test, the minimum output power of the first test signal source is-50 dBm, and the power loss when the test signal sent by the first test signal source reaches the chip 14 to be tested through the signal transmission medium 15 is [ -60, -30] dBm.
When the structure of the signal transmission medium 15 is actually designed, the power loss of the test signal sent by the test signal source 12 on the signal transmission medium 15 can be flexibly designed or adjusted according to the dynamic range of the maximum and minimum output power corresponding to the test signal of the test signal source 12, so that the test signal reaching the chip 14 to be tested can meet the actual receiving requirement of the chip 14 to be tested on the test signal.
Another embodiment of the present invention relates to a test signal transmission method, which is applicable to the test system provided in the above embodiment. As shown in fig. 2, the test signal transmission method includes the following steps.
Step 201: and the upper computer sends a test instruction to at least one test signal source through the control bus according to the test signal receiving requirement.
The test signal receiving requirement is that the test signal received by the chip 14 under test in the normal test environment should meet the standard, for example, the received test signal should meet the standard of frequency, power, etc.
Specifically, the upper computer 11 may send a test instruction to at least one test signal source 12 in the test system through the control bus 13 according to the receiving requirement of the chip 14 to be tested for the test signal; the test instructions may include a test signal source 12 that directs the transmission of test signals, as well as the frequency and power requirements of the transmitted test signals.
The manner in which the test instructions are sent varies depending on the manner in which the data is transmitted over the control bus 13 of different designs.
Mode one: the upper computer 11 may send a test command to each test signal source via the control bus 13 according to the test signal receiving requirement, where the test command includes a signal source identifier of the test signal source instructed to send the test signal, and a frequency and power requirement of the sent test signal.
For example, after determining the test signal source 12 that needs to transmit the test signal and the frequency and power requirements of the transmitted test signal according to the test signal receiving requirement, the upper computer 11 will send a test instruction including the signal source identifier of the test signal source 12 that needs to transmit the test signal and the frequency and power requirements of the transmitted test signal to each test signal source 12 through the control bus 13. Wherein each source identification may uniquely identify a test source 12. When the test signal source 12 receives the test instruction, it can determine whether the test instruction indicates the test signal source to send the test signal by identifying whether the test instruction carries the signal source identifier identical to the signal source identifier of the test signal source 12, and further identify the frequency and power requirement of the sent test signal when it is identified that the test signal needs to be sent.
By adopting the mode I for sending the test instruction, each test signal source 12 can synchronously receive the test instruction, so that the speed of subsequently sending the test signal is improved, and the operation delay caused by asynchronous receiving of the test instruction is reduced.
Mode two: the upper computer respectively sends test instructions to the designated test signal sources through the control bus according to the test signal receiving requirements, wherein the test instructions comprise frequency and power requirements for indicating the test signals sent by the designated test signal sources.
For example, after determining the test signal source 12 that needs to send the test signal and the frequency and power requirements of the sent test signal according to the test signal receiving requirement, the host computer 11 sends test instructions specific to the test signal source 12 that needs to send the test signal to the test signal source 12 through the control bus 13, where the test instructions include the frequency and power requirements of the test signal that indicate the test signal source 12 needs to send. When a test command is received by a certain test signal source 12, the test signal source 12 determines by default that it needs to send a test signal, and further identifies the test command to obtain the frequency and power requirements of the sent test signal.
By adopting the mode two for sending the test instruction, the test instruction can be received only by the test signal source 12 which needs to send the test signal, the test instruction does not need to be additionally sent to the test signal source 12 which does not need to send the test signal, and the signal source identifier does not need to be additionally added in the test instruction, so that the data transmission quantity is reduced, and the bandwidth requirement on the control bus 13 is also reduced.
Step 202: at least one test signal source sends test signals to the chip to be tested according to the received test instructions, and the total test signals received by the chip to be tested meet the test signal receiving requirements.
Specifically, after the host computer 11 issues a test instruction to the test signal source 12, the test signal source 12 that receives the test instruction will send a test signal to the chip to be tested according to the frequency and power indicated in the received test instruction and required to send the test signal by the test signal source 12. After all the test signals sent by the test signal source 12 sending the test signals reach the chip 14 to be tested through the signal transmission medium 15, that is, the total test signals received by the chip 14 to be tested should meet the preset test signal receiving requirements, so as to realize the subsequent test links.
The manner in which the test signal source 12 transmits the test signal varies depending on the manner in which the host computer 11 transmits the test instruction.
In some embodiments, as a continuation of the sending of the test instruction in the above manner, the sending, by the at least one test signal source, the test signal to the chip under test according to the received test instruction may include: and the test signal source corresponding to the signal source identifier sends a test signal meeting the frequency and power requirements indicated by the test signal source in the test instruction to the chip to be tested.
Specifically, after each test signal source 12 receives the test instruction, whether the test instruction instructs the test signal source to send the test signal can be judged by identifying whether the test instruction carries the signal source identifier identical to the signal source identifier of the test signal source 12, and when the test signal is identified to be sent, the frequency and the power requirement of the sent test signal are further identified. After the test signal source 12 corresponding to the signal source identifier receives the test instruction, the requirement of the test signal sent by the test signal source 12 is extracted from the test instruction, and then the test signal meeting the frequency and power requirements indicated by the test signal source 12 in the test instruction is sent to the chip 14 to be tested according to the requirement.
In other embodiments, as a continuation of the second method for sending the test instruction, the at least one test signal source sends a test signal to the chip to be tested according to the received test instruction, which may include: and the test signal source receives the test instruction and sends the test signal with the frequency and power requirements indicated in the received test instruction to the chip to be tested.
Specifically, after a certain test signal source 12 receives a test instruction, the test signal source 12 determines that it needs to send a test signal by default, extracts a requirement of the test signal sent by the test signal source 12 from the received test instruction, and then sends a test signal meeting the frequency and power requirements indicated in the test instruction to the chip 14 to be tested according to the requirement.
In addition, the frequency and the power of the test signal source 12 indicated in the test instruction sent by the upper computer 11 and the frequency and the power of the test signal indicated to be sent are determined in advance by the upper computer 11 after multiple adjustment and calibration, and the requirement of receiving the test signal is met. That is, in some embodiments of the present application, the method further includes the following steps: the upper computer adjusts and calibrates the test signals sent by the test signal sources for a plurality of times to determine the number of the test signal sources used for sending the test signals to the chip to be tested and the frequency and the power of the sent test signals.
In the present embodiment, the process of adjusting and calibrating the number of the test signal sources 12 for transmitting the test signal and the combination relationship of the frequency and the power of the test signal transmitted by each test signal source 12 by the host computer 11 is not limited.
In some embodiments, the upper computer 11 performs adjustment and calibration on the test signals sent by the test signal sources 12 multiple times, and the method may include steps one to two.
Step one: and the upper computer sends a reference signal instruction to at least one test signal source through the control bus according to the test signal receiving requirement, wherein the reference signal instruction comprises the frequency and the power of the test signal source for sending the reference signal and the reference signal.
Before the initial adjustment and calibration of the test signals, the upper computer 11 will preset one or more test signal sources 12 that need to send test signals for the current test scene according to the test signal receiving requirements, and set an initial value of the test signals, also called a reference signal, for these test signal sources 12, where the specific setting content includes the frequency and power of the reference signal. Then, the upper computer 11 transmits a reference signal instruction including the frequency and power of the test signal source 12 transmitting the reference signal and the reference signal to these initially set test signal sources 12 through the control bus 13. The specific transmission mode may refer to the first mode and the second mode of the upper computer transmitting the test instruction in the foregoing embodiment, which is not limited in this embodiment.
In some embodiments, the selection of the reference signal also requires the host computer 11 to be preset. For example: the upper computer can select the test signal source 12 for transmitting the reference signal and determine the frequency and power of the transmitted reference signal according to the output power range of each test signal source 12, the power loss when the test signal transmitted by the test signal source 12 reaches the chip 14 to be tested through the signal transmission medium 15, and the test signal receiving requirement.
For example, when the output power of each test signal source in the test system is [ -20, 10] dBm and the current test scenario is CG test, one or two test signal sources 12 may be selected to transmit reference signals in combination with consideration of the power loss when the test signal sent by the test signal source 12 reaches the chip 14 to be tested through the signal transmission medium 15 and the test signal receiving requirement (such as frequency 77GHz, power dynamic range is 30 dBm), and the frequency of the reference signal transmitted by each test signal source 12 is 77GHz, and the power is any power value of [ -20, 10] dBm.
Step two: the upper computer adjusts and indicates the test signal source for transmitting the calibration signal and the frequency and the power of the calibration signal for a plurality of times according to the frequency and the power of the reference signal received by the chip to be tested until the calibration signal received by the chip to be tested meets the receiving requirement of the test signal when being used as the received test signal; the calibration signal sent by the test signal source each time is a signal obtained by adjusting the reference signal sent last time or the calibration signal sent last time.
Specifically, after the test signal source 12 sends out the reference signal, the upper computer 11 determines the difference between the received reference signal and the target test signal by monitoring the frequency and the power of the reference signal received by the chip 14 to be tested, then continuously adjusts the reference signal, and sends the adjusted signal, i.e. the calibration signal, to the chip 14 to be tested again through the instruction test signal source 12, and evaluates the calibration signal received by the chip 14 to be tested, and determines whether the calibration signal meets the receiving requirement of the chip 14 to be tested for the test signal in the current test scene when being used as the received test signal.
If the receiving requirement is met, the current calibration signal is used as a test signal used in a subsequent test scene; if the receiving requirement is not met, continuing to adjust based on the current calibration signal again to generate a new calibration signal, sending the adjusted new calibration signal to the chip to be tested 14 again through the indication test signal source 12, evaluating the new calibration signal received by the chip to be tested 14, judging whether the new calibration signal meets the receiving requirement of the chip to be tested 14 for the test signal in the current test scene when being used as the received test signal, and repeating the steps until the latest calibration signal meets the receiving requirement when being used as the received test signal, and taking the latest calibration signal as the test signal used in the subsequent test scene.
It can also be seen that the calibration signals each time the test signal source 12 sends out are divided into two types, one being the signal obtained after adjustment for the reference signal sent out last time, that is, the adjustment calibration process is performed only 1 time; the other is a signal obtained after adjustment for the calibration signal sent last time, that is, the adjustment calibration process is performed at least 2 times.
In an actual application scenario, the test system supporting millimeter wave emission provided by the application may include three test signal sources and a set of digital control buses for performing radio frequency parameter calibration.
Each test signal source parameter:
the highest simultaneously supports 4 transmitters, and 4 receivers operate simultaneously. Before the test starts, the calibration kit is used to calibrate the radio frequency parameters via the control bus.
The frequency ranges are 59Ghz-64Ghz,77Ghz-81Ghz;
transmitting end power range after calibration: -70dBm to +10dBm;
the receiving end can receive the signal to be measured of +15dBm after calibration.
The transmission and reception precision after calibration is <0.3dB.
The calibrated diphone signal can support-50 dBm to +13dBm;
based on the parameters, the test system can provide comprehensive coverage for gain test, linearity test and gain compression point test of the millimeter wave transceiver.
Compared with the related art, in the embodiment of the application, the upper computer sends the test instruction to at least one test signal source through the control bus according to the test signal receiving requirement; at least one test signal source sends test signals to the chip to be tested according to the received test instructions, and the total test signals received by the chip to be tested meet the test signal receiving requirements. According to the scheme, the upper computer can start different test signal sources through the control bus according to different test items, so that the test signals generated by the test signal sources support a high power dynamic range, and the receiving requirements of the chip to be tested on the test signals are met.
Another embodiment of the invention is directed to an electronic device, as shown in fig. 3, comprising at least one processor 202; and a memory 201 communicatively coupled to the at least one processor 202; wherein the memory 201 stores instructions executable by the at least one processor 202, the instructions being executable by the at least one processor 202 to enable the at least one processor 202 to perform any one of the method embodiments described above.
Where memory 201 and processor 202 are connected by a bus, the bus may comprise any number of interconnected buses and bridges, the buses connecting together various circuits of one or more of the processor 202 and memory 201. The bus may also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or may be a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor 202 is transmitted over a wireless medium via an antenna, which further receives the data and transmits the data to the processor 202.
The processor 202 is responsible for managing the bus and general processing and may also provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. And memory 201 may be used to store data used by processor 202 in performing operations.
Another embodiment of the present invention relates to a computer-readable storage medium storing a computer program. The computer program, when executed by a processor, implements any of the method embodiments described above.
That is, it will be understood by those skilled in the art that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program stored in a storage medium, where the program includes several instructions for causing a device (which may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps in the methods of the embodiments described herein. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the invention and that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims (17)
1. A test system, comprising: the system comprises an upper computer, at least two test signal sources, a control bus, a chip to be tested and a signal transmission medium, wherein the upper computer is connected with the test signal sources through the control bus, and the test signal sources are in communication connection with the chip to be tested through the signal transmission medium;
the upper computer is used for sending test instructions to the at least two test signal sources through the control bus according to the test signal receiving requirements so as to instruct at least one of the test signal sources to send test signals to the chip to be tested, and the total test signals received by the chip to be tested meet the test signal receiving requirements.
2. The test system of claim 1, wherein the test system comprises a plurality of test cells,
the upper computer is further used for adjusting and calibrating the test signals sent by the test signal sources for a plurality of times to determine the number of the test signal sources used for sending the test signals to the chip to be tested and the frequency and the power of the sent test signals.
3. The test system of claim 1, wherein the test signal source is a test chip.
4. The test system of claim 1, wherein test signals from the at least two test signal sources are collected to a same location via the signal transmission medium and then transmitted to the chip under test.
5. The test system of claim 1, wherein the dynamic power range of the test signals from the at least two test signal sources when received by the chip under test is greater than or equal to 80db.
6. The test system of claim 5, wherein the chip under test is a millimeter wave radar chip.
7. The test system of claim 1, wherein the signal transmission medium is a waveguide structure or an antenna.
8. The test system of claim 1, wherein the at least two test signal sources comprise: the first test signal source, the second test signal source and the third test signal source;
the first test signal source is used for sending a test signal to the chip to be tested in CG test;
the second test signal source is used for sending test signals to the chip to be tested in the 2tone test together with the first test signal source; and the signal test module is used for sending a signal test to the chip to be tested which is in an RX blocker test;
And the third test signal source is used for sending a signal test to the chip to be tested which is in the RX blocker test.
9. The test system of claim 8, wherein the test system comprises a plurality of test cells,
the output power of each test signal source in the at least two test signal sources is [ -20, 10] dBm;
when in CG test, the maximum output power of the first test signal source is-70 dBm, and the power loss when the test signal sent by the first test signal source reaches the chip to be tested through the signal transmission medium is [ -80, -50] dBm;
when in CG test, the minimum output power of the first test signal source is-50 dBm, and the power loss when the test signal sent by the first test signal source reaches the chip to be tested through the signal transmission medium is [ -60, -30] dBm.
10. A test signal transmission method applied to the test system of any one of claims 1 to 9, the method comprising:
the upper computer sends a test instruction to at least one test signal source through a control bus according to the test signal receiving requirement;
and the at least one test signal source sends test signals to the chip to be tested according to the received test instruction, and the total test signals received by the chip to be tested meet the test signal receiving requirement.
11. The method of claim 10, wherein the step of determining the position of the first electrode is performed,
the upper computer sends a test instruction to at least one test signal source through a control bus according to the test signal receiving requirement, and the method comprises the following steps: the upper computer sends a test instruction to each test signal source through the control bus according to the test signal receiving requirement, wherein the test instruction comprises a signal source identifier of the test signal source instructed to send the test signal and the frequency and power requirements of the sent test signal;
the at least one test signal source sends test signals to the chip to be tested according to the received test instruction, and the method comprises the following steps: and the test signal source corresponding to the signal source identifier sends a test signal meeting the frequency and power requirements indicated by the test signal source in the test instruction to the chip to be tested.
12. The method of claim 10, wherein the step of determining the position of the first electrode is performed,
the upper computer sends a test instruction to at least one test signal source through a control bus according to the test signal receiving requirement, and the method comprises the following steps: the upper computer respectively sends test instructions to the appointed test signal sources through a control bus according to the test signal receiving requirement, wherein the test instructions comprise frequency and power requirements for indicating the test signals sent by the appointed test signal sources;
The at least one test signal source sends test signals to the chip to be tested according to the received test instruction, and the method comprises the following steps: and the test signal source receives the test instruction and sends a test signal with frequency and power requirements indicated in the received test instruction to the chip to be tested.
13. The method as recited in claim 10, further comprising:
and the upper computer adjusts and calibrates the test signals sent by the test signal sources for a plurality of times to determine the number of the test signal sources used for sending the test signals to the chip to be tested and the frequency and the power of the sent test signals.
14. The method of claim 13, wherein the host computer adjusts and calibrates the test signal sent by each of the test signal sources a plurality of times, comprising:
the upper computer sends a reference signal instruction to at least one test signal source through a control bus according to the test signal receiving requirement, wherein the reference signal instruction comprises the frequency and the power of the test signal source for sending a reference signal and the reference signal;
the upper computer adjusts and indicates the frequency and the power of the test signal source for sending the calibration signal and the frequency and the power of the calibration signal for many times according to the frequency and the power of the reference signal received by the chip to be tested until the calibration signal received by the chip to be tested meets the receiving requirement of the test signal when being used as the received test signal;
The calibration signal sent by the test signal source each time is a signal obtained by adjusting the reference signal sent last time or the calibration signal sent last time.
15. The method as recited in claim 14, further comprising:
the upper computer selects the test signal sources for transmitting the reference signals and determines the frequency and the power of the transmitted reference signals according to the output power range of each test signal source, the power loss when the test signals transmitted by the test signal sources reach the chip to be tested through a signal transmission medium and the test signal receiving requirement.
16. An electronic device, comprising:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the test signaling method of any one of claims 10-15.
17. A computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the test signaling method of any of claims 10-15.
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