CN117651227A - Image processing device, method, chip, liquid crystal display and storage medium - Google Patents
Image processing device, method, chip, liquid crystal display and storage medium Download PDFInfo
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- 238000003672 processing method Methods 0.000 claims description 19
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
- H04N23/68—Control of cameras or camera modules for stable pick-up of the scene, e.g. compensating for camera body vibrations
- H04N23/682—Vibration or motion blur correction
- H04N23/685—Vibration or motion blur correction performed by mechanical compensation
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
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Abstract
The invention provides an image processing device, a method, a chip, a liquid crystal display and a storage medium, wherein an adaptive space-time domain dithering index logic table is selected for the current frame of pixel data, and the same bit width adjustment bit width dithering process is carried out through repeated multiplexing, so that the bit width of the pixel data is converted into the driving bit width of the liquid crystal display, on one hand, the aim of multi-step space-time domain dithering is fulfilled under the condition that a hardware logic circuit and a hardware storage space are not greatly increased, the high-bit width image data is displayed on the liquid crystal display with low driving bit width, a good display effect is achieved, and the richness and smoothness of display colors are ensured; on the other hand, noise caused by overlapping local area brightness by using a single lookup table can be avoided. Meanwhile, the call of storage and operation resources is reduced, and the cost is reduced.
Description
Technical Field
The disclosure relates to the technical field of displays, and in particular relates to an image processing device, an image processing method, a chip, a liquid crystal display and a storage medium.
Background
In the liquid crystal display, each liquid crystal molecule is driven by different voltages to turn over to different degrees, so that different light amounts pass through the color filter, and colors with different brightness are displayed.
The finer the control of the voltage, i.e., the higher the driving bit width of the display panel, the higher the fineness of the displayed image, the smoother the color transition, and the better the image quality. However, finer voltage control requires more circuits, which increases driving cost. In order to save driving cost and maintain image quality, a dithering technique is mainly used at present.
The frame rate control algorithm utilizes the visual inertia of human eyes to brightness change, and achieves the aim of displaying more colors through the dithering of multiple frames. The frame rate control algorithm combines time and space dithering to realize the brightness balance in time domain and space domain, and achieve better color mixing effect. Through dithering in the space domain, the brightness of a plurality of pixel points in the space domain is the effect of equally dividing the brightness when the human eyes acquire the brightness, so that the intermediate gray scale corresponding to the high gray scale data originally can be acquired.
However, the existing dithering processing algorithm occupies a lot of operation resources, but has low processing efficiency and poor processing effect, and can cause uneven brightness distribution of high-bit data in screen display on a low-bit panel and have bad phenomena such as flickering.
Disclosure of Invention
The application provides an image processing device, an image processing method, a chip, a liquid crystal display and a storage medium, which can achieve the aim of multi-step time-space domain dithering under the condition of not greatly increasing a hardware logic circuit and a hardware storage space, enable high-bit data to achieve good display effect on a low-bit panel, reduce the call of storage and operation resources and reduce the cost.
According to a first aspect of the present application, there is provided an image processing apparatus comprising:
an acquisition unit configured to acquire pixel data in image data, the pixel data having an initial bit width higher than a driving bit width at the time of display of a liquid crystal display;
a bit width processing unit for performing a bit width reduction process on one of a plurality of spatial-temporal dithering index logic tables selectively configured for a current frame of the pixel data through multiplexing so that the pixel data is converted from the initial bit width to the driving bit width,
the panel driving chip of the liquid crystal display displays the acquired pixel data after the bit width processing,
and the plurality of space-time domain dithering index logic tables are used for representing the corresponding relation of the values of the pixel data before and after the bit width processing, and the adjustment bit widths adapted by different space-time domain dithering index logic tables are different.
In one possible implementation, the bit width processing unit includes:
and the dithering module is used for correspondingly searching and acquiring a space domain lookup table in the storage module to dither the current frame of the current pixel data through the space domain dithering index logic table with the index adapted to the current adjustment bit width, so that the adjustment bit width is subtracted from the current bit width by the current pixel data.
In another possible implementation, the dithering module is further configured to:
and controlling a plurality of data blocks in the current frame of the current pixel data to index to the same spatial domain lookup table, or controlling a plurality of data blocks in the current frame of the current pixel data to index to the corresponding spatial domain lookup tables respectively.
In another possible implementation manner, the multiplexed space-time domain dithering index logic table is multiplexed in the multi-frame bit width adjustment that adapts the pixel data in the same period, if the adjustment bit widths of different frames are the same.
In another possible implementation manner, the image processing apparatus further includes:
a color compensation unit for performing color compensation on pixel data in the image data;
The motion compensation unit is used for performing motion compensation on the pixel data subjected to the color compensation, and the acquisition unit is specifically used for acquiring the pixel data subjected to the motion compensation in the image data;
and the data mapping unit is used for logically arranging the pixel data subjected to the dithering treatment according to the gate circuit design of the panel of the liquid crystal display and re-mapping and arranging the input image data according to the panel driving chip.
In another possible implementation manner, when the at least one dithering module performs dithering processing on the pixel data by using a preset n frame as a period in the process of adapting the space-time domain dithering index logic table through an index, when determining a value of a least significant bit, querying an n x n space domain lookup table corresponding to the least significant bit according to a frame number of a current processed image, and searching an i n x n space domain lookup table according to an i frame image data in any period, wherein i=0, 1, 2, … … n-1, n is a positive integer.
According to a second aspect of embodiments of the present application, there is provided an image processing method, including:
acquiring pixel data in image data, wherein the pixel data has an initial bit width which is higher than a driving bit width when a liquid crystal display displays;
Performing bit width reduction processing on one of a plurality of space-time domain dithering index logic tables selectively configured for a current frame of the pixel data through multiplexing so that the pixel data is converted from the initial bit width to the driving bit width;
display is performed based on the pixel data after the bit width processing,
the space-time domain dithering index logic tables are used for representing the corresponding relation of the values of pixel data before and after bit width processing, and the adjustment bit widths adapted by different space-time domain dithering index logic tables are different.
In one possible implementation manner, the step of performing the bit width reduction processing through multiplexing by using one of the plurality of space-time domain dithering index logic tables selectively configured for the current frame of the pixel data includes:
adapting the space-time domain jitter index logic table with the current adjustment bit width through indexes by utilizing at least one jitter module;
and correspondingly searching and acquiring a spatial domain lookup table in the storage module to dither the current frame of the current pixel data, so that the current pixel data subtracts the adjustment bit width from the current bit width.
In another possible implementation manner, the step of correspondingly searching and acquiring a spatial look-up table in the storage module to dither the current frame of the current pixel data, so that the current pixel data subtracts the adjustment bit width from the current bit width includes:
And controlling a plurality of data blocks in the current frame of the current pixel data to index to the same spatial domain lookup table, or controlling a plurality of data blocks in the current frame of the current pixel data to index to the corresponding spatial domain lookup tables respectively.
In another possible implementation manner, the multiplexed space-time domain dithering index logic table is multiplexed in the multi-frame bit width adjustment that adapts the pixel data in the same period, if the adjustment bit widths of different frames are the same.
In another possible implementation manner, the step of adapting the space-time domain jitter index logic table of the current adjustment bit width by indexing by using at least one jitter module includes:
and in the process of dithering the pixel data, when a preset n frame is taken as a period and the value of the least significant bit is determined, inquiring an n x n space domain lookup table corresponding to the least significant bit according to the frame number of the current processed image, and searching an i th n x n space domain lookup table according to the i th frame of image data in any period, wherein i=0, 1, 2 and … … n-1, and n is a positive integer.
According to a third aspect of the present application, there is provided a chip comprising the image processing apparatus according to the embodiment of the first aspect.
According to a fourth aspect of the present application, there is provided a liquid crystal display comprising:
a display panel; and
the chip of the third aspect.
According to a fifth aspect of the present application, there is provided a computer readable storage medium having stored thereon a computer program or instructions which, when executed, control a device on which the storage medium is located to perform an image processing method according to an embodiment of the second aspect.
The beneficial effects that this application provided technical scheme brought are: the adaptive space-time domain dithering index logic table is selected for the current frame of the pixel data, and the same bit width reducing dithering process is carried out by multiplexing for a plurality of times, so that the bit width of the pixel data is converted into the driving bit width of the liquid crystal display, on one hand, the aim of multi-step time-space dithering is fulfilled under the condition that a hardware logic circuit and a hardware storage space are not greatly increased, the high-bit-width image data is displayed on the liquid crystal display with low driving bit width, a good display effect is achieved, and the richness and smoothness of display colors are ensured; on the other hand, noise caused by overlapping local area brightness by using a single lookup table can be avoided.
In addition, in the multi-frame bit width adjustment of the adaptive pixel data in the same period, if the adjustment bit widths of different frames are the same, the above-mentioned spatial-temporal dithering index logic table is multiplexed, the least significant bit of each frame in each dithering module is changed, and each step has a corresponding lookup table, but based on the same adjustment bit width, the lookup table can be multiplexed for multiple times, so that the modification of the adjustment mapping logic and the call of the operation resource are reduced, and the multi-step bit width reduction processing replaces the original one-step bit width reduction processing, thereby not only reducing the operation cost and the storage cost, but also further ensuring the stability and smooth transition of the dithering processing process, and the processed image data has good display effect.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
FIG. 1 shows a process diagram of high-bit data to a display in an embodiment of the present application;
FIG. 2 is a schematic view showing the structure of an image processing apparatus in one embodiment of the present application;
FIG. 3 is a schematic diagram illustrating a process of processing data by a dithering module in a bit width processing unit according to an embodiment of the present application;
Fig. 4 shows a flowchart of an image processing method in an embodiment of the present application;
FIG. 5 shows a process schematic of an image processing method in one embodiment of the present application;
FIG. 6 shows a process schematic of an image processing method in another embodiment of the present application;
FIG. 7 is a diagram of a lookup table of a dithering module in performing multi-step low 3-bit dithering in accordance with an embodiment of the present application;
FIG. 8 is a diagram of a lookup table of a dithering module in performing multi-step low 2-bit dithering in an embodiment of the present application;
fig. 9 shows a schematic structural diagram of an image processing apparatus in still another embodiment of the present application.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
The LCD panel mainly comprises an upper polarizer, a lower polarizer, a color filter, a liquid crystal layer, a TFT substrate and a backlight source, wherein the LCD panel converts received digital signals of three primary colors (red, green and blue) into analog voltage signals, liquid crystals are organic compounds between solid and liquid states, when different voltages are applied to liquid crystal molecules, the liquid crystal molecules can deflect to different degrees, the arrangement mode of the liquid crystal molecules is changed, the incident light beam is influenced to produce intensity change through the liquid crystal, and the liquid crystal display panel displays colors with different brightness after being processed through the color filter.
The larger the bit width is, the finer the analog circuit voltage control of the display panel is, so that the control of luminous flux can be accurately realized, the more accurate color display and the better image quality are realized, but the increase of the bit width requires the addition of more control circuits, and the cost for manufacturing the LCD can be greatly increased. Therefore, in image processing, it is often necessary to convert a high-level image into a low-level image, so as to ensure that a storage device or a display device can cooperate with each other, for example, when 10 bits of image data are to be output on an 8-bit liquid crystal display, the conversion of the image data from 10 bits of extra-high level to 8 bits of low level is required. If a simple truncate operator or a truncating operator is adopted to realize the conversion from a high color level to a low color level, mach band effect (Mach band effect) exists in the finally obtained image, and the viewing effect is poor. In order to avoid the mach band effect, a common conversion method is dithering (dimming) process, and the dithering process on the time domain and the space domain is utilized to realize that the low-color-level image has the visual picture quality close to or even the same as that of the high-color-level image, so that the dithering of the time domain and the space domain, called 3D dithering process of the time domain and the space domain, is often adopted in the image processing, so as to better reduce the mach band effect introduced by converting the high-color-level image into the low-color-level image.
However, in practical applications, it is found that the existing time domain and space domain dithering processing technology adopts a mode of space domain dithering and time domain dithering, that is, multi-bit data is firstly reduced through space domain dithering, and when 2 bits or 3 bits of data are reduced through space domain dithering, for example, from 14 bits to 6 bits are needed, then 6 bits of space domain dithering and 2 bits of time domain dithering are needed, but the mode of space domain and time domain dithering still may cause a problem of local or whole flicker (flicker) of an image frame because a fixed dithering matrix is used for the first step of space domain dithering, and these phenomena are particularly obvious when the image is static, are visually visible, reduce the picture quality and influence the viewing experience of viewers.
In addition, the whole image or the whole area of the traditional dithering algorithm adopts a fixed dithering matrix at present, so that the processed image is accompanied by stable dithering noise, and obvious flickering phenomenon can occur for some panels with poor quality. If the data displayed by the panel is a still picture, a fixed dither matrix is used. The logic circuits for processing these blocks are the same for each block of the current frame, and the current block can be regarded as uniform in space, but the brightness distribution is uneven because of overlapping at the same position every time in time, and flicker phenomenon exists, resulting in poor display performance of the liquid crystal display. Therefore, the present disclosure proposes a strategy for reducing the data bit width by multiple time-space domain dithering.
The present disclosure is described in detail below with reference to the accompanying drawings.
The LCD mainly completes the processing of display data through a display logic operation chip, the panel driving chip controls the panel to display different colors, the display logic operation chip always adopts a high-bit operation mode in order to keep higher precision in the operation process, after the intermediate link data processing is completed, a low-bit panel cannot display high-bit data, the high-bit data is required to be converted into the low-bit data, when the panel is directly taken for displaying the corresponding bit width of the high-bit data, the display quality of the display is poor, a plurality of band-shaped truncated textures can appear on the image, and in order to keep more data information, the display effect of the high-bit data is displayed on the low-bit panel in a shaking mode, namely, the display effect of displaying 10 bits on the 8-bit panel is theoretically realized, and the production cost is reduced.
A process diagram of high-bit data to a display is given as shown in fig. 1. After the TCON display logic operation chip receives the input high-bit data (image data), the TCON display logic operation chip processes the high-bit data and outputs the low-bit data which is suitable for the panel to the panel driving chip, and the purpose of displaying the high-bit data on the display panel can be achieved.
It is understood that the panel driving chip of the liquid crystal display may be, for example: the gate driving chip (Gate Driving Integrated Chip, GIP) and the source driving chip (Source Driving Integrated Chip) are combined in one or more ways, the TCON display logic operation chip in communication connection with the panel driving chip can process image data according to a mapping table stored in the storage device to generate data required by the gate driving chip and the source driving chip, the gate driving chip and the source driving chip convert the received data into switching signals and voltage signals according to a certain time sequence and drive liquid crystal molecules corresponding to each pixel in the display panel to turn over in different degrees, so that light passes through the liquid crystal and passes through the color filter plate, and the display panel presents different color levels.
Fig. 2 shows a schematic structural diagram of an image processing apparatus in one embodiment of the present application. Fig. 3 is a schematic diagram illustrating a process of processing data by a dithering module in a bit width processing unit according to an embodiment of the present application.
As shown in fig. 2, in one embodiment of the present application, the image processing apparatus 100 includes at least: an acquisition unit 110 and a bit width processing unit 120.
The acquiring unit 110 is configured to acquire pixel data in the input image data, where the pixel data has an initial bit width higher than a driving bit width when the liquid crystal display displays;
The bit width processing unit 120 is configured to perform a bit width reduction process by multiplexing one of a plurality of spatial-temporal dithering index logic tables selectively configured for a current frame of pixel data, such that the pixel data is converted from an initial bit width to a driving bit width,
the panel driving chip 210 of the lcd 200 displays the obtained pixel data after the bit width processing, and the above-mentioned multiple space-time domain dithering index logic tables are used to characterize the corresponding relationship between the values of the pixel data before and after the bit width processing.
In this embodiment, the adjusting bit widths of the different space-time domain dithering index logic tables are different, for example, the adjusting bit widths may be 2 bits or 3 bits, and a smaller number of bits is generally selected, so that on one hand, compatibility is stronger, in multi-step bit width processing of different frames of current pixel data, the configured lookup tables can be used as universal lookup tables to multiplex each other, modification of the mapping logic is only performed in the using stage, when multi-step lowering bit width processing is performed on input data with different bit widths, the probability that the selectable space-time domain dithering index logic table is multiplexed is larger, resource utilization rate is high, on the other hand, because the adjusting bit width value is small, the lowering bit width value of each lowering bit width processing is also small, a large amount of data is not easy to be lost before and after the relative processing, and is displayed on the panel display end, so that transition of displaying tone steps is smooth, the stripe appearing in the image caused in the process of directly lowering the bit width of high-bit (bit) data to the low-level phenomenon data which accords with panel driving in the prior art can be effectively improved, the stripe display effect is greatly improved, and the bandwidth of the stripe display is greatly improved, and the bandwidth is small in the operation, the operation is small, the operation cost is reduced, and the operation is small, and the operation cost is small.
In some embodiments, the bit width processing unit includes: at least one dithering module, each dithering module can be used for adapting the space-time domain dithering index logic table of the current adjusting bit width through indexes, and correspondingly searching and acquiring the space-domain lookup table in the storage module to dither the current frame of the current pixel data, so that the current pixel data subtracts the adjusting bit width from the current bit width.
As shown in fig. 3, in the present embodiment, the bit width processing unit 120 includes: the number of dither modules 1, 2, and 3 is of course given by way of example only, and in other alternative embodiments the actual number of uses may be set by reference and the configuration of each dither module is the same.
In some embodiments, the dithering module described above may also be used to: and controlling a plurality of data blocks in the current frame of the current pixel data to index to the same spatial domain lookup table, or controlling a plurality of data blocks in the current frame of the current pixel data to index to the corresponding spatial domain lookup tables respectively.
In this embodiment, in order to achieve the purpose of dithering high-bit data to low-bit data, a general 2-bit or 3-bit space-time domain dithering index logic table is designed, and the table is composed of a plurality of n×n lookup tables (LUTs), and each data block space domain of the current frame of the current data is simultaneously indexed with a lookup table, or each data block can be searched for a respective n×n lookup table according to a corresponding lookup logic. In particular, for the purpose of multi-step down bit width, it is necessary to define the index logic of each step of the lookup table to ensure that there is a differentiation in the lookup table for each frame, while multiplexing the already input lookup tables.
The following describes in detail the technical solutions of the image processing method and the image processing apparatus provided in the present application with reference to fig. 3 to 9.
What needs to be explained here is: the image processing method provided by the embodiment of the application is applied to a time sequence control chip of a liquid crystal display, for example.
Fig. 3 is a schematic flow chart of an image processing method in an embodiment of the present application, and referring to fig. 3, the method may include:
s110: pixel data in the image data is acquired.
The pixel data has an initial bit width, which is higher than the driving bit width of the liquid crystal display.
It is known that, the display panel of the liquid crystal display has a plurality of pixel points, and each pixel point needs to perform color display according to the corresponding pixel data in the process of displaying the image of the liquid crystal display, and the pixel data corresponding to each pixel point is obtained from the image data.
Generally, in order to save driving cost, a liquid crystal display device often adopts a low driving bit width. In order to improve the display effect, the bit width of the pixel data in the image data input to the liquid crystal display is often relatively high. Therefore, the initial bit width of the pixel data in the image data is higher than the driving bit width of the liquid crystal display. For example: the liquid crystal display has a driving bit width of 6-bit, and the pixel data in the image data has a bit width of 8-bit, 10-bit, 12-bit, or the like.
Currently, the mainstream displays are 8-bit driving, there are some 6-bit (bit) and 10-bit driving panels, 6-bit panel theory displays 262626144 (64 x 64) colors at most, the 8-bit panel theory shows a maximum of 16777216 (256 x 256) colors, 10-bit panel theory maximum display 1070599167 (1023×1023×1023) colors.
S120: one of a plurality of spatial-temporal dithering index logic tables selectively configured for a current frame of the pixel data is subjected to a bit width reduction process through multiplexing such that the pixel data is converted from the initial bit width to the driving bit width.
The space-time domain dithering index logic tables are used for representing the corresponding relation of the values of pixel data before and after bit width processing, and the adjustment bit widths adapted by different space-time domain dithering index logic tables are different.
S130: and displaying based on the pixel data after the bit width processing.
After the dithering processing of the pixel data with low bit width is performed for a plurality of times, the time sequence control chip can continue to process the pixel data into the data required by the panel driving chip. And the panel driving chip controls the display panel to display images. In this way, the display of the high-bit-width image data on the low-drive bit-width liquid crystal display is completed.
It should be noted that, in this embodiment, since the process of reducing the initial bit width to the driving bit width requires multiple bit width reducing processes, and based on the lookup table of the preset low bit (adjusting bit width), the adjusting bit width must be divided by the reduced bit number, and the adjusting bit width value is a smaller prime number, so that in the process of reducing the bit number by the multiple steps, the configured space-time domain jitter index logic table is always multiplexed, thereby realizing effective utilization of resources, having small operation amount, occupying less storage resources and greatly saving cost.
Taking the pixel data bit width of the input image data as 14 bits as an example, the input image data is subjected to multi-step bit width reduction processing, so that the input image data can be normally displayed in a display with 8 bits of driving bit width.
Fig. 5 is a schematic diagram of a process of reducing bit width and dithering in an embodiment of the present application, which is applied to the bit width processing unit in the above. Referring to fig. 5, 14-bit dithering to 8-bit may employ the following dithering scheme: the 14 bits are subjected to 3 times of 2-bit space-time dithering to reduce the bit width to 8 bits (i.e., 14 bits are dithered to 12 bits, 12 bits are dithered to 10 bits, 10 bits are dithered to 8 bits, and so on, the bit width of the above pixel data is dithered to 6 bits similarly to the above operation), and when image display is required, the image data (Video Stream) is decoded from the source and input to the bit width processing unit 120. The dithering module in the bit width processing unit 120 performs the following processing for the pixel data of the input high bit:
(1) The dithering module 1 queries the storage module to obtain a space-time domain 2-bit dithering lookup table 1 according to a configured space-time domain dithering index logic table 1 for a frame or an image block, wherein the space-time domain 2-bit dithering lookup table 1 comprises a space-time domain 2-bit dithering lookup table 1 of an R channel, a space-time domain 2-bit dithering lookup table 1 of a G channel and a space-time domain 2-bit dithering lookup table 1 of a B channel, and the space-time domain 2-bit dithering lookup table 1 is used for carrying out logic operation by the dithering module 1. According to the number of the lowest bit of the current dithering module 1, inquiring a 2-bit dithering lookup table 1 to perform 2-bit space-time dithering, respectively reducing the 14-bit pixel data of an R channel to 12-bit, the 14-bit pixel data of a G channel to 12-bit, and the 14-bit pixel data of a B channel to 12-bit, reducing the initial bit width of the current pixel data to 14-12 bit, and then sending the dithering to the dithering module 2;
(2) The dithering module 2 queries the storage module to obtain a space-time domain 2-bit dithering lookup table 2 according to a configured space-time domain dithering index logic table 2 for a frame or an image block, wherein the space-time domain 2-bit dithering lookup table 2 comprises a space-time domain 2-bit dithering lookup table 2 of an R channel, a space-time domain 2-bit dithering lookup table 2 of a G channel and a space-time domain 2-bit dithering lookup table 2 of a B channel, the logic operation is performed by the dithering module 2, the data bit width of the current dithering module 2 is 12 bits, the 2-bit dithering lookup table 2 is queried according to the number of the lowest bits of the current dithering module 2 to perform 2-bit space-time dithering processing, the 12-bit pixel data of the R channel is reduced to 10-bit, the 12-bit pixel data of the G channel is reduced to 10-bit, the bit width of the current pixel data is reduced to 12 bits, and then the dithering processing is performed and then the dithering module 3 is sent;
(3) The dithering module 3 queries the storage module to obtain a space-time domain 2-bit dithering lookup table 3 according to a configured space-time domain dithering index logic table 3 for a frame or an image block, wherein the space-time domain 2-bit dithering lookup table 3 comprises a space-time domain 2-bit dithering lookup table 3 of an R channel, a space-time domain 2-bit dithering lookup table 3 of a G channel and a space-time domain 2-bit dithering lookup table 3 of a B channel, the logic operation is performed by the dithering module 3, the data bit width of the current dithering module 3 is 10 bits, the space-time dithering processing is performed by querying the 2-bit dithering lookup table 3 according to the number of the lowest bits of the current dithering module 3, the 10-bit pixel data of the R channel is reduced to 8-bit, the 10-bit pixel data of the G channel is reduced to 8-bit, the 10-bit pixel data of the B channel is reduced to 8-bit, the bit width of the current pixel data is reduced to 8 bits, and then the dithering processing is performed and then the dithering processing is transmitted to a panel driving chip.
Through the operation, after the pixel data is subjected to the bit width reduction dithering processing of 3 times and 2 bits, the time sequence control chip can continuously process the pixel data into the data required by the panel driving chip. And the panel driving chip controls the display panel to display images. Thus, the full-color-level and higher-quality display effect of the high-bit-width image data on the low-drive-bit-width liquid crystal display is achieved, and the manufacturing cost of the chip can be greatly reduced.
Fig. 6 is a schematic diagram of a process of bit width reduction and dithering according to another embodiment of the present application, which is applied to the bit width processing unit. Referring to fig. 6, 14-bit dithering to 8-bit dithering may also employ the following dithering scheme: the 14 bits are subjected to 2 times 3 bits of space-time domain dithering to reduce the bit width to 8 bits (i.e., 14 bits are dithered to 11 bits, 11 bits are dithered to 8 bits, and so on, the bit width of the above pixel data is dithered to 6 bits similarly to the above operation), and when image display is required, the image data (Video Stream) is decoded from the source and input to the bit width processing unit 120. The dithering module in the bit width processing unit 120 performs the following processing for the pixel data of the input high bit:
(1) The dithering module 1 queries the storage module to obtain a space-time domain 3-bit dithering lookup table 1 according to a configured space-time domain dithering index logic table 1 for a frame or an image block, wherein the space-time domain 3-bit dithering lookup table 1 comprises a space-time domain 3-bit dithering lookup table 1 of an R channel, a space-time domain 3-bit dithering lookup table 1 of a G channel and a space-time domain 3-bit dithering lookup table 1 of a B channel, the logic operation is performed by the dithering module 1, the 3-bit dithering lookup table 1 is queried according to the number of the lowest bit of the current dithering module 1 to perform 3-bit space-time dithering processing, 14-bit pixel data of the R channel is reduced to 11-bit, 14-bit pixel data of the G channel is reduced to 11-bit, the initial bit width of the current pixel data is reduced to 14-11 bit, and then the dithering processing is performed and the dithering processing is sent to the dithering module 2;
(2) The dithering module 2 queries the storage module to obtain a space-time domain 3-bit dithering lookup table 2 according to a configured space-time domain dithering index logic table 2 for a frame or an image block, wherein the space-time domain 3-bit dithering lookup table 2 comprises a space-time domain 3-bit dithering lookup table 2 of an R channel, a space-time domain 3-bit dithering lookup table 2 of a G channel and a space-time domain 3-bit dithering lookup table 2 of a B channel, the logic operation is performed by the dithering module 2, the data bit width of the current dithering module 2 is 11 bits, the 3-bit dithering lookup table 2 is queried according to the number of the lowest bits of the current dithering module 2 to perform 3-bit space-time dithering processing, the 11-bit pixel data of the R channel is reduced to 8-bit, the 11-bit pixel data of the G channel is reduced to 8-bit, the 11-bit pixel data of the B channel is reduced to 8-bit, and the bit width of the current pixel data is reduced to 11 bits, and then the dithering processing is performed and then sent to a panel driving chip.
Through the operation, after the pixel data is subjected to the bit width reduction dithering processing of 2 times and 3 bits, the time sequence control chip can continuously process the pixel data into the data required by the panel driving chip. And the panel driving chip controls the display panel to display images. Thus, the full-color-level and higher-quality display effect of the high-bit-width image data on the low-drive-bit-width liquid crystal display is achieved, and the manufacturing cost of the chip can be greatly reduced.
In the above embodiment, the same lookup table queried based on space-time domain dithering is sequentially searched by a plurality of dithering modules, the bit width of pixel data in the image data is reduced to the driving bit width of the liquid crystal display, and dithering processing is performed, so that high-bit-width image data is displayed on the liquid crystal display with low driving bit width, and the phenomena of data missing and fixed noise occurring in a fixed dithering matrix used in the large-amplitude bit-width reduction processing and space domain dithering and streak phenomenon generated on a low-bit panel of a picture with smooth transition on a high-bit display panel are avoided.
In this embodiment, when the dithering module performs dithering processing on pixel data by using an index to adapt to a space-time domain dithering index logic table, a preset n frame is taken as a period, and when a value of a least significant bit (Least Significant Bit, LSB) is determined, an n×n space domain lookup table corresponding to the least significant bit is queried according to a frame number of a current processed image, and an i-th frame image data in any period looks up an i n×n space domain lookup table, where i=0, 1, 2, … … n-1, n is a positive integer.
In the embodiment of the application, in the adjustment of the multi-frame bit width of the adaptive pixel data in the same period, if the adjustment bit widths of different frames are the same, the multiplexed space-time domain dithering index logic table is multiplexed.
Fig. 7 and 8 are schematic diagrams showing lookup tables of the dithering module when performing multi-step low 3-bit dithering process and the dithering module when performing multi-step low 2-bit dithering process, respectively, in the embodiment of the present application. More specifically, referring to fig. 7 and 8, the process flow of the dithering module is as follows:
in connection with the foregoing, if the dithering module performs multi-step low 2-bit dithering during processing, the dithering module 1 first indexes the lookup table 1 of the dithering module 1 in the storage module according to the defined space-time domain dithering index logic table 1 for the frame or the image block, and the dithering logic operation module in the dithering module 1 queries the lookup table as shown in fig. 7, wherein the gray block is 1 and the white block is 0.
When LSB [1:0] is 0b01, the LUT corresponding to 0b01 is inquired according to the frame number of the current processing image, when 0b10 is inquired according to the frame number of the current processing image, the LUT corresponding to 0b10 is inquired, and when 0b10 is inquired according to the frame number of the current processing image, the LUT corresponding to 0b11 is inquired. Wherein, [1:0] represents the low 2-bit of the current gray scale value.
In the embodiment of the present application, the LSB [1,0] is based on the low 2-bit data outputted. Taking 8 frames as one period as an example, each channel of the R/G/B three channels is provided with an independent LUT of the dithering module 2, the 8-frame LUT corresponding to 0B01 is inquired according to the frame number of the current processing image when LSB [1:0] is 0B01, the 8-frame LUT corresponding to 0B10 is inquired according to the frame number of the current processing image when 0B10 is 0B10, and the 8-frame LUT corresponding to 0B10 is inquired according to the frame number of the current processing image when 0B11 is 0B 11.
In the dithering module 1, the change of the least significant bit of each frame, the zeroth frame queries the 0 th 8x8 spatial LUT corresponding to the current LSB, the first frame queries the first 8x8 spatial LUT corresponding to the current LSB, and so on. The dithering module 1 is spatial domain dithering in a single frame, and is represented as space-time domain dithering in multiple frames, and through the space-time domain dithering, the block effect of local area brightness superposition caused by using a single LUT can be avoided.
Specifically, the dithering module 1 indexes the data operation in the LUT of the current pixel point as follows:
1) Determining an 8x8LUT corresponding to the current index in the current period according to the frame number in the period of the current frame;
2) According to the positions ln and px of the sub-pixels in the whole image, idx_ln in the horizontal direction and idx_px in the vertical direction in the LUT are calculated, and the numerical value in the LUT is LUT _val;
3) Final output= (input data > > 2) +lookup value lut _val;
after being processed by the time-space domain dithering module 1, the data bit width is up to 12 bits, then the dithering module 2 indexes the LUT2 of the dithering module 2 in a storage module according to the defined space-time domain dithering index logic table 2, the rest logic operation is the same as that of the dithering module 1, the data bit width after dithering is 10 bits, and the logic operation of the dithering module 2 is the same as that of the dithering module 1.
After being processed by the dithering module 2, the data bit width is 10 bits, then the dithering module 3 indexes the LUT3 of the dithering module 3 in the storage module according to the defined space-time dithering index logic table 3, the rest logic operation is the same as that of the dithering module 1, the data bit width after dithering is 8 bits, and the logic operation of the dithering module 3 is the same as that of the dithering module 1.
In the embodiment of the present application, if the dithering module performs multi-step low 3-bit dithering during processing, the dithering module 1 first indexes the lookup table 1 of the dithering module 1 in the storage module according to the defined space-time domain dithering index logic table 1 for the frame or the image block, and the dithering logic operation module in the dithering module 1 queries the lookup table as shown in fig. 8, wherein the gray block is 1 and the white block is 0.
In the embodiment of the present application, the LSB [2,0] is based on the low 3-bit data output. Taking 8 frames as one period as an example, each channel of the R/G/B three channels is provided with an independent LUT of the dithering module 2, when LSB [2:0] is 0B001, the LUT of 8 frames corresponding to 0B001 is inquired according to the number of frames of the current processing image, when 0B010 is 0B010, the LUT of 8 frames corresponding to 0B010 is inquired according to the number of frames of the current processing image, and the like are carried out. Wherein LSB [2:0] represents the low 3-bit of the current gray scale value.
In the dithering module 1, the change of the least significant bit of each frame, the zeroth frame queries the 0 th 8x8 spatial LUT corresponding to the current LSB, the first frame queries the first 8x8 spatial LUT corresponding to the current LSB, and so on. The dithering module 1 is spatial domain dithering in a single frame, and is represented as space-time domain dithering in multiple frames, and can avoid the problem of non-uniformity or flickering of local brightness such as noise superimposed on local area brightness caused by using a single LUT through space-time domain dithering.
Specifically, the dithering module 1 indexes the data operation in the LUT of the current pixel point as follows:
1) Determining an 8x8LUT corresponding to the current index in the current period according to the frame number in the period of the current frame;
2) According to the positions ln and px of the sub-pixels in the whole image, idx_ln in the horizontal direction and idx_px in the vertical direction in the LUT are calculated, and the numerical value in the LUT is LUT _val;
3) Final output= (input data > > 2) +lookup value lut _val;
after the data is processed by the time-space domain dithering module 1, the data bit width is 11 bits, then the dithering module 2 indexes the LUT2 of the dithering module 2 in a storage module according to the defined space-time domain dithering index logic table 2, and the logic operation of the dithering module 2 is the same as that of the dithering module 1.
The input image data is processed by the dithering module and then is processed by the pixel value rearrangement mapping module to be data which accords with the display of the LCD panel and is transmitted to the LCD panel, and the LCD panel driving chip changes the arrangement mode of liquid crystal molecules according to the transmitted data, so that the light intensity passing through the color filter is changed, and the color to be displayed is displayed.
In the TCON display logic operation chip, in order to keep higher precision, the operation of the intermediate module generally adopts a high-bit processing mode, but at the display end, manufacturing cost is greatly increased by manufacturing a high-bit display panel, and more display panels are driven at 8 bits or 6 bits. The different operation modes of the dithering module can design a corresponding dithering logic circuit according to the display bit width (or the driving bit width) of a specific display panel, can achieve the purpose of multi-step time-space domain dithering under the condition of not greatly increasing the hardware logic circuit and the hardware storage space, achieves a good display effect on a low-bit panel, and ensures the richness and smoothness of display colors. Through the design scheme in the embodiment of the application, the problem of stable noise caused by excessive bit reduction of high-bit data on a panel with poor quality in the traditional space domain jitter and time-space domain jitter scheme can be avoided.
Based on the same inventive concept, the embodiments of the present application also provide a liquid crystal display, which may include a display panel and a chip having the image processing apparatus 100.
Referring to fig. 9, in still another embodiment of the present application, a liquid crystal display 200 is proposed, the liquid crystal display 200 including a chip having an image processing apparatus 100 and a display panel (not shown), wherein the image processing apparatus 100 in the chip is similar in structure to the image processing apparatus in the foregoing embodiment, except that the image processing apparatus 100 in the present embodiment further includes: color compensation unit 130, motion compensation unit 140, and data mapping unit 150.
Wherein, the color compensation unit 130 is used for performing color compensation on pixel data in the image data;
the motion compensation unit 140 is configured to perform motion compensation on the color-compensated pixel data, and the acquiring unit 110 is specifically configured to acquire the motion-compensated pixel data in the image data;
the data mapping unit 150 is configured to logically arrange the pixel data subjected to the dithering process of the bit width processing unit 120 according to the gate circuit design of the display panel of the liquid crystal display 200, and to re-map the input image data according to the panel driving chip 210.
Optionally, in other optional embodiments, the image processing method of the foregoing embodiment may further include, before step S110:
color compensation and motion compensation (not shown) are performed on pixel data in the image data;
step S110 may include: and acquiring pixel data subjected to color compensation and motion compensation in the image data.
Before the pixel data is subjected to bit width reduction, the pixel data is subjected to color compensation and motion compensation so as to achieve better display effect in a display panel.
In order to keep more precision in operation, the panel driving chip generally calculates under high bit width, in order to control the manufacturing cost, the panel driving chip generally drives under low bit, directly reduces the bit width of high bit (bit) data to low bit data conforming to the bit width of the panel driving by shifting, which causes the loss of the lowest bit (LSB), is represented on a panel display end, causes the unsmooth transition of the display color level, and has obvious banded stripes in an image, so the display effect is poor.
Along with the increasing of the manufacturing area of the display panel, the delay on the gate drive and the source drive is more and more serious, so that the color cast exists in the reduction of the display effect of the panel, and the display effect, namely the display color, of the same picture at different positions on the panel is particularly different.
Further, specifically, for the input high-bit video stream data, the operation processes such as color compensation and motion compensation are generally operated under high bit, and then the processed data is transmitted to the dithering module for processing, the dithering module will be the low-bit data required by the display panel for displaying, the pixel value rearrangement mapping module (the data mapping unit 150 in this embodiment) rearranges the input image data according to the hardware gate circuit design arrangement of the LCD panel and the source driving chip, so as to meet the display requirement of the LCD panel, and thus the purpose of displaying the high-bit data on the low-bit panel can be achieved.
In addition, because of the influence of the viscosity coefficient of the liquid crystal material, the thickness of the liquid crystal cell and the driving circuit of the liquid crystal cell, the gray scale response speed of the display panel is slower and has deviation with the actual required time, so that the outline blurring or smear phenomenon occurs on the moving picture.
When image display is required, image data (Video Stream) is decoded from a source and input to a color compensation module. The color compensation module performs color compensation on the image data by searching a color compensation table, and sends the image data after the color compensation to the motion compensation module. The motion compensation module sends the image data after motion compensation to the bit width reduction processing module for bit width reduction processing, and the pixel data after bit width reduction processing is processed into data which accords with the display of the LCD panel by the pixel value rearrangement mapping module and is sent to the panel driving chip. The panel driving chip converts the received data into a switching signal and a voltage signal according to a certain time sequence and drives the display panel to display. Thus, a full-color-level, higher-quality display effect of high-bit-width image data on a low-drive-bit-width liquid crystal display is achieved.
According to the technical scheme in each embodiment of the application, the adaptive space-time domain dithering index logic table is selected for the current frame of the pixel data, and the same bit width lowering dithering process is carried out by multiplexing for a plurality of times, so that the bit width of the pixel data is converted into the driving bit width of the liquid crystal display, on one hand, the aim of multi-step space-time domain dithering is fulfilled under the condition that a hardware logic circuit and a hardware storage space are not greatly increased, the high-bit width image data is displayed on the liquid crystal display with low driving bit width, a good display effect is achieved, and the richness and the smoothness of display colors are ensured; on the other hand, noise caused by overlapping local area brightness by using a single lookup table can be avoided.
In addition, in the multi-frame bit width adjustment of the adaptive pixel data in the same period, if the adjustment bit widths of different frames are the same, the spatial-temporal dithering index logic table is called, the least significant bit of each frame in each dithering module is changed, each step is provided with a corresponding lookup table, but the lookup table can be multiplexed for multiple times based on the same adjustment bit width, so that the modification of the adjustment mapping logic and the invocation of operation resources are reduced, and the original large-amplitude one-step bit width reduction processing is replaced by multi-step bit width reduction processing, thereby effectively improving the noise problem of a panel with poor quality when the panel driving chip dithers high bit data to low bit data, reducing the operation cost and the storage cost, further ensuring the stability of the dithering processing process, and enabling the panel display picture to be smoothly transited, thereby enabling the processed image data to have good display effect.
The panel driving chip is a general-purpose chip such as 74HC595, for driving and displaying the processed pixel data. Of course, a dedicated chip may be used to drive the display of the pixel data. The specific type of the driving chip is not limited herein.
It should be noted here that: the description of the apparatus embodiments above is similar to that of the method embodiments above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.
Based on the same inventive concept, as an implementation of the above method, the embodiments of the present application further provide a chip, which may be used to perform the image processing method in one or more of the embodiments described above.
It should be noted here that: the description of the chip embodiments above is similar to that of the method embodiments above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the chip embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.
Based on the same inventive concept, the embodiments of the present application also provide a chip, which may include the image processing apparatus in one or more of the above embodiments.
It should be noted here that: the above description of the liquid crystal display embodiments is similar to that of the chip embodiments described above, with similar advantageous effects as the chip embodiments. For technical details not disclosed in the embodiments of the liquid crystal display of the present application, please refer to the description of the embodiments of the chip of the present application for understanding.
Based on the same inventive concept, the embodiments of the present application also provide a computer-readable storage medium having a computer program or instructions stored thereon; wherein the computer program or instructions, when executed, control a device in which the storage medium resides to perform the image processing method in one or more embodiments described above.
It should be noted here that: the description of the storage medium embodiments above is similar to that of the method embodiments described above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the storage medium embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.
It should be noted that, in the embodiment of the present application, the division of the units is schematic, which is merely a logic function division, and other division manners may be implemented in actual practice. In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a processor-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in part or all or part of the technical solution contributing to the prior art or in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) having computer-usable program code embodied therein.
It should be noted that in the description of the present application, it should be understood that the terms "upper," "lower," "inner," and the like indicate an orientation or a positional relationship, and are merely for convenience of description and simplification of the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it is apparent that the above examples are only examples for clearly illustrating the present application and are not limiting to the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are intended to be within the scope of the present application.
Claims (14)
1. An image processing apparatus, comprising:
an acquisition unit configured to acquire pixel data in image data, the pixel data having an initial bit width higher than a driving bit width at the time of display of a liquid crystal display;
a bit width processing unit for performing a bit width reduction process on one of a plurality of spatial-temporal dithering index logic tables selectively configured for a current frame of the pixel data through multiplexing so that the pixel data is converted from the initial bit width to the driving bit width,
the panel driving chip of the liquid crystal display displays the acquired pixel data after the bit width processing,
and the plurality of space-time domain dithering index logic tables are used for representing the corresponding relation of the values of the pixel data before and after the bit width processing, and the adjustment bit widths adapted by different space-time domain dithering index logic tables are different.
2. The image processing apparatus according to claim 1, wherein the bit width processing unit includes:
and the dithering module is used for correspondingly searching and acquiring a space domain lookup table in the storage module to dither the current frame of the current pixel data through the space domain dithering index logic table with the index adapted to the current adjustment bit width, so that the adjustment bit width is subtracted from the current bit width by the current pixel data.
3. The image processing apparatus of claim 1, wherein the dithering module is further configured to:
and controlling a plurality of data blocks in the current frame of the current pixel data to index to the same spatial domain lookup table, or controlling a plurality of data blocks in the current frame of the current pixel data to index to the corresponding spatial domain lookup tables respectively.
4. The image processing apparatus according to claim 2, wherein the spatial-temporal dithering index logic table that is multiplexed in adapting the multi-frame bit width adjustment of the pixel data in the same period, if the adjustment bit widths of different frames are the same.
5. The image processing apparatus according to claim 2, further comprising:
a color compensation unit for performing color compensation on pixel data in the image data;
the motion compensation unit is used for performing motion compensation on the pixel data subjected to the color compensation, and the acquisition unit is specifically used for acquiring the pixel data subjected to the motion compensation in the image data;
and the data mapping unit is used for logically arranging the pixel data subjected to the dithering treatment according to the gate circuit design of the panel of the liquid crystal display and re-mapping and arranging the input image data according to the panel driving chip.
6. The image processing apparatus according to claim 2, wherein the at least one dithering module, when performing dithering processing on the pixel data by indexing the spatial-temporal dithering index logic table, queries an n x n spatial lookup table corresponding to the least significant bit according to a frame number of a currently processed image when determining a value of the least significant bit with a preset n frame as one period, and searches an i n x n spatial lookup table according to an i frame image data in any period, wherein i=0, 1, 2, … … n-1, n is a positive integer.
7. An image processing method, comprising:
acquiring pixel data in image data, wherein the pixel data has an initial bit width which is higher than a driving bit width when a liquid crystal display displays;
performing bit width reduction processing on one of a plurality of space-time domain dithering index logic tables selectively configured for a current frame of the pixel data through multiplexing so that the pixel data is converted from the initial bit width to the driving bit width;
display is performed based on the pixel data after the bit width processing,
the space-time domain dithering index logic tables are used for representing the corresponding relation of the values of pixel data before and after bit width processing, and the adjustment bit widths adapted by different space-time domain dithering index logic tables are different.
8. The image processing method of claim 7, wherein the step of performing the bit-width reduction process by multiplexing one of the plurality of spatial-temporal dithering index logic tables selectively configured for the current frame of the pixel data through a plurality of times comprises:
adapting the space-time domain jitter index logic table with the current adjustment bit width through indexes by utilizing at least one jitter module;
and correspondingly searching and acquiring a spatial domain lookup table in the storage module to dither the current frame of the current pixel data, so that the current pixel data subtracts the adjustment bit width from the current bit width.
9. The image processing method of claim 8, wherein the step of correspondingly searching and acquiring a spatial look-up table in the memory module to dither a current frame of the current pixel data such that the current pixel data subtracts the adjustment bit width from the current bit width comprises:
and controlling a plurality of data blocks in the current frame of the current pixel data to index to the same spatial domain lookup table, or controlling a plurality of data blocks in the current frame of the current pixel data to index to the corresponding spatial domain lookup tables respectively.
10. The image processing method of claim 7, wherein the spatial-temporal dithering index logic table is multiplexed in adapting the multi-frame bit width adjustment of the pixel data in the same period, if the adjustment bit widths of different frames are the same.
11. The image processing method of claim 8, wherein the adapting the spatial-temporal dithering index logic table of the current adjustment bit width by indexing with at least one dithering module comprises:
and in the process of dithering the pixel data, when a preset n frame is taken as a period and the value of the least significant bit is determined, inquiring an n x n space domain lookup table corresponding to the least significant bit according to the frame number of the current processed image, and searching an i th n x n space domain lookup table according to the i th frame of image data in any period, wherein i=0, 1, 2 and … … n-1, and n is a positive integer.
12. A chip comprising the image processing apparatus according to any one of claims 1 to 6.
13. A liquid crystal display, comprising:
a display panel; and
the chip of claim 12.
14. A computer-readable storage medium, wherein the storage medium has stored thereon a computer program or instructions which, when executed, control a device in which the storage medium is located to perform the image processing method according to any one of claims 7 to 11.
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