CN117650117A - Semiconductor structure and preparation method thereof - Google Patents

Abstract

The present disclosure relates to a semiconductor structure and a method of fabricating the same. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, wherein a conductive pattern layer is formed on the substrate; forming a dielectric layer on the conductive pattern layer, wherein the dielectric layer is provided with a pattern for exposing part of the conductive pattern layer; filling a bonding pad material in the graph of the dielectric layer to form a bonding pad layer; the pad layer is correspondingly connected with the conductive pattern layer. According to the embodiment of the disclosure, the preparation stability of the bonding pad can be improved, so that the risk of collapse of the bonding pad is reduced, and the production yield of the semiconductor structure is effectively improved.

Description

Semiconductor structure and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor integrated circuit manufacturing technology, and in particular, to a semiconductor structure and a method for manufacturing the same.

Background

A dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor memory that randomly writes and reads data at high speed, and is widely used in data storage devices or apparatuses. DRAM is comprised of a plurality of repeating memory cells. Each memory cell typically includes a capacitance structure and a transistor having a gate connected to a word line, a drain connected to a bit line, and a source connected to the capacitance structure.

At present, with the development of semiconductor technology, particularly after the semiconductor process enters into deep submicron and nanometer stages, the size of each component element and the distance between adjacent elements in DRAM are also smaller and smaller, and the preparation of partial elements is widely performed by using high aspect ratio ion etching technology. For example, in preparing the pad layer, it is necessary to form the pad material layer first and then pattern the pad material layer using a high aspect ratio ion etching technique to form the pad. However, as the size of each component element and the spacing between adjacent elements in the DRAM become smaller, the pads prepared by the above method are prone to collapse, which affects the yield of the DRAM.

From the above, how to effectively avoid the collapse of the bonding pad prepared by adopting the high aspect ratio ion etching technology is also a problem to be solved in the related technology.

Disclosure of Invention

Based on this, the embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which can improve the preparation stability of a bonding pad, so as to reduce the risk of collapse of the bonding pad, thereby effectively improving the production yield of the semiconductor structure.

In one aspect, some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a substrate, wherein a conductive pattern layer is formed on the substrate; forming a dielectric layer on the conductive pattern layer, wherein the dielectric layer is provided with a pattern for exposing part of the conductive pattern layer; filling a bonding pad material in the graph of the dielectric layer to form a bonding pad layer; the pad layer is correspondingly connected with the conductive pattern layer.

In some embodiments of the present disclosure, before the forming of the pad layer, the preparation method further includes: and grinding the structure obtained after filling the bonding pad material.

In some embodiments of the present disclosure, before the forming of the pad layer, the preparation method further includes: and cleaning the structure obtained after grinding.

In some embodiments of the present disclosure, after the forming of the pad layer, the preparing method further includes: performing a rib cutting molding process on the obtained structure after the bonding pad layer is formed to form a plurality of bonding pads; wherein the conductive pattern layer includes a plurality of conductive portions; the bonding pad is correspondingly connected with the conductive part.

In some embodiments of the present disclosure, the substrate includes a cell array region and a core circuit region located beside the cell array region; the bonding pad in the cell array area is a contact pad, and the conductive part in the cell array area is a conductive contact structure; the contact pad is correspondingly connected with the conductive contact structure, and the orthographic projection of the contact pad on the substrate is positioned on one side of the orthographic projection of the conductive contact structure on the substrate and is overlapped with the orthographic projection part of the conductive contact structure on the substrate.

In some embodiments of the present disclosure, the forming a dielectric layer on the conductive pattern layer includes: and sequentially stacking a first dielectric material layer and a second dielectric material layer on the conductive pattern layer, and performing a first patterning process on the first dielectric material layer and the second dielectric material layer to form a first initial dielectric layer and a second initial dielectric layer.

In some embodiments of the present disclosure, the first patterning process includes a self-aligned dual imaging process or a self-aligned quad imaging process.

In some embodiments of the present disclosure, the first dielectric material layer is formed to a thickness greater than the second dielectric material layer.

In some embodiments of the present disclosure, the substrate includes a cell array region and a core circuit region located beside the cell array region; the performing a first patterning process on the first dielectric material layer and the second dielectric material layer includes: a grid pattern is formed in a portion of the first dielectric material layer and the second dielectric material layer located within the cell array region, and a linear pattern is formed in a portion of the first dielectric material layer and the second dielectric material layer located within the core circuit region.

In some embodiments of the present disclosure, the performing a dicing process on the resulting structure after forming the pad layer includes:

forming a mask on the second initial dielectric layer and the bonding pad layer; the mask is provided with a rib cutting pattern; based on the rib cutting pattern, performing a second patterning process on the first initial dielectric layer and the second initial dielectric layer to form a first dielectric layer and a second dielectric layer; and removing the mask and the second dielectric layer to form a plurality of bonding pads.

In some embodiments of the present disclosure, the forming a mask on the second initial dielectric layer and the pad layer includes: forming a barrier material layer on the second initial dielectric layer and the bonding pad layer, and forming the mask on the barrier material layer; the preparation method further comprises the following steps: based on the rib cutting pattern, synchronously executing the second patterning process on the barrier material layer, the first initial dielectric layer and the second initial dielectric layer to form a barrier layer, the first dielectric layer and the second dielectric layer; and removing the barrier layer.

In some embodiments of the present disclosure, the barrier layer and the second dielectric layer are both oxide layers; and removing the blocking layer and the second dielectric layer synchronously.

In another aspect, some embodiments of the present disclosure provide a semiconductor structure comprising: a substrate; a conductive pattern layer disposed on the substrate; the conductive pattern layer includes a plurality of conductive portions; the first dielectric layer is arranged on the conductive pattern layer; the first dielectric layer is provided with a pattern, and part of the conductive pattern layer is exposed by the pattern; a plurality of bonding pads filled in the graph of the first dielectric layer; the bonding pad is correspondingly connected with the conductive part.

In some embodiments of the present disclosure, with reference to the substrate, a surface of the pad facing away from the substrate is higher than a surface of the first dielectric layer facing away from the substrate.

In some embodiments of the present disclosure, the substrate includes a cell array region and a core circuit region located beside the cell array region; the bonding pad in the cell array area is a contact pad, and the conductive part in the cell array area is a conductive contact structure; the contact pad is correspondingly connected with the conductive contact structure, and the orthographic projection of the contact pad on the substrate is positioned on one side of the orthographic projection of the conductive contact structure on the substrate and is overlapped with the orthographic projection part of the conductive contact structure on the substrate.

The semiconductor structure and the preparation method thereof provided by the embodiment of the disclosure are as described above. In the embodiment of the disclosure, the preparation flow of the bonding pad is optimized. A dielectric layer having a pattern for exposing a portion of the conductive pattern layer is formed on the conductive pattern layer prior to the formation of the pad layer, and may be used to define the pattern of the pad layer. Based on this, the pad material is filled in the pattern of the dielectric layer, thereby forming the pad layer. In this way, the method for forming the pad layer by firstly defining the pad layer pattern and refilling the pad material can improve the preparation stability of each pad in the pad layer, especially for the pad with a higher depth-to-width ratio, so that the risk of collapse of the pad in the pad layer is effectively reduced, and the production yield of the semiconductor structure is further effectively improved.

Drawings

In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;

FIG. 2 (a) is a schematic cross-sectional view showing a structure of a cell array region after forming a conductive pattern layer according to one embodiment; FIG. 2 (b) is a schematic top view of a structure of a cell array region after forming a conductive pattern layer according to one embodiment;

FIG. 3 (a) is a schematic cross-sectional view of a structure obtained by forming a first patterned reticle and then forming a cell array region according to one embodiment; FIG. 3 (b) is a schematic top view of a first patterned reticle in a cell array region according to one embodiment;

FIG. 4 (a) is a schematic cross-sectional view of a structure of a cell array region after forming a second hard mask layer according to one embodiment; FIG. 4 (b) is a schematic top view of a second hard mask layer in a cell array region according to one embodiment;

FIG. 5 (a) is a schematic cross-sectional view of a structure obtained by forming a cell array region after forming a third hard mask initial structure according to one embodiment; FIG. 5 (b) is a schematic top view of a third hard mask initial structure in a cell array region according to one embodiment;

FIG. 6 (a) is a schematic cross-sectional view of a structure of a cell array region after forming a third hard mask layer according to one embodiment; FIG. 6 (b) is a schematic top view of a third hard mask layer in the cell array region according to one embodiment;

FIG. 7 (a) is a schematic cross-sectional view of a structure obtained by forming a second patterned reticle and then forming a cell array region according to one embodiment; FIG. 7 (b) is a schematic top view of a second patterned reticle in a cell array region according to one embodiment;

FIG. 8 (a) is a schematic cross-sectional view of a structure of a cell array region after forming a fifth hard mask layer according to one embodiment; FIG. 8 (b) is a schematic top view of a fifth hard mask layer in a cell array region according to one embodiment;

FIG. 9 (a) is a schematic cross-sectional view of a structure obtained by forming a cell array region after forming a sixth hard mask initial structure according to one embodiment; FIG. 9 (b) is a schematic top view of a sixth hard mask initial structure in a cell array region according to one embodiment;

FIG. 10 (a) is a schematic cross-sectional view of a structure of a cell array region after forming a sixth hard mask layer according to one embodiment; FIG. 10 (b) is a schematic top view of a sixth hard mask layer in the cell array region according to one embodiment;

FIG. 11 (a) is a schematic cross-sectional view of a structure of a cell array region after forming a first initial dielectric layer and a second initial dielectric layer according to one embodiment; FIG. 11 (b) is a schematic diagram showing a pattern distribution of a second initial dielectric layer in a cell array region according to one embodiment;

FIG. 12 (a) is a schematic cross-sectional view showing a structure of a cell array region after forming a pad layer according to one embodiment; FIG. 12 (b) is a schematic diagram showing a distribution of pads in a cell array region according to one embodiment;

FIG. 13 (a) is a schematic cross-sectional view of a structure obtained by forming a third patterned reticle and then forming a cell array region according to one embodiment; FIG. 13 (b) is a schematic top view of a third patterned reticle in a cell array region according to one embodiment;

FIG. 14 (a) is a schematic cross-sectional view of a structure obtained by forming a post-mask cell array region according to one embodiment; FIG. 14 (b) is a schematic top view of a mask in a cell array region according to one embodiment;

FIG. 15 (a) is a schematic cross-sectional view of a structure obtained by forming a barrier layer in a cell array region according to one embodiment; FIG. 15 (b) is a schematic top view of a barrier layer in a cell array region according to one embodiment;

FIG. 16 (a) is a schematic cross-sectional view of a structure of a cell array region after removing the barrier layer and the second dielectric layer, according to one embodiment; FIG. 16 (b) is a schematic top view of a bonding pad in a cell array region according to one embodiment; fig. 16 (a) and 16 (b) are schematic structural diagrams of a semiconductor structure according to an embodiment;

FIG. 17 is a schematic top view of a relative position between a contact pad and a conductive contact structure within a cell array region according to one embodiment;

FIG. 18 (a) is a schematic cross-sectional view of a structure of a core circuit region after forming a conductive pattern layer according to one embodiment; FIG. 18 (b) is a schematic top view of a structure of a core circuit area after forming a conductive pattern layer according to one embodiment;

FIG. 19 (a) is a schematic cross-sectional view of a structure resulting from forming a first patterned reticle with core circuitry regions, according to one embodiment; FIG. 19 (b) is a schematic top view of a first patterned reticle in a core circuitry region according to one embodiment;

FIG. 20 (a) is a schematic cross-sectional view of a structure of a core circuit region after forming a second hard mask layer, according to one embodiment; FIG. 20 (b) is a schematic top view of a second hard mask layer in a core circuit region according to one embodiment;

FIG. 21 (a) is a schematic cross-sectional view of a resulting structure of a core circuit region after forming a third hard mask initial structure, as provided in one embodiment; FIG. 21 (b) is a schematic top view of a third hard mask blank structure in a core circuit region according to one embodiment;

FIG. 22 (a) is a schematic cross-sectional view of a structure of a core circuit region after forming a third hard mask layer, according to one embodiment; FIG. 22 (b) is a schematic top view of a third hard mask layer in the core circuit region according to one embodiment;

FIG. 23 (a) is a schematic cross-sectional view of a structure obtained by forming a core circuit region after a second patterned reticle, according to one embodiment; FIG. 23 (b) is a schematic top view of a second patterned reticle in a core circuitry region according to one embodiment;

FIG. 24 (a) is a schematic cross-sectional view of a structure of a core circuit region after forming a fifth hard mask layer, according to one embodiment; FIG. 24 (b) is a schematic top view of a fifth hard mask layer in the core circuit region according to one embodiment;

FIG. 25 (a) is a schematic cross-sectional view of a structure resulting from forming a core circuit region after forming a sixth hard mask initial structure, as provided in one embodiment; FIG. 25 (b) is a schematic top view of a sixth hard mask blank structure in the core circuit region according to one embodiment;

FIG. 26 (a) is a schematic cross-sectional view of a structure of a core circuit region after forming a sixth hard mask layer, according to one embodiment; FIG. 26 (b) is a schematic top view of a structure of a core circuit region after forming a sixth hard mask layer, according to one embodiment;

FIG. 27 (a) is a schematic cross-sectional view of a structure of a core circuit region after forming a first initial dielectric layer and a second initial dielectric layer, according to one embodiment; FIG. 27 (b) is a schematic diagram showing a second initial dielectric layer in a core circuit region according to one embodiment;

FIG. 28 (a) is a schematic cross-sectional view of a structure of a core circuit region after forming a pad layer according to one embodiment; FIG. 28 (b) is a schematic top view of a pad layer in a core circuit area according to one embodiment;

FIG. 29 (a) is a schematic cross-sectional view of a structure resulting from forming a third patterned reticle with a core circuit region according to one embodiment; FIG. 29 (b) is a schematic top view of a third patterned reticle in a core circuitry region according to one embodiment;

FIG. 30 (a) is a schematic cross-sectional view of a structure resulting from the formation of a masked core circuit region, as provided in one embodiment; FIG. 30 (b) is a schematic top view of a mask in a core circuit area according to one embodiment;

FIG. 31 (a) is a schematic cross-sectional view of a structure of a core circuit region after forming a barrier layer according to one embodiment; FIG. 31 (b) is a schematic top view of a barrier layer in a core circuit region according to one embodiment;

FIG. 32 (a) is a schematic cross-sectional view of a structure of a core circuit area after removing a barrier layer and a second dielectric layer, according to one embodiment; FIG. 32 (b) is a schematic diagram showing a distribution of pads in a core circuit area according to one embodiment; fig. 32 (a) and 32 (b) are schematic structural diagrams of a semiconductor structure according to an embodiment.

Reference numerals illustrate:

10-a substrate; 11-a conductive pattern layer; 111-a conductive contact structure; 12-a conductive structure; 13-a bottom dielectric layer; 210-a first initial dielectric layer; 2100-a first layer of dielectric material; 30-a pad layer; 31-bonding pads; 311-contact pads; 400-a first hard mask material layer; 410-a second hard mask material layer; 41-a second hard mask layer; 420-a first sacrificial material layer; 430-a second sacrificial material layer; 440-a third hard mask initial structure; 44-a third hard mask layer; 450-fourth hard mask material layer; 460-a fifth hard mask material layer; 46-a fifth hard mask layer; 470-a third sacrificial material layer; 480-fourth sacrificial material layers; 490-sixth hard mask initial structure; 49-a sixth hard mask layer; 50-a first patterned mask; 60-a second patterned mask; 700-a layer of barrier material; 800-a layer of mask material; 80-masking; 810-a fifth sacrificial material layer; 90-third patterned reticle.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present.

It will be understood that, although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.

As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (Physical Vapor Deposition, PVD for short), chemical vapor deposition (Chemical Vapor Deposition, CVD for short), or atomic layer deposition (Atomic Layer Deposition, ALD for short).

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

Currently, with the development of semiconductor technology, especially after the semiconductor process enters deep submicron and nanometer stages, the product yield requirements in the production process of dynamic random access memories (Dynamic Random Access Memory, abbreviated as DRAMs) are increasing. When the pad layer is prepared using the conventional pad preparation method, it is necessary to form the pad material layer first and then pattern the pad material layer to form the pads, i.e., to form a plurality of pads. However, in the process of applying the high aspect ratio ion etching technique to pattern the pad material layer, a partial pad collapse is liable to occur. Illustratively, the bond pads are connected to the corresponding conductive layers by barrier layers; that is, a barrier layer is typically formed prior to forming the pad material layer. Therefore, after forming the pad material layer, in order to remove the barrier layer such as titanium (Ti)/titanium nitride (TiN) and titanium (Ti) by-products remaining on the surface, the barrier layer needs to be laterally etched, which results in easy collapse of the pad during patterning of the pad material layer.

Based on the above, the embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which can effectively avoid the collapse of a bonding pad, thereby improving the product yield of the semiconductor structure. But is not limited thereto, embodiments of the present disclosure may be applied to any structure where collapse needs to be avoided.

Referring to fig. 1, some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The preparation method comprises the following steps.

S10, providing a substrate, wherein a conductive pattern layer is formed on the substrate.

S20, forming a dielectric layer on the conductive pattern layer, wherein the dielectric layer is provided with a pattern for exposing part of the conductive pattern layer.

S30, filling a bonding pad material in the graph of the dielectric layer to form a bonding pad layer; the pad layer is correspondingly connected with the conductive pattern layer.

In the embodiment of the disclosure, the preparation flow of the bonding pad is optimized. A dielectric layer having a pattern for exposing a portion of the conductive pattern layer is formed on the conductive pattern layer prior to the formation of the pad layer, and may be used to define the pattern of the pad layer. Based on this, the pad material is filled in the pattern of the dielectric layer, thereby forming the pad layer. In this way, the method for forming the pad layer by firstly defining the pad layer pattern and refilling the pad material can improve the preparation stability of each pad in the pad layer, especially for the pad with a higher aspect ratio, so that the risk of pad collapse in the pad layer is effectively reduced, and the production yield of the semiconductor structure is effectively improved, for example, the production yield of the dynamic random access memory (Dynamic Random Access Memory, DRAM) is improved.

The patterns in the dielectric layer are used for defining the patterns of the pad layer which are formed later. The patterns in the dielectric layer can be designed according to the number, the size and the positions of the bonding pads to be formed later. The dielectric layer may be formed by patterning after the dielectric material layer is formed.

The dielectric layer may have a single-layer structure or a stacked-layer structure.

The dielectric layer may be formed of an insulating material such as oxide, nitride, or oxynitride, for example.

In some embodiments of the present disclosure, a dielectric layer is formed on the conductive pattern layer in step S20, including steps S21 and S22.

S21, sequentially stacking a first dielectric material layer and a second dielectric material layer on the conductive pattern layer.

S22, a first patterning process is carried out on the first dielectric material layer and the second dielectric material layer, and a first initial dielectric layer and a second initial dielectric layer are formed.

Optionally, the first patterning process includes a self-aligned dual imaging process or a self-aligned quad imaging process.

Optionally, the first dielectric material layer is formed to a thickness greater than the second dielectric material layer. It will be appreciated that the thickness of the second dielectric material layer may be selected based on the exposed height of the formed pads.

It will be appreciated that in some embodiments of the present disclosure, the substrate includes a cell array region and a core circuit region located beside the cell array region. And matching different structural designs of the semiconductor structure in the cell array area and the nuclear power circuit area, wherein patterns formed in the first initial dielectric layer and the second initial dielectric layer are different.

Illustratively, performing a first patterning process on the first dielectric material layer and the second dielectric material layer includes: a grid pattern is formed in a portion of the first dielectric material layer and the second dielectric material layer located within the cell array region, and a linear pattern is formed in a portion of the first dielectric material layer and the second dielectric material layer located within the core circuit region.

Here, the mesh pattern may be, for example, a rectangular mesh, a circular mesh, an elliptical mesh, or the like.

In some embodiments of the present disclosure, after filling the pad material in the pattern of the dielectric layer and before forming the pad layer in step S30, the preparation method further includes: the resulting structure after filling the pad material is ground. It will be appreciated that the pad material is also easily deposited on the surface of the dielectric layer by filling the pad material within the pattern of the dielectric layer by a filling process. Thus, by adopting the grinding process, the part of the pad material covering the dielectric layer can be removed to completely expose the dielectric layer, so that the pad layer with a flat surface can be formed in the pattern of the dielectric layer.

Based on this, in some embodiments of the present disclosure, after grinding the resulting structure after filling the pad material and after forming the pad layer in step S30, the manufacturing method further includes: and cleaning the structure obtained after grinding. In this way, specific impurities of the resulting structure after polishing, such as residual abrasive, organic residues, and metallic contaminants, etc., can be removed to form a pad layer having a better surface quality.

In some embodiments of the present disclosure, after forming the pad layer in step S30, the manufacturing method further includes: and step S40.

S40, performing a rib cutting molding process on the obtained structure after the bonding pad layer is formed, so as to form a plurality of bonding pads; wherein the conductive pattern layer comprises a plurality of conductive parts; the bonding pad is correspondingly connected with the conductive part.

Alternatively, the pads are connected in one-to-one correspondence with the conductive portions. Alternatively, one pad is correspondingly connected to a plurality of conductive portions.

In some embodiments of the present disclosure, a dicing process is performed on the resulting structure after forming the pad layer in step S40, including steps S41 to S43.

S41, forming a mask on the second initial dielectric layer and the bonding pad layer; the mask has a cut rib pattern.

S42, based on the rib cutting pattern, a second patterning process is carried out on the first initial dielectric layer and the second initial dielectric layer, and the first dielectric layer and the second dielectric layer are formed.

S43, removing the mask and the second dielectric layer to form a plurality of bonding pads.

In some embodiments of the present disclosure, forming a mask on the second initial dielectric layer and the pad layer in step S41 includes: a barrier material layer is formed on the second initial dielectric layer and the bonding pad layer, and a mask is formed on the barrier material layer. Correspondingly, step S42 further includes: and synchronously executing a second patterning process on the barrier material layer, the first initial dielectric layer and the second initial dielectric layer based on the rib cutting pattern to form the barrier layer, the first dielectric layer and the second dielectric layer. Step S43 further includes: and removing the barrier layer.

Optionally, the barrier layer and the second dielectric layer are both oxide layers. Therefore, the barrier layer and the second dielectric layer are removed synchronously, and the preparation process of the semiconductor structure is simplified.

It should be added that in some embodiments of the present disclosure, the substrate includes a cell array region and a core circuit region located beside the cell array region; the bonding pad in the cell array area is a contact pad, and the conductive part in the cell array area is a conductive contact structure; the contact pad is correspondingly connected with the conductive contact structure, and the orthographic projection of the contact pad on the substrate is positioned on one side of the orthographic projection of the conductive contact structure on the substrate and is overlapped with the orthographic projection part of the conductive contact structure on the substrate.

Here, the conductive contact structure may alternatively be a storage node contact structure.

In the embodiment of the disclosure, the orthographic projection of the contact pad on the substrate is positioned on one side of the orthographic projection of the conductive contact structure on the substrate and is overlapped with the orthographic projection of the conductive contact structure on the substrate, so that the contact pad is conveniently arranged in a staggered manner, and the space utilization rate is improved.

In order to more clearly illustrate the method for fabricating a semiconductor structure in some of the above embodiments, please understand with reference to fig. 2 (a) to 32 (b), the following embodiments describe a method for fabricating a semiconductor structure according to an embodiment of the disclosure in detail.

In the semiconductor structure, the substrate generally includes a cell array region and a core circuit region beside the cell array region. In order to facilitate the distinguishing understanding, the following is detailed in connection with the preparation methods of the structures of the semiconductor structure in the cell array region and the core circuit region, respectively.

First, taking a method for preparing a semiconductor structure in a cell array region as an example, please understand with reference to fig. 2 (a) to 17.

In step S10, referring to fig. 2 (a) and 2 (b), a substrate 10 is provided, and a conductive pattern layer 11 is formed on the substrate 10.

In some embodiments, the substrate 10 may be constructed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 10 may have a single-layer structure or a multilayer structure. For example, the substrate 10 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, and also for example, the substrate 10 may be a layered substrate comprising a material such as Si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

In some embodiments, in step S10, the conductive pattern layer 11 on the substrate 10 may be formed using steps S11 and S12 as follows.

S11, a conductive pattern material layer is formed on the substrate 10.

S12, patterning the conductive pattern material layer to form the conductive pattern layer 11.

Here, the conductive pattern layer 11 may be directly formed on the surface of the substrate 10, or may be formed on the surface of the target structure on the substrate 10.

Illustratively, as shown in fig. 2 (a), the conductive pattern layer 11 is connected to the substrate 10 through the conductive structure 12, and the orthographic projection of the conductive pattern layer 11 on the upper surface of the substrate 10 coincides with the orthographic projection of the conductive structure 12 on the upper surface of the substrate 10. That is, the conductive structure 12 may be formed on the substrate 10 before the conductive pattern layer 11 is formed over the conductive structure 12. The conductive pattern layer 11 may be made of the same material as the conductive structure 12 or a different material.

It should be noted that, in some embodiments, please continue to refer to fig. 2 (a) and fig. 2 (b), after the conductive pattern layer 11 is formed on the substrate 10, the method further includes: a bottom dielectric layer 13 is deposited on the substrate 10. The bottom dielectric layer 13 covers the surface of the substrate 10 having the conductive pattern layer 11, the sidewalls of the conductive pattern layer 11, and the sidewalls of the conductive structure 12.

Illustratively, the top of the bottom dielectric layer 13 is flush with the top of the conductive pattern layer 11.

The conductive pattern layer 11 is, for example, a conductive metal layer. The material of the conductive pattern layer 11 includes, but is not limited to, tungsten. The conductive structure 12 is a conductive metal and the material of the conductive structure 12 includes, but is not limited to, aluminum. The material of the bottom dielectric layer 13 includes, but is not limited to, silicon nitride.

It will be appreciated that in some examples, a trench isolation structure (not shown) is provided within the substrate 10, and that a plurality of active regions may be partitioned within the substrate using the trench isolation structure to facilitate the formation of transistors within the corresponding active regions. The conductive pattern layer 11 and the conductive structure 12 may be used as a component of a transistor or as a connection lead-out portion of a transistor.

In step S20, referring to fig. 3 (a) to 11 (b), a dielectric layer is formed on the conductive pattern layer 11, and the dielectric layer has a pattern for exposing a portion of the conductive pattern layer 11.

Illustratively, the dielectric layer includes a first dielectric layer and a second dielectric layer disposed in a stack. Accordingly, step S20 further includes steps S21 and S22.

In step S21, referring to fig. 3 (a) and 3 (b), a first dielectric material layer 2100 and a second dielectric material layer 2200 are sequentially stacked on the conductive pattern layer 11.

In step S22, referring to fig. 4 (a) to 11 (b), a first patterning process is performed on the first dielectric material layer 2100 and the second dielectric material layer 2200 to form a first initial dielectric layer 210 and a second initial dielectric layer 220.

By way of example only, the process may be performed,the material of the first dielectric material layer 2100 includes, but is not limited to, silicon nitride (Si ₃ N ₄ ) The method comprises the steps of carrying out a first treatment on the surface of the The material of the second dielectric material layer 2200 includes, but is not limited to, silicon oxide (SiO ₂ )。

Illustratively, the first dielectric material layer 2100 is formed to a thickness greater than the second dielectric material layer 2200. It will be appreciated that the thickness of the second dielectric material layer 2200 may be selected based on the exposed height of the formed pads.

Illustratively, the first patterning process includes a self-aligned dual imaging process or a self-aligned quad imaging process.

The following examples provide one possible implementation of the first patterning process, but are not limited thereto.

As shown in fig. 3 (a) and 3 (b), after sequentially forming the first dielectric material layer 2100 and the second dielectric material layer 2200, the first hard mask material layer 400, the second hard mask material layer 410, and the first patterned reticle 50 may be sequentially stacked on the second dielectric material layer 2200.

Here, the first patterned reticle 50 may be a patterned photoresist layer. The pattern of the first patterned reticle 50 may be designed according to the pattern of the structure to be formed. For example, as shown in fig. 3 (b), the first patterned reticle 50 has a linear pattern, which extends, for example, in a first direction.

And, optionally, with continued reference to fig. 3 (a), a first sacrificial material layer 420 is formed between the first hard mask material layer 400 and the second hard mask material layer 410, and a second sacrificial material layer 430 is formed between the second hard mask material layer 410 and the first patterned reticle 50. Materials of the first hard mask material layer 400 and the second hard mask material layer 410 include, for example, but are not limited to, silicon nitride (Si) ₃ N ₄ ). The first sacrificial material layer 420 and the second sacrificial material layer 430 include, for example, but are not limited to, an anti-reflective material.

As shown in fig. 4 (a) and 4 (b), the second hard mask material layer 410 is patterned based on the first patterned reticle 50 to form the second hard mask layer 41.

Here, in an example in which the second sacrificial material layer 430 is formed, the second sacrificial material layer 430 may be patterned in synchronization with the second hard mask material layer 410 and removed after the second hard mask layer 41 is formed.

As shown in fig. 5 (a) and 5 (b), after forming the second hard mask layer 41, the manufacturing method further includes: a third hard mask initiation structure 440 is formed on the surface (including sidewalls and top surface) of second hard mask layer 41.

Here, the third hard mask initial structure 440 may be optionally formed using a deposition process. Optionally, the material of the third hard mask initial structure 440 includes, but is not limited to, silicon oxide (SiO) ₂ )。

As shown in fig. 6 (a) and 6 (b), after forming the third hard mask initial structure 440, patterning the third hard mask initial structure 440 to form the third hard mask layer 44; and, removing the second hard mask layer 41.

Here, the third hard mask layer 44 includes, for example, a plurality of linear patterns extending in the first direction.

On the basis, referring to fig. 7 (a) and 7 (b), after forming the third hard mask layer 44, a fourth hard mask material layer 450 filling the space between adjacent linear patterns in the third hard mask layer 44, and a fifth hard mask material layer 460 and a second patterned mask 60 stacked in sequence may be formed; wherein the fourth hard mask material layer 450 is flush or substantially flush with the upper surface of the third hard mask layer 44.

Here, the second patterned reticle 60 may be a patterned photoresist layer. The pattern of the second patterned reticle 60 may be designed according to the pattern of the structure to be formed. For example, as shown in fig. 7 (b), the second patterned reticle 60 has a linear pattern, for example, extending in the second direction; the second direction intersects the first direction, and a grid pattern may be formed.

And, optionally, with continued reference to fig. 7 (a), a third sacrificial material layer 470 is formed between the fifth hard mask material layer 460 and both the fourth hard mask material layer 450 and the third hard mask layer 44, and a fourth sacrificial material layer 480 is formed between the fifth hard mask material layer 460 and the second patterned reticle 60. Here, a fourth hard mask material layer 45Materials of the 0 and fifth hard mask material layers 460 include, for example, but are not limited to, silicon nitride (Si) ₃ N ₄ ). Materials of the third sacrificial material layer 470 and the fourth sacrificial material layer 480 include, for example, but are not limited to, an anti-reflective material.

Referring to fig. 8 (a) and 8 (b), the fifth hard mask material layer 460 is patterned to form the fifth hard mask layer 46 based on the second patterned reticle 60.

Here, in an example in which the fourth sacrificial material layer 480 is formed, the fourth sacrificial material layer 480 may be patterned in synchronization with the fifth hard mask material layer 460 and removed after the fifth hard mask layer 46 is formed.

Referring to fig. 9 (a) and 9 (b), after forming the fifth hard mask layer 46, the preparation method further includes: a sixth hard mask initial structure 490 is formed over the surface (including sidewalls and top surface) of the fifth hard mask layer 46.

Here, the sixth hard mask initial structure 490 may be optionally formed using a deposition process. Optionally, the material of the sixth hard mask initial structure 490 includes, but is not limited to, silicon oxide (SiO) ₂ )。

As shown in fig. 10 (a) and 10 (b), after forming the sixth hard mask initial structure 490, patterning the sixth hard mask initial structure 490 to form a sixth hard mask layer 49; and, removing the fifth hard mask layer 46.

Here, the sixth hard mask layer 49 includes, for example, a plurality of linear patterns extending in the second direction.

After forming the third hard mask layer 44 and the sixth hard mask layer 49, the first hard mask material layer 400 may be patterned based on the third hard mask layer 44 and the sixth hard mask layer 49 to form a first hard mask layer (not shown) having a grid pattern in the cell array region on the surface of the second dielectric material layer 2200. Then, the sixth hard mask layer 49, the third sacrificial material layer 470, the third hard mask layer 44, and the first sacrificial material layer 420 may be removed.

Referring to fig. 11 a and 11 b, based on a grid pattern (not shown) of the first hard mask layer in the cell array region, the second dielectric material layer 2200 may be patterned to form the second initial dielectric layer 220, and the first dielectric material layer 2100 may be patterned to form the first initial dielectric layer 210. Thus, referring to fig. 11 (b), a grid pattern may be formed in each of the first initial dielectric layer 210 and the second initial dielectric layer 220.

In step S30, referring to fig. 12 (a) and 12 (b), a pad material is filled in the pattern of the dielectric layer to form a pad layer 30; the pad layer 30 is correspondingly connected to the conductive pattern layer 11.

Here, the dielectric layer may be represented as: the first and second initial dielectric layers 210 and 220 are stacked. The pattern of the dielectric layer may be represented as a mesh pattern formed by the aforementioned preparation.

Illustratively, the material of the pad layer 30 may include, but is not limited to, tungsten.

It will be appreciated that when the pad material is filled in the pattern of the dielectric layer by the filling process, the pad material is also easily deposited on the surface of the dielectric layer. In some examples, the method of making further comprises: the resulting structure after filling the pad material is ground. Thus, the portion of the pad material covering the dielectric layer may be removed using a grinding process to completely expose the dielectric layer to ensure that a planar surface of the pad layer 30 is formed within the pattern of the dielectric layer.

The resulting structure after filling the pad material may be polished, for example, by a chemical mechanical polishing process to ensure that the top surface of the pad layer 30 is planar.

Accordingly, in some examples, the method of making further comprises: and cleaning the structure obtained after grinding. In this way, specific impurities of the resulting structure after polishing, such as residual abrasive, organic residues, and metallic contaminants, etc., can be removed to form a pad layer having a better surface quality.

In step S40, referring to fig. 13 (a) to 16 (b), a rib cutting molding process is performed on the obtained structure after forming the pad layer 30 to form a plurality of pads 31; wherein the conductive pattern layer 11 includes a plurality of conductive parts; the pads 31 are connected to the conductive portions.

The following examples provide one possible implementation of the rib cutting molding process, but are not limited thereto. Step S40 includes, for example, steps S41 to S43.

In step S41, referring to fig. 13 (a) to 14 (b), a mask 80 is formed on the second initial dielectric layer 220 and the pad layer 30; the mask 80 has a rib pattern.

Alternatively, as shown in fig. 13 (a) and 13 (b), a barrier material layer 700, a mask material layer 800, and a third patterned mask 90 are sequentially stacked on the second initial dielectric layer 220 and the pad layer 30. Also, with continued reference to fig. 13 (a), a fifth sacrificial material layer 810 may be formed between the mask material layer 800 and the third patterned reticle 90.

Here, the third patterned reticle 90 may be, for example, a patterned photoresist layer. The material of the barrier material layer 700 includes, for example, but is not limited to, silicon oxide (SiO ₂ ). The material of the mask material layer 800 includes, for example, but is not limited to, silicon nitride (Si ₃ N ₄ ). The material of the fifth sacrificial material layer 810 includes, for example, but is not limited to, an anti-reflective material.

It will be appreciated that in some examples, the bonding pad layer 30 suitable for the beading process is typically the portion of the bonding pad layer 30 located in the core circuit region. That is, the portion of the third patterned reticle 90 located within the cell array region may not have a pattern, for example, as shown in fig. 13 (b). Similarly, the portion of the mask material layer 800 located in the cell array region does not need to be subjected to a patterning process. In this manner, based on the pattern in the third patterned reticle 90, the mask 80 may be obtained after patterning the portion of the mask material layer 800 located within the core circuit region. The portion of the mask 80 located in the cell array region has no pattern, as shown in fig. 14 (a) and 14 (b). The portion of the mask 80 located in the core circuit region has a cut-out pattern. Here, after forming the mask 80, the third patterned reticle 90 may be removed.

In step S42, referring to fig. 15 (a) and 15 (b), a second patterning process is performed on the first initial dielectric layer 210 and the second initial dielectric layer 220 based on the rib cutting pattern of the mask 80, so as to form the first dielectric layer 21 and the second dielectric layer 22.

In the example where the barrier material layer 700 is formed, the barrier material layer 700 performs the aforementioned second patterning process in synchronization with the second initial dielectric layer 220, the first initial dielectric layer 210, and the barrier layer 70 is formed.

It will be appreciated that in some examples, the rib pattern of mask 80 is located in the core circuit region. Accordingly, the structure in which the first dielectric layer 21 and the second dielectric layer 22 are located in the cell array region may not be changed with respect to the structure in which the first initial dielectric layer 210 and the second initial dielectric layer 220 are located in the cell array region.

In step S43, referring to fig. 16 (a) and 16 (b), the mask 80 and the second dielectric layer 22 are removed to form a plurality of pads 31.

Optionally, the barrier layer 70 and the second dielectric layer 2 are both oxide layers, such as silicon oxide (SiO) ₂ ). In this manner, barrier layer 70 and second dielectric layer 22 may be removed simultaneously using the same process.

In some embodiments, the conductive pattern layer 11 includes a plurality of conductive portions arranged in parallel at intervals. Referring to fig. 17, a conductive portion in a cell array region is, for example, a conductive contact structure 111. The plurality of conductive contact structures 111 may be distributed in an array. After the patterned pad layer 30 forms the plurality of pads 31, the pads 31 located in the cell array region are, for example, contact pads 311. The contact pads 311 may be connected in one-to-one correspondence with the conductive contact structures 111.

Alternatively, with continued reference to fig. 17, the contact pad 311 is correspondingly connected to the conductive contact structure 111, and the orthographic projection of the contact pad 311 on the substrate 10 is located on the orthographic projection side of the conductive contact structure 111 on the substrate 10 and overlaps with the orthographic projection portion of the conductive contact structure 111 on the substrate 10. Thus, the contact pads 311 are arranged in a staggered manner, so that the space utilization rate is improved.

Next, taking a method for preparing a semiconductor structure in the core circuit region as an example, fig. 18 (a) to 32 (b) are taken as an example. It should be noted that the same steps as those in the method for manufacturing the structure of the cell array region in the semiconductor structure described above in some embodiments are not described in detail, and only differences are focused on the description.

In step S10, referring to fig. 18 (a) and 18 (b), a substrate 10 is provided, and a conductive pattern layer 11 is formed on the substrate 10.

In step S20, referring to fig. 19 (a) to 27 (b), a dielectric layer is formed on the conductive pattern layer 11, and the dielectric layer has a pattern for exposing a portion of the conductive pattern layer 11.

Illustratively, the dielectric layer includes a first dielectric layer and a second dielectric layer disposed in a stack. Accordingly, step S20 further includes steps S21 and S22.

In step S21, referring to fig. 19 (a) and 19 (b), a first dielectric material layer 2100 and a second dielectric material layer 2200 are sequentially stacked on the conductive pattern layer 11.

For example, as shown in fig. 19 (a) and 19 (b), after sequentially forming the first dielectric material layer 2100 and the second dielectric material layer 2200, the first hard mask material layer 400, the second hard mask material layer 410, and the first patterned reticle 50 may be sequentially stacked on the second dielectric material layer 2200.

Here, the first patterned reticle 50 may be a patterned photoresist layer. The first patterned reticle 50 may be located in a different pattern in the core circuitry region than in the cell array region. For example, as shown in fig. 19 (b), the first patterned reticle 50 has a linear pattern, which extends, for example, in a third direction, which is different from the aforementioned first direction.

And, optionally, with continued reference to fig. 19 (a), a first sacrificial material layer 420 is formed between the first hard mask material layer 400 and the second hard mask material layer 410, and a second sacrificial material layer 430 is formed between the second hard mask material layer 410 and the first patterned reticle 50.

In step S22, referring to fig. 20 (a) to 27 (b), a first patterning process is performed on the first dielectric material layer 2100 and the second dielectric material layer 2200 to form a first initial dielectric layer 210 and a second initial dielectric layer 220.

As shown in fig. 20 (a) and 20 (b), the second hard mask material layer 410 is patterned based on the first patterned reticle 50 to form the second hard mask layer 41.

Here, in an example in which the second sacrificial material layer 430 is formed, the second sacrificial material layer 430 may be patterned in synchronization with the second hard mask material layer 410 and removed after the second hard mask layer 41 is formed.

As shown in fig. 21 (a) and 21 (b), after forming the second hard mask layer 41, the manufacturing method further includes: a third hard mask initiation structure 440 is formed on the surface (including sidewalls and top surface) of second hard mask layer 41.

As shown in fig. 22 (a) and 22 (b), after forming the third hard mask initial structure 440, patterning the third hard mask initial structure 440 to form the third hard mask layer 44; and, removing the second hard mask layer 41.

Here, the pattern of the third hard mask layer 44 in the core circuit region may be different from that of the cell array region. The pattern of the third hard mask layer 44 in the core circuit region includes, for example, a plurality of linear patterns extending in a third direction.

On the basis, referring to fig. 23 (a) and 23 (b), after forming the third hard mask layer 44, a fourth hard mask material layer 450 filling the space between adjacent linear patterns in the third hard mask layer 44, and a fifth hard mask material layer 460 and a second patterned mask 60 stacked in sequence may be formed; wherein the fourth hard mask material layer 450 is flush or substantially flush with the upper surface of the third hard mask layer 44.

Here, the second patterned reticle 60 may be a patterned photoresist layer. Unlike the cell array region, the portion of the second patterned reticle 60 located in the core circuit region may have no pattern, for example, as shown in fig. 23 (b).

Optionally, with continued reference to fig. 23 (a), a third sacrificial material layer 470 is formed between the fifth hard mask material layer 460 and both the fourth hard mask material layer 450 and the third hard mask layer 44, and a fourth sacrificial material layer 480 is formed between the fifth hard mask material layer 460 and the second patterned reticle 60.

Referring to fig. 24 (a) and 24 (b), the fifth hard mask material layer 460 is patterned to form the fifth hard mask layer 46 based on the second patterned reticle 60.

Here, the patterning of the fifth hard mask material layer 460 is performed in the cell array region, and the portion of the fifth hard mask layer 46 located in the core circuit region may not have a pattern, as shown in fig. 24 (b).

Referring to fig. 25 (a) and 25 (b), after forming the fifth hard mask layer 46, the preparation method further includes: a sixth hard mask initiation structure 490 is formed over the surface of the fifth hard mask layer 46.

As shown in fig. 26 (a) and 26 (b), after forming the sixth hard mask initial structure 490, patterning the sixth hard mask initial structure 490 to form a sixth hard mask layer 49; and, removing the fifth hard mask layer 46.

Here, patterning of the sixth hard mask layer 49 is performed in the cell array region. After the fifth hard mask layer 46 is removed, the surface of the third sacrificial material layer 470 at the core circuit region is exposed, as shown in fig. 26 (b).

With continued reference to fig. 26 (a), it is to be appreciated that after the third sacrificial material layer 470 and the fourth hard mask material layer 450 are removed, the first mask material layer 400 may be patterned based on the pattern of the third hard mask layer 44 in the core circuit region to form a first hard mask layer (not shown) having a linear pattern in the core array region on the surface of the second dielectric material layer 2200. The third hard mask layer 44 and the first sacrificial material layer 420 may then be removed.

Referring to fig. 27 a and 27 b, based on the linear pattern (not shown) of the first hard mask layer in the core circuit region, the second dielectric material layer 2200 is patterned to form the second initial dielectric layer 220, and the first dielectric material layer 2100 is patterned to form the first initial dielectric layer 210. Thus, referring to fig. 27 (b), a linear pattern may be formed in the first initial dielectric layer 210 and the second initial dielectric layer 220.

In step S30, referring to fig. 28 (a) and 28 (b), a pad material is filled in the pattern of the dielectric layer to form a pad layer 30; the pad layer 30 is correspondingly connected to the conductive pattern layer 11.

Here, the dielectric layer may be represented as: the first and second initial dielectric layers 210 and 220 are stacked. The pattern of the dielectric layer may be represented as a linear pattern formed by the aforementioned preparation.

In some examples, the method of making further comprises: the resulting structure after filling the pad material is ground. Accordingly, in some examples, the method of making further comprises: and cleaning the structure obtained after grinding.

In step S40, referring to fig. 29 (a) to 29 (b), a rib cutting molding process is performed on the resulting structure after forming the pad layer 30, to form a plurality of pads 31; wherein the conductive pattern layer 11 includes a plurality of conductive parts; the pads 31 are connected to the conductive portions.

The following examples provide one possible implementation of the rib cutting molding process, but are not limited thereto. Step S40 includes, for example, steps S41 to S43.

In step S41, referring to fig. 29 (a) to 30 (b), a mask 80 is formed on the second initial dielectric layer 220 and the pad layer 30; the mask 80 has a rib pattern.

Alternatively, as shown in fig. 29 (a) and 29 (b), a barrier material layer 700, a mask material layer 800, and a third patterned mask 90 are sequentially stacked on the second initial dielectric layer 220 and the pad layer 30. Also, with continued reference to fig. 29 (a), a fifth sacrificial material layer 810 may be formed between the mask material layer 800 and the third patterned reticle 90.

Referring to fig. 30 (a) and 30 (b), based on the pattern in the third patterned reticle 90, after patterning a portion of the mask material layer 800 located within the core circuit region, a mask 80 may be obtained. The portion of the mask 80 located in the core circuit region has a cut-out pattern. Here, after forming the mask 80, the third patterned reticle 90 may be removed.

In step S42, referring to fig. 31 (a) and 31 (b), a second patterning process is performed on the first initial dielectric layer 210 and the second initial dielectric layer 220 based on the rib cutting pattern of the mask 80, so as to form the first dielectric layer 21 and the second dielectric layer 22.

In the example where the barrier material layer 700 is formed, the barrier material layer 700 performs the aforementioned second patterning process in synchronization with the second initial dielectric layer 220, the first initial dielectric layer 210, and the barrier layer 70 is formed.

In step S43, referring to fig. 32 (a) and 32 (b), the mask 80 and the second dielectric layer 22 are removed to form a plurality of pads 31.

Optionally, the barrier layer 70 and the second dielectric layer 2 are both oxide layers, such as silicon oxide (SiO) ₂ ). In this manner, barrier layer 70 and second dielectric layer 22 may be removed simultaneously using the same process.

In some embodiments, referring to fig. 32 (b), after the patterned pad layer 30 forms a plurality of pads 31, the pads 31 located in the core circuit area may be bonding pads.

Some embodiments of the present disclosure also provide a semiconductor structure obtained using the preparation methods described in some embodiments above. Referring to fig. 16 (a), 16 (b), 32 (a) and 32 (b), the semiconductor structure includes: a substrate 10, a conductive pattern layer 11 and a first dielectric layer 21 provided on the substrate 10; wherein the first dielectric layer 21 has a pattern for exposing a portion of the conductive pattern layer 11. The semiconductor structure further includes: the plurality of pads 31 are filled in the corresponding patterns of the first dielectric layer 21 and are correspondingly connected to the conductive portions in the conductive pattern layer 11.

The semiconductor structure in the embodiment of the disclosure is formed by adopting the preparation method, and the preparation method has technical advantages, and the semiconductor structure is also provided, which is not described herein.

In some embodiments of the present disclosure, the surface of the pad 31 facing away from the substrate 10 is higher than the surface of the first dielectric layer 21 facing away from the substrate 10, based on the substrate 10.

In some embodiments of the present disclosure, the bonding pad 31 located in the cell array region is a contact pad 311, and the conductive portion located in the cell array region is a conductive contact structure 111. The contact pad 311 is correspondingly connected to the conductive contact structure 111, and the orthographic projection of the contact pad 311 on the substrate 10 is located on the orthographic projection side of the conductive contact structure 111 on the substrate 10 and partially overlaps with the orthographic projection of the conductive contact structure 111 on the substrate 10.

Here, the conductive contact structure 111 may alternatively be a storage node contact structure.

In the embodiment of the disclosure, the orthographic projection of the contact pad 311 on the substrate 10 is located on one side of the orthographic projection of the conductive contact structure 111 on the substrate 10 and overlaps with the orthographic projection of the conductive contact structure 111 on the substrate 10, so that the contact pad 311 is conveniently arranged in a staggered manner, thereby improving the space utilization rate.

In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (15)

1. A method of fabricating a semiconductor structure, comprising:

providing a substrate, wherein a conductive pattern layer is formed on the substrate;

forming a dielectric layer on the conductive pattern layer, wherein the dielectric layer is provided with a pattern for exposing part of the conductive pattern layer;

filling a bonding pad material in the graph of the dielectric layer to form a bonding pad layer; the pad layer is correspondingly connected with the conductive pattern layer.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein before the forming of the pad layer, the method further comprises:

and grinding the structure obtained after filling the bonding pad material.

3. The method of manufacturing a semiconductor structure according to claim 2, wherein before the forming of the pad layer, the method further comprises: and cleaning the structure obtained after grinding.

4. The method of manufacturing a semiconductor structure according to claim 1, wherein after the forming of the pad layer, the method further comprises:

performing a rib cutting molding process on the obtained structure after the bonding pad layer is formed to form a plurality of bonding pads;

wherein the conductive pattern layer includes a plurality of conductive portions; the bonding pad is correspondingly connected with the conductive part.

5. The method of manufacturing a semiconductor structure according to claim 4, wherein the substrate includes a cell array region and a core circuit region located beside the cell array region; wherein,

the bonding pad in the cell array area is a contact pad, and the conductive part in the cell array area is a conductive contact structure;

the contact pad is correspondingly connected with the conductive contact structure, and the orthographic projection of the contact pad on the substrate is positioned on one side of the orthographic projection of the conductive contact structure on the substrate and is overlapped with the orthographic projection part of the conductive contact structure on the substrate.

6. The method of manufacturing a semiconductor structure as claimed in claim 4, wherein,

the forming a dielectric layer on the conductive pattern layer includes: and sequentially stacking a first dielectric material layer and a second dielectric material layer on the conductive pattern layer, and performing a first patterning process on the first dielectric material layer and the second dielectric material layer to form a first initial dielectric layer and a second initial dielectric layer.

7. The method of claim 6, wherein the first patterning process comprises a self-aligned dual imaging process or a self-aligned quad imaging process.

8. The method of claim 6, wherein the first dielectric material layer is formed to a thickness greater than a thickness of the second dielectric material layer.

9. The method of manufacturing a semiconductor structure according to claim 6, wherein the substrate includes a cell array region and a core circuit region located beside the cell array region;

the performing a first patterning process on the first dielectric material layer and the second dielectric material layer includes: a grid pattern is formed in a portion of the first dielectric material layer and the second dielectric material layer located within the cell array region, and a linear pattern is formed in a portion of the first dielectric material layer and the second dielectric material layer located within the core circuit region.

10. The method of manufacturing a semiconductor structure according to claim 6, wherein the performing a dicing process on the resulting structure after forming the pad layer comprises:

forming a mask on the second initial dielectric layer and the bonding pad layer; the mask is provided with a rib cutting pattern;

based on the rib cutting pattern, performing a second patterning process on the first initial dielectric layer and the second initial dielectric layer to form a first dielectric layer and a second dielectric layer;

And removing the mask and the second dielectric layer to form a plurality of bonding pads.

11. The method of claim 10, wherein forming a mask over the second initial dielectric layer and the pad layer comprises: forming a barrier material layer on the second initial dielectric layer and the bonding pad layer, and forming the mask on the barrier material layer;

the preparation method further comprises the following steps: based on the rib cutting pattern, synchronously executing the second patterning process on the barrier material layer, the first initial dielectric layer and the second initial dielectric layer to form a barrier layer, the first dielectric layer and the second dielectric layer; and removing the barrier layer.

12. The method of claim 11, wherein the barrier layer and the second dielectric layer are both oxide layers; and removing the blocking layer and the second dielectric layer synchronously.

13. A semiconductor structure, the semiconductor structure comprising:

a substrate;

a conductive pattern layer disposed on the substrate; the conductive pattern layer includes a plurality of conductive portions;

the first dielectric layer is arranged on the conductive pattern layer; the first dielectric layer is provided with a pattern, and part of the conductive pattern layer is exposed by the pattern;

A plurality of bonding pads filled in the graph of the first dielectric layer; the bonding pad is correspondingly connected with the conductive part.

14. The semiconductor structure of claim 13, wherein a surface of the pad facing away from the substrate is higher than a surface of the first dielectric layer facing away from the substrate, based on the substrate.

15. The semiconductor structure of claim 13, wherein the substrate includes a cell array region and a core circuit region located beside the cell array region; wherein,

the bonding pad in the cell array area is a contact pad, and the conductive part in the cell array area is a conductive contact structure;

the contact pad is correspondingly connected with the conductive contact structure, and the orthographic projection of the contact pad on the substrate is positioned on one side of the orthographic projection of the conductive contact structure on the substrate and is overlapped with the orthographic projection part of the conductive contact structure on the substrate.