CN117650101A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device is disclosed that includes forming a first fin structure and a second fin structure, wherein an isolation region is located between the first fin structure and the second fin structure, and wherein a gap is located between the first fin structure and the second fin structure and above the isolation region; depositing a barrier layer over the first fin structure, the isolation region, and the second fin structure, wherein an upper portion of the barrier layer is over the first fin structure and the second fin structure, and wherein a lower portion of the barrier layer fills a gap between the first fin structure and the second fin structure; removing the upper portion of the barrier layer; and when the lower part of the barrier layer is reserved above the isolation region, an etching process is performed to recess the first fin structure and the second fin structure.

Description

Method for manufacturing semiconductor device

Technical Field

The present disclosure relates to a method of manufacturing a semiconductor device.

Background

As the semiconductor industry moves into the nanotechnology node for higher device density, higher performance, and lower cost, challenges from fabrication and design have led to the development of three-dimensional designs, such as multi-gate field effect transistors (field effect transistor, FETs), including Fin field effect transistors (Fin field effect transistor, fin FETs) and Gate All Around (GAA) field effect transistors. In a Fin field effect transistor (Fin FET), the gate electrode abuts three side surfaces of the channel region with a gate dielectric layer interposed therebetween. Because the gate structure encloses (surrounds) three surfaces of the fin structure, the transistor basically has three gates to control the current through the fin or channel region. Unfortunately, the fourth side, the bottom portion of the channel, is far from the gate electrode, so the gate cannot control it tightly. In contrast, in a wrap-around gate field effect transistor, all surfaces of the channel region are surrounded by the gate electrode, which allows the empty region (depletion region) in the channel region to be more complete and results in less short channel effects due to steeper sub-threshold current swings (sub-threshold current swing, SS) and less drain induced barrier lowering (drain induced barrier lowering, DIBL). As transistor sizes continue to shrink to technology nodes smaller than 10 to 15 nanometers (nm), further improvements in surrounding gate field effect transistors are indispensable.

Disclosure of Invention

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including: forming a first structure and a second structure, wherein the first structure and the second structure respectively comprise a plurality of alternately stacked first and second semiconductor layers over the semiconductor substrate, wherein a first sidewall of the first structure faces a second sidewall of the second structure and is separated from the second structure by a gap; forming an isolation material in the gap; forming a spacer layer over the first structure, the spacer material, and the second structure, wherein the spacer layer comprises: a first upper portion above the first structure, a second upper portion above the second structure, a first sidewall portion laterally adjacent the first sidewall, a second sidewall portion laterally adjacent the second sidewall, and a lower portion above the spacer material and extending from the first sidewall portion to the second sidewall portion; depositing a barrier layer over the spacer layer, wherein an upper portion of the barrier layer is above the first structure and the second structure, and wherein a structural gap of the barrier layer is between the first structure and the second structure; removing the upper portion of the barrier layer to expose the first upper portion and the second upper portion of the spacer layer; and performing an etching process to remove some of the alternately stacked first and second semiconductor layers over the semiconductor substrate while the spacer layer remains over the isolation material.

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including: forming a structure between the first trench and the second trench, wherein the structure has a first sidewall and a second sidewall; forming an isolation material in the first trench and the second trench; forming a spacer layer over the structure and the spacer material, wherein the spacer layer comprises: the upper portion being above the structure, the first sidewall portion being laterally adjacent to the first sidewall, the second sidewall portion being laterally adjacent to the second sidewall, the first trench portion being above the isolation material in the first trench, and the second trench portion being above the isolation material in the second trench; depositing a barrier layer over the spacer layer, wherein an upper portion of the barrier layer is above the structure, and wherein a lower portion of the barrier layer is laterally adjacent to the structure; removing the upper portion of the barrier layer to expose the upper portion of the spacer layer; removing the upper part of the spacer layer to expose the structure; and an etching process is performed to recess the structure with the spacer layer remaining over the isolation material.

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including: forming a first fin structure and a second fin structure, wherein an isolation region is located between the first fin structure and the second fin structure, and wherein a gap is located between the first fin structure and the second fin structure and above the isolation region; depositing a barrier layer over the first fin structure, the isolation region, and the second fin structure, wherein an upper portion of the barrier layer is over the first fin structure and the second fin structure, and wherein a lower portion of the barrier layer fills a space between the first fin structure and the second fin structure; removing the upper portion of the barrier layer; and when the lower part of the barrier layer is reserved above the isolation region, an etching process is performed to recess the first fin structure and the second fin structure.

Drawings

The aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features are not drawn to scale in accordance with standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a method flow diagram according to some embodiments;

fig. 2, 3, and 4 are perspective views of successive stages in the manufacture of a semiconductor device in accordance with some embodiments;

fig. 5, 6, 7, 8, 9, and 10 disclose cross-sectional views of the semiconductor device of fig. 2-4 along a "Y-axis tangent" or parallel to the Y-axis in accordance with some embodiments at a stage of fabrication.

[ symbolic description ]

100: method of

200: manufacturing structure

201: semiconductor substrate

202: interface(s)

210: first semiconductor layer

211: first semiconductor bottom layer

220: second semiconductor layer

221: second semiconductor top layer

250: mask layer

300: fin structure

301: first fin structure

302: second fin structure

310: first side wall

320: a second side wall

360: top surface

380: lower part

390: upper part

400: isolation material

401: uppermost surface

500: spacer mat

510: first side wall part

519: uppermost surface of groove

520: a second side wall part

530: upper part

540: lower part

548: top surface

549: bottom-most surface

600: barrier layer

601: bottom edge

602: the topmost edge

660: upper part

680: structural space

681: groove surface

699: barrier layer

700: source/drain regions

800: gap of

900: groove(s)

901: first groove

902: second groove

5-5: cross section of

A: internal angle

X: x-axis

Y: y-axis

Z: z-axis

S101-191: step (a)

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various examples and/or configurations discussed.

For brevity, conventional techniques related to conventional semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein.

In addition, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. When spatially relative terms such as those listed above are used to describe a first element relative to a second element, the first element may be directly on another element or intervening elements or layers may be present. When an element or layer is referred to as being "on" another element or layer, it is directly on and in contact with the other element or layer.

As used herein, a "layer of material" or a layer that is a "material" includes at least 50 weight percent of an identification material, such as at least 60 weight percent of an identification material, such as at least 75 weight percent of an identification material or at least 90 weight percent of an identification material. For example, each germanium layer and one-layer sheet contains at least 50 weight percent, at least 60 weight percent, at least 75 weight percent, or at least 90 weight percent germanium.

Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various examples and/or configurations discussed.

The present disclosure relates generally to semiconductor devices and methods of forming the same. Various embodiments are discussed herein in the specific context, in the context of GAA FETs or devices. It should be noted, however, that the present disclosure is not limited to processes for manufacturing GAA devices.

GAA devices include any device having a gate structure or portion thereof formed on four sides of a channel region (e.g., a channel region surrounding a portion). The channel region of the GAA device includes a plurality of nanowire channels, stripe-shaped channels, and/or other suitable channel configurations. In a particular embodiment, the GAA device forms first and second semiconductor layers over a semiconductor substrate in alternating stacks, selectively removing one type of semiconductor layer to create voids around the other type of semiconductor layer, and filling the voids with gate material.

In some embodiments, the channel region of the GAA device may have a plurality of horizontal nanowires or a plurality of vertically spaced horizontal stripes, making the GAA device a stacked horizontal GAA (S-HGAA) device. GAA devices presented herein may include p-type metal oxide semiconductor GAA devices or n-type metal oxide semiconductor GAA devices. Further, GAA devices may have one or more channel regions (e.g., nanowires) associated with a single, continuous gate structure, or multiple gate structures. Other examples of semiconductor devices will be apparent to those of ordinary skill in the art from this disclosure.

In the process, a fin structure may be formed over the substrate and the isolation region may be formed adjacent to the fin structure. Further, dummy gate structures may be formed over the fin structures, defining gate regions and source/drain regions. In the source/drain regions of the fin structure, strained source/drain may be formed by etching the fin structure to form a cavity, followed by epitaxially growing a source/drain material in the cavity. In this etching process, the isolation regions between fin structures may be damaged by etching or other reasons. For example, the semiconductor substrate material under the isolation region may be exposed. The semiconductor material exposed during source/drain formation may cause epitaxial material to grow from one fin structure to an adjacent fin structure, even merging epitaxial material between adjacent fin structures. In PMOS (positive channel metal oxide semiconductor, PMOS) structures, the fusion of epitaxial material between adjacent fin structures may be of particular concern.

Embodiments herein protect the isolation regions from being etched or otherwise damaged during the etching process that forms the source/drain cavities. The results show that epitaxial material fusion between adjacent fin structures is not caused when source/drain material is epitaxially grown in the source/drain cavities. In particular embodiments, the process for forming strained source/drain regions may allow for zero loss of isolation material adjacent to the source/drain regions. The results show that the process yield can be improved as described herein.

For convenience of subsequent discussion, fig. 1 provides a flowchart of a method 100 of fabricating a semiconductor device according to various embodiments. The method 100 is illustrative of GAA devices formed using an alternative gate process. However, it should be understood that the method 100 may be equally applied to other types of structures or processes without departing from the scope of the present disclosure. It should be appreciated that the method 100 includes steps having Complementary Metal Oxide Semiconductor (CMOS) process features and is therefore only briefly described herein. Furthermore, additional steps may be performed before, after, and/or during method 100.

Referring to fig. 2 for initial steps of method 100, fig. 2 illustrates a stage in the fabrication of a structure 200 (semiconductor device). Referring to fig. 1 and 2 in synchronization, step S101 in the method 100 includes forming a plurality of alternately stacked semiconductor layers over a semiconductor substrate 201. These alternately stacked semiconductor layers include a plurality of first semiconductor layers 210 and a plurality of second semiconductor layers 220.

In some embodiments, the semiconductor substrate 201 includes a single crystal semiconductor layer on at least one surface portion. The semiconductor substrate 201 includes a single crystal semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), germanium silicide (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (inaias), gallium indium arsenide (InGaAs), gaSbP (gallium antimonide), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In a particular embodiment, the semiconductor substrate 201 is made of crystalline silicon (Si).

The semiconductor substrate 201 may include one or more buffer layers (not shown) at a surface region thereof. The buffer layer may be used to gradually change the lattice constant of the substrate to that of the source/drain regions 700. The buffer layer may be formed of an epitaxially grown single crystal semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), germanium tin alloy (GeSn), germanium silicide (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (inaias), gallium arsenide (InGaAs), gallium antimonide (GaSbP), gallium antimonide (GaAsSb), gallium nitride (GaN), gallium phosphide (GaP), and indium phosphide (InP). In one embodiment, the semiconductor substrate 201 includes a germanium silicide (SiGe) buffer layer epitaxially grown on the silicon semiconductor substrate 201. The germanium concentration of the germanosilicide buffer layer may be increased from the bottom 30 atomic percent of the buffer layer to 70 atomic percent of the top of the buffer layer.

In some embodiments, impurity ions (dopants) are implanted into the silicon semiconductor substrate 201 to form a well region. Ion implantation is performed to prevent tunneling. The semiconductor substrate 201 may include various regions (e.g., p-type or n-type conductivity) that have been appropriately doped with impurities. For example, for an n-type Fin FET, the dopant is boron (BF ₂ ) For a p-type Fin FET, the dopant is phosphorus.

In certain embodiments, the first semiconductor layer 210 and the second semiconductor layer 220 are made of materials having different lattice constants, and may include one or more layers of Si (silicon), ge (germanium), siGe (germanium silicide), gaAs (gallium arsenide), inSb (indium antimonide), gaP (gallium phosphide), gaSb (gallium antimonide), inaias (aluminum indium arsenide), inGaAs (gallium arsenide indium), gaSbP (gallium antimonide), gaAsSb (gallium arsenide antimonide), and InP (indium phosphide).

In some embodiments, the first semiconductor layer 210 and the second semiconductor layer 220 are made of silicon (Si), a silicon (Si) compound, germanium silicide (SiGe), germanium (Ge), or a germanium (Ge) compound.

In fig. 2, four first semiconductor layers 210 and four second semiconductor layers 220 are provided. However, the number of layers is not limited to four, and may be as small as one layer (the first semiconductor layer 210 and the second semiconductor layer 220), and in some embodiments, two to ten layers of each of the first semiconductor layer 210 and the second semiconductor layer 220 are formed. By adjusting the number of stacked layers, the drive current of the GAA FET device can be adjusted.

In a particular embodiment, the first semiconductor layer 210 and the second semiconductor layer 220 are epitaxially formed over the semiconductor substrate 201. The thickness of the first semiconductor layer 210 may be equal to or greater than the thickness of the second semiconductor layer 220. For example, the thickness of the first semiconductor layer 210 may be 2 to 20 nanometers (nm) in some embodiments, and may be 5 to 15 nanometers in some embodiments. The thickness of the second semiconductor layer 220 may be 2 to 20 nanometers in some embodiments, and may be 5 to 15 nanometers in some embodiments. The thicknesses of the first semiconductor layer 210 and the second semiconductor layer 220 may be the same or different.

In some embodiments, the first semiconductor bottom layer 211 (the layer closest to the semiconductor substrate 201) is thicker than the remaining first semiconductor layers 210. In some embodiments, the thickness of the first semiconductor bottom layer 211 may be 10 to 50 nanometers, or in some embodiments 20 to 40 nanometers.

As shown in fig. 2, an interface 202 is defined between the first semiconductor base layer 211 and the semiconductor substrate 201.

Referring to fig. 1-3, step S103 of the method 100 includes forming a fin structure 300 from a portion of the stacked semiconductor layers and semiconductor substrate 201. Specifically, a plurality of trenches 900 are etched through the stacked semiconductor layers and into the semiconductor substrate 201.

As shown in fig. 3, a mask layer 250 (mask) is formed on the first semiconductor layer 210 (stacked layer) and the second semiconductor layer 220 (stacked layer). In some embodiments, the mask layer 250 includes a first mask layer and a second mask layer. The first mask layer may be a pad oxide layer made of silicon oxide, which may be formed by thermal oxidation. The second mask layer may be made of nitrogen Silicide (SiN), which may be formed by chemical vapor deposition (chemical vapor deposition, CVD), including low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced CVD (PECVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (atomic layer deposition, ALD), or other suitable processes.

As shown in fig. 4, the mask layer 250 may be patterned into a mask pattern by a patterning operation including photolithography and etching. As further shown in fig. 4, step S103 includes patterning the stacked layers of the first semiconductor layer 210 and the second semiconductor layer 220 with the patterned mask layer 250, whereby the stacked layers form fin structures 300 extending along the X-axis direction. In fig. 4, two fin structures 300 are spaced apart from each other in the Y-axis direction. The number of fin structures is not limited to two, but may be as small as one, three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure 300 to improve pattern fidelity in patterning operations.

As shown in fig. 4, the fin structure 300 has an upper portion 390 composed of the stacked first semiconductor layer 210 (stacked semiconductor layer) and the second semiconductor layer 220 (stacked semiconductor layer). In addition, the fin structure 300 has a lower portion 380 or well region formed by the semiconductor substrate 201. Accordingly, the exemplary fin structure 300 includes alternating stacks of first and second semiconductor layers 210, 220 and an upper portion 390 of the semiconductor substrate 201.

In some embodiments, the thickness or width (in the Y-axis direction) of the upper portion 390 of the fin structure 300 may be 10 to 40 nanometers, and in some embodiments may be 20 to 30 nanometers. In some embodiments, the height (in the Z-axis direction, i.e., perpendicular to the semiconductor substrate 201) of the upper portion 390 of each fin structure 300 may be from 100 to 200 nanometers.

The stacked fin structure 300 may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes that combine photolithography and self-alignment processes can create, for example, patterns with smaller pitches than processes that use single, direct photolithography. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the stacked fin structure 300.

Referring to fig. 1 and 4 in synchronization, the method 100 may be followed by step S105, wherein an isolation material 400 comprising one or more layers of insulating material may be formed over the semiconductor substrate 201 and in the plurality of trenches 900 such that the fin structure 300 is fully embedded in the isolation material 400. The insulating material of the insulating layer may include silicon oxide (si oxide), silicon nitride (si nitride), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), fluorine doped silicon oxide (FSG), or a low dielectric constant material formed by Low Pressure Chemical Vapor Deposition (LPCVD), plasma CVD, or flowable CVD. An annealing operation may be performed after the insulating layer is formed.

Next, a planarization operation, such as a chemical-mechanical planarization (CMP) method and/or an etch-back method, is performed such that an upper surface of the top second semiconductor layer 221 is exposed from the insulating material layer. In some embodiments, a fin liner layer may be formed over the fin structure 300 prior to forming the isolation material 400. Such fin liner layer may be made of silicon nitride (SiN) or a silicon nitride based material (e.g., siON, siCN, or SiOCN).

Next, as shown in fig. 4, the layer of insulating material is recessed to define an isolation material 400 in the trench 900 such that an upper portion 390 of the fin structure 300 is exposed. Through this operation, the fin structures 300 are electrically isolated from each other by the isolation material 400, which is also referred to as shallow trench isolation (shallow trench isolation, STI).

In the embodiment shown in fig. 4. The insulating material layer may be recessed such that the first semiconductor bottom layer 211 is not covered by the isolation material 400. In the gate region, the first semiconductor layer 210 is a sacrificial layer, which is then partially removed, and the second semiconductor layer 220 is then formed into a plurality of semiconductor lines as channel layers of the GAA FET.

Fig. 5 is a "Y-cut" side cross-sectional view of the partially fabricated structure 200 of fig. 4, taken along line 5-5 in fig. 4, as shown in fig. 5, four fin structures 300, each fin structure 300 having three first semiconductor layers 210 and three second semiconductor layers 220. As described above, there may be as few as one fin structure 300 or multiple fin structures 300, with a minority of one or more first semiconductor layers 210 (semiconductor layers) and second semiconductor layers 220 (semiconductor layers) of the first semiconductor layers 210 (semiconductor layers) and second semiconductor layers 220 (semiconductor layers).

As shown in fig. 5, the plurality of fin structures 300 includes a first fin structure 301 (first structure) and a second fin structure 302 (second structure), and the plurality of trenches 900 includes a first trench 901 (trench) and a second trench 902 (trench). In addition, each fin structure 300 has a first sidewall 310 (sidewall) and a second sidewall 320 (sidewall). A trench 900 is defined between adjacent fin structures 300. For example, the first trench 901 is located between the first sidewall 310 of the first fin structure 301 and the second sidewall 320 of the second fin structure 302. In other words, the second sidewall 320 of the first fin structure 301 faces the first sidewall 310 of the second fin structure 302 and is separated from the first sidewall 310 by the first trench 901. Furthermore, a space or gap 800 is defined between adjacent fin structures 300 over the isolation material 400.

As shown in fig. 5, after the isolation material 400 is formed in the trench 900, the uppermost surface 401 of the isolation material 400 is lower than each interface 202 between the first semiconductor base layer 211 and the semiconductor substrate 201.

After forming the isolation material 400 in the plurality of trenches 900, the method 100 may continue with the gate process following step S111. For example, the gate process S111 may include forming a sacrificial (dummy) gate structure over the exposed fin structure 300. A sacrificial gate structure may be formed over a portion of the fin structure 300 that will become the channel region. The sacrificial gate structure defines the channel region of the GAA FET. In an exemplary embodiment, the sacrificial gate structures extend in an X-axis direction perpendicular to the fin structure 300 and are spaced apart from each other in a Y-axis direction.

The sacrificial gate structure may include a sacrificial gate dielectric layer and a sacrificial gate electrode layer. The sacrificial gate dielectric layer may comprise one or more layers of insulating material, such as a silicon oxide based material. In one embodiment, the silicon oxide may be formed by CVD.

The sacrificial gate structure may be formed over the fin structure 300 by a first blanket deposition of a sacrificial gate dielectric layer. A sacrificial gate electrode layer is then blanket deposited over the sacrificial gate dielectric layer and the fin structure 300 such that the fin structure 300 is fully embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer comprises silicon, such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer is between about 100 nanometers and about 200 nanometers. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using a variety of deposition methods, including Chemical Vapor Deposition (CVD), including Low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or other suitable deposition processes. Subsequently, a mask layer 250 is formed over the sacrificial gate electrode layer. The mask layer 250 includes a liner silicon nitride layer and a silicon oxide mask layer.

Further, the gate process S111 may include patterning the mask layer 250, and then the sacrificial gate electrode layer is patterned into a sacrificial gate structure. The sacrificial gate structure includes a sacrificial gate dielectric layer, a sacrificial gate electrode layer (e.g., polysilicon), a liner silicon nitride layer, and a silicon oxide mask layer. The stacked layer portions of the first semiconductor layer 210 and the second semiconductor layer 220 are exposed to opposite sides of the sacrificial gate structure by patterning the sacrificial gate structure, thereby defining source/drain (S/D) regions. In the present disclosure, the source and drain are used interchangeably, so that the structure of the two is substantially the same.

Referring to fig. 1 and 6 in synchronization, the gate process of step S111 may further include step S121 of forming a spacer 500 over the partially fabricated structure 200 of fig. 5. Specifically, the spacer layer 500 is conformally deposited over the fin structure 300 and the isolation material 400. Spacer 500 may be more conformally deposited over the sacrificial gate structure.

Referring to fig. 5 and 6 in synchronization, spacer layer 500 includes first sidewall portions 510 (sidewall portions), each first sidewall portion 510 being laterally adjacent (i.e., in the Y-axis direction) to a corresponding first sidewall 310; second sidewall portions 520, each sidewall portion laterally adjacent (i.e., in the Y-axis direction) to a respective second sidewall 320; upper portions 530, each upper portion 530 directly above a respective fin structure 300; and lower portions 540, each lower portion 540 directly overlying a respective spacer material 400. The example lower portion 540 extends from the respective first sidewall portion 510 to the respective second sidewall portion 520.

As shown in fig. 6, the spacer layer 500 is continuous from the lower portion 540 to the first sidewall portion 510, to the upper portion 530 (i.e., the upper portion of the first structure 301), to the second sidewall portion 520, to the lower portion 540, etc., i.e., the partially fabricated structure 200 in fig. 5 is completely covered by the spacer layer 500. In an exemplary embodiment, after forming the spacer 500 over the fin structures 300 and the isolation material 400, the spacer 500 is in contact with the semiconductor substrate 201 in each fin structure 300. Specifically, spacer layer 500 contacts semiconductor substrate 201 between uppermost surface 401 of isolation material 400 and interface 202.

In an exemplary embodiment, the spacer 500 is made of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon dioxide (SiO ₂ ) Or silicon carbide (SiC). In an exemplary embodiment, the spacer layer 500 has a thickness of 1 to 20 nanometers, for example, 1 to 15 nanometers.

Referring to fig. 1 and 6 in synchronization, the gate process of step S111 may further include step S131 of forming a bottom cap or barrier layer 600 over the gate and source/drain regions 700 (shown in fig. 10). In the source/drain regions 700 (shown in fig. 10), a barrier layer 600 is formed overlying the spacer layer 500 of the partially fabricated structure 200. For example, a bottom barrier layer 600 (protective layer) may be deposited over the spacer layer 500, and the spacer layer 500 covers the fin structure 300 in the source/drain regions 700 (shown in fig. 10), as shown in fig. 6, and over the sacrificial gate structure (not shown in fig. 6), for example by a blanket deposition process.

As shown in fig. 6, the barrier 600 includes lower portions or structure spacers 680 that are laterally adjacent (in the Y-axis direction) and between respective adjacent fin structures 300. In an exemplary embodiment, the structure spacers 680 of the barrier layer 600 fill in the spaces 800 (gaps) between adjacent fin structures 300. The inter-structure portion 680 extends to the bottommost edge 601 closest to the semiconductor substrate 201.

Furthermore, the barrier layer 600 comprises an upper portion 660 located above the fin structure 300. More specifically, the height (Z-axis direction) of the upper portion 660 of the barrier layer 600 above the semiconductor substrate 201 is greater than the height (Z-axis direction) of the fin structure 300 above the semiconductor substrate 201. An upper portion 660 of the barrier layer 600 may be planarized to the topmost edge 602.

The exemplary barrier layer 600 has a thickness or height (in the Z-axis direction) from the bottom-most edge 601 to the top-most edge 602 of 2000 to 3000 angstroms (a), for example about 2400A.

In addition, the gate process of step S111 may further include step S141 of forming a second capping layer or barrier layer 699 over the first capping layer 600 (barrier layer) in the gate region and the source/drain region 700 (shown in fig. 10), as shown in fig. 6. The barrier layer 699 may be planarized after deposition. Exemplary barrier layer 699 has a thickness or height (in the Z-axis direction) of from 200 to 600 angstroms (a), for example about 400A.

Referring to fig. 1 and 7 in synchronization, the gate process of step S111 may further include step S142 of removing the barrier layer 699 from the gate region and the source/drain regions 700 (as shown in fig. 10).

In addition, the gate process of step S111 may further include step S132, removing a portion of the barrier layer 600. For example, the barrier layer 600 is removed from the gate region and a portion of the barrier layer 600 is removed from the source/drain region 700 (as shown in fig. 10). In a particular embodiment, removing portions of the barrier layer 600 from the source/drain regions 700 (as shown in fig. 10) includes removing an upper portion 660 of the barrier layer 600 to expose an upper portion 530 of the spacer layer 500 (above the respective fin structure 300). In a particular embodiment, an etching process may be performed to remove all of the upper portion 660 of the barrier layer 600 and a portion of the structural spacers 680 of the barrier layer 600. Thus, each structure-to-structure portion 680 of the barrier 600 is formed with a recessed surface 681 located in a corresponding trench 900 between fin structures 300.

In an exemplary embodiment, the structural spacers 680 of the barrier layer 600 have a thickness from the bottommost edge 601 to the groove surface 681 of at least 5 nanometers, at least 10 nanometers, at least 15 nanometers, at least 20 nanometers, at least 25 nanometers, at least 30 nanometers, at least 40 nanometers, at least 50 nanometers, at least 60 nanometers, at least 70 nanometers, at least 80 nanometers, at least 90 nanometers, or at least 100 nanometers; and a height (in the Z-axis direction) of at most 250 nanometers, at most 240 nanometers, at most 230 nanometers, at most 220 nanometers, at most 210 nanometers, at most 200 nanometers, or at most 150 nanometers. In an exemplary embodiment, the height (in the Z-axis direction) of the structural gap 680 of the barrier layer 600 from the bottommost edge 601 to the groove surface 681 is 10 to 200 nanometers.

In an exemplary embodiment, step S132 includes etching the barrier layer 600 using a dry etching process. For example, the dry etching process may utilize nitrogen/oxygen (N ₂ /O ₂ ) The gas controls the amount of barrier layer 600 that is etched. In an exemplary embodiment, the dry etch process is performed at a pressure of 3 millitorr (mTorr) to 20 millitorr using a nitrogen/oxygen gas, a bias power of 50 volts (V) to 300V, and a process time of 10 seconds to 300 seconds.

Referring to fig. 1 and 8 in synchronization, the method 100 continues with step S151 in which an upper portion 530 of the spacer layer 500 covering the fin structure 300 (above the corresponding fin structure 300) is removed. Thus, the top surface 360 of the fin structure 300 is uncovered and exposed. In an exemplary embodiment, step S151 includes performing a selective etching process to etch spacer 500 material. Further, in an exemplary embodiment, the etching process is an anisotropic etching process.

While etching to remove the upper portion 530 of the spacer 500 (above the corresponding fin structure 300), the structure spacers 680 of the barrier layer 600 remain above the lower portion 540 of the spacer 500, and the structure spacers 680 remain above the underlying isolation material 400 (isolation region). Accordingly, the etching performed during step S151 does not etch or damage the spacer 500 or the lower portion 540 of the isolation material 400.

At the stage of fabrication of fig. 8, i.e., before performing an etching process to remove the alternately stacked first semiconductor layers 210 and second semiconductor layers 220 from above the semiconductor substrate 201, there is at least 15 nanometers, at least 20 nanometers, at least 25 nanometers, at least 30 nanometers, or at least 35 nanometers from the bottom surface of the first semiconductor bottom layer 211 to the upper surface of the second semiconductor top layer 221 in the alternately stacked first and second semiconductor layers; up to 100 nanometers, up to 90 nanometers, up to 80 nanometers, up to 70 nanometers, up to 60 nanometers; for example 30 to 70 nm (in the Z-axis direction).

Referring to fig. 1 and 9 in synchronization, the method 100 further includes step S161 of recessing the fin structure 300. For example, step S161 may include removing an upper portion 390 of the fin structure 300. Specifically, step S161 may include performing an etching process to remove the alternately stacked first semiconductor layers 210 and second semiconductor layers 220 from above the semiconductor substrate 201. In an exemplary embodiment, step S161 is performed when the spacer layer 500 is held over the spacer material 400. Specifically, step S161 is performed before, during, and after performing an etching process to recess the fin structure 300, while the isolation material 400 is encapsulated between the semiconductor substrate 201 and the spacer layer 500. In an exemplary embodiment, performing an etching process to recess the fin structure 300 includes removing a structure spacer 680 of the barrier layer 600, as shown in fig. 9.

In an exemplary embodiment, the heights of the first and second sidewall parts 510 and 520 may be reduced while an etching process is performed to remove the alternately stacked first and second semiconductor layers 210 and 220 from above the semiconductor substrate 201.

In an exemplary embodiment, after an etching process is performed to remove the alternately stacked first and second semiconductor layers 210 and 220 from above the semiconductor substrate 201, the first and second sidewall portions 510 and 520 of the spacer layer 500 may be recessed and terminate at the groove uppermost surface 519. The maximum vertical height (i.e., in the Z-axis direction) of the groove first side wall portion 510 and the second side wall portion 520 is defined from the groove uppermost surface 519 to the lowermost surface 549 of the lower portion 540 of the spacer layer 500. In exemplary embodiments, the maximum vertical height is at least 10 nanometers, at least 15 nanometers, at least 20 nanometers, or at least 25 nanometers; at most 40 nanometers, at most 35 nanometers, at most 30 nanometers, or at most 25 nanometers; for example from 10 nm to 30 nm.

In an exemplary embodiment, after the etching process is performed to remove the alternately stacked first semiconductor layers 210 and second semiconductor layers 220 from above the semiconductor substrate 201, as shown in fig. 9, a thickness or height (in the Z-axis direction) from the lowermost surface 549 to the top surface 548 opposite to the lowermost surface 549 is 1 to 15 nm at a central region of each remaining lower portion 540 of the spacer layer 500.

Meanwhile, in the exemplary embodiment, after the etching process is performed to remove the alternately stacked first semiconductor layers 210 and second semiconductor layers 220 from above the semiconductor substrate 201, as shown in fig. 9, an internal angle a is formed between an inner surface of each lower portion 540 and a corresponding inner surface of a remaining portion of the adjacent first sidewall portion 510 or second sidewall portion 520. In an exemplary embodiment, the internal angle a is 80 to 90 degrees.

Referring to fig. 1 and 10 in conjunction, a step S171 of the method 100 may be continued, the step S171 comprising selectively epitaxially growing material on the fin structure 300 over the semiconductor substrate 201 to form the source/drain regions 700. In an exemplary embodiment, the source/drain regions 700 are strained source/drain regions 700. During the growth of the epitaxial material, the spacer 500 and the isolation material 400 cover the remaining first sidewall 310 and second sidewall 320 to prevent epitaxial growth thereon. In addition, the first sidewall portion 510 and the second sidewall portion 520 of the spacer 500 may prevent epitaxial material from growing into the trench 900.

The epitaxial material may include silicon (Si), silicon phosphide (SiP), silicon carbide (SiC), and silicon phosphide (SiCP) for one or more layers of an n-channel FET or silicon (Si), germanium silicide (SiGe), germanium (Ge) for a p-channel FET. For P-channel FETs, boron (B) may also be included in the source/drain. The source/drain epitaxial layers may be formed by epitaxial growth methods such as CVD, ALD, or Molecular Beam Epitaxy (MBE).

As shown in fig. 1, further Complementary Metal Oxide Semiconductor (CMOS) processes may continue at step S191 in the method 100 to complete the fabrication of the fabricated structure 200. Such processes may include removal of sacrificial gate structures, metal gate formation, contact/via formation, interconnect metal layers, dielectric layers, passivation layers, and the like.

Some methods of fabricating semiconductor devices are provided according to certain embodiments.

Methods of fabricating semiconductor devices in some cases include forming a first structure and a second structure, wherein the first structure and the second structure each comprise a plurality of alternately stacked first and second semiconductor layers over a semiconductor substrate, wherein a first sidewall of the first structure faces a second sidewall of the second structure and is separated from the second structure by a gap; forming an isolation material in the gap; forming a spacer layer over the first structure, the spacer material, and the second structure, wherein the spacer layer comprises: a first upper portion above the first structure, a second upper portion above the second structure, a first sidewall portion laterally adjacent the first sidewall, a second sidewall portion laterally adjacent the second sidewall, and a lower portion above the spacer material and extending from the first sidewall portion to the second sidewall portion; depositing a barrier layer over the spacer layer, wherein an upper portion of the barrier layer is above the first structure and the second structure, and wherein a structural gap of the barrier layer is between the first structure and the second structure; removing the upper portion of the barrier layer to expose the first upper portion and the second upper portion of the spacer layer; and performing an etching process to remove the alternately stacked first and second semiconductor layers over the semiconductor substrate while the spacer layer remains over the isolation material.

In a specific implementation, the etching process is performed to remove the alternately stacked first and second semiconductor layers above the semiconductor substrate, thereby lowering the heights of the first and second sidewall portions of the spacer.

In a particular implementation, after performing an etching process to remove some of the alternately stacked first and second semiconductor layers over the semiconductor substrate, the first and second sidewall portions of the spacer layer terminate at a plurality of upper surfaces at a distance of 10 to 30 nanometers from the lower portion.

In a specific implementation, the lower portion of the spacer layer has a thickness of from 1 to 15 nanometers in a direction perpendicular to the semiconductor substrate.

In a particular implementation, the etching process is performed to remove some of the alternately stacked first and second semiconductor layers above the semiconductor substrate, the some of the alternately stacked first and second semiconductor layers having a stack height from 30 to 70 nanometers in a direction perpendicular to the semiconductor substrate.

In a specific implementation method, the first sidewall portion and the second sidewall portion of the spacer form an internal angle of 80 to 90 degrees with the lower portion of the spacer, respectively.

In certain embodiments, the spacer layer is silicon nitride, silicon oxycarbonitride, silicon oxycarbide, silicon dioxide, or silicon carbide.

In a particular embodiment, a selective epitaxial growth material is also included over the first structure of the semiconductor substrate and over the second structure of the semiconductor substrate to form source/drain regions, wherein a spacer layer and an isolation material are over the first sidewall and the second sidewall to prevent epitaxial growth on the first sidewall and the second sidewall. In some embodiments, the method further comprises removing the spacer layer after the selective epitaxial growth of material to form source/drain regions.

In a specific implementation method, after forming the first structure and the second structure, the first structure and the second structure respectively include an interface between the lowest second semiconductor layer and the semiconductor substrate; and after forming the spacer material in the gap, the spacer material has an uppermost surface, the uppermost surface being lower than each interface. In some embodiments, after forming the spacer layer over the first structure, the isolation material, and the second structure, the spacer layer is in contact with the first structure and the second structure of the semiconductor substrate.

In further embodiments, a method of fabricating a semiconductor device includes forming a structure between a first trench and a second trench, wherein the structure has a first sidewall and a second sidewall; forming an isolation material in the first trench and the second trench; forming a spacer layer over the structure and the isolation material, wherein the spacer layer comprises an upper portion over the structure, a first sidewall portion laterally adjacent to the first sidewall, a second sidewall portion laterally adjacent to the second sidewall, a first trench portion over the isolation material in the first trench, and a second trench portion over the isolation material in the second trench; depositing a barrier layer over the spacer layer, wherein an upper portion of the barrier layer is above the structure, and wherein a lower portion of the barrier layer is laterally adjacent to the structure; removing the upper portion of the barrier layer to expose the upper portion of the spacer layer; removing the upper part of the spacer layer to expose the structure; and an etching process is performed to recess the structure with the spacer layer remaining over the isolation material.

In a particular implementation, forming a structure between a first trench and a second trench includes etching a semiconductor material to form the first trench and the second trench. In such embodiments, the semiconductor material comprises a plurality of alternately stacked first and second semiconductor layers and an underlying semiconductor substrate, and wherein etching the first trench and the second trench comprises etching the first trench and the second trench and through some of the alternately stacked first and second semiconductor layers and into the underlying semiconductor substrate.

In certain implementations, performing an etching process to recess the structure includes recessing a first sidewall portion and a second sidewall portion of the spacer.

In certain implementations, performing an etching process to recess the structure includes removing a lower portion of the barrier layer.

In a further embodiment, a method of manufacturing a semiconductor device includes: forming a first fin structure and a second fin structure, wherein an isolation region is located between the first fin structure and the second fin structure, and wherein a gap is located between the first fin structure and the second fin structure and above the isolation region; depositing a barrier layer over the first fin structure, the isolation region, and the second fin structure, wherein an upper portion of the barrier layer is over the first fin structure and the second fin structure, and wherein a lower portion of the barrier layer fills a space between the first fin structure and the second fin structure; removing the upper portion of the barrier layer; and when the lower part of the barrier layer is reserved above the isolation region, an etching process is performed to recess the first fin structure and the second fin structure.

In a particular embodiment, the method further comprises: planarizing an upper surface of an upper portion of the barrier layer; forming an upper barrier layer over an upper surface of an upper portion of the barrier layer; and removing the upper barrier layer before removing the upper portion of the barrier layer.

In a particular embodiment, the method further comprises: forming a spacer layer over the first fin structure, the isolation region, and the second fin structure, wherein a barrier layer is deposited on the spacer layer; and removing the upper portion of the spacer layer after removing the upper portion of the barrier layer to expose the first fin structure and the second fin structure.

In a particular implementation, the isolation region is encapsulated under the spacer layer before, during, and after the etching process is performed to recess the first fin structure and the second fin structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:

forming a first structure and a second structure, wherein the first structure and the second structure respectively comprise a plurality of alternately stacked first and second semiconductor layers over a semiconductor substrate, wherein a first sidewall of the first structure faces a second sidewall of the second structure and is separated from the second structure by a gap;

forming an isolation material in the gap;

forming a spacer layer over the first structure, the spacer material, and the second structure, wherein the spacer layer comprises: a first upper portion above the first structure, a second upper portion above the second structure, a first sidewall portion laterally adjacent the first sidewall, a second sidewall portion laterally adjacent the second sidewall, and a lower portion above the spacer material and extending from the first sidewall portion to the second sidewall portion;

depositing a barrier layer over the spacer layer, wherein an upper portion of the barrier layer is positioned over the first structure and the second structure, and wherein a structural gap of the barrier layer is positioned between the first structure and the second structure;

removing the upper portion of the barrier layer to expose the first upper portion and the second upper portion of the spacer layer; and is also provided with

An etching process is performed to remove the plurality of alternately stacked first and second semiconductor layers over the semiconductor substrate while the spacer remains over the isolation material.

2. The method of claim 1, wherein the etching process is performed to remove the plurality of alternately stacked first and second semiconductor layers over the semiconductor substrate, lowering the heights of the first sidewall portion and the second sidewall portion of the spacer.

3. The method of claim 1, wherein after performing the etching process to remove the plurality of alternately stacked first and second semiconductor layers over the semiconductor substrate, the first sidewall portion and the second sidewall portion of the spacer terminate at a plurality of upper surfaces at a distance of 10 to 30 nanometers from the lower portion.

4. The method of claim 1, further comprising selectively epitaxially growing material over the first structure of the semiconductor substrate and over the second structure of the semiconductor substrate to form a source/drain region, wherein the spacer layer and the isolation material are over the first sidewall and the second sidewall to prevent epitaxial growth on the first sidewall and the second sidewall.

5. The method as recited in claim 1, wherein:

after forming the first structure and the second structure, the first structure and the second structure respectively comprise an interface between a lowest second semiconductor layer and the semiconductor substrate; and is also provided with

After forming the isolation material in the gap, the isolation material has an uppermost surface that is lower than each of the interfaces.

6. A method of manufacturing a semiconductor device, comprising:

forming a structure between a first trench and a second trench, wherein the structure has a first sidewall and a second sidewall;

forming an isolation material in the first trench and the second trench;

forming a spacer layer over the structure and the spacer material, wherein the spacer layer comprises: an upper portion above the structure, a first sidewall portion laterally adjacent to the first sidewall, a second sidewall portion laterally adjacent to the second sidewall, a first trench portion above the isolation material in the first trench, and a second trench portion above the isolation material in the second trench;

depositing a barrier layer over the spacer layer, wherein an upper portion of the barrier layer is above the structure, and wherein a lower portion of the barrier layer is laterally adjacent to the structure;

Removing the upper portion of the barrier layer to expose the upper portion of the spacer layer;

removing the upper portion of the spacer layer to expose the structure; and is also provided with

An etching process is performed to recess the structure, wherein the spacer remains over the isolation material.

7. The method of claim 6, wherein forming the structure between the first trench and the second trench comprises etching a semiconductor material to form the first trench and the second trench.

8. A method of manufacturing a semiconductor device, comprising:

forming a first fin structure and a second fin structure, wherein an isolation region is located between the first fin structure and the second fin structure, and wherein a gap is located between the first fin structure and the second fin structure and above the isolation region;

depositing a barrier layer over the first fin structure, the isolation region, and the second fin structure, wherein an upper portion of the barrier layer is over the first fin structure and the second fin structure, and wherein a lower portion of the barrier layer fills the space between the first fin structure and the second fin structure;

Removing the upper portion of the barrier layer; and is also provided with

And when the lower part of the barrier layer is reserved above the isolation region, an etching process is performed to recess the first fin structure and the second fin structure.

9. The method as recited in claim 8, further comprising:

planarizing an upper surface of the upper portion of the barrier layer;

forming an upper barrier layer over the upper surface of the upper portion of the barrier layer; and removing the upper barrier layer prior to removing the upper portion of the barrier layer.

10. The method as recited in claim 8, further comprising:

forming a spacer layer over the first fin structure, the isolation region, and the second fin structure, wherein the barrier layer is deposited on the spacer layer; and removing the upper portion of the spacer layer after removing the upper portion of the barrier layer to expose the first fin structure and the second fin structure.