CN117650061A - Chip processing method - Google Patents
Chip processing method Download PDFInfo
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- CN117650061A CN117650061A CN202311407401.4A CN202311407401A CN117650061A CN 117650061 A CN117650061 A CN 117650061A CN 202311407401 A CN202311407401 A CN 202311407401A CN 117650061 A CN117650061 A CN 117650061A
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- 238000003672 processing method Methods 0.000 title claims abstract description 35
- 235000012431 wafers Nutrition 0.000 claims abstract description 154
- 239000002356 single layer Substances 0.000 claims abstract description 113
- 239000002131 composite material Substances 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000003466 welding Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000005520 cutting process Methods 0.000 claims abstract description 9
- 238000005476 soldering Methods 0.000 claims description 24
- 230000004907 flux Effects 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 claims description 6
- XBWAZCLHZCFCGK-UHFFFAOYSA-N 7-chloro-1-methyl-5-phenyl-3,4-dihydro-2h-1,4-benzodiazepin-1-ium;chloride Chemical compound [Cl-].C12=CC(Cl)=CC=C2[NH+](C)CCN=C1C1=CC=CC=C1 XBWAZCLHZCFCGK-UHFFFAOYSA-N 0.000 claims description 3
- 238000000465 moulding Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 abstract description 18
- 230000008569 process Effects 0.000 abstract description 8
- 150000001875 compounds Chemical class 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 2
- 239000011149 active material Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
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Abstract
The application relates to the technical field of chip production, and particularly discloses a chip processing method, which comprises the following steps: stacking a plurality of single-layer wafers, and welding two adjacent single-layer wafers to form a composite wafer; cutting the composite wafer to form a plurality of composite chips; and welding each composite chip to one side surface of the substrate. In the chip processing process, firstly, a plurality of single-layer wafers are stacked and welded into a composite wafer, then the composite wafer is cut into composite chips with required sizes, and finally, the composite chips are respectively welded to the surface of one side of the substrate. Compared with the traditional chip processing method, in the method, after a plurality of single-layer wafers are compounded, the single-layer wafers are directly cut into the required compound chips, the effect of directly achieving a plurality of single-layer chips can be achieved only by once confirming and identifying the welding of the compound chips and the base plate, the phenomenon that the chips are welded for a plurality of times is avoided, the waiting time is long, and the chip processing efficiency can be improved.
Description
Technical Field
The application relates to the technical field of chip production, in particular to a chip processing method.
Background
Along with the rapid development of chips, the application of packaging technology is becoming wider and wider, and when a multilayer chip product is produced, a processing method mainly adopted is to cut a wafer into chips and then weld the chips one by one in a flip-chip manner so as to weld the chips and a substrate, and when each chip is welded, the processing method needs to carry out independent confirmation and identification on each chip, so that the processing efficiency is low.
Disclosure of Invention
Based on this, it is necessary to provide a chip processing method that includes the following steps: stacking a plurality of single-layer wafers, and welding two adjacent single-layer wafers to form a composite wafer;
cutting the composite wafer to form a plurality of composite chips;
and welding each composite chip to one side surface of the substrate.
In one embodiment, in the step of stacking a plurality of single-layer wafers, flux is coated on the surface to be stacked of each single-layer wafer;
in the step of bonding the adjacent two single-layer wafers, the soldering is performed on the adjacent two single-layer wafers by combining the flux between the adjacent two single-layer wafers.
In one embodiment, the surface to be stacked of the single-layer wafer is the opposite surface of the surface where the welding spot of the single-layer wafer is located; in the step of stacking a plurality of single-layer wafers, the welding spot of one single-layer wafer of two adjacent single-layer wafers is connected with the surface to be stacked of the other single-layer wafer.
In one embodiment, in the step of stacking a plurality of single-layer wafers, a plurality of single-layer wafers are stacked according to anchor points.
In one embodiment, in the step of bonding adjacent two single-layer wafers, a plurality of single-layer wafers arranged in a stack are put into a vacuum molding apparatus.
In one embodiment, before the step of dicing the composite wafer, the chip processing method further includes: and a scribing protective film is arranged on the surface of one side of the composite wafer far away from the welding point.
In one embodiment, before the step of dicing the composite wafer, the chip processing method further includes: and removing the soldering flux between the two adjacent single-layer wafers.
In one embodiment, in the step of soldering each of the composite chips to one side surface of the substrate, the solder joints of the plurality of composite chips are soldered to the silicon pins of the substrate by TCB soldering technology.
In one embodiment, each of the solder joints is in one-to-one correspondence with a respective silicon die pin on the substrate.
In one embodiment, before the step of stacking a plurality of single-layer wafers, the chip processing method further includes: each single-layer wafer is divided into rows and columns, and adjacent single-layer wafers are aligned according to the rows and the columns.
The chip processing method provided by the embodiment of the application comprises the following steps:
stacking a plurality of single-layer wafers, and welding two adjacent single-layer wafers to form a composite wafer;
cutting the composite wafer to form a plurality of composite chips;
and welding each composite chip to one side surface of the substrate.
In the chip processing process, firstly, a plurality of single-layer wafers are stacked and welded into a composite wafer, then the composite wafer is cut into a plurality of composite chips with required sizes, and finally, each composite chip is welded to the surface of one side of the substrate respectively. Compared with the traditional chip processing method that a plurality of single-layer wafers are cut into chips one by one and then welded to a substrate, in the method, after a plurality of single-layer wafers are compounded, the single-layer wafers are directly cut into the required compound chips, the effect of the single-layer chips can be directly achieved only by once confirming and identifying the compound chips and the substrate, the phenomenon that the chips are welded repeatedly is avoided, the waiting time is long, and the chip processing efficiency can be improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
FIG. 1 is a flow chart of a chip processing method according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a chip processing method according to an embodiment of the present application.
Reference numerals illustrate:
100. a single layer wafer; 110. soldering flux; 120. welding spots; 130. a surface to be stacked; 200. a composite wafer; 210. dicing the protective film; 300. a composite chip; 400. a substrate.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. The drawings illustrate preferred embodiments of the present application. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In one embodiment, a chip processing method is provided that may be applied to chip production, including but not limited to soldering a chip.
Referring to fig. 1 and 2, the chip processing method provided in this embodiment includes the following steps:
step S100, stacking a plurality of single-layer wafers 100, and welding two adjacent single-layer wafers 100 to form a composite wafer 200;
step S200, cutting the composite wafer 200 to form a plurality of composite chips 300;
step S300, each composite chip 300 is soldered to one side surface of the substrate 400.
In the practical application scenario of the chip processing method, firstly, a plurality of single-layer wafers 100 are stacked and welded into a composite wafer 200, then the composite wafer 200 is cut into composite chips 300 with required sizes, and finally, the composite chips 300 are respectively welded to the surface of one side of the substrate 400. Compared with the traditional chip processing method that chips are welded on the substrate 400 one by one, in the method, after a plurality of single-layer wafers 100 are compounded, the single-layer wafers 100 are directly cut into the required compound chips 300, and the effect of the single-layer chips can be directly achieved only by once confirming and identifying the welding of the compound chips 300 and the substrate 400, so that the phenomenon that the chips are welded for many times, the waiting time is long, and the chip processing efficiency can be improved.
Further, the size of the diced composite wafer 200 depends on the size of the desired composite chips 300, and a plurality of composite chips 300 are provided on the composite wafer 200.
In one embodiment, in the step of stacking a plurality of single-layer wafers 200 in step S100, the surface 130 to be stacked of each single-layer wafer 200 is coated with the flux 110;
in the step of soldering the adjacent two single-layer wafers 100 in step S100, the adjacent two single-layer wafers 100 are soldered in combination with the flux 110 between the adjacent two single-layer wafers 100.
In the step of forming the composite wafer 200 in step S100, it may include applying the flux 110 on the surface 130 to be stacked of the single-layer wafers 100 and stacking a plurality of single-layer wafers 100, and finally soldering two adjacent single-layer wafers 100. The flux 110 is coated between two adjacent single-layer wafers 100 and welded, so that the two single-layer wafers 100 can be combined to obtain a combined multi-layer wafer, and when the combined wafer 200 is operated once in the subsequent wafer processing process, a plurality of single-layer wafers 100 in the combined wafer can be simultaneously operated the same time, compared with the traditional processing means for a plurality of single-layer wafers 100, the processing is performed after the single-layer wafers 100 are combined, the processing times can be reduced, the waiting time for chip processing can be shortened, and the processing efficiency is improved.
Further, the selection of the flux 110 depends on the requirements of the soldering apparatus, and the flux 110 needs to be uniformly applied, so that displacement of two adjacent single-layer wafers 100 during soldering is avoided, and the soldering effect is prevented.
Referring to fig. 2, in one embodiment, the surface 130 of the single-layer wafer 100 to be stacked is the opposite surface of the single-layer wafer 100 where the pads 120 are located; in the step of stacking the plurality of single-layer wafers 100 in step S100, the solder joint 120 of one single-layer wafer 100 of the adjacent two single-layer wafers 100 is connected to the surface 130 to be stacked of the other single-layer wafer 100.
When two adjacent single-layer wafers 100 are stacked, the welding spot 120 of one single-layer wafer 100 is connected to the surface 130 to be stacked of the other single-layer wafer 100, so that the two single-layer wafers 100 stacked after welding can be conducted, the composite chip 300 cut by the composite wafer 200 can be conducted, and the requirement of chip processing can be met.
Further, the bonding method of two adjacent single-layer wafers 100 may not be soldering, mainly depending on whether the solder joint 120 can be directly bonded to another single-layer wafer 100.
In one embodiment, in the step of stacking the plurality of single-layer wafers 100 in step S100, the plurality of single-layer wafers 100 are stacked according to the positioning points.
When a plurality of single-layer wafers 100 are stacked, positioning points are arranged on each single-layer wafer 100, and when stacking, connecting lines of the positioning points of two adjacent single-layer wafers 100 can be perpendicular to the surfaces of the single-layer wafers 100, so that the two adjacent single-layer wafers 100 are aligned in the thickness direction, when cutting the composite wafer 200, the positioning points can be stacked to avoid the chips which are cut into the composite chips 300 and damage one side, and the chip processing quality can be improved.
Referring to fig. 2, in one embodiment, in the step of bonding adjacent two single-layer wafers 100 at step S100, a plurality of single-layer wafers 100 arranged in a stack are put into a vacuum molding apparatus. The stacked single-layer wafers 100 are placed in a vacuum pressing device, the pressing device can control the processing environment of the single-layer wafers 100, the stacked relationship of the single-layer wafers 100 can be kept unchanged in the process of pressing the single-layer wafers 100 into the composite wafer 200, the temperature and the like of the single-layer wafers 100 can be kept in a good range, and the quality of the pressed composite wafer 200 can be improved.
Further, in the above-described embodiments, the selection of the vacuum compression molding apparatus may be based on the size of the single-layer wafer 100 to be compressed and the desired compression environment parameters.
Referring to fig. 2, in one embodiment, before the step of dicing the composite wafer 200 in step S200, the chip processing method provided in this embodiment further includes: a dicing protective film 210 is provided on a side surface of the composite wafer 200 remote from the pads 120. The dicing protective film 210 is disposed on the composite wafer 200, and when the composite wafer 200 is diced, the composite wafer 200 is adhered to the protective film, so that the integrity of the composite chip 300 in the dicing process can be maintained, the breakage generated in the dicing process can be reduced, the situation that the composite chip 300 does not displace and fall in the normal conveying process can be ensured, and the quality of the diced composite chip 300 is improved.
In one embodiment, before the step of dicing the composite wafer 200 in step S200, the chip processing method further includes: the flux 110 between adjacent two single-layer wafers 100 is removed. The soldering flux 110 is coated among the single-layer wafers 100 in the composite wafer 200, the soldering flux 110 provides an auxiliary positioning function in the process of welding the single-layer wafers 100, the soldering flux 110 needs to be removed before cutting the composite wafer 200 after welding is finished, the influence of the soldering flux 110 on the cutting precision when cutting the composite wafer 200 is avoided, and the quality of the cut composite chips 300 can be improved.
Further, if the step of removing the flux 110 is not performed before dicing, the diced composite chip 300 contains the flux 110, and in the subsequent processing, if filling is required, the presence of the flux 110 may affect the performance of the filling step, and the flux 110 is an active material, and bubbles or oxidation are easily generated, so that the quality of the composite chip 300 is easily degraded.
Referring to fig. 2, in one embodiment, in the step of soldering each of the composite chips 300 to one side surface of the substrate 400 in step S300, the pads 120 of the several composite chips 300 are soldered to the silicon pins of the substrate 400 by TCB soldering technology. When the composite chip 200 is welded to the substrate, the welding points of the composite chip 300 are welded to the silicon chip pins of the substrate 400, so that electrical conduction between the composite chip 300 and the substrate 400 can be realized, and the processing effect can be improved.
Further, when soldering two adjacent single-layer chips, soldering can be performed between the solder joint and the silicon chip pin.
Referring to fig. 2, in the above embodiment, TCB bonding technology is a chip packaging technology, mainly flip-chip bonding a composite chip 300 onto a substrate 400.
In one embodiment, each bond pad 120 is in a one-to-one correspondence with a respective silicon die pin on the substrate 400. In actual production, the number of the welding spots 120 on the composite chip 300 is not necessarily equal to the number of the silicon chip pins on the substrate 400, and the welding spots 120 are connected with the silicon chip pins to the greatest extent during welding, so that the transmission speed between the composite chip 300 and the substrate 400 after the welding is finished is faster, and the effect of the processing method is improved.
In one embodiment, before the step of stacking a plurality of single-layer wafers 100 in step S100, the chip processing method further includes: each single-layer wafer 100 is divided into rows and columns, and adjacent single-layer wafers 100 are aligned in accordance with the rows and columns. The distribution of the solder joints 120 on the single-layer wafer 100 is not uniform, the single-layer wafer 100 is divided into rows and columns, and then the rows and columns are aligned, so that the accuracy of welding the adjacent single-layer wafers 100 can be improved, the electrical conduction of the composite wafer 200 can be ensured, and the chip processing requirement can be met.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the patent. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. The chip processing method is characterized by comprising the following steps of:
stacking a plurality of single-layer wafers, and welding two adjacent single-layer wafers to form a composite wafer;
cutting the composite wafer to form a plurality of composite chips;
and welding each composite chip to one side surface of the substrate.
2. The chip processing method according to claim 1, wherein in the step of stacking a plurality of single-layer wafers, flux is applied to a surface to be stacked of each of the single-layer wafers;
in the step of bonding the adjacent two single-layer wafers, the soldering is performed on the adjacent two single-layer wafers by combining the flux between the adjacent two single-layer wafers.
3. The chip processing method according to claim 2, wherein the surface to be stacked of the single-layer wafers is an opposite surface to a surface where pads of the single-layer wafers are located; in the step of stacking a plurality of single-layer wafers, the welding spot of one single-layer wafer of two adjacent single-layer wafers is connected with the surface to be stacked of the other single-layer wafer.
4. The chip processing method according to claim 1, wherein in the step of stacking a plurality of single-layer wafers, a plurality of single-layer wafers are stacked according to anchor points.
5. The chip processing method according to claim 1, wherein in the step of bonding adjacent two single-layer wafers, a plurality of single-layer wafers arranged in a stack are put into a vacuum press molding apparatus.
6. The chip processing method according to claim 5, wherein before the step of dicing the composite wafer, the chip processing method further comprises: and a scribing protective film is arranged on the surface of one side of the composite wafer far away from the welding point.
7. The chip processing method according to claim 2, characterized in that before the step of dicing the composite wafer, the chip processing method further comprises: and removing the soldering flux between the two adjacent single-layer wafers.
8. The chip processing method according to claim 1, wherein in the step of soldering each of the composite chips to one side surface of the substrate, the solder joints of the plurality of composite chips to the silicon chip pins of the substrate are soldered by TCB soldering technique.
9. The method of claim 8, wherein each of the solder joints is in one-to-one correspondence with a respective silicon die pin on the substrate.
10. The chip processing method according to claim 1, characterized in that before the step of stacking a plurality of single-layer wafers, the chip processing method further comprises: each single-layer wafer is divided into rows and columns, and adjacent single-layer wafers are aligned according to the rows and the columns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311407401.4A CN117650061A (en) | 2023-10-27 | 2023-10-27 | Chip processing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311407401.4A CN117650061A (en) | 2023-10-27 | 2023-10-27 | Chip processing method |
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| CN117650061A true CN117650061A (en) | 2024-03-05 |
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| CN202311407401.4A Pending CN117650061A (en) | 2023-10-27 | 2023-10-27 | Chip processing method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080006299A (en) * | 2006-07-12 | 2008-01-16 | 한국광기술원 | Wafer level packaged devices and the fabrication method |
| CN102556948A (en) * | 2010-11-23 | 2012-07-11 | 霍尼韦尔国际公司 | Batch fabricated 3d interconnect |
| CN103094236A (en) * | 2012-12-28 | 2013-05-08 | 华天科技（西安）有限公司 | Single-chip package part with wafer thinned after bottom fillers cures and manufacture process thereof |
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2023
- 2023-10-27 CN CN202311407401.4A patent/CN117650061A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080006299A (en) * | 2006-07-12 | 2008-01-16 | 한국광기술원 | Wafer level packaged devices and the fabrication method |
| CN102556948A (en) * | 2010-11-23 | 2012-07-11 | 霍尼韦尔国际公司 | Batch fabricated 3d interconnect |
| CN103094236A (en) * | 2012-12-28 | 2013-05-08 | 华天科技（西安）有限公司 | Single-chip package part with wafer thinned after bottom fillers cures and manufacture process thereof |
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