CN117648273A - Improved SRAM controller with error correction code checking function - Google Patents

Abstract

The invention relates to an improved SRAM controller with an error correction code checking function. The controller includes: an advanced high-performance bus configured to connect communication among the processor, the memory, and the high-speed peripheral; a controller module with a data buffer configured to perform timing conversion of the higher-level high-performance bus interface and the SRAM interface, and perform SRAM read and write control with the data buffer; an error correction code verification module configured to perform error correction code verification; an SRAM module is configured to contain a plurality of SRAM cells. The improved SRAM controller with the error correction code checking function provided by the invention has the advantages that the data buffer is added in the controller module, and compared with the existing circuit structure, the read-write efficiency can be greatly improved.

Description

Improved SRAM controller with error correction code checking function

Technical Field

The invention relates to the technical field of memories, in particular to an improved SRAM controller with an error correction code checking function.

Background

A Static Random-Access Memory (SRAM) is one type of Random Access Memory. The memory can always hold the data stored therein as long as the memory is kept powered on. SRAM is mainly used in high performance computing devices and in scenarios where fast data access is required, such as processor caches, graphics Processors (GPUs), etc.

FIG. 1 is a schematic diagram of a conventional SRAM controller. As shown in fig. 1, the conventional SRAM controller with an error correction code checking function includes an Advanced High-performance Bus (AHB), a controller module (Controller without Data Buffer module) without a data buffer, an error correction code (Error Correction Code, ECC) checking module, and an SRAM module. The conventional SRAM controller generates excessive latency in the operation logic of SRAM read-then-write, resulting in low read-write efficiency.

Disclosure of Invention

In view of some or all of the problems in the prior art, the present invention provides an improved SRAM controller with error correction code verification functionality, the controller comprising:

an advanced high-performance bus configured to connect communication among the processor, the memory, and the high-speed peripheral;

a controller module with a data buffer configured to perform timing conversion of the higher-level high-performance bus interface and the SRAM interface, and perform SRAM read and write control with the data buffer;

an error correction code verification module configured to perform error correction code verification;

an SRAM module is configured to contain a plurality of SRAM cells.

Further, the high-performance bus receives commands and data information sent by the processor, and returns state information fed back by the SRAM controller during working to the processor.

Further, the controller module with the data buffer is connected with the high-level high-performance bus, the error correction code verification module and the SRAM module.

Further, the data buffer is preferably a register composed of D flip-flops.

Further, the SRAM controller supports byte/halfword/word read and write operations.

Further, when the SRAM controller performs a byte/halfword write operation, the following steps are automatically completed:

reading 32bits of data corresponding to the byte/half word;

splicing the written data of the byte/half word to obtain new 32bits data;

and executing the writing operation on the new 32bit data.

Further, when no read/write operation is generated after the conversion from the high-performance bus timing to the SRAM module interface timing, performing operations includes:

the data buffer has no data, and no read operation or write operation is executed;

and the data buffer is provided with data, and the original data in the data buffer is written into the SRAM module.

Further, performing a write operation on the SRAM module includes:

the data buffer has no data, and external data is written into the SRAM module;

and the data buffer is provided with data, the original data in the data buffer is written into the SRAM module, and the external data is stored in the data buffer.

Further, performing a read operation on the SRAM module includes:

the data buffer has no data, and the data is read from the SRAM module;

the data buffer is provided with data; reading data from the data buffer memory, wherein the reading addresses are consistent; or reading data from the SRAM module, wherein the reading addresses are inconsistent.

Further, performing read and write operations simultaneously on the SRAM module includes:

the data buffer is free of data, and external data are stored in the data buffer; reading data from the data buffer memory, wherein the read-write addresses are consistent; or, reading data from the SRAM module, wherein the read-write addresses are inconsistent;

the data buffer is provided with data, the original data in the data buffer is written into the SRAM module, external data are stored in the data buffer, and READYOUT is pulled down by one clock period; in the next clock period, the reading address is consistent with the corresponding address of the data in the data buffer, and the data is read from the data buffer; or in the next clock cycle, the read address is inconsistent with the corresponding address of the data in the data buffer, and the data is read from the SRAM module.

Compared with the prior art, the invention has the beneficial effects that: the improved SRAM controller structure with the error correction code checking function is realized, and compared with the existing circuit structure, the read-write efficiency can be greatly improved.

Drawings

To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.

FIG. 1 is a schematic diagram of a general architecture of a conventional SRAM controller;

FIG. 2 is a schematic diagram of an overall architecture of an SRAM controller according to one embodiment of the present invention;

FIG. 3 is a timing diagram of an advanced high performance bus interface and SRAM interface according to one embodiment of the present invention.

Detailed Description

In the following description, the present invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers and configurations are set forth in order to provide a thorough understanding of embodiments of the present invention. However, the invention is not limited to these specific details.

Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

It should be noted that the embodiments of the present invention describe the steps of the method in a specific order, however, this is merely for the purpose of illustrating the specific embodiments, and not for limiting the order of the steps. In contrast, in different embodiments of the present invention, the sequence of each step may be adjusted according to the adjustment of the actual requirement.

In the present invention, the modules of the system according to the present invention may be implemented using software, hardware, firmware or a combination thereof. When implemented in software, the functions of the modules may be performed by a computer program flow, e.g., the modules may be implemented by code segments (e.g., code segments in a language such as C, C ++) stored in a storage device (e.g., hard disk, memory, etc.), which when executed by a processor, perform the corresponding functions of the modules. When a module is implemented in hardware, the functionality of the module may be implemented by providing corresponding hardware structures, such as by hardware programming of a programmable device, e.g., a Field Programmable Gate Array (FPGA), or by designing an Application Specific Integrated Circuit (ASIC) comprising a plurality of transistors, resistors, and capacitors, etc. When implemented in firmware, the functions of the module may be written in program code form in a read-only memory of the device, such as EPROM or EEPROM, and the corresponding functions of the module may be implemented when the program code is executed by a processor. In addition, some functions of the module may need to be implemented by separate hardware or by cooperation with the hardware, for example, a detection function is implemented by a corresponding sensor (e.g., a proximity sensor, an acceleration sensor, a gyroscope, etc.), a signal transmission function is implemented by a corresponding communication device (e.g., a bluetooth device, an infrared communication device, a baseband communication device, a Wi-Fi communication device, etc.), an output function is implemented by a corresponding output device (e.g., a display, a speaker, etc.), and so on.

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

FIG. 2 is a schematic diagram of an overall architecture of an SRAM controller according to one embodiment of the present invention. As shown in fig. 2, the controller includes: advanced High-performance Bus (AHB), controller module (Controller with Data Buffer module) with data buffer, error correction code check module (ECC check module), SRAM module.

The advanced high-performance bus is a high-performance, high-bandwidth bus protocol configured to connect communications between processors, memory, and high-speed peripherals. The high-level high-performance bus receives commands and data information sent by the processor, and returns state information fed back by the SRAM controller during working to the processor.

A controller module with data buffer configured to perform timing conversion of the higher-level high-performance bus interface and the SRAM interface, and to perform SRAM read and write control with data buffer. The data buffer is preferably a register consisting of D flip-flops.

An error correction code verification module configured to perform error correction code verification.

An SRAM module is configured to contain a plurality of SRAM cells.

As shown in fig. 2, the connection relationship between each part of the SRAM controller is: the controller module with the data buffer is connected with the high-level high-performance bus, the error correction code verification module and the SRAM module.

The read and write operations of the SRAM controller in the non-error correction code mode and the error correction code mode are described in detail below.

FIG. 3 is a timing diagram of an advanced high performance bus interface and SRAM interface according to one embodiment of the present invention. As shown in FIG. 3, taking the example of a 16-bit write operation that initiates three different addresses and data on the higher-level high-performance bus, the upper portion of FIG. 3 is the higher-level high-performance bus timing, and the lower portion is the SRAM module interface timing. W (Write) represents Write, R (Read) represents Read, a (Address) represents Address, and D (Data) represents Data; numeral 16 indicates 16bits (half-word), and numeral 32 indicates 32bits (word); the lower right hand corner of the letter indicates 1 st read/write, 2 nd read/write, and so on. In fig. 3, all addresses and data are different, i.e., a1+.a2+.a3, w1+.w2+.w3, rd1+.rd2+.rd3).

Table 1 is the SRAM module read and write operations in FIG. 3. The SRAM controller supports byte/halfword/word read and write operations. When the SRAM controller executes the writing operation of the byte/half word, the following steps are automatically completed: firstly, reading 32bits of data corresponding to the byte/half word; then, splicing the data written in the byte/half word to obtain new 32bits data; finally, the write operation is performed on the new 32-bit data.

Table 1 SRAM module read and write operations in fig. 3

Clock Cycle	Read and write operations for SRAM modules
		T1	SRAM→RD 1
T2	RD 1 +WD 1 →BUF，SRAM→RD 2
		T3	RD 2 +WD 2 →BUF，BUF→RAM
T4	SRAM→RD 3
		T5	RD 3 +WD 3 →BUF，BUF→SRAM
T6	BUF→SRAM

As shown in table 1, the read and write operations of the SRAM module are: at time T1, reading data RD1 from SRAM module (A1); at the time of T2, splicing 16bits WD1 to be written into a new 32bits with 16bits and WD1 corresponding to the 32bits of the read 32bits RD1, storing the new 32bits in a data buffer (buffer), and reading data RD2 from an SRAM module (A2); at the time of T3, splicing 16bits WD2 to be written into new 32bits with 16bits and WD2 corresponding to the 32bits read from RD2, storing the new 32bits in a buffer, and writing data RD1+WD1 in the buffer at the previous time into an SRAM module (A1); the SRAM module (A3) cannot be read at the time T3, and the HREADY signal is low; at time T4, data RD3 is read from SRAM block (A3), at which time the HREADY signal is high; at the time of T5, splicing 16bits WD3 to be written into new 32bits with 16bits and WD3 corresponding to the read 32bits RD3, storing the new 32bits in a buffer, and writing data RD2+WD2 in the buffer at the previous time into an SRAM module (A2); at time T6, data rd3+wd3 in buffer is written into SRAM block (A3).

Table 2 is a summary of all read and write conditions of the SRAM module interface of the SRAM controller according to one embodiment of the present invention. In table 2, NA indicates that no read/write operation is generated after the conversion from the higher-level high-performance bus timing to the SRAM module interface timing; the invalid indicates that no data exists in a data buffer (buffer); valid indicates that there is data in buffer; w represents performing a write operation to the SRAM module; r represents performing a read operation on the SRAM module; r_req indicates the state where there is currently a read request to the SRAM module, but HREADY is low. Described in table 2 is the state of the read-write process, and the SRAM module read and write timing is not considered.

Table 2 summary of all read and write conditions of the SRAM module interface of the SRAM controller of one embodiment of the present invention

And when no read-write operation is generated after the interface time sequence of the SRAM module is converted from the high-level high-performance bus time sequence to the interface time sequence of the SRAM module, executing operations including operations in two states of NA+invalid and NA+valid. In the na+invalid state, no read operation and no write operation are performed, and no data is available in the buffer. And in the NA+valid state, writing original data in the buffer into the SRAM module, and completing writing operation, wherein no data exists in the buffer.

And executing operation under two states of W+valid and W+invalid on the SRAM module. And in the W+valid state, writing original data in the buffer into the SRAM module, and storing external data in the buffer. And in the W+invalid state, writing external data into the SRAM module, and completing read-write operation without data in the buffer.

And simultaneously executing read operation and write operation on the SRAM module, wherein the operations comprise W+R+invalid and W+R_rea+valid. Storing external data in a buffer in a W+R+invalid state; reading data from buffer, wherein the read-write addresses are consistent; or, the read-write addresses are inconsistent, and data is read from the SRAM module. Under two states of W+R_rea+valid, writing original data in a buffer into the SRAM module, storing external data in the buffer, and simultaneously pulling READYOUT down by one clock cycle; in the next clock period, the read address is consistent with the corresponding address of the data in the buffer, and the data is read from the buffer; or in the next clock period, the read address is inconsistent with the corresponding address of the data in the buffer, and the data is read from the SRAM module.

And executing the reading operation on the SRAM module, wherein the reading operation comprises the operation under two states of R+valid and R+invalid. And in the R+invalid state, reading data from the SRAM module, and finishing read-write operation without data in the buffer. In the R+valid state, the reading addresses are consistent, and data is read from the data buffer; or reading data from the SRAM module, wherein the reading addresses are inconsistent.

In the prior art, readyout is 0 in both states w+r+invalid and w+r_req+valid. The invention adds the data buffer internally, and the readyout is 0 only in the W+R_req+valid state. When readyout is 0, one more beat is needed in the read-write time sequence. Compared with the prior art, the invention greatly improves the reading and writing efficiency.

The improved SRAM controller with the error correction code checking function provided by the invention has the advantages that the data buffer is added in the controller module, and compared with the existing circuit structure, the read-write efficiency can be greatly improved.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (10)

1. An improved SRAM controller with error correction code verification, comprising:

an advanced high-performance bus configured to connect communication among the processor, the memory, and the high-speed peripheral;

a controller module with a data buffer configured to perform timing conversion of the higher-level high-performance bus interface and the SRAM interface, and perform SRAM read and write control with the data buffer;

an error correction code verification module configured to perform error correction code verification;

an SRAM module is configured to contain a plurality of SRAM cells.

2. The SRAM controller of claim 1, wherein said higher-level high-performance bus receives commands and data information from a processor, and returns status information fed back by the SRAM controller during operation to said processor.

3. The SRAM controller of claim 1, wherein said data buffered controller module is coupled to said advanced high performance bus, said error correction code verification module, and said SRAM module.

4. The SRAM controller of claim 1, wherein said data buffer is preferably a register comprised of D flip-flops.

5. The SRAM controller of claim 1, wherein the SRAM controller supports byte/half word/word read and write operations.

6. The SRAM controller of claim 5, wherein said SRAM controller performs a byte/halfword write operation by automatically:

reading 32bits of data corresponding to the byte/half word;

splicing the writing data of the byte/half word to obtain new 32bi ts data;

and executing the writing operation on the new 32bi data.

7. The SRAM controller of claim 1, wherein performing operations when no read or write operations occur after the high-performance bus timing to SRAM module interface timing conversion comprises:

the data buffer has no data, and no read operation or write operation is executed;

and the data buffer is provided with data, and the original data in the data buffer is written into the SRAM module.

8. The SRAM controller of claim 1, wherein performing a write operation on the SRAM module comprises:

the data buffer has no data, and external data is written into the SRAM module;

and the data buffer is provided with data, the original data in the data buffer is written into the SRAM module, and the external data is stored in the data buffer.

9. The SRAM controller of claim 1, wherein performing a read operation on the SRAM module comprises:

the data buffer has no data, and the data is read from the SRAM module;

the data buffer is provided with data; reading data from the data buffer memory, wherein the reading addresses are consistent; or reading data from the SRAM module, wherein the reading addresses are inconsistent.

10. The SRAM controller of claim 1, wherein concurrently performing a read operation and a write operation on the SRAM module comprises:

the data buffer is free of data, and external data are stored in the data buffer; reading data from the data buffer memory, wherein the read-write addresses are consistent; or, reading data from the SRAM module, wherein the read-write addresses are inconsistent;

the data buffer is provided with data, the original data in the data buffer is written into the SRAM module, external data are stored in the data buffer, and READYOUT is pulled down by one clock period; in the next clock period, the reading address is consistent with the corresponding address of the data in the data buffer, and the data is read from the data buffer; or in the next clock cycle, the read address is inconsistent with the corresponding address of the data in the data buffer, and the data is read from the SRAM module.