CN117648019A

CN117648019A - Backboard system, computing device and management method for computing device

Info

Publication number: CN117648019A
Application number: CN202211078307.4A
Authority: CN
Inventors: 雷虎宝; 包云兵
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-09-05
Filing date: 2022-09-05
Publication date: 2024-03-05
Also published as: WO2024051453A1

Abstract

A backboard system, a computing device and a management method for the computing device relate to the field of computers. The back plate system includes: a plurality of backplates arranged in parallel to each other and spaced apart from each other, each backplate comprising: a first port; a second port configured to connect to a memory; and a third port configured to be connected to the controller; and a flexible circuit member connected to the first port of each of the plurality of backplanes, and configured to transmit signals between the plurality of backplanes. The system energy efficiency can be improved, flexible expansion of the backboard and the memory can be realized, and the application range of the backboard system and the computing equipment is enlarged.

Description

Backboard system, computing device and management method for computing device

Technical Field

The present disclosure relates to the field of computer technology, and more particularly, to a backplane system, a computing device including the backplane system, and a management method for the computing device.

Background

With the rapid development of new technologies such as big data, cloud computing, and the like, high-performance computing devices such as servers are widely used in various industries and scenarios. Such computing devices typically include components such as a central processing unit (central processing unit, CPU), motherboard, memory, and the like. As the demand for computing power in various applications continues to increase, the system power consumption of computing devices increases substantially, and the temperature rise caused by the substantially increased power consumption can inhibit the performance of processors such as CPUs. As a result, the demands placed on heat dissipation by computing devices are also increasing in order to ensure that the high power consumption processor performance is still adequately relaxed.

Currently, in order to increase heat dissipation capacity in a computing device such as a server, the air volume of the air-cooled system may be increased by increasing the rotational speed of the fan of the system. However, since a back plate such as a memory (also referred to as a hard disk back plate) is disposed perpendicular to a main board (main board) where a CPU is located, the hard disk back plate is disposed between the CPU and the fan, which causes the hard disk back plate to block a cooling air flow. Although the flow of cooling air can be increased by arranging the vent holes on the hard disk backboard, the positions and the number of the vent holes are limited due to the fact that factors such as circuit wiring, device arrangement and the like are required to be considered in the hard disk backboard, so that the air quantity in the computing equipment is limited, and the heat dissipation requirement of the continuously-improved processor cannot be met.

Disclosure of Invention

In order to solve the above-described problems, the present disclosure provides an improved backplane system, a computing device, and a management method for the computing device.

In a first aspect, there is provided a back plate system comprising: a plurality of backplates arranged in parallel to each other and spaced apart from each other, each backplate comprising: a first port; a second port configured to connect to a memory; and a third port configured to be connected to a memory controller; and a flexible circuit member connected to the first port of each of the plurality of backplanes, and configured to transmit signals between the plurality of backplanes.

In the scheme of the present disclosure, by providing a plurality of backplanes arranged in parallel and flexible circuit parts interconnecting the plurality of backplanes, flexible expansion of the backplanes and the memory can be realized while realizing low wind resistance and high energy efficiency, and custom devices are not required, so that the applicable scenes and the range of the backplate system and the computing device comprising the backplate system are expanded at lower cost.

In one possible implementation, the back plate system further comprises: at least one set of first indicator lights disposed on the flexible circuit member, each set of first indicator lights configured to indicate a status of a corresponding memory of at least one memory connected to the plurality of backplanes and adapted to be connected to a set of second indicator lights located on a housing of the corresponding memory via the light guiding studs. The memory status indicator lamp can be arranged more conveniently and flexibly.

In another possible implementation, each set of first indicator lights includes a plurality of first indicator lights, each first indicator light being disposed directly on a surface of the flexible circuit member. Therefore, the cost is increased by specially customizing the first indicator lamps which are mutually overlapped is avoided, and the universality of the device is enhanced.

In another possible implementation, each of the plurality of backplanes includes a plurality of second ports to form a plurality of columns of second ports on one side of the plurality of backplanes, wherein the flexible circuit part includes a plurality of first sections and second sections interconnecting the plurality of first sections, each first section being arranged adjacent to a corresponding column of second ports and extending in a direction in which the plurality of backplanes are stacked, and wherein each set of first indicator lights is arranged adjacent to a second port for a corresponding memory. In the case where each back plate has a plurality of memories, the corresponding first indicator lamp, light guide column, and second indicator lamp can be easily arranged for each memory, which reduces the difficulty of arrangement.

In another possible implementation, each back plate includes at least one recess portion that accommodates the flexible circuit member, each recess portion being located between two adjacent second ports. The flexible circuit member can be arranged more compactly and space occupation can be reduced.

In another possible implementation, the back plate system further includes a support plate, the flexible circuit member being secured to a plate surface of the support plate. Helping to guide and secure the flexible circuit member so that the flexible circuit member is connected to each back plate.

In another possible implementation, the plurality of backplanes includes a master backplane and a slave backplane, the master backplane being adapted to be connected to a baseboard management controller, the baseboard management controller being configured to manage the master backplane and to manage the slave backplane via the master backplane. Other backplanes are managed by the main backplane and management signals are transmitted by means of flexible circuit components, so that a simple and efficient management is achieved with a large number of backplanes and possibly further extensions.

In another possible implementation, each back plate includes a control unit and a master-slave mode control terminal interconnected to each other, the flexible circuit member includes a pull-down terminal and a floating terminal, and wherein the master-slave mode control terminal of the master back plate is connected to one of the pull-down terminal and the floating terminal, and the master-slave mode control terminal of the slave back plate is connected to the other of the pull-down terminal and the floating terminal. The arrangement of the master-slave mode for a plurality of backplanes can be performed in a simple and efficient manner.

In another possible implementation, each back plate includes: and a fourth port connected to the control unit and adapted to be connected to the baseboard management controller. Management of a plurality of backplanes can be achieved simply and efficiently.

In another possible implementation, each back plate further includes: a first gating device and a second gating device each including a device connection, a first channel, and a second channel, and configured to connect the device connection to the first channel or the second channel based on a selection signal from the control unit, wherein the device connection of the first gating device is connected to the fourth port, the first channel of the first gating device is connected to the firmware update interface of the control unit, and the second channel of the first gating device is connected to the satellite management controller of the control unit; and wherein the device connection of the second gating device is connected to the first port, the first channel of the second gating device is connected to the satellite management controller, and the second channel of the second gating device is connected to the device connection of the first gating device, the satellite management controller of the main backplane being configured to forward firmware update data from the second channel of the first gating device to the first channel of the second gating device. A data transmission path may be provided from the baseboard management controller to the control unit of the master backplane and from the baseboard management controller to the control unit of the slave backplane via the control unit of the master backplane to facilitate firmware updates of the master and slave backplanes.

In another possible implementation, the control unit of the main backplane is configured to: in response to a firmware update to the main backplane itself, sending a selection signal to a first gating device of the main backplane to connect a device connection of the first gating device to the first channel; and in response to a firmware update to the slave backplane, sending a select signal to a first gating device of the master backplane to connect a device connection of the first gating device to the second channel and sending a select signal to a second gating device of the master backplane to connect a device connection of the second gating device to the first channel, and wherein the control unit of the slave backplane is configured to: a select signal is sent to a first gating device from the back plane to connect the device connection end of the first gating device to the first channel, and a select signal is sent to a second gating device from the back plane to connect the device connection end of the second gating device to the second channel. Firmware updates of the master backplane may be implemented and the slave backplane with the help of the master backplane.

In another possible implementation, in each backplane, the fourth port is connected to a satellite management controller of the control unit via a data bus, the satellite management controller is connected to the first port via its high-speed serial interface, and the satellite management controller is configured to obtain information about at least one of the memory state of the belonging backplane, the FRU of the backplane, and the sensed temperature of the backplane, and wherein the satellite management controller of the master backplane is further configured to provide the information of the master backplane to the baseboard management controller, and to receive information from the slave backplane and to provide the information to the baseboard management controller. The information of the main backboard can be obtained, and the information of the slave backboard is obtained by utilizing the main backboard, so that the efficient management of a plurality of backboard is realized.

In another possible implementation, the control unit of each back plate is configured to control one or more sets of first indicator lights corresponding thereto. The memory status indicator lamp can be controlled simply and effectively.

In another possible implementation, each backplane further comprises an expander adapted to expand the number of memories connected to the backplane. More memories or hard disks can be expansion connected on a single backplane.

In a second aspect, there is provided a computing device comprising: the back plate system according to the first aspect.

In a third aspect, there is provided a management method for a computing device according to the second aspect, the management method comprising: managing, by a baseboard management controller, a master backplane of the plurality of backplanes, the baseboard management controller being connected to the master backplane; and managing, by the baseboard management controller, a slave backplane of the plurality of backplanes via the master backplane.

In one possible implementation, the master-slave mode control terminal of the master back plate is connected to one of the pull-down terminal and the flying terminal of the flexible circuit member, and the slave-slave mode control terminal of the slave back plate is connected to the other of the pull-down terminal and the flying terminal of the flexible circuit member.

In another possible implementation, managing, by the baseboard management controller, a master backplane of the plurality of backplanes includes: a control unit of the main backboard sends a selection signal to a first gating device of the main backboard; and providing, by the baseboard management controller, firmware update data to the control unit of the master backplane via the first gating device of the master backplane to perform firmware update to the control unit of the master backplane, and wherein managing, by the baseboard management controller, a slave backplane of the plurality of backplanes via the master backplane comprises: the control unit of the main backboard sends out selection signals to the first gating device and the second gating device of the main backboard; transmitting a selection signal to the first gating device and the second gating device of the slave back plate by the control unit of the slave back plate; and providing, by the baseboard management controller, firmware update data to the control unit of the slave backplane via the first and second gating devices of the master backplane, the control unit and the second gating device, the flexible circuit member, and the second and first gating devices of the slave backplane to perform firmware update on the control unit of the slave backplane.

In another possible implementation, managing, by the baseboard management controller, a master backplane of the plurality of backplanes includes: acquiring, by a control unit of the primary backplate, information related to at least one of a memory state, a FRU of the backplate, and a sensed temperature of the backplate; and forwarding, by the control unit of the master backplane, the acquired information to the baseboard management controller, and wherein managing, by the baseboard management controller, a slave backplane of the plurality of backplanes via the master backplane comprises acquiring, by the control unit of each of the slave backplanes, information pertaining to at least one of a memory state, a FRU of the backplane, and a sensed temperature of the backplane of the slave backplane; and forwarding the acquired information to the baseboard management controller by the control unit of the slave backboard via the control unit of the master backboard.

In a fourth aspect, a management apparatus of a computing device is provided, where the management apparatus includes modules for performing the method of managing a computing device in the third aspect or any of the possible implementation manners of the third aspect.

In a fifth aspect, the present application provides a computer readable storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the method of the above aspects.

In a sixth aspect, the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the above aspects.

Further combinations of the present application may be made to provide further implementations based on the implementations provided in the above aspects.

Drawings

Fig. 1 shows a back plate system in a conventional approach.

Fig. 2 shows a schematic diagram of a computing device provided in accordance with the present disclosure.

Fig. 3 shows a simplified schematic diagram of a back plate system provided in accordance with the present disclosure.

Fig. 4 shows a schematic perspective view of a back plate in a back plate system provided according to the present disclosure.

Fig. 5 illustrates a perspective view of a back plate system provided in accordance with the present disclosure.

Fig. 6 illustrates a front view of a back plate system provided in accordance with the present disclosure.

Fig. 7 illustrates a side view of a back plate system provided in accordance with the present disclosure.

Fig. 8 illustrates a top view of a back plate system provided in accordance with the present disclosure.

Fig. 9 illustrates a perspective view of a memory-mounted backplane system provided in accordance with the present disclosure.

Fig. 10 illustrates a front view of a memory-mounted backplane system provided in accordance with the present disclosure.

Fig. 11 shows a circuit block diagram of a portion of circuitry in a computing device provided in accordance with the present disclosure.

Fig. 12 shows a schematic diagram of a portion of a circuit for determining a master-slave backplane of a computing device provided in accordance with the present disclosure.

Fig. 13 shows a schematic diagram of a portion of circuitry of a computing device for implementing firmware upgrades according to the present disclosure.

Fig. 14 shows a schematic diagram of a portion of circuitry of a computing device for implementing firmware upgrades according to the present disclosure.

Fig. 15 shows a schematic diagram of a portion of the circuitry of a computing device for implementing memory, indicator lights, and backplane management, provided in accordance with the present disclosure.

Fig. 16 shows a schematic flow chart diagram of a management method for a computing device provided in accordance with the present disclosure.

Fig. 17 shows a schematic flow chart of a method of managing a primary backplane according to the present disclosure.

Fig. 18 shows a schematic flow chart of a method of managing slave backplanes according to the present disclosure.

Fig. 19 shows a schematic flow chart of a method of managing a primary backplane according to the present disclosure.

Fig. 20 shows a schematic flow chart of a method of managing slave backplanes according to the present disclosure.

Description of the reference numerals

100': back plate system 110': opening 1000: computing device 100: back plane system 110-1 … … 110-N: back plate 111: first port 112: second port 113: third port 114: recess 115: control unit 1151: satellite management controller 116: first gating device 117: second gating device 118: expander 119: fourth port 120: flexible circuit member 121: support plates 122-1, 122-2: first section 123 of flexible circuit member: second section 130-1 … … -L of flexible circuit member: first indicator light 200: memory 300: memory controller 400: the baseboard management controller 500: motherboard and central processing unit D1: first direction D2: second direction

Detailed Description

To enhance the heat dissipation capability of a computing device, the present disclosure provides an improved backplane system, a computing device including the backplane system, and a method for managing a computing device. In a modification, a plurality of backplanes are arranged in a parallel spaced arrangement and interconnected with flexible circuit members. Therefore, not only can the airflow wind resistance be effectively reduced and the air quantity be increased, and therefore the energy efficiency of the system is improved, but also the number of back plates and the number of memories can be flexibly expanded without specially customizing devices for different products and applications, so that a storage solution with high energy efficiency, low cost and good expansibility is provided.

The backplate system of the present disclosure will be described in more detail below with reference to the accompanying drawings.

Fig. 1 shows a backplane system 100' in one conventional approach. The backplane system 100' is used to provide a connection for the motherboard and memory (or hard disk) of the server and is typically disposed between the fan and the CPU, where the CPU is the larger power-consuming component of the server and is the important heat sink for the fan. As shown in fig. 1, the back plate system 100 'employs a vertically integrated back plate solution, and openings 110' are provided in the back plate for cooling air flow therethrough. In other words, the board surface of the backplate system 100' is perpendicular to the air flow from the cooling fan, and thus the cooling air flow needs to pass through the apertures 110' of the backplate system 100' to enter the area to be cooled behind, thereby providing heat dissipation for the CPU and other components.

However, the open cell content of the back-plate system 100' is typically low, e.g., less than 20%. In a server or other computing device provided with the back panel system 100', if the air volume and heat dissipation capacity are increased only by increasing the rotational speed of the fan, such a low aperture ratio may cause the system to have a large wind resistance and severely limit the increase in air volume. In this case, the fan consumes more power, resulting in a reduction in energy efficiency of the system that fails to meet the energy efficiency requirements in a high-computing-force scene.

Fig. 2 shows a schematic diagram of a computing device 1000 according to an embodiment of the disclosure. By way of example, the computing device 1000 may be a server, such as a general purpose rack server, which may be arranged as a node in a network to enable processing of data and information. However, it is to be appreciated that the implementation of computing device 1000 is not so limited, and may be any suitable type of computing or processing device.

As shown in fig. 2, the computing device 1000 may include a backplane system 100, at least one memory 200, at least one memory controller 300, and a motherboard and a central processing unit 500. As an example, motherboard and central processing unit 500 may include a central processing unit and a motherboard carrying the central processing unit and other electrical and electronic components. The central processing unit may access the at least one memory 200 through the at least one memory controller 300 and the backplane system 100 to perform related operations such as reading data from the memory 200, processing the data, and writing and storing the data. The at least one memory controller 300 may include, but is not limited to, a serially connected small computer system interface (serial attached small computer system interface, SAS) controller, a peripheral component interconnect express (peripheral component interconnect express, PCIe) controller, a Unified Bus (UB) controller, a computing standard link (compute express link, CXL) controller, and the like. The at least one memory 200 may include, but is not limited to, SAS hard drives, serial advanced technology attachment (serial advanced technology attachment, SATA) hard drives, non-volatile high speed transmission bus (non-volatile memory express, NVMe) hard drives, and other types of hard drives, and may also include storage media such as CXL, UB, etc. that are memory semantic. The backplane system 100 may couple the at least one memory 200 to the at least one memory controller 300 such that data reading from, writing to, and storing to the at least one memory 200 may be accomplished under the control of the at least one memory controller 300. In addition, in addition to providing interconnection to memory (or hard disk) and a motherboard in computing device 1000, backplane system 100 may also provide a framework for power and data signal transmission for the motherboard.

Fig. 3 shows a simplified schematic diagram of a backplate system 100 according to embodiments of the present disclosure, and fig. 4 shows a perspective schematic diagram of a plurality of backplates in the backplate system 100 according to embodiments of the present disclosure. While the backplane system 100 is shown above as part of the computing device 1000, this description is merely exemplary, and it is to be understood that the backplane system 100 may be widely applicable to information and communication technology (information and communications technology, ICT) infrastructure devices such as network devices and storage devices, or other suitable devices or apparatuses requiring the use of memory. As shown in fig. 2-4, the backplate system 100 includes a plurality of backplates 110-1 … … 110-N, with the plurality of backplates 110-1 … … -N being arranged to be stacked parallel to one another and spaced apart from one another. As an example, each of the plurality of backplanes 110-1 … … 110-N may be a rigid printed circuit board (printed circuit board, PCB) to provide a high speed connection between the memory 200 and the memory controller 300. The plurality of back plates 110-1 … … 110-N may be stacked one on another in the first direction D1 and at a distance from each other so as to form a sufficiently large gap between adjacent back plates. When the backplate system 100 is disposed in a server, the cooling fans of the air cooling system may form a cooling air flow traveling in a second direction D2 substantially perpendicular to the first direction D1, and the cooling air flow may flow in a gap between adjacent backplates, passing through the backplate system 100 into a rear area to be cooled.

It can be seen that the back plate system 100 employs a horizontal back plate arrangement, unlike the back plate system 100' of fig. 1. That is, the back plate surface of the back plate system 100 is parallel to the air flow from the cooling fan, which effectively increases the opening ratio of the back plate system 100 and reduces wind resistance. This arrangement can greatly reduce the blocking of cooling air flow by the backplate system 100, thereby improving the cooling air volume without excessively increasing the rotation speed of the radiator fan, which avoids increasing the power consumption of the radiator fan and effectively improves the energy efficiency of the system.

In accordance with the computing device of the present disclosure, each backplane of the plurality of backplanes 110-1 … … 110-N may include a first port 111, a second port 112 configured to connect to the memory 200, and a third port 113 configured to connect to the memory controller 300. As an example, the second ports 112 may include memory connectors (e.g., hard disk connectors), and M second ports 112 may be provided on each backplane such that M memories (i.e., memory 1 through memory M) may be connected to the corresponding second ports 112, where M is an integer greater than or equal to 1. The third port 113 may include a controller connector. For example, if storage controller 300 comprises a SAS controller, third port 113 may comprise a SAS high-speed connector corresponding to the SAS controller, and if storage controller 300 comprises a UB/CXL/PCIe controller, third port 113 may also comprise a UB/CXL/PCIe high-speed connector corresponding to the UB/CXL/PCIe controller. That is, the third port 113 may include one or more ports for connecting one or more of a SAS controller, a UB/CXL/PCIe controller, and other types of controllers, respectively. In addition, each backplane is further provided with a first port 111, which first port 111 may provide each backplane with an interface to other backplanes to facilitate signal interaction, such as low-speed management signal interaction, between the plurality of backplanes 110-1 … … 110-N.

In accordance with an embodiment of the present disclosure, the backplane system 100 further includes a flexible circuit member 120, the flexible circuit member 120 is connected to the first port 111 of each of the plurality of backplanes 110-1 … … 110-N, and the flexible circuit member 120 is configured to transmit signals between the plurality of backplanes 110-1 … … 110-N. As an example, the flexible circuit member 120 may be a flexible circuit board (flexible printed circuit, FPC), and each of the first ports 111 may include an FPC connector so as to be connected with an FPC as the flexible circuit member 120. The FPC may be a flexible printed circuit board made of polyimide or mylar, for example, and has characteristics of high wiring density, light weight, thin thickness, flexibility, and the like. The selection of the flexible circuit member 120 as an interconnection member between the plurality of backplanes 110-1 … … 110-N may provide flexibility of connection and various advantages over using a rigid connector to connect multiple backplanes. In particular, if a rigid connector is used to connect the multi-layered backplanes, the rigid connector interconnecting the two-layered backplanes requires special customization to accommodate the different products, which results in a lack of versatility of the device and increases development costs, since the distance between adjacent backplanes may vary for the different products. In addition, due to Pin density and structural steering limitations of the hard connector, the backplane system will not be able to extend more horizontal backplanes and/or more memories or hard disks, thus resulting in a system that is less scalable, which further limits the applicable scenarios and ranges. In contrast, embodiments of the present disclosure employ flexible circuit members 120 that are free to flex, which allows for flexibility in placement of the plurality of backplanes 110-1 … … 110-N without having to take into account the spacing distance of adjacent ones of the plurality of backplanes 110-1 … … 110-N, and without tailoring the connectors between backplanes to the spacing distances of backplanes in different products. In addition, the back plane can be easily expanded or added according to the storage requirements and the size and specification of the chassis, and only the wiring of the flexible circuit member 120 needs to be added and connected to the newly expanded back plane. For example, for a standard rack server of 19 inches, a single horizontal backplane of 2U (8.89 cm thick) equipment may be configured with 6 2.5 inch hard disks and may extend 5 tiers of backplanes, thus extending up to 30 hard disk slots at maximum.

In some embodiments of the present disclosure, each of the backplanes 110-1 … … 110-N may include an expander 118, the expander 118 being adapted to expand the number of memories connected to the backplane. The number of expanders 118 disposed on the backplane may be one or more and include, but are not limited to, SAS expanders (SAS expanders), UB/CXL/PCIe switches (UB/CXL/PCIe switches), and other types of expansion devices. Thus, more memories or hard disks can be expanded and connected on a single back plate. However, it will be appreciated that some or all of the backplanes may not be provided with expanders 118, and that memory or hard disks may be expanded in a manner that is straight out by SAS and PCIe/UB/CXL.

It follows that by providing the flexible circuit member 120, flexible expansion of the back plane and memory can be achieved while providing a low wind resistance and energy efficient horizontal back plane arrangement, and without custom devices, thereby greatly increasing the applicable scenarios and scope of back plane systems and computing devices at a lower cost.

Fig. 5 to 8 show perspective, front, side and top views, respectively, of a backplate system 100 according to embodiments of the present disclosure, and fig. 9 and 10 show perspective and front views, respectively, of a backplate system 100 with a memory 200 mounted according to embodiments of the present disclosure. For ease of understanding, a back plate system including two back plates 110-1 and 110-2 is described below as an example. By way of example only, each backplane has only two second ports 112, i.e., each backplane can be connected to at most two memories or hard disks. However, it will be appreciated that the number of backplanes in the backplane system 100 and the number of second ports 112 per backplane are not so limited, and may be other suitable numbers.

In some embodiments of the present disclosure, for ease of maintenance, the status of the memory may be displayed by setting an indicator light. The backplate system 100 further comprises at least one set of first indicator lights 130-1 … … -L disposed on the flexible circuit member 120, each set of first indicator lights 130-1 … … -L configured to indicate the status of a corresponding one of the at least one memories 200 connected to the plurality of backplates 110-1 … … 110-N and adapted to be connected via light guiding posts to a set of second indicator lights 220 located on the housing 210 of the corresponding memory (see fig. 10). As an example, for each memory connected to the backplane system 100, a corresponding set of first indicator lights may be provided on the flexible circuit member 120. In other words, in the case where the number of backplanes is N and the number of memories connected per backplane is M, the first indicator lamps of L groups may be provided, where l=n×m. Each set of first indicator lights may indicate a state of a corresponding memory. For example, each set of first indicator lights may include an indicator light for indicating that the memory is in an ACTIVE state (ACTIVE) or in a FAULT state (FAULT), and an indicator light for indicating that the memory is in a place state (location), where the indicator light in the ACTIVE state (ACTIVE) or in the FAULT state (FAULT) may be one indicator light for displaying different colors for the two states, respectively, or may be two indicator lights independent of each other. It will be appreciated that more or fewer indicator lights may be provided in addition to or instead of some or all of the indicator lights used to indicate other states of the memory, as desired. Each set of first indicator lights may transmit light signals through the light guide posts to a corresponding set of second indicator lights 220 on the housing 210 of the corresponding memory, which is advantageous for an operator to more easily observe and understand the state of the memory.

Providing the first indicator light on the flexible circuit member 120 has more benefits than providing the first indicator light on the back plate. Specifically, each set of first indicator lights of the back-plate system needs to be coupled to another set of second indicator lights on the housing of the memory through a light guide column capable of conducting light signals, so that an operator knows the state of the memory by observing the second indicator lights on the housing of the memory or the hard disk. However, if each set of first indicator lights in the back panel system is disposed on a horizontal back panel, it is often difficult for the arrangement direction of the plurality of indicator lights in each set of first indicator lights to be consistent with the corresponding second indicator lights on the housing of the memory. For example, the devices arranged on the horizontal back plate are typically arranged in a horizontal direction, but the plurality of indicator lights on the housing of the memory are typically arranged in a vertical direction. In this case, in order to facilitate the arrangement of the light guide column, two or more first indicator lamps of the same group of first indicator lamps can only be stacked on each other in the vertical direction so that the arrangement direction of the group of first indicator lamps is the same as the arrangement direction of a corresponding group of second indicator lamps on the housing of the memory. However, such two first indicator lamps, which are vertically stacked on each other, require special customization, which increases the complexity and cost of the memory indicator lamp. Embodiments of the present disclosure may avoid the above-described problems by providing at least one set of first indicator lights 130-1 … … 130-L on the flexible circuit member 120. The flexible circuit member 120 may be bent as needed, and its length extends substantially in the vertical direction or the stacking direction of the back plates, while its width extends in the horizontal direction. Accordingly, the first indicator lamp can be correspondingly arranged at the flexible circuit member 120 according to the arrangement condition of the second indicator lamp on the housing of the memory and a certain inconsistency is allowed without increasing the difficulty of arranging the light guide posts, which increases the flexibility of arranging the memory status indicator lamps.

In some embodiments of the present disclosure, each set of first indicator lights 130-1 … … -L includes a plurality of first indicator lights, each first indicator light being disposed directly on a surface of the flexible circuit member 200. As an example, in the case where the corresponding sets of the second lamps 220 on the housing of the memory are arranged in the vertical direction, instead of providing the customized lamps shown in fig. 2 stacked in the vertical direction, all the first lamps of each set of the first lamps may be sequentially and directly disposed on the flexible circuit member 200 in the vertical direction, which avoids the increased cost of specially customizing the first lamps stacked one on another and enhances the versatility of the device.

In some embodiments of the present disclosure, each of the plurality of backplanes 110-1 … … 110-N includes a plurality of second ports 112 to form a plurality of columns of second ports on one side of the plurality of backplanes 110-1 … … 110-N, and the flexible circuit member 120 includes a plurality of first sections 122-1, 122-2 and a second section 123 (see fig. 6) interconnecting the plurality of first sections 122-1, 122-2, each first section 122-1 or 122-2 being disposed adjacent to a corresponding column of second ports and extending along a direction D1 of the plurality of backplanes stack. Thus, each set of first indicator lights 130-1 … … 130-L can be disposed adjacent to the second port 112 for the corresponding memory. For example, when each backplane has two second ports 112, a first section 122-1 of the flexible circuit member 120 may extend along a first column of second ports, a first section 122-2 may extend along a second column of second ports, and the two first sections 122-1 and 122-2 are interconnected by a second section 123. It will be appreciated that each back plate may have more second ports and that the flexible circuit member 120 may be provided with more first sections corresponding to the number of columns of second ports. Since there is a section of the flexible circuit member 120 extending past near each column of second ports, each set of first indicator lights provided on the flexible circuit member 120 may be closer to the corresponding second port and thus to the corresponding memory. Thus, each set of first indicator lights can be conveniently connected directly to a set of second indicator lights 220 on the housing of the corresponding reservoir through the light guide posts.

In some embodiments of the present disclosure, each of the plurality of backplates 110-1 … … 110-N includes at least one notch portion 114 (see fig. 5) that accommodates the flexible circuit member 120, each notch portion 114 being located between two adjacent second ports 112. In this way, the flexible circuit member 120 can be more compactly arranged and space occupation can be reduced.

In some embodiments of the present disclosure, the back-plate system 100 further includes a support plate 121 (see fig. 5), and the flexible circuit member 120 is fixed to a plate surface of the support plate 121. Specifically, in order to facilitate the arrangement of the flexible circuit member 120, a support plate 121 may be provided to guide and fix the flexible circuit member 120. In this way, the flexible circuit member 120 may be arranged in a desired appropriate position to facilitate connection of the flexible circuit member 120 to the respective back plane.

Fig. 11 shows a circuit block diagram of a portion of circuitry in a computing device 1000 according to an embodiment of the disclosure. As shown in fig. 11, the plurality of backplanes 110-1 … … 110-N may include a master backplane 110-1 and a slave backplane 110-2 … … -N, the master backplane 110-1 being adapted to be connected to a baseboard management controller (baseboard management controller, BMC) 400, the BMC 400 being configured to manage the master backplane 110-1 and to manage the slave backplane 110-2 … … 110-N via the master backplane 110-1. As an example, the BMC 400 may implement various management functions that can manage other backplanes through the main backplate 110-1 and transmit management signals using the flexible circuit member 120, which enables simple and efficient management with a large number of backplanes and possibly further expansion. It will be appreciated that the primary backing plate in fig. 11 is the first layer backing plate 110-1, but any other layer backing plate may be selected as the primary backing plate, as well, which may implement aspects of the present disclosure.

Fig. 12 shows a schematic diagram of a portion of a circuit of a computing device 1000 for determining a master-slave backplane according to an embodiment of the disclosure. As shown in fig. 11 and 12, each of the plurality of backplates 110-1 … … 110-N includes a control unit 115 and a master-slave mode control terminal bp_slot interconnected with each other, the flexible circuit member 120 includes a pull-down terminal and a floating terminal, wherein the master-slave mode control terminal bp_slot of the master backplate 110-1 is connected to one of the pull-down terminal and the floating terminal, and the master-slave mode control terminal bp_slot of the slave backplate 110-2 … … 110-N is connected to the other of the pull-down terminal and the floating terminal. As an example, the control unit 115 may be a complex programmable logic device (complex programmable logic device, CPLD) and may include a plurality of modules, such as a satellite management controller (satellite manager controller, SMC) 1151, a memory lighting module, and related modules for data transmission, state parsing, and information collection of a memory, etc. The pin of the CPLD for controlling the operating mode may be connected to a 3.3V supply potential and to a master-slave mode control terminal bp_slot via a resistor. For example, the master-slave mode control terminal BP_Slot of the back-plane 110-1 may be connected to the pull-down terminal of the flexible circuit member 120, such that BP_Slot is placed at zero potential and the control unit 115 of the back-plane 110-1 will be considered the control unit of the master back-plane; the master-slave mode control terminal bp_slot of each of the backplanes 110-2 … … 110-N may be connected to the floating terminal of the flex circuit assembly 120 such that bp_slot is placed at a non-zero potential and the control unit of the backplanes 110-2 … … 110-N will be considered the control unit of the slave backplane. Therefore, the arrangement of the master-slave backboard can be simply and effectively completed. In addition, bp_slot of the main back plate may be connected to the floating terminal of the flexible circuit member 120, and bp_slot of the slave back plate may be connected to the pull-down terminal of the flexible circuit member 120, which may also implement the scheme of the present disclosure.

In some embodiments of the present disclosure, each of the plurality of backplanes 110-1 … … 110-N includes a fourth port 119, the fourth port 119 being connected to the control unit 115 and adapted to be connected to the BMC 400. As an example, the fourth port 119 may include a low-speed connector. The BMC 400 may connect to the control unit 115 of the master backplane via the fourth port 119 of the master backplane in the backplane 110-1 … … 110-N and manage the plurality of backplanes 110-1 … … 110-N to provide various management functions including, for example, hard disk state resolution, obtaining hard disk in-place, resetting, state information, collecting FRU (field replace unit) and temperature information of the backplane, CPLD firmware upgrades of the backplane, hard disk management (which includes managing hard disk temperatures, hard disk firmware information, hard disk failure diagnostic information, etc.), and the like.

Fig. 13 shows a schematic diagram of a portion of circuitry of computing device 1000 for implementing firmware upgrades according to an embodiment of the present disclosure. As shown in fig. 11 and 13, each of the plurality of backplanes 110-1 … … 110-N further includes a first gating device 116 and a second gating device 117, the first gating device 116 and the second gating device 117 each including a device connection, a first channel (i.e., channel 0) and a second channel (i.e., channel 1), and configured to connect the device connection to either the first channel or the second channel based on a selection signal from the control unit 115. As an example, the first and second gating devices 116 and 117 may be devices such as a Multiplexer (MUX). For example, when the selection signal input to the gate device is a first level (e.g., low level), the device connection terminal may be selectively connected to the first channel for signal transmission through the first channel, and when the selection signal input to the gate device is a second level (e.g., high level), the device connection terminal may be selectively connected to the second channel for signal transmission through the second channel, whereby different data or signal transmission paths may be selected as needed.

The device connection of the first gating device 116 of each backplane is connected to the fourth port 119, the first channel of the first gating device 116 is connected to the firmware update interface 1152 of the control unit 115, and the second channel of the first gating device 116 is connected to the SMC 1151 of the control unit 115. As an example, firmware update interface 1152 may be a joint test action group (joint test action group, JTAG) interface of the CPLD and is used to receive data to update or upgrade the firmware of the CPLD. Further, the device connection of the second gating device 117 is connected to the first port 111, the first channel of the second gating device 117 is connected to the SMC 1151, and the second channel of the second gating device 117 is connected to the device connection or fourth port 119 of the first gating device 116. The SMC 1151 of the backplane 110-1, which is configured as a master backplane, is configured to be able to forward firmware update data from the second channel of the first gating device 116 to the first channel of the second gating device 117.

With this arrangement, a data transmission path from the BMC 400 to the firmware update interface 1152 of the control unit 115 of the master backplane may be formed in the master backplane by controlling the first gating device 116 of the master backplane. In addition, a data transmission path from the BMC 400 to the flexible circuit member 120 through the SMC 1151 may be formed in the main back plane by controlling the first and second gating devices 116 and 117 of the main back plane, and a data transmission path from the flexible circuit member 120 to the firmware update interface of the control unit may be formed in the back plane by controlling the first and second gating devices 116 and 117 of the main back plane.

If a firmware update is made to the primary backplane, the control unit 115 of the primary backplane 110-1 is configured to: in response to a firmware update to the primary backplane 110-1 itself, a select signal is sent to the first gating device 116 of the primary backplane 110-1 to connect the device connection of the first gating device 116 to the first channel. In other words, when the primary backplane 110-1 itself performs a firmware update, the first gating device 116 of the primary backplane 110-1 needs to be selected with its first channel (i.e., channel 0 in fig. 11 and 13) as the transmission channel. At this time, the BMC 400 connected to the main back plane 110-1 may transmit update data to the firmware update interface 1152 via the fourth port 119 of the main back plane 110-1 and the first channel of the first strobe device 116, thereby completing the firmware update of the control unit 115 of the main back plane 110-1.

If a firmware update is made to the slave backplane, the control unit 115 of the master backplane 110-1 is configured to: in response to a firmware update to the slave backplane 110-2 … … 110-N, a select signal is sent to the first gating device 116 of the master backplane 110-1 to connect the device connection of the first gating device 116 to the second channel and a select signal is sent to the second gating device 117 of the master backplane 110-1 to connect the device connection of the second gating device 117 to the first channel. Further, the control unit 115 of the slave back plate 110-2 … … 110-N is configured to: a select signal is sent to the first gating device 116 from the back plane 110-2 … … 110-N to connect the device connection of the first gating device 116 to the first channel and a select signal is sent to the second gating device 117 from the back plane 110-2 … … 110-N to connect the device connection of the second gating device 117 to the second channel.

In other words, BMC 400 may provide data for firmware updates to a target slave backplane via a master backplane. Specifically, when a firmware update is performed from the control unit 115 of the main backplane 110-N, the first gating device 116 of the main backplane 110-1 needs to be selected with its second channel (i.e., channel 1) as a transmission channel, and also the first channel (i.e., channel 0) of the second gating device 117 of the main backplane 110-1 needs to be selected as a transmission channel. Thus, firmware update data from BMC 400 may be transferred to slave backplane 110-N via strobe device 116, SMC 1151, strobe device 117, and flex circuit assembly 120 of master backplane 110-1 in sequence. In addition, the second pass device (i.e., MUX 1) from the back plane 110-N is switched to the second pass (i.e., pass 1) and the first pass device (i.e., MUX 0) from the back plane 110-N is switched to the first pass (i.e., pass 0). Thus, the firmware update data transferred to the flexible circuit member 120 may be further transferred to the firmware update interface JTAG of the control unit of the slave back plane 110-N via the second strobe device MUX1 and the first strobe device MUX0 of the slave back plane 110-N, thereby completing the firmware update for the control unit of the slave back plane 110-N.

Fig. 14 further illustrates a schematic diagram of a portion of circuitry of computing device 1000 for implementing firmware upgrades according to an embodiment of the present disclosure. In a process of firmware update to the slave backplane with the master backplane's SMC, the master backplane 110-1 SMC 1151 may forward firmware update data from the BMC 400 to the control units of the respective slave backplanes 110-2 … … 110-N via the flexible circuit member 120. For example, the CPLD of the master backplane 110-1 as the control unit may provide a CPLD_JTAG interface that may be connected to the CPLDs of the respective slave backplanes 110-2 … … 110-N as the control units via wiring of the flexible circuit member 120, respectively. In this way, the CPLD of the master backplane 110-1 may interact with the CPLD of the slave backplane 110-2 … … 110-N using the CPLD_JTAG interface and facilitate the completion of firmware updates by the CPLD of the slave backplane.

Fig. 15 shows a schematic diagram of a portion of circuitry of a computing device 1000 for implementing memory, indicator lights, and backplane management in accordance with an embodiment of the disclosure. As shown in fig. 11 and 15, in each backplane, the fourth port 119 is connected to the SMC 1151 of the control unit 115 via a data bus, the SMC 1151 is connected to the first port 111 via its high speed serial interface, and the SMC 1151 is configured to acquire information about at least one of a memory state, an FRU of the backplane, and a sensed temperature of the backplane to which it belongs. The SMC 1151 of the master backplane 110-1 is also configured to provide information of the master backplane 110-1 to the BMC 400 and to receive information from the slave backplane 110-2 … … 110-N and provide it to the BMC 400.

As an example, in each backplane, the fourth port 119 may be connected to the SMC 1151 of the control unit 115 via an inter-integrated circuit (I2C) bus or other type of bus in addition to the transmission path formed by the first gating device 116, and the control unit 115 or the SMC 1151 may acquire and collect various information related to the backplane, such as hard disk state information. In the case where the backplane is a master backplane, the BMC 400 will connect to the fourth port 119 of the backplane and obtain the information collected by the SMC 1151 from the SMC 1151 of the backplane via the I2C bus. In addition, BMC 400 may obtain information from the backplane by means of the master backplane. In particular, the control unit 115 or SMC 1151 of the primary backplane may define a high-speed serial interface (high speed serial port, hiSport) and connect the HiSport interface to the first port 111 to connect to other backplanes via the flexible circuit component 120. Thus, the control unit 115 or the SMC 1151 of the master backplane may receive information from the control unit or the SMC of the slave backplane via the HiSport interface, and provide the acquired information of the other backplane to the BMC 400, thereby implementing management for the slave backplane.

In some embodiments of the present disclosure, the control unit 115 of each of the plurality of backplates 110-1 … … 110-N is configured to control one or more sets of first indicator lights corresponding thereto. As an example, the control unit 115 may be provided with a memory lighting module, and the module may signal the flexible circuit part 120 to control a corresponding set of first indicator lamps to emit light according to the state of the hard disk parsed by the control unit, thereby indicating that the hard disk is in an in-place state, an active state, or a malfunction state. In one embodiment, the analysis of the hard disk state of each backboard may be independently completed by the control unit of the backboard itself, and the control unit of each backboard may independently control the corresponding one or more groups of the first indicator lights to emit light.

The computing device provided according to the present application is described in detail above in conjunction with fig. 1 to 15, and the device management method provided according to the present application based on the above-described computing device will be described below in conjunction with fig. 16 to 20.

Fig. 16 shows a schematic flow chart diagram of a management method 1600 for a computing device 1000 according to an embodiment of the disclosure. The management method 1600 may be implemented in the computing device 1000 of fig. 2 and 11. It will be appreciated that the various aspects described above with respect to fig. 2-15 may be applicable to the management method 1600. For discussion purposes, the management method 1600 will be described in connection with fig. 2-15.

At block 1601, a master backplane 110-1 of a plurality of backplanes 110-1 … … 110-N is managed by a baseboard management controller 400, the baseboard management controller 400 being connected to the master backplane 110-1.

At block 1602, a slave backplane 110-2 … … 110-N of a plurality of backplanes 110-1 … … 110-N is managed by the baseboard management controller 400 via the master backplane 110-1.

In some embodiments of the present disclosure, the master slave mode control terminal bp_slot of the master backplane 110-1 is connected to one of the pull-down terminal and the floating terminal of the flexible circuit component 120, and the master slave mode control terminal bp_slot of the slave backplane 110-2 … … 110-N is connected to the other of the pull-down terminal and the floating terminal of the flexible circuit component 120.

Fig. 17 shows a schematic flow diagram of a method 1700 of managing a master backplane in some embodiments of the disclosure. The method 1700 may be implemented at block 1601 of fig. 16.

At block 1701, a select signal is issued by the control unit 115 of the primary backplane 110-1 to the first gating device 116 of the primary backplane 110-1.

At block 1702, firmware update data is provided by the baseboard management controller 400 to the control unit 115 of the primary backplane 110-1 via the first gating device 116 of the primary backplane 110-1 to perform a firmware update to the control unit 115 of the primary backplane 110-1.

Fig. 18 shows a schematic flow chart of a method 1800 of managing slave backplanes in some embodiments of the disclosure. The method 1800 may be implemented at block 1602 of fig. 16.

At block 1801, a selection signal is issued by the control unit 115 of the primary backplane 110-1 to the first gating device 116 and the second gating device 117 of the primary backplane 110-1.

At block 1802, a select signal is sent by the control unit 115 of the slave backplane 110-2 … … 110-N to the first and second gating devices 116, 117 of the slave backplane 110-2 … … 110-N.

At block 1803, firmware update data is provided by the baseboard management controller 400 to the control unit 115 of the slave backplane 110-2 … … 110-N via the first gate device 116, the control unit 115, and the second gate device 117 of the master backplane 110-1, the flexible circuit member 120, and the second gate device 117 and the first gate device 116 of the slave backplane 110-2 … … 110-N to perform a firmware update to the control unit 115 of the slave backplane 110-2 … … 110-N.

Fig. 19 shows a schematic flow chart diagram of another method 1900 of managing a primary backplane in some embodiments of the disclosure. Method 1900 may be implemented at block 1601 of fig. 16.

At block 1901, information about at least one of the memory state, the FRU of the backplane, and the sensed temperature of the backplane of the primary backplane 110-1 is obtained by the control unit 115 of the primary backplane 110-1.

At block 1902, the acquired information is forwarded by the control unit 115 of the primary backplane 110-1 to the baseboard management controller 400.

Fig. 20 shows a schematic flow chart of another method 2000 of managing slave backplanes in some embodiments of the disclosure. The method 2000 may be implemented at block 1602 of fig. 16.

At block 2001, information pertaining to at least one of a memory state, a FRU of the backplane, and a sensed temperature of the backplane is obtained by the control unit 115 of each of the slave backplanes 110-2 … … 110-N of the slave backplane.

At block 2002, the acquired information is forwarded by the control unit 115 of the slave backplane 110-2 … … 110-N to the baseboard management controller 400 via the control unit 115 of the master backplane 110-1.

In one possible implementation manner, the present application further provides a baseboard management controller, where the baseboard management controller is configured to implement the operation steps of the methods performed by the corresponding bodies in fig. 16 to fig. 20.

As a possible implementation manner, the management device is configured to implement the operation steps of each method in fig. 16 to 20.

By embodiments of the present disclosure, a flexible extended energy efficient storage solution is provided. The scheme effectively improves the air quantity of the system, reduces the power consumption of the air cooling system and improves the energy efficiency of the system, and simultaneously realizes flexible expansion of the multi-layer backboard and the memory without high-cost device customization, thereby expanding the applicable scenes and the range of the backboard system and the computing equipment. Furthermore, embodiments of the present disclosure may also enable efficient management of a backplane system comprising a plurality of backplanes.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces, in whole or in part, a flow or function according to embodiments of the present invention. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more sets of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a Solid State Disk (SSD).

Many modifications and other embodiments of the disclosure set forth herein will come to mind to one skilled in the art to which this disclosure pertains having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the embodiments of the disclosure are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the disclosure. Furthermore, while the foregoing description and related drawings describe example embodiments in the context of certain example combinations of components and/or functions, it should be appreciated that different combinations of components and/or functions may be provided by alternative embodiments without departing from the scope of the present disclosure. In this regard, for example, other combinations of different components and/or functions than those explicitly described above are also contemplated as being within the scope of the present disclosure. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A back panel system (100), comprising:

a plurality of backplates (110-1 … … 110-N) arranged to be stacked parallel to each other and spaced apart from each other, each backplate (110-1 … … 110-N) comprising:

A first port (111);

a second port (112) configured to be connected to a memory (200); and

a third port (113) configured to be connected to a memory controller (300); and

a flexible circuit member (120) connected to the first port (111) of each of the plurality of backplanes (110-1 … … 110-N), and the flexible circuit member (120) is configured to transmit signals between the plurality of backplanes (110-1 … … 110-N).

2. The backplate system (100) according to claim 1, further comprising:

at least one set of first indicator lights (130-1 … … -L) disposed on the flexible circuit member (120), each set of first indicator lights (130-1 … … -L) configured to indicate a status of a corresponding memory (200) of at least one memory (200) connected to the plurality of backplanes (110-1 … … 110-N) and adapted to be connected to a set of second indicator lights (220) located on a housing (210) of the corresponding memory via a light guiding stud.

3. The backplane system (100) of claim 2, wherein each set of first indicator lights (130-1 … … -L) comprises a plurality of first indicator lights, each first indicator light being disposed directly on a surface of the flexible circuit member (200).

4. The backplane system (100) of claim 3, wherein each backplane (110-1 … … 110-N) of the plurality of backplanes (110-1 … … 110-N) comprises a plurality of second ports (112) to form a plurality of columns of second ports on one side of the plurality of backplanes (110-1 … … 110-N),

wherein the flexible circuit member (120) comprises a plurality of first sections (122-1, 122-2) and second sections (123) interconnecting the plurality of first sections (122-1, 122-2), each first section (122-1, 122-2) being arranged adjacent to a corresponding column of second ports and extending in the direction of the plurality of back plane stacks, and

wherein each set of first indicator lights (130-1 … … 130-L) is arranged adjacent to a second port (112) for the corresponding memory.

5. The backplane system (100) of claim 4, wherein each backplane (110-1 … … 110-N) comprises at least one recess (114) to receive the flexible circuit member (120), each recess (114) being located between two adjacent second ports.

6. The back-plate system (100) according to claim 1, further comprising a support plate (121), the flexible circuit member (120) being fixed to a plate surface of the support plate (121).

7. The backplane system (100) of claim 1, wherein the plurality of backplanes (110-1 … …, 110-N) comprises a master backplane (110-1) and a slave backplane (110-2 … …, 110-N), the master backplane (110-1) being adapted to be connected to a baseboard management controller (400), the baseboard management controller (400) being configured to manage the master backplane (110-1) and to manage the slave backplane (110-2 … …, 110-N) via the master backplane (110-1).

8. The backplane system (100) of claim 7, wherein each backplane (110-1 … … 110-N) comprises a control unit (115) and a master-slave mode control terminal (bp_slot) interconnected to each other, the flexible circuit member (120) comprises a pull-down terminal and a floating terminal, and

wherein the master-slave mode control terminal (bp_slot) of the master back plate (110-1) is connected to one of the pull-down terminal and the floating terminal, and the master-slave mode control terminal (bp_slot) of the slave back plate (110-2 … … 110-N) is connected to the other of the pull-down terminal and the floating terminal.

9. The backplane system (100) of claim 8, wherein each backplane (110-1 … … 110-N) comprises: -a fourth port (119) connected to the control unit (115) and adapted to be connected to the baseboard management controller (400).

10. The backplane system (100) of claim 9, wherein each backplane (110-1 … … 110-N) further comprises: a first gating device (116) and a second gating device (117), each comprising a device connection, a first channel and a second channel, and being configured to connect the device connection to the first channel or the second channel based on a selection signal from the control unit (115),

wherein the device connection of the first gating device (116) is connected to the fourth port (119), the first channel of the first gating device (116) is connected to a firmware update interface (1152) of the control unit (115), and the second channel of the first gating device (116) is connected to a satellite management controller (1151) of the control unit (115); and is also provided with

Wherein the device connection of the second gating device (117) is connected to the first port (111), the first channel of the second gating device (117) is connected to the satellite management controller (1151), and the second channel of the second gating device (117) is connected to the device connection of the first gating device (116), the satellite management controller (1151) of the main backplane (110-1) is configured to forward firmware update data from the second channel of the first gating device (116) to the first channel of the second gating device (117).

11. The backplane system (100) according to claim 10, wherein the control unit (115) of the primary backplane (110-1) is configured to: in response to a firmware update to the primary backplane (110-1) itself, sending a select signal to a first gating device (116) of the primary backplane (110-1) to connect a device connection of the first gating device (116) to a first channel; and in response to a firmware update to the slave backplane (110-2 … … 110-N), issuing a selection signal to the first gating device (116) of the master backplane (110-1) to connect a device connection of the first gating device (116) to a second channel and issuing a selection signal to the second gating device (117) of the master backplane (110-1) to connect a device connection of the second gating device (117) to the first channel, and

wherein the control unit (115) of the slave backplate (110-2 … … 110-N) is configured to: -issuing a selection signal to the first gating device (116) of the slave backplane (110-2 … …, 110-N) to connect the device connection of the first gating device (116) to a first channel, and-issuing a selection signal to the second gating device (117) of the slave backplane (110-2 … …, 110-N) to connect the device connection of the second gating device (117) to a second channel.

12. The backplane system (100) according to claim 9, wherein in each backplane (110-1 … … 110-N) the fourth port (119) is connected via a data bus to a satellite management controller (1151) of the control unit (115), the satellite management controller (1151) is connected via its high-speed serial interface to the first port (111), and the satellite management controller (1151) is configured to obtain information about at least one of a memory state of the belonging backplane, a FRU of the backplane, and a sensed temperature of the backplane, and

wherein the satellite management controller (1151) of the master backplane (110-1) is further configured to provide the information of the master backplane (110-1) to the baseboard management controller (400) and to receive the information from the slave backplane (110-2 … … 110-N) and to provide the information to the baseboard management controller (400).

13. The backplane system (100) of claim 8, wherein the control unit (115) of each backplane (110-1 … … 110-N) is configured to control one or more sets of first indicator lights (130-1 … … 130-L) corresponding to that backplane.

14. The backplane system (100) of claim 1, wherein each backplane (110-1 … … 110-N) further comprises an expander (118), the expander (118) being adapted to expand the number of memories connected to the backplane.

15. A computing device comprising the backplane system of any of claims 1-14.

16. A management method for a computing device (1000) according to claim 15, comprising:

-managing, by the baseboard management controller (400), a master backplane (110-1) of a plurality of backplanes (110-1 … … 110-N), the baseboard management controller (400) being connected to the master backplane (110-1); and

the slave backplane (110-2 … … 110-N) of the plurality of backplanes (110-1 … … 110-N) is managed by the baseboard management controller (400) via the master backplane (110-1).

17. The management method according to claim 16, wherein the master-slave mode control terminal (bp_slot) of the master back plate (110-1) is connected to one of a pull-down terminal and a floating terminal of the flexible circuit member (120), and the master-slave mode control terminal (bp_slot) of the slave back plate (110-2 … … 110-N) is connected to the other of the pull-down terminal and the floating terminal of the flexible circuit member (120).

18. The management method of claim 16, wherein managing, by the baseboard management controller (400), a master backplane (110-1) of a plurality of backplanes (110-1 … … 110-N) comprises:

-issuing, by a control unit (115) of said main backplane (110-1), a selection signal to a first gating device (116) of said main backplane (110-1); and

providing firmware update data by a baseboard management controller (400) to a control unit (115) of the main backplane (110-1) via a first gating device (116) of the main backplane (110-1) to perform firmware update to the control unit (115) of the main backplane (110-1), and

wherein managing, by the baseboard management controller (400) via the master backplane (110-1), a slave backplane (110-2 … … 110-N) of a plurality of backplanes (110-1 … … 110-N) comprises:

-issuing, by a control unit (115) of said main back plate (110-1), a selection signal to a first gating device (116) and a second gating device (117) of said main back plate (110-1);

-issuing, by the control unit (115) of the slave backplate (110-2 … … 110-N), a selection signal to the first gating device (116) and the second gating device (117) of the slave backplate (110-2 … … -N); and

firmware update data is provided by a baseboard management controller (400) to a control unit (115) of the slave backplane (110-2 … … 110-N) via a first gating device (116), a control unit (115), and a second gating device (117) of the master backplane (110-1), a flexible circuit member (120), and the second gating device (117) and the first gating device (116) of the slave backplane (110-2 … … 110-N) to firmware update the control unit (115) of the slave backplane (110-2 … … 110-N).

19. The method of managing according to claim 16, wherein managing, by the baseboard management controller (400), a master backplane (110-1) of a plurality of backplanes (110-1 … … 110-N) comprises:

acquiring, by a control unit (115) of the primary backplane (110-1), information about at least one of a memory state, a FRU of a backplane, and a sensed temperature of a backplane of the primary backplane (110-1); and

forwarding the acquired information to the baseboard management controller (400) by the control unit (115) of the main backboard (110-1), and

wherein managing, by the baseboard management controller (400) via the master backplane (110-1), a slave backplane (110-2 … … 110-N) of a plurality of backplanes (110-1 … … 110-N) includes

Obtaining, by each of the slave backplanes (110-2 … … 110-N), information pertaining to at least one of a memory state, a FRU of the slave backplate, and a sensed temperature of the backplate by a control unit (115) of the slave backplate; and

the acquired information is forwarded by the control unit (115) of the slave backplane (110-2 … … 110-N) to the baseboard management controller (400) via the control unit (115) of the master backplane (110-1).