CN1176440A - Method of realizing parallel access of neighborhood image data and neighborhood image frame memory - Google Patents
Method of realizing parallel access of neighborhood image data and neighborhood image frame memory Download PDFInfo
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Abstract
The present invention belongs to superhigh speed image processing method. In the present invention, memory array comprising memory chips with independent address lines and data lines, two-way multiplexer, address mapping circuit, sorting circuit and control circuit constitute the neighborhood image frame memory so as to realize parallel access of neighborhood image data and increase greatly transmission rate of image data.
Description
The invention belongs to the digital image processing field of broad sense, particularly the hypervelocity method of picture processing.
Target following militarily, in real-time online Image Detection and in the image analysis of many high speeds measures, usually require superfast image processing, for reaching the requirement of hypervelocity image processing, for a long time, the researchist in this field mainly concentrates on notice in the research of hardware processor, and most hardware processor adopts dsp chip, with getting the more TMS320 family chip that American TI Company is arranged and the A100 of Britain INMOS company, the A110 chip, in order to improve processing speed, go all out to improve the performance of dsp chip on the one hand, also adopt simultaneously a plurality of dsp chip parallel processings, structurally, some Processing Structure have also been adopted, a plurality of CPU parallel processings of the also employing that has such as SYSTOLIC, so all, often spent expensive cost and produced little effect.Trace it to its cause, its crux is at the tissue of pictorial data.Because all relating to image neighbourhood, handle many algorithms of image processing, effectively provide the neighborhood pictorial data to hardware processor at a high speed in time, accomplish that data parallel, processing walk abreast, so that reach real parallel image processing, this is only the key point of hypervelocity image processing.Current digital image processing system, the data stream of its picture frame memory bank have two kinds of forms substantially: the single-point and the data organization form of single file at random in proper order.Video image in order single file deposit that picture frame is deposited in or in order single file deposit from picture frame and read video image successively, in order to realize real-time process of convolution, some dsp chips are built-in SRAM storer (as the A110 chip) also adopts method that row postpones to form the needed pictorial data of process of convolution, and this method limitation is big, complex time and can not realize the access of random neighborhood pictorial data.
The objective of the invention is at present picture frame deposit data structure dumb, do not satisfy the weak point of the multiple needs of hypervelocity image processing, the structure of neighborhood picture frame memory bank has been proposed, thereby realized the parallel access of neighborhood pictorial data in neighborhood picture frame memory bank, and greatly improved the pictorial data transfer rate.
The adjacent region data that the present invention refers to comprises the adjacent region data (minimum 2 points that should comprise adjacent two row and adjacent column) of adjacent two row or row order adjacent region data more than adjacent two row (minimum 2 points that should comprise adjacent two row and adjacent column) and random address.
The present invention proposes a kind of method of M*N neighborhood pictorial data access of going order, it is characterized in that, may further comprise the steps:
1). determine that pending image neighbourhood is of a size of M*N, M is row, and N is row, M 〉=2, N 〉=1.
2). with the individual neighborhood picture frame memory bank of L/D (D 〉=1), realize M*1 adjacent region data of primary access operation parallel access with parallel access L*1 structure of storage chip formation of independent address lines and data line, wherein, L=2
b, b 〉=1, L satisfies 2
B-1The condition of≤M≤L.
3). the determined storage unit in each address of storage chip is deposited D image pixel (D 〉=1), deposits image pixel in different storage chip respectively, and its storage rule is:
The row address of image pixel is L*I+K
I=0 wherein, 1,2,3, K=0,1,2 ... (L-1)/D
With row address is that the image pixel of L*I+K deposits the K storage chip in.
4). when pictorial data deposits this storage array in, then come the sequential of writing of control store chip with the numerical value of K, the mask word so that the arrangement of D comes the control store chip reaches the purpose that writes correct data with this.
5). when pictorial data was read this storage array, a read operation parallel read-out comprised the capable adjacent region data of M*1 adjacent lines, and the time sequential routine of each chip is identical.
6). when this storage chip of pictorial data parallel read-out, for each I that determines, if the line number of the adjacent region data that is taken out all is in the L*I+K scope, then the row address of each storage chip all is identical, is I; If the line number of the adjacent region data that is taken out not all is in the L*I+K scope, the row address that then is in the storage chip in the L*I+K scope is I, and the row address that is not in the storage chip in the L*I+K scope is I+1.
7). be connected to the data sorting circuit that the data to memory chip output sort at the data output end of video memory array, to form correct row order adjacent region data.After the data sorting circuit, be connected to M*N data latch, formed parallel M*N neighborhood pictorial data thus.
2. the method for M*N random neighborhood pictorial data access:
1). determine that pending image neighbourhood is of a size of M*N, M is row, and N is row, M 〉=2, N 〉=1.
2). with the individual storage chip with independent address lines and data line of (H/C) * (W/D) constitute a parallel access W*H structure neighborhood picture frame memory bank.Realize primary access operation parallel access M*N adjacent region data, wherein H=2
b, b 〉=1, H satisfies 2
B-1The condition of≤M≤H ,=2
b, b 〉=1 satisfies 2
B-1The condition of≤M≤W (C 〉=1, D 〉=1).
3). the determined storage unit in each address of storage chip is deposited C*D (C is row, and D is row) image pixel, deposits image pixel in different storage chip respectively, and its storage rule is as follows:
The row address of image pixel is H*I+K
I=0 wherein, 1,2,3, K=0,1,2 ... (H-1)/C
The column address of image pixel is W*J+F
J=0 wherein, 1,2,3, F=0,1,2 ... (W-1)/D
With row address is that H*I+K and column address are that the image pixel of W*J+F deposits in the storage chip that label is KF.
4). when pictorial data deposited this storage array in, then with the sequential of writing of the numerical value rice control store chip of K, the mask word with the arrangement control store chip of C and D reached the purpose that writes correct data with this.
5). when pictorial data was read this storage array, a read operation parallel read-out comprised the capable adjacent region data of a plurality of adjacent lines, and the time sequential routine of each chip is identical.
6). when this storage array of pictorial data parallel read-out, for each I that determines, if the line number of the adjacent region data that is taken out all is in the H*I+K scope, then the row address of each storage chip all is identical, is I; If the line number of the adjacent region data that is taken out not all is in the H*I+K scope, the row address that then is in the storage chip in the H*I+K scope is I, and the row address that is not in the storage chip in the H*I+K scope is I+1.And for each J that determines, if the columns of the adjacent region data that is taken out all is in the W*J+F scope, then the row address of each storage chip all is identical, is J; If the line number of the adjacent region data that is taken out not all is in the W*J+F scope, the column address that then is in the storage chip in the W*J+F scope is J, and the row address that is not in the storage chip in the W*J+F scope is J+1.
7). be connected to the data sorting circuit that the data to storer output sort at the data output end of video memory array, to form correct row order adjacent region data.After the data sorting circuit, be connected to M*N data latch, formed parallel M*N neighborhood pictorial data thus.
The field picture frame memory bank of realization field image parallel access, it is characterized in that by a plurality of independent address lines, the storage array that the storage chip of data line constitutes, pictorial data is imported, is exported the two-way multi-way switch of each storage chip in the said storage array respectively, storage unit is carried out the address translation circuit of neighborhood addressing, to the ranking circuit that output data sorts, provide the read-write sequence control circuit of correct sequential to reading and writing data.
A data mode of the present invention such as a following M group:
Group 1: a kind of (" O " represents data, down together) in the N kind adjacent region data in single job access two adjacent lines
J J J+1 J J+1?J+2 J J+1 J+2 J+N-1
The Lie Lielielielielielielie row
The capable O O of the capable O I of I capable O O I O ... the capable O O of I O ... O
The capable O O of the capable O I+1 of I+1 capable O O I+1 O ... the capable O O of I+1 O ... O
(1) (2) (3) (N)
Group 2: a kind of in the N kind adjacent region data in single job access three adjacent lines
J J J+1 J J+1?J+2 J J+1?J+2 J+N-1
The Lie Lielielielielielielie row
The capable O O of the capable O I of I capable O O I O ... the capable O O of I O ... O
The capable O O of the capable O I+1 of I+1 capable O O I+1 O ... the capable O O of I+1 O ... O
The capable O O of the capable O I+2 of I+2 capable O O I+2 O ... the capable O O of I+2 O ... O
(1) (2) (3) (N)
Group M: the capable O O of a kind of J J J+1 J J+1 J+2 J J+1 J+2 J+N-1 Lie Lielielielielielielie row row I capable O I capable O O I O in the N kind adjacent region data in the once-through operation access M adjacent lines ... the capable O O of I O ... the capable O O of the capable O I+1 of OI+1 capable O O I+1 O ... the capable O O of I+1 O ... the capable O O of the capable O I+2 of OI+2 capable O O I+2 O ... the capable O O of I+2 O ... the capable O O of O I+M capable O I+M capable O O I+M O ... the capable O O of I+M O ... O (1) (2) (3) (N)
A read operation cycle in a neighborhood picture frame memory bank, write cycles, one are read the FI and the FO operating cycle of writing transmission operating cycle, a fifo chip of reading to transmit operating cycle, a VRAM that rewriting operation cycle, a page read operation cycle, a page write cycles, a page read rewriting operation cycle, a VRAM, one of the sam port of/VRAM chip seals in and goes here and there out the operating cycle, reads or write the adjacent region data of following type simultaneously:
(I). the row order adjacent region data (minimum 2 points that should comprise adjacent two row and adjacent column) that adjacent two row or adjacent two row are above.
This class data characteristic is: in neighborhood picture frame memory bank, the data of each access can be the adjacent region datas of arbitrary address, but adjacent twice with generic operation in, the data of its access must be go together mutually or adjacent lines (then being adjacent two row during staggered scanning);
(II). the adjacent region data of random address (minimum 2 points that should comprise adjacent two row and adjacent column),
This class data characteristic is: in neighborhood picture frame memory bank, the data of each access can be the adjacent region datas of arbitrary address, adjacent twice with generic operation in, its rank addresses can be different.Its data mode is one or more in M the group of the above row order adjacent region data of adjacent two row shown in M group or adjacent two row as above.
The adjacent region data of neighborhood picture frame memory bank of the present invention access can be many bit on pixel bit bit length, this class adjacent region data belongs to many gray scale images (abbreviating gray scale image as) and true colour imagery adjacent region data, this class neighborhood picture frame memory bank is referred to as gray scale neighborhood picture frame memory bank, the adjacent region data of above-mentioned neighborhood picture frame memory bank access can be 1bit on pixel bit bit length, and this class neighborhood picture frame memory bank is called two-value neighborhood picture frame memory bank.
Neighborhood picture frame memory bank structurally is divided into complete address structure and incomplete address structure neighborhood picture frame memory bank, so-called address structure neighborhood picture frame memory bank fully, be meant the corresponding image pixel (no matter being many-valued neighborhood picture frame memory bank or two-value neighborhood picture frame memory bank) of storage unit of each neighborhood picture frame memory bank, that is to say that the memory unit address of the storage chip of neighborhood picture frame memory bank and image pixel are one to one under this structure.It is the situation of D=1 in the said method.So-called not exclusively address structure neighborhood picture frame memory bank, be meant the corresponding two or more image pixels (no matter being many-valued neighborhood picture frame memory bank or two-value neighborhood picture frame memory bank) of storage unit of a neighborhood picture frame memory bank, that is to say, the memory unit address of the storage chip of neighborhood picture frame memory bank and image pixel are not one to one under this structure, life is corresponding two image pixels, the i.e. situation of D in the said method＞1 of the memory unit address of a storage chip less.For example constitute many gray scales neighborhood picture frame memory bank of 8bit word length with the storage chip of 16bit word length, can be structured to the neighborhood storage of corresponding two image pixels of memory unit address of a storage chip, its structure as shown in Figure 2, constitute the two-value neighborhood picture frame memory bank of 1bit word length for another example with the storage chip of 4bit word length, can be structured to the neighborhood storage of corresponding four image pixels of memory unit address of a storage chip, its structure as shown in Figure 3.
In the structure neighborhood picture frame memory bank of incomplete address, the address capability of the storage chip in the neighborhood picture frame memory bank can be less than a width of cloth digital image pixel number, and the bit quantity of each storage unit of the storage chip in the neighborhood picture frame memory bank is necessarily greater than the bit number of the single pixel of image.
The present invention has following characteristics:
1. can constitute the neighborhood picture frame memory bank of 2*2,3*3,4*4,8*8 and even bigger random neighborhood data, and can be in the random neighborhood data more than the access of single memory bank store access cycle.
2. can form adjacent 2 row multiple rows, 3 row multiple rows, 4 row multiple rows and even bigger row order adjacent region data and can in up to the time of 33ns, obtain above row adjacent region data in proper order.
3. mix circuit such as A/D circuit, interface circuit, neighborhood hardware handles, connect equipment and corresponding softwares such as microcomputer (or single-chip microcomputer, dsp chip), video camera, constitute various High Speed Systems.
Brief Description Of Drawings:
Fig. 1 is the block diagram of neighborhood picture frame memory bank.
Fig. 2 is the storage unit of a storage chip.
Fig. 3 is corresponding four image pixels of the memory unit address of a storage chip.
Fig. 4. being connected of example 1 address bus and data bus.
Fig. 5. example 1 pictorial data is stored in the position in the storage chip.
Fig. 6. the 4*4 adjacent region data of reading is arranged.
Fig. 7. constitute the neighborhood picture frame memory bank of the row order adjacent region data of adjacent two row with the 256K*4bitVRAM chip.
Fig. 8. being connected of the address bus of example 2 and data bus.
Fig. 9. the pictorial data of example 2 is stored in the position in the storage chip.
Figure 10. constitute the two-value random neighborhood picture frame memory bank of 3*3 adjacent region data with the 256K*4bitVRAM chip.
Figure 11. the image neighbourhood frame is deposited four kinds of data modes of support
The present invention proposes two neighborhood picture frame bank structure that realize field pictorial data parallel access, shown in Fig. 4～14, is described with reference to the accompanying drawings as follows:
Being connected as shown in Figure 4 of this bank-address bus and data bus, pictorial data be stored in the storage chip the position as shown in Figure 5.
As can be seen from Figure 4, each storage chip all has oneself independently address wire (AN) and data line (DN), 16 independently storage chip constituted the neighborhood picture frame storage array of a 4*4 neighborhood, can finish the parallel access of 4*4 adjacent region data.In Fig. 5, " O " represents each pictorial data, the sequence number of the storage chip that this pictorial data is positioned is indicated in its below, top line is indicated the column address of the pictorial data of each storage chip correspondence among the figure, one of left side row are indicated the row address of the pictorial data of each storage chip correspondence, the 4*4 data neighborhood at random of a box indicating among the figure among the figure.In given pictorial data was stored in position in the storage chip, we can see, each pictorial data is stored in the neighborhood picture frame memory bank shown in Figure 4, and its address is made up of two parts: plot+offset address.In neighborhood access each time, the row address of the pictorial data of each storage chip correspondence is designated as A ' H, then:
A′
H＝4(N+M)+K ······ (1)
In the formula, 4 (N+M) part is a plot, and K is an offset address, M=0,1, K=0,1,2,3.
In like manner, in neighborhood access each time, the column address of the pictorial data of each storage chip correspondence is designated as A '
v, then:
A′
v＝4(J+I)+L ······ (2)
In the formula, 4 (J+I) part is a plot, and L is an offset address, I=0,1, L=0,1,2,3.
The address of delivering to 16 storage chips is the plot of pictorial data, the actual address of 16 storage chips and pictorial data address are different, neighborhood picture frame memory bank at 4*4 neighborhood shown in Figure 4, the plot of pictorial data row address moves to right two and then is the row address of storage chip, in like manner the plot of pictorial data column address moves to right two and then is the column address of storage chip, so, in neighborhood access each time, the row address of each storage chip is designated as AH, then:
A
H＝N+M ······ (3)
In the formula, M=0,1.
In like manner, in neighborhood access each time, the column address of each storage chip is designated as AV, then:
A
v＝J+I ······ (4)
In the formula, I=0,1.
In neighborhood access each time, 16 storage chip address (A1～A16) not necessarily identical separately independently, with the 4*4 data neighborhood that square frame was comprised among Fig. 5 is example, 16 vertex neighborhood data by from a left side to from top to bottom series arrangement, the chip of its storage should be in proper order: T6, T7, T4, T5, T10, T11, T8, T9, T14, T15, T12, T13, T2, T3, T1, T2, as can be seen, in neighborhood access this time, the M=1 of the row address of T4, T5, T8, T9, T12, T13, T0, T1 storage chip, the M=0 of the row address of other storage chip.In like manner, in neighborhood access this time, the M=1 of the column address of T2, T3, T0, T1 storage chip, the M=0 of the column address of other storage chip.From this example as can be seen, a neighborhood picture frame memory bank must carry out address arithmetic, that is to say to be provided with totalizer, carry out the computing of formula 3, formula 4.
On the other hand, in when the parallel read-out operation of adjacent region data, need the data of being read be sorted, so that obtaining with the upper left corner is the 4*4 data neighborhood of order of starting point, among Fig. 4 16 independently the data line exported separately of storage chip be respectively D0～D15, wherein one group of data line is represented with DN, and correct 4*4 adjacent region data line is respectively D0 '～D15 ', put in order as shown in Figure 6, wherein one group of data line is represented with D ' N, one group of data line of 4*4 data neighborhood upper left corner starting point represents with D0 ', then: arrange
D′0＝DN ······ (5)
N=4*I+M in the formula
Obtained after the storage chip number of D ' 0 correspondence, counted the storage chip number that I, M can extrapolate D ' N correspondence by the ranks plot.Fig. 5 pictorial data that explained in precise term is stored in position in the storage chip, can obtain the address mapping and the data sorting of the neighborhood picture frame memory bank of 4*4 neighborhood thus.The neighborhood picture frame memory bank of 4*4 neighborhood shown in Figure 4 can be the neighborhood picture frame memory bank of many bit, also can be the neighborhood picture frame memory bank of two-value, and this will see the bit length of the storage chip that each independent frame of formation is deposited.
Example 1: constitute the 1st group (2) with the VRAM chip and plant the neighborhood picture frame memory bank of adjacent region data (word length is 8bit) and adopt address structure completely.Utilize the SAM quick port of this chip to read the neighborhood pictorial data, can obtain the row order adjacent region data of adjacent two row, thereby real-time robet algorithm, the two-value of realization TV cut apart and statistics with histogram.The circuit block diagram of this neighborhood picture frame memory bank as shown in Figure 7.
Among the figure, T0～T3 is four VRAM storage chips, can select the TC524256BZ-80VRAM storage chip of Toshiba Corp for use, in order to simplify circuit, selected the TMS34010 chip of American TI Company for use, this chipset computer interface, synchronous sequence produce, frame deposits that sequential forms and hardware handles, use more convenient.The VRAM storage chip divides DRAM port and sam port, in this structure, the computer access frame is deposited, used the DRAM port of VRAM storage chip, at this moment data channel comprises that bi-directional data drives (1), TMS34010, bi-directional data drives (2), wherein high four figures is according to (MD4～MD7), low four figures is according to (MD0～MD3) on the DRAM data line of linking T1, T3 storage chip on the DRAM data line of linking T0, T2 storage chip.Fireballing A/D, D/A and hardware handles are then used the sam port of VRAM storage chip, as shown in the figure, the data line of four sam ports is respectively OD0～OD3, OD4～OD7, OD8～OD11, OD12～OD15, these data lines are linked two-way multi-way switch, the video image that video camera comes forms the data of AD0～AD7 and also delivers to two-way multi-way switch after the A/D conversion, when image acquisition, can deposit the video image data of numeral in the memory bank in.Two-way multi-way switch is exported three circuit-switched data, one the tunnel delivers to D/A goes as video data (DA0～DA7), two-way is delivered to ranking circuit in addition, and the effect of ranking circuit is to export 2 data exactly, makes the row address on this road of D0 always lack 1 than the row address on this road of D1.Then through same the latching of two-stage, latch pulse is VCLK, each grade latch can be made of two 74LS374, and pictorial data (1D0～1D7,2D0～2D7,3D0～3D7,4D0～4D7), the adjacent region data that provides the Robet algorithm to need of the 2*2 neighborhood of row order is provided thus.The address of memory bank is divided into two-way, T0, T1 use one tunnel address (A1), T2, T3 use another address, road (A2), the pictorial data of T0, T1 memory chip stores even number line, the pictorial data of T2, T3 memory chip stores odd-numbered line, in address converter, be provided with totalizer,, automatically export the two-way address in the address converter according to the first location of current access.Timing sequencer provides storage chip needed all sequential, this sequential is divided into two-way, one the tunnel gives T0, T1 storage chip, and T2, T3 storage chip are given in another road, this two paths of signals all comprise the VRAM chip needed/RAS ,/CAS ,/WE ,/OE ,/SOE and SC signal.The synchronous sequence that also generation system of TMS34010 chip uses, comprise row synchronously, field synchronization and composite blanking signal.Too many or too much for use full address structure of example 2. realizes the two-value neighborhood picture frame memory bank of 3*3 neighborhood.
Here the bit number of selecting each storage unit of storage chip for use is 4bit, being connected as shown in Figure 8 of this bank-address bus and data bus, pictorial data be stored in the storage chip the position as shown in Figure 9.
The structure of example 2 is different with the structure of example 1, example 1 is the neighborhood picture frame memory bank of the 4*4 neighborhood that is made of complete address, each image pixel is a storage unit of a corresponding storage chip all, in order to constitute the neighborhood picture frame storage of 4*4 neighborhood, at least need 16 storage chips, and 2 li of examples, respectively corresponding four pixels of four bit of a storage unit of a storage chip, in order to constitute the conditional two-value neighborhood picture frame memory bank of incomplete 4*4 neighborhood, then only need four storage chips, this miraculous minimizing will make the two-value neighborhood picture frame memory bank of big neighborhood be easy to realize.Here why be called conditional two-value neighborhood picture frame memory bank, be meant in storage organization shown in Figure 8, if the neighborhood of random access 4*4, the rank addresses of the first location of its image pixel must be an even number all, and Here it is is called the cause of conditional two-value neighborhood picture frame memory bank.But, by the two-value neighborhood picture frame memory bank that storage organization shown in Figure 8 forms, can become the two-value neighborhood picture frame memory bank of 3*3 neighborhood, the rank addresses of the first location of its image pixel is no longer limited.The 3*3 neighborhood that solid box among Fig. 9 is surrounded is exactly a 3*3 neighborhood at random.Similar with example 1, example 2 also has the problem of the data sorting of address mapping, no longer superfluous here chatting.
Example 2: realize the function of example (2) with the VRAM chip, the full address structure of promptly toing many or too much for use realizes the two-value neighborhood picture frame memory bank of 3*3 neighborhood, and the circuit block diagram of this neighborhood picture frame memory bank as shown in figure 10.
Among the figure, T0～T3 is four VRAM storage chips, can select the TC524258BZ-80VRAM storage chip of Toshiba Corp for use, its capacity is 256K*4bit, the storage organization that this two-value neighborhood picture frame memory bank adopts Fig. 8 to use, its pictorial data is stored in the position in the storage chip, also as shown in Figure 9.1bit binary image data FD0 at a high speed writes the SAM of VRAM chip according to video rate by multi-way switch, then through writing the transmission operation, by data structure shown in Figure 9, deposit the storage chip of T0～T3 in, the address wire of these four storage chips, data line (comprises the DRAM port, sam port) all be independently, address converter has provided four tunnel address A0～A3 independently, be added to respectively on the address wire of T0～T3 storage chip, the 3*3 adjacent region data is to form through ranking circuit after reading from the DRAM port of VRAM chip again, 3*3 adjacent region data as the solid line wicket among Fig. 9, order is for from left to right, from the top down, data are designated as LD0～LD8 successively, the 3*3 adjacent region data is the adjacent region data on any random address, as long as a given address, just can read with this address is the 3*3 adjacent region data at center, this storage organization, follow the tracks of on the border that is particularly suitable for chain construction, because this algorithm is exactly the 3*3 adjacent region data that needs on the random address.Certainly, this example also can obtain the adjacent region data of 4*4, but the rank addresses of the starting point of the adjacent region data of 4*4 (upper left point) must be an even number.The argumentation such as the example 1 of other parts of this example (as TMS34010 etc.).
Neighborhood picture frame memory bank has solved the problem of the parallel access of M*N image neighbourhood effectively, that is to say, can realize the parallel access of M*N image neighbourhood in an accessing operation of memory bank the cycle, theoretically, the value of M and N can be very big, this shows that its access efficiency is very high.For instance, in example 1, if constitute with VRAM complete address structure the 4*4 neighborhood neighborhood picture frame memory bank and adopt the SAM quick port of VRAM chip, can accomplish in the time of 40ns, to obtain simultaneously the image neighbourhood data of 16 8bit (even more bit), at this moment data throughput is equivalent to 40 times (data transmission rates that promptly are equivalent to 16MBYTE/S) of real-time video pictorial data transfer rate, if constitute the neighborhood picture frame memory bank of bigger image neighbourhood, its data transmission frequency is surprisingly high especially.For another example 2 li of examples, if constitute with VRAM incomplete address structure the 3*3 neighborhood two-value neighborhood picture frame memory bank and adopt the DRAM port of VRAM chip, can carry out reading of 3*3 random neighborhood image like this, thus and then realize that the border of the chain construction of hardware follows the tracks of, the high speed tracking velocity that is reached thus is that other hardware and software method is inaccessible at present.As seen, adopt neighborhood picture frame memory bank to constitute image processing system at a high speed, hardware processor will no longer be to wait for pictorial data, but be difficult in time handle neighborhood pictorial data the most at a high speed.
The image neighbourhood frame of structure of the present invention is deposited and is supported four kinds of data modes, as shown in figure 11, wherein scheme (a), (b) two kinds of data modes are data modes that conventional picture frame is deposited normal use, data mode shown in the figure (a) also comprises the data mode of depositing the identical point of access simultaneously from two independent frames, data mode shown in the figure (b) also comprises from two independent frames deposits the data mode that access is simultaneously gone together mutually, and scheme (c), figure (d) then is the particular data form that the image neighbourhood frame is deposited, and also comprises the data mode of depositing the while access identical point neighborhood and the neighborhood of going together mutually from two independent image neighbourhood frames certainly.
The two-value neighborhood picture frame memory bank of incomplete address structure that is noted that similar example 1 has important effect in the image processing of two-value neighborhood; The neighborhood picture frame memory bank of the capable order of the multirow of similar example 2 adjacent region data has important effect in the image processing of many gray scales neighborhood.
The present invention has solved the problem of the parallel access of M*N image neighbourhood effectively, that is to say, can realize the parallel access of M*N image neighbourhood in an accessing operation of memory bank the cycle, theoretically, the value of M and N can be very big, this shows, its access efficiency is very high.For instance, from example 1, if constitute with VRAM complete address structure the 4*4 neighborhood neighborhood picture frame memory bank and adopt the SAM quick port of VRAM chip, can accomplish in the time of 40ns, to obtain simultaneously the image neighbourhood data of 16 8bit (even more bit), at this moment data throughput is equivalent to 40 times (data transmission rates that promptly are equivalent to 16MBYTE/S) of real-time video pictorial data transfer rate, if constitute the neighborhood picture frame memory bank of bigger image neighbourhood, its data transmission frequency is surprisingly high especially.For another example 2 li of examples, if constitute with VRAM incomplete address structure the 3*3 neighborhood two-value neighborhood picture frame memory bank and adopt the DRAM port of VRAM chip, can carry out reading of 3*3 random neighborhood image like this, thus and then realize that the border of the chain construction of hardware follows the tracks of, the high speed tracking velocity that is reached thus is that other hardware approach is inaccessible at present.As seen, adopt neighborhood picture frame memory bank to constitute image processing system at a high speed, hardware processor will no longer be to wait for pictorial data, but be difficult in time handle neighborhood pictorial data the most at a high speed.
Claims (3)
1, the present invention proposes a kind of method of M*N neighborhood pictorial data access of going order, it is characterized in that, may further comprise the steps:
1). determine that pending image neighbourhood is of a size of M*N, M is row, and N is row, M 〉=2, N 〉=1.
2). with the individual neighborhood picture frame memory bank of L/D (D 〉=1), realize M*1 adjacent region data of primary access operation parallel access with parallel access L*1 structure of storage chip formation of independent address lines and data line, wherein, L=2
b, b 〉=1, L satisfies 2
B-1The condition of≤M≤L.
3). the determined storage unit in each address of storage chip is deposited D image pixel (D 〉=1), deposits image pixel in different storage chip respectively, and its storage rule is: the row address of image pixel is L*I+K
I=0 wherein, 1,2,3, K=0,1,2 ... (L-1)/D
With row address is that the image pixel of L*I+K deposits the K storage chip in.
4). when pictorial data deposits this storage array in, then come the sequential of writing of control store chip with the numerical value of K, the mask word so that the arrangement of J comes the control store chip reaches the purpose that writes correct data with this.
5). when pictorial data was read this storage array, a read operation parallel read-out comprised the capable adjacent region data of M*I adjacent lines, and the time sequential routine of each chip is identical.
6). when this storage array of pictorial data parallel read-out, for each I that determines, if the line number of the adjacent region data that is taken out all is in the L*I+M scope, then the row address of each storage chip all is identical, is I; If the line number of the adjacent region data that is taken out not all is in the L*I+M scope, the row address that then is in the storage chip in the L*I+M scope is I, and the row address that is not in the storage chip in the L*I+M scope is I+1.
7). be connected to the data sorting circuit that the data to memory array output sort at the data output end of video memory array, to form correct row order adjacent region data.After the data sorting circuit, be connected to M*N data latch, formed parallel M*N neighborhood pictorial data thus.
2. the method for M*N random neighborhood pictorial data access:
1). determine that pending image neighbourhood is of a size of M*N, M is row, and N is row, M 〉=2, N 〉=1.
2). with the individual storage chip with independent address lines and data line of (H/C) * (W/D) constitute a parallel access W*H structure neighborhood picture frame memory bank.Realize primary access operation parallel access M*N adjacent region data, wherein H=2
b, b 〉=1, H satisfies 2
B-1The condition of≤M≤H ,=2
b, b 〉=1 satisfies 2
B-1The condition of≤M≤W (C 〉=1, D 〉=1).
3). the determined storage unit in each address of storage chip is deposited C*D (C is row, D) is row) image pixel, deposits image pixel in different storage chip respectively, and its storage rule is as follows:
The row address of image pixel is H*I+K
I=0 wherein, 1,2,3, K=0,1,2 ... (H-1)/C
The column address of image pixel is W*J+F
J=0 wherein, 1,2,3, F=0,1,2 ... (W-1)/D
With row address is that H*I+K and column address are that the image pixel of W*J+F deposits in the storage chip that label is KF.
4). when pictorial data deposits this storage array in, then come the sequential of writing of control store chip with the numerical value of K, the mask word with the arrangement control store chip of C and D reaches the purpose that writes correct data with this.
5). when pictorial data was read this storage array, a read operation parallel read-out comprised the capable adjacent region data of a plurality of adjacent lines, and the time sequential routine of each chip is identical.
6). when this storage array of pictorial data parallel read-out, for each I that determines, if the line number of the adjacent region data that is taken out all is in the H*I+K scope, then the row address of each storage chip all is identical, is I; If the line number of the adjacent region data that is taken out not all is in the H*I+K scope, the row address that then is in the storage chip in the H*I+K scope is I, and the row address that is not in the storage chip in the H*I+K scope is I+1.And for each J that determines, if the columns of neighbour who is taken out or data all is in the W*J+F scope, then the row address of each storage chip all is identical, is J; If the line number of the adjacent region data that is taken out not all is in the W*J+F scope, the column address that then is in the storage chip in the W*J+F scope is J, and the row address that is not in the storage chip in the W*J+F scope is J+1.
7). be connected to the data sorting circuit that the data to memory array output sort at the data output end of video memory array, to form correct row order adjacent region data.After the data sorting circuit, be connected to M*N data latch, formed parallel M*N neighborhood pictorial data thus.
3, the field picture frame memory bank of realization field image parallel access, it is characterized in that by a plurality of independent address lines, the storage array that the storage chip of data line constitutes, pictorial data is imported, is exported the two-way multi-way switch of each storage chip in the said storage array respectively, storage unit is carried out the address translation circuit of field addressing, to the ranking circuit that output data sorts, provide the read-write sequence control circuit of correct sequential to reading and writing data.
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| Application Number | Priority Date | Filing Date | Title |
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| CN97112577A CN1081368C (en) | 1997-06-27 | 1997-06-27 | Method of realizing parallel access of neighborhood image data and neighborhood image frame memory |
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| CN97112577A CN1081368C (en) | 1997-06-27 | 1997-06-27 | Method of realizing parallel access of neighborhood image data and neighborhood image frame memory |
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| CN1081368C CN1081368C (en) | 2002-03-20 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297939C (en) * | 2001-12-12 | 2007-01-31 | 索尼公司 | Image processing apparatus and method thereof |
| CN101159061B (en) * | 2007-11-16 | 2010-04-21 | 清华大学 | Great neighborhood image parallel processing method |
| CN101388110B (en) * | 2008-10-31 | 2011-08-17 | 深圳市同洲电子股份有限公司 | Data rapidly-reading method and apparatus |
| CN112098770A (en) * | 2020-08-20 | 2020-12-18 | 深圳市宏旺微电子有限公司 | Test method and device for simulating extreme environment aiming at dynamic coupling fault |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1010437B (en) * | 1988-06-02 | 1990-11-14 | 清华大学 | real-time image neighborhood processor |
| DE69619586T2 (en) * | 1995-05-18 | 2002-09-05 | Canon K.K., Tokio/Tokyo | Image processing method and apparatus |
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1997
- 1997-06-27 CN CN97112577A patent/CN1081368C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297939C (en) * | 2001-12-12 | 2007-01-31 | 索尼公司 | Image processing apparatus and method thereof |
| CN101159061B (en) * | 2007-11-16 | 2010-04-21 | 清华大学 | Great neighborhood image parallel processing method |
| CN101388110B (en) * | 2008-10-31 | 2011-08-17 | 深圳市同洲电子股份有限公司 | Data rapidly-reading method and apparatus |
| CN112098770A (en) * | 2020-08-20 | 2020-12-18 | 深圳市宏旺微电子有限公司 | Test method and device for simulating extreme environment aiming at dynamic coupling fault |
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| CN1081368C (en) | 2002-03-20 |
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