CN117639817A

CN117639817A - Wake-up receiver

Info

Publication number: CN117639817A
Application number: CN202311095223.6A
Authority: CN
Inventors: 达尔尚·巴斯卡尔·谢蒂; 克里斯托夫·斯特凡; 杰拉尔德·霍尔韦格
Original assignee: Cypress Semiconductor Corp
Current assignee: Cypress Semiconductor Corp
Priority date: 2022-08-30
Filing date: 2023-08-28
Publication date: 2024-03-01

Abstract

The invention provides a wake-up receiver. One or more devices, systems, and/or methods are provided. In examples of the technology presented herein, a wake-up receiver includes a power management unit configured to receive a supply voltage generated from an input signal and to generate a current reference. The envelope detector is configured to generate a signal corresponding to a transition in the input signal. The signal processing unit is configured to generate an interrupt signal in response to detecting an awake mode in a signal from the envelope detector. The envelope detector comprises a first diode compensated by a current reference.

Description

Wake-up receiver

Technical Field

The invention relates to a wake-up receiver, a system and a method.

Background

Low power networking devices, such as internet of things (IoT) devices, require energy efficiency. The vast network of battery operated low power IoT devices is limited by their battery usage. Application fields such as home automation require IoT devices operating in a random sparse event mode, which results in high power consumption due to the idle listening time of the transceiver.

Disclosure of Invention

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key factors or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

In examples of the technology presented herein, a wake-up receiver includes a power management unit configured to receive a supply voltage generated from an input signal and to generate a current reference. The envelope detector is configured to generate a signal corresponding to a transition in the input signal. The signal processing unit is configured to generate an interrupt signal in response to detecting an awake mode in a signal from the envelope detector. The envelope detector comprises a first diode compensated by a current reference.

In an example of the technology presented herein, a system includes: a radio frequency to direct current (RF-DC) converter configured to generate a supply voltage based on an RF input signal; a power management unit configured to receive a supply voltage and generate a current reference; and an envelope detector configured to generate a signal corresponding to a transition in the RF input signal, wherein the envelope detector comprises a first diode compensated by a current reference threshold and the RF-DC converter comprises a second diode compensated by the current reference threshold.

In an example of the technology presented herein, a system includes: the apparatus includes means for receiving a Radio Frequency (RF) input signal, means for harvesting energy from the RF input signal to generate a supply voltage, means for generating a current reference based on the supply voltage, means for generating a signal corresponding to a transition in the RF input signal using a first diode, and means for compensating a threshold of the first diode using the current reference.

In an example of the technology presented herein, a method includes: receiving a Radio Frequency (RF) input signal; collecting energy from the RF input signal to generate a supply voltage; generating a current reference based on the supply voltage; generating a signal corresponding to a transition in the RF input signal using a first diode; and compensating the threshold of the first diode using the current reference.

To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth certain illustrative aspects and implementations. These illustrative aspects and implementations are indicative of but a few of the various ways in which one or more aspects may be employed. Other aspects, advantages, and novel features of the disclosure will become apparent from the following detailed description when considered in conjunction with the drawings.

Drawings

Fig. 1 is a block diagram of a wake-up receiver (WuRX) according to some embodiments.

Fig. 2 is a circuit diagram of an RF-DC converter according to some embodiments.

Fig. 3 is a circuit diagram of an envelope detector according to some embodiments.

Fig. 4A is a diagram of a p-type threshold compensation diode according to some embodiments.

Fig. 4B is a diagram of a p-type rectifying transistor according to some embodiments.

Fig. 4C is a diagram of a p-type compensation transistor according to some embodiments.

Fig. 5A is a diagram of an n-type threshold compensation diode according to some embodiments.

Fig. 5B is a diagram of an n-type rectifying transistor according to some embodiments.

Fig. 5C is a diagram of an n-type compensation transistor according to some embodiments.

Fig. 6 is a diagram of a current reference cell according to some embodiments.

Fig. 7 and 8 are signal diagrams according to some embodiments.

Fig. 9 is a flowchart illustrating an example method for diode threshold compensation according to some embodiments.

Detailed Description

The claimed subject matter is now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. It may be evident, however, that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the claimed subject matter.

It should be understood that the following description of embodiments should not be taken in a limiting sense. The scope of the present disclosure is not intended to be limited to the embodiments or figures described below, which are to be regarded as illustrative only. The figures are to be regarded as schematic representations and the elements shown in the figures are not necessarily to scale. Rather, the various elements are represented such that their function and general purpose will be apparent to those skilled in the art.

All numerical values in the detailed description and claims herein are indicative of "about" or "approximately" modified and take into account experimental errors and variations that may be expected by one of ordinary skill in the art.

According to some embodiments, a wake-up receiver (WuRX) collects energy from a Radio Frequency (RF) signal and generates a Direct Current (DC) voltage for use by components of WuRX. WuRX includes an RF-DC converter for collecting energy and an envelope detector for detecting a wake-up signal embedded in the RF signal. In some embodiments, the RF-DC converter and/or the envelope detector employ a threshold compensation diode comprising a primary transistor connected in series and a compensation connected in parallel. The threshold compensation diode reduces sensitivity to process corner variations and temperature variations. WuRX can be said to be passive in that it does not require energy from the battery. In contrast, wuRX uses energy collected from RF signals. Collecting energy from the RF signal enables the associated IoT device to operate in a power-saving manner, e.g., by remaining in a sleep state, unless/until the associated IoT device is activated by the wake-up signal.

Fig. 1 is a block diagram of WuRX 100 according to some embodiments. In some embodiments, wuRX 100 includes an RF-DC converter 102, an envelope detector 104, a power management unit 106, a signal processing unit 108, and an antenna 110. The RF-DC converter 102, the envelope detector 104, the power management unit 106, and the signal processing unit 108 may be disposed on a semiconductor die 112, and the antenna 110 may be connected to an input terminal 114 of the semiconductor die 112. The antenna 110 and the semiconductor die 112 may be disposed on a printed circuit board. The antenna 110 may be a loop antenna such as a small loop antenna that matches the input impedance of the envelope detector 104. WuRX 100 is entirely passive in that it does not require energy from a battery or an external voltage source, but rather collects energy from the RF input signal. Other structures and/or configurations of WuRX 100 are within the scope of the present disclosure.

The RF-DC converter 102 is an energy harvester that receives an RF signal from the antenna 110, harvests energy from the RF signal, and generates a DC output voltage V at the output terminal 116 _OUT . The power management unit 106 includes a voltage reference (V _REF ) Unit 118, low Dropout (LDO) regulator 120, power On Reset (POR) unit 122, current reference (I _REF ) A unit 124, an internal storage unit 126 for storing excess collected energy, and an external storage unit 127. The LDO regulator 120 generates a supply voltage (V) for the signal processing unit 108 _DD ). Other structures and/or configurations of the power management unit 106 are within the scope of the present disclosure.

In some implementations, the signal processing unit 108 includes a comparator 128, a digital correlator 130, and a clock 132. The comparator 128 receives the output of the envelope detector 104 to identify a binary transition in the RF signal, and the digital correlator 130 detects the presence of a binary pattern and generates an interrupt signal (IRQ) at the interrupt terminal 134 in response to the binary pattern being detected. For example, the wake-up signal may be a binary pattern 101101110101 followed by a pattern 101010101010. The binary pattern may vary. The clock 132 generates timing signals for the comparator 128 and the digital correlator 130. In some implementations, the comparator 128 is a high-arm latch comparator with zero static power that generates a rail-to-rail output. Other structures and/or configurations of the signal processing unit 108 are within the scope of the present disclosure.

Fig. 2 is a circuit diagram of RF-DC converter 102 according to some embodiments. The RF-DC converter 102 includes: input electrostatic discharge (ESD) protection devices 200, 202; positive gain stages 204A through 204E; and a negative gain stage 205. Each positive gain stage 204A-204E includes an n-type threshold compensation diode 206, a p-type threshold compensation diode 208, a sampling capacitor 210, and a load capacitor 212. The sampling capacitor 210 is connected to a node between the output of the n-type threshold compensation diode 206 and the input of the p-type threshold compensation diode 208. The load capacitor 212 is connected to the output of the p-type threshold compensation diode 208. The negative gain stage 205 includes a sampling capacitor 214, a load capacitor 216, and two diode-connected n-type transistors 218, 220. Negative gain stage 205 creates a negative output voltage V _NEG The negative output voltage V _NEG The p-type threshold compensation diode 208 in the first positive gain stage 204A is provided with a lower supply voltage. The ESD protection devices 200, 202 may be antiparallel p+/n-well and n+/p-well junction diodes that provide reliable operation of the RF-DC converter 102 across a wide input power range. The gain stages 204A to 204E, 205 employ a Dickson topology for voltage rectification to generate an output voltage V _OUT 。

POR cell 122 generates a POR signal and is responsive to voltage V of RF-DC converter 102 _OUT WuRX 100 is operated in the first mode beyond the minimum voltage to allow for the reception of data in the RF input signal. In some embodiments, POR cell 122 operates WuRX 100 in the second mode in response to the presence of sufficient voltage to charge memory cell 126 or to charge memory cell 127 by activating switch 128. In some implementations, the memory cell 126 includes a capacitor. The storage unit 127 may comprise a thin film battery, a solid state battery, or some other suitable energy storage device.

Fig. 3 is a circuit diagram of the envelope detector 104 according to some embodiments. Envelope detector 104 takesRectifying and tracking an input RF signal with a Dickson topology and providing a pseudo-differential output V using p-type threshold compensation diodes 300, 302 _ED1 、V _ED2 . The p-type threshold compensation diode 300 includes a p-type rectifying transistor 304, a p-type compensation transistor 306, and a current source 308. In some implementations, the negative gain stage 205 creates a negative output voltage V _NEG The negative output voltage V _NEG Providing a lower supply voltage to the current sources 308, 314. In some embodiments, the lower supply voltage of the current sources 308, 314 is V _SS (ground). The output of the p-type rectifying transistor 304 and the output of the p-type compensating transistor 306 are connected, and a current source 308 is connected to the gate of the p-type rectifying transistor 304 and the gate of the p-type compensating transistor 306. The threshold-compensated p-type diode 302 includes a p-type rectifying transistor 310, a p-type compensating transistor 312, and a current source 314. An output of the p-type rectifying transistor 310 and an output of the p-type compensating transistor 312 are connected, and a current source 314 is connected to a gate of the p-type rectifying transistor 304 and a gate of the p-type compensating transistor 306. A capacitor 316 and a current source 318 are connected in parallel with the p-type threshold compensation diode 300. In some embodiments, the p-type compensation transistors 306, 312 are diode connected because the input is connected to the gate. A capacitor 320 and a voltage divider 322 are connected in parallel with the threshold compensation p-type diode 302. The voltage divider 322 includes resistors 324, 326 connected in series and a capacitor 328 connected in parallel with the resistor 326. Capacitor 316 has a much lower capacitance than capacitor 320 so that it is charged with capacitor 320 to generate V _ED2 Capacitor 316 charges faster than the signal to generate V _ED1 A signal. Current source 318 generates a current N x I _BIAS The current N is I _BIAS Is the current I generated by the current sources 308, 314 _BIAS Is a multiple of (2). As discussed below with reference to fig. 3, the current source 318 provides an adjustable rate of change to the envelope detector 104. The rate of change may be adjusted based on the bit rate of the input signal.

Current reference I represented by current sources 308, 314 _BIAS Generated by the current reference unit 124 in the power management unit 106 and creates a voltage drop across the p-type compensation transistors 306, 312. This voltage causes a p-type rectifying transistor 304. 310. Thus, the p-type rectifying transistors 304, 310 are slightly forward biased to their optimal values, which can be determined using simulation. This forward bias reduces the input impedance of the envelope detector 104 and increases the sensitivity to low amplitude signals. The rate of change may be adjusted based on the bit rate of the input signal.

Fig. 4A is a diagram of a p-type threshold compensation diode 400 (such as p-type threshold compensation diodes 208, 300, 302) according to some embodiments. The p-type threshold compensation diode 400 includes a p-type rectifying transistor 402 connected to a p-type compensation transistor 404 and is used to provide a current reference I _BIAS Is provided) and a current source 406 of the same. The current source 406 may reference V _NEG (p-type threshold compensation diode 208 for first gain stage 204A or p-type threshold compensation diodes 300, 302) or V _SS (p-type threshold compensation diode 208 for the other gain stages 204B-204E). The output of the p-type rectifying transistor 402 and the output of the p-type compensating transistor 404 are connected, and a current source 406 is connected to the gate of the p-type rectifying transistor 402 and the gate of the p-type compensating transistor 404. In some embodiments, the p-type compensation transistor 404 is diode connected because the input is connected to the gate.

Fig. 4B and 4C are diagrams of a p-type rectifying transistor 402 and a p-type compensating transistor 404, respectively, according to some embodiments. Referring to fig. 4b, the p-type rectifying transistor 402 includes a first p-type unit cell transistor 406 connected in parallel with a second p-type unit cell transistor (p-type unit cell transistor) 408. The parallel arrangement of the p-type unit cell transistors 406, 408 increases the transconductance of the p-type rectifying transistor 402.

Referring to fig. 4c, the p-type compensation transistor 404 includes p-type unit cell transistors 410, 412, 414, 416, 418, 420, 422, 424 connected in series. The number of p-type unit cell transistors 410, 412, 414, 416, 418, 420, 422, 424 may vary. The series arrangement of the p-type unit cell transistors 410, 412, 414, 416, 418, 420, 422, 424 increases the gate length of the p-type compensation transistor 404 to facilitate a given bias current I _BIAS A desired gate precharge voltage for the p-type rectifying transistor 402 is generated. Unit cellThe use of (c) helps to achieve robustness of the generated precharge voltage against process corner and temperature fluctuations.

Fig. 5A is a diagram of an n-type threshold compensation diode 500 (such as n-type threshold compensation diode 206) according to some embodiments. The n-type threshold compensation diode 500 includes an n-type rectifying transistor 502 connected to an n-type compensation transistor 504 and a circuit for providing a current reference I _BIAS Is provided). An output terminal of the n-type rectifying transistor 502 and an output terminal of the n-type compensating transistor 504 are connected, and a current source 506 is connected to a gate of the n-type rectifying transistor 502 and a gate of the n-type compensating transistor 504. In some embodiments, n-type compensation transistor 504 is diode connected because the input is connected to the gate.

Fig. 5B and 5C are diagrams of an n-type rectifying transistor 502 and an n-type compensating transistor 504, respectively, according to some embodiments. Referring to fig. 5b, the n-type rectifying transistor 502 includes a first n-type unit cell transistor 508 connected in parallel with a second n-type unit cell transistor 510. The parallel arrangement of the n-type unit cell transistors 508, 510 increases the transconductance of the n-type rectifying transistor 502.

Referring to fig. 5c, the n-type compensation transistor 504 includes n-type unit cell transistors 512, 514, 516, 518, 520, 522, 524, 526 connected in series. The number of n-type unit cell transistors 512, 514, 516, 518, 520, 512, 522, 524, 526 may vary. The series arrangement of n-type unit cell transistors 512, 514, 516, 518, 520, 522, 524, 526 increases the gate length of the n-type compensation transistor 504 to facilitate a given bias current I _BIAS A desired gate precharge voltage for the n-type rectifying transistor 502 is generated. The use of unit cells helps to achieve robustness of the generated precharge voltage to process corner and temperature fluctuations.

Fig. 6 is a diagram of a current reference cell 124 according to some embodiments. The current reference unit 124 generates a first order temperature compensated current that is used as the current reference I for the threshold compensation diodes 206, 208, 300, 302, 500 _BIAS 。

In some embodiments, the current reference unit 124 includes: a start-up circuit 602 for generating a start-upKinetic current I _STRT The method comprises the steps of carrying out a first treatment on the surface of the A self-biasing beta multiplier current reference 604 for generating an absolute temperature proportional I _PTAT A current; and VGS/R current reference circuit 606 for generating I to absolute temperature _CTAT And (5) current compensation. Will I _PTAT Current sum I _CTAT Current combination to obtain temperature compensated output current I _BIAS 。I _PTAT Current path and I of current _CTAT The current paths of the currents are combined through shared resistor 608. In some implementations, the resistor 608 may be variable. The resistance value of resistor 608 may be trimmed by selectively shorting one or more serially connected resistors.

Fig. 7 and 8 are signal diagrams illustrating the operation of WuRX 100 according to some embodiments. Referring to fig. 7, a signal diagram 700 is provided that illustrates the operation of the envelope detector 104. The RF signal 702 is used to generate power and to signal a wake-up condition. During signaling of a wake-up, the RF signal 702 includes a pulse period and a cut-off period defining a binary pattern. During the on period, with V _ED2 Signal 706 is compared with V _ED1 Signal 704 reacts rapidly due to the reduced time constant. V (V) _ED1 The apparent rate of change of signal 704 during active discharge depends on the multiplier N used in current source 318. V (V) _ED2 Signal 706 is directed to V _ED1 Signal 704 provides an average reference. When V is _ED1 Signal 704 exceeds V _ED2 Comparator 128 identifies a logic "1" when signal 706, and when V _ED1 Signal 704 is below V _ED2 Upon signal 706, comparator 128 identifies a logic "0".

Fig. 8 shows a diagram 800 in WuRX 100 during a wake event. FIG. 8 shows input RF signals 810, V _OUT Signals 812, V _DD Signal 814, POR signal 816, clock signal 818, V _ED1 Signal 820A, V _ED2 Signal 820B, comparator output signal 822, V _COMP And IRQ signals 824 (e.g., wake-up signals). As in V _OUT As seen in the rising level of signal 812, the initial portion of RF signal 810 does not include an interruption that allows power to be collected. When V is generated by LDO regulator 120 _DD Signal 814 exceeds a thresholdAt this time, POR signal 816 is asserted (asserted). POR signal 816 resets the digital circuitry in signal processing unit 108 and clock 132 begins to oscillate. V (V) _ED2 Signal 820B is established to generate a detection threshold. At 826, an awake mode is set in the RF signal 810. At V _ED1 The pattern can be seen in signal 820A and comparator output signal 822. In response to the digital correlator 130 detecting the wake mode, the IRQ signal 824 is asserted at 828.

Fig. 9 is a flow chart illustrating an example method 900 of diode threshold compensation according to some embodiments. At 902, an RF input signal is received. At 904, energy is harvested from the RF input signal to generate a supply voltage. At 906, a current reference is generated based on the supply voltage. At 908, a signal corresponding to a transition in the RF input signal is generated using a first diode. At 910, a threshold of the first diode is compensated using the current reference.

In examples of the technology presented herein, a wake-up receiver includes a power management unit configured to receive a supply voltage generated from an input signal and to generate a current reference. The envelope detector is configured to generate a signal corresponding to a transition in the input signal. The signal processing unit is configured to: an interrupt signal is generated in response to detecting the wake-up pattern in the signal from the envelope detector. The envelope detector comprises a first diode compensated by a current reference.

In examples of the technology presented herein, the wake-up receiver includes an energy harvester configured to generate a supply voltage based on an input signal.

In an example of the technology presented herein, the first diode comprises: a compensation transistor having a first gate, a first input terminal, and a first output terminal connected to the first gate; a rectifying transistor having a second gate and a second output terminal connected to the first input terminal; and a current source connected to the first gate and the second gate and configured to generate a current reference.

In examples of the technology presented herein, a rectifying transistor includes a first transistor and a second transistor connected in parallel with the first transistor.

In examples of the technology presented herein, the compensation transistor includes a first transistor and a second transistor connected to the first transistor.

In an example of the technology presented herein, the second transistor is connected in series with the first transistor.

In examples of the technology presented herein, the rectifying and compensating transistors comprise p-type transistors.

In an example of the technology presented herein, an envelope detector includes: a first capacitor connected in parallel with the first diode; and a current source configured to generate an integer multiple of a current reference connected in parallel with the first diode.

In an example of the technology presented herein, the envelope detector includes a second diode compensated by the current reference, a second capacitor connected in parallel with the second diode, and a voltage divider connected in parallel with the second diode.

In an example of the technology presented herein, a system includes: a radio frequency to direct current (RF-DC) converter configured to generate a supply voltage based on an RF input signal; a power management unit configured to receive a supply voltage and generate a current reference; and an envelope detector configured to generate a signal corresponding to a transition in the RF input signal, wherein the envelope detector comprises a first diode compensated by a current reference threshold, and the RF-DC converter comprises a second diode compensated by the current reference threshold.

In an example of the technology presented herein, a system includes: a storage unit configured to store energy; and a power-on reset unit configured to: the system is operated in a first mode in response to a supply voltage generated by the RF-DC converter exceeding a minimum voltage that allows for receipt of data in the RF input signal, and is operated in a second mode in response to the supply voltage generated by the RF-DC converter being sufficient to charge the memory unit.

In an example of the technology presented herein, a system includes a small loop antenna connected to an RF-DC converter and an envelope detector.

In an example of the technology presented herein, the first diode comprises: a diode-connected compensation transistor having a first gate and a first output; a rectifying transistor having a second gate and a second output terminal connected to the first output terminal; and a current source connected to the first gate and the second gate and configured to generate a current reference.

In an example of the technology presented herein, the rectifying transistor includes a first transistor and a second transistor connected in parallel with the first transistor, and the diode-connected compensation transistor includes a third transistor and a fourth transistor connected in series with the third transistor.

In an example of the technology presented herein, an envelope detector includes: a first capacitor connected in parallel with the first diode; a current source configured to generate an integer multiple of a current reference connected in parallel with the first diode; a third diode compensating for the threshold by the current reference; a second capacitor connected in parallel with the third diode; and a voltage divider connected in parallel with the third diode.

In an example of the technology presented herein, the second diode comprises an n-type diode, the RF-DC converter comprises a p-type diode compensated by a current reference and connected to the n-type diode, the sampling capacitor is connected to a node between an input of the p-type diode and an output of the n-type diode, and the load capacitor is connected to the output of the p-type diode.

In examples of the technology presented herein, harvesting energy from an RF input signal includes: the threshold of the n-type diode is compensated using the current reference and the threshold of the p-type diode is compensated using the current reference, wherein the n-type diode is connected to the p-type diode, the sampling capacitor is connected to a node between an input terminal of the p-type diode and an output terminal of the n-type diode, and the load capacitor is connected to the output terminal of the p-type diode.

In an example of the technology presented herein, a method includes: detecting a mode in transition in the RF input signal after the supply voltage exceeds the first voltage; and storing at least some of the energy in the energy storage device in response to the supply voltage exceeding a second voltage that is greater than the first voltage.

In examples of the techniques presented herein, generating a signal corresponding to a transition in an RF input signal includes: generating a first reference signal using a first diode, a first capacitor connected in parallel with the first diode, and a current source configured to generate an integer multiple of a current reference connected in parallel with the first diode; and generating a second reference signal using a second diode compensated by the current reference, a second capacitor connected in parallel with the second diode, and a voltage divider connected in parallel with the second diode.

Any aspect or design described herein as "example" is not necessarily to be construed as advantageous over other aspects or designs. Rather, use of the word "example" is intended to present one possible aspect and/or implementation that may be related to the techniques presented herein. Such examples are not necessary or intended to be limiting for such techniques. Various implementations of such techniques may include such examples alone or in combination with other features, and/or may vary and/or omit examples shown.

As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise or clear from context, "X employs a or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A, X employs B, or X employs both a and B, then "X employs a or B" is satisfied in any of the foregoing cases. In addition, the articles "a" and "an" as used in this application and the appended claims may generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Furthermore, unless specified otherwise, "first," "second," etc. are not intended to imply temporal, spatial, ordering, etc. Rather, such terms are merely used as identifiers, names, etc. of features, elements, items, etc. For example, a first element and a second element generally correspond to element a and element B or two different elements or two identical elements or the same element.

Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed as to imply that these operations are necessarily order dependent. Alternative ordering may be implemented without departing from the scope of this disclosure. Furthermore, it will be understood that not all operations need be present in every embodiment provided herein. Further, it will be understood that not all operations are necessary in some embodiments.

Furthermore, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present disclosure includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated example implementations of the disclosure. Furthermore, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the term "includes," having, "" has, "" with, "or variants thereof is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term" comprising.

Claims

1. A wake-up receiver comprising:

a power management unit configured to receive a supply voltage generated from an input signal and generate a current reference;

an envelope detector configured to generate a signal corresponding to a transition in the input signal; and

a signal processing unit configured to generate an interrupt signal in response to detecting an awake mode in a signal from the envelope detector, wherein:

the envelope detector includes a first diode compensated by the current reference.

2. The wake-up receiver of claim 1, comprising:

an energy harvester configured to generate the supply voltage based on the input signal.

3. The wake-up receiver of claim 1, wherein the first diode comprises:

a compensation transistor having a first gate, a first input terminal, and a first output terminal connected to the first gate;

a rectifying transistor having a second gate and a second output terminal connected to the first input terminal; and

a current source connected to the first gate and the second gate and configured to generate the current reference.

4. A wake-up receiver as claimed in claim 3, wherein the rectifying transistor comprises:

a first transistor; and

and a second transistor connected in parallel with the first transistor.

5. A wake-up receiver as claimed in claim 3, wherein the compensation transistor comprises:

a first transistor; and

a second transistor connected to the first transistor.

6. The wake-up receiver of claim 4, wherein the second transistor is connected in series with the first transistor.

7. A wake-up receiver as claimed in claim 3, wherein the rectifying and compensating transistors comprise p-type transistors.

8. The wake-up receiver of claim 1, wherein the envelope detector comprises:

a first capacitor connected in parallel with the first diode; and

a current source configured to generate an integer multiple of a current reference connected in parallel with the first diode.

9. The wake-up receiver of claim 8, wherein the envelope detector comprises:

a second diode, the threshold of the second diode being compensated by the current reference;

a second capacitor connected in parallel with the second diode; and

and the voltage divider is connected with the second diode in parallel.

10. A system, comprising:

a radio frequency to direct current, RF-DC, converter configured to generate a supply voltage based on an RF input signal;

a power management unit configured to receive the supply voltage and generate a current reference; and

an envelope detector configured to generate a signal corresponding to a transition in the RF input signal, wherein:

the envelope detector includes a first diode compensated by the current reference, and

the RF-DC converter includes a second diode compensated by the current reference.

11. The system of claim 10, comprising:

a storage unit configured to store energy; and

a power-on reset unit configured to: the system is operated in a first mode in response to a supply voltage generated by the RF-DC converter exceeding a minimum voltage that allows for receipt of data in the RF input signal, and is operated in a second mode in response to the supply voltage generated by the RF-DC converter being sufficient to charge the memory cell.

12. The system of claim 10, comprising:

a small loop antenna connected to the RF-DC converter and the envelope detector.

13. The system of claim 10, wherein the first diode comprises:

a diode-connected compensation transistor having a first gate and a first output;

a rectifying transistor having a second gate and a second output terminal connected to the first output terminal; and

14. The system of claim 13, wherein:

the rectifying transistor includes:

a first transistor; and

a second transistor connected in parallel with the first transistor, and the diode-connected compensation transistor includes:

a third transistor; and

and a fourth transistor connected in series with the third transistor.

15. The system of claim 10, wherein the envelope detector comprises:

a first capacitor connected in parallel with the first diode;

a current source configured to generate an integer multiple of a current reference connected in parallel with the first diode;

a third diode, the threshold of which is compensated by the current reference;

a second capacitor connected in parallel with the third diode; and

and the voltage divider is connected with the third diode in parallel.

16. The system of claim 10, wherein:

the second diode comprises an n-type diode,

the RF-DC converter comprises a p-type diode, the threshold of which is compensated by the current reference and which is connected to the n-type diode,

a sampling capacitor is connected to a node between an input of the p-type diode and an output of the n-type diode; and

a load capacitor is connected to the output of the p-type diode.

17. A method, comprising:

receiving a radio frequency, RF, input signal;

collecting energy from the RF input signal to generate a supply voltage;

generating a current reference based on the supply voltage;

generating a signal corresponding to a transition in the RF input signal using a first diode; and

the threshold of the first diode is compensated using the current reference.

18. The method of claim 17, wherein harvesting energy from the RF input signal comprises:

compensating a threshold of an n-type diode using the current reference; and

compensating a threshold of a p-type diode using the current reference, wherein:

the n-type diode is connected to the p-type diode,

a load capacitor is connected to the output of the p-type diode.

19. The method of claim 17, comprising:

detecting a mode in transition in the RF input signal after the supply voltage exceeds a first voltage; and

at least some of the energy is stored in an energy storage device in response to the supply voltage exceeding a second voltage, the second voltage being greater than the first voltage.

20. The method of claim 17, wherein generating a signal corresponding to a transition in the RF input signal comprises:

generating a first reference signal using the first diode, a first capacitor connected in parallel with the first diode, and a current source configured to generate an integer multiple of a current reference connected in parallel with the first diode; and

a second reference signal is generated using a second diode compensated by the current reference, a second capacitor connected in parallel with the second diode, and a voltage divider connected in parallel with the second diode.