CN117637845A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN117637845A
CN117637845A CN202311461422.4A CN202311461422A CN117637845A CN 117637845 A CN117637845 A CN 117637845A CN 202311461422 A CN202311461422 A CN 202311461422A CN 117637845 A CN117637845 A CN 117637845A
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China
Prior art keywords
dielectric
layer
source
gate
sidewall spacer
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CN202311461422.4A
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Chinese (zh)
Inventor
潘冠廷
江国诚
朱熙甯
张家豪
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US18/106,724 external-priority patent/US20240154014A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN117637845A publication Critical patent/CN117637845A/en
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Abstract

Embodiments of the present disclosure provide a fork blade structure in a semiconductor device and a method of manufacturing the same. The fork strap structure according to embodiments of the present disclosure includes a dielectric wall disposed between two channel regions inside the gate structure and not extending through the sidewall spacers to the source/drain regions. In some embodiments, a Cut Metal Gate (CMG) dielectric structure is formed in the gate structure along with the dielectric wall. The gate dielectric layer is in contact with the dielectric wall. In some embodiments, the dielectric layer surrounds the semiconductor channel in the channel region. In other embodiments, the gate dielectric layer surrounds a portion of the semiconductor channel that is located in the channel region, such as forming a pi-shaped cross-sectional profile around the semiconductor channel. Embodiments of the present application also relate to semiconductor devices and methods of manufacturing the same.

Description

Semiconductor device and method for manufacturing the same
Technical Field
Embodiments of the present application relate to a semiconductor device and a method of manufacturing the same.
Background
The semiconductor Integrated Circuit (IC) industry has experienced a rapid growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component that can be created using a manufacturing process) has decreased. Such advances have increased the complexity of manufacturing and handling ICs; similar developments in IC processing and manufacturing are being developed to meet this advancement.
Disclosure of Invention
Some embodiments of the present application provide a semiconductor device including: a first source/drain region; a second source/drain region disposed adjacent to the first source/drain region; fork piece structure includes: a first channel region in contact with the first source/drain region; a second channel region in contact with the second source/drain region; a dielectric wall disposed between the first channel region and the second channel region, wherein the dielectric wall has a first surface facing the first channel region, a second surface facing the second channel region, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface; a first sidewall spacer disposed on a first side of the fork blade structure, wherein the first sidewall spacer is disposed between the first and second source/drain regions and the first and second channel regions; and a second sidewall spacer disposed on a second side of the fork blade structure, wherein the dielectric wall is disposed between the first sidewall spacer and the second sidewall spacer.
Other embodiments of the present application provide a semiconductor device comprising: a first source/drain region; a second source/drain region; a first channel region disposed between and connected to the first and second source/drain regions; a first gate structure comprising: a first gate dielectric layer disposed on the first channel region; and a first gate electrode layer disposed on the first gate dielectric layer; a first sidewall spacer and a second sidewall spacer disposed on opposite sides of the first gate structure, wherein the first source/drain region is in contact with the first sidewall spacer and the second source/drain region is in contact with the second sidewall spacer; and a dielectric wall, wherein the dielectric wall has a first end, a second end, and a first surface connecting the first end and the second end, the first end of the dielectric wall terminates at the first sidewall spacer, the second end of the dielectric wall terminates at the second sidewall spacer, and the first gate dielectric layer is in contact with the first surface of the dielectric wall.
Still further embodiments of the present application provide a method of manufacturing a semiconductor device, comprising: forming a first fin structure and a second fin structure along a first direction; forming a sacrificial gate structure along a second direction and across the first fin structure and the second fin structure; forming first and second sidewall spacers on opposite sidewalls of the sacrificial gate structure; etching back the first fin structure and the second fin structure to form source/drain openings on opposite sides of the sacrificial gate structure; forming epitaxial source/drain regions in the source/drain openings; forming a wall opening in the sacrificial gate structure between the first sidewall spacer and the second sidewall spacer; forming a dielectric wall in the wall opening between the first sidewall spacer and the second sidewall spacer; removing the sacrificial gate structure; and forming a first replacement gate structure and a second replacement gate structure, wherein the dielectric wall isolates the first replacement gate structure from the second replacement gate structure.
Drawings
The various aspects of the embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 2 is a schematic layout diagram of a semiconductor device according to an embodiment of the present disclosure.
Fig. 3 to 6, 7A to 7C, 8A to 8C, 9A to 9C, 10A to 10C, 11A to 11C, 12A to 12C, 13A to 13C, 14A to 14C, 15A to 15C, 16A to 16C, 17, 18A to 18C, 19A to 19C, 20A to 20G, 21A to 21B, and 22A to 22D schematically illustrate various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 23 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 24 to 34, 35A to 35B, 36A to 36E, and 37A to 37B schematically illustrate various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 38A-38B are schematic cross-sectional views of dielectric walls according to embodiments of the present disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure embodiments. These are, of course, merely examples and are not intended to limit the disclosed embodiments. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, embodiments of the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms such as "under …," "under …," "lower," "above …," "over …," "top," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The foregoing generally outlines some aspects of the embodiments described in the embodiments of the present disclosure. Although some embodiments described herein are described in the context of a nanoflake channel FET, implementations of some aspects of the disclosed embodiments may be used in other processes and/or other devices, such as planar FETs, fin FETs, horizontal full-gate (HGAA) FETs, vertical full-gate (VGAA) FETs, and other suitable devices. Those of ordinary skill in the art will readily appreciate that other modifications that may be made are contemplated within the scope of the disclosed embodiments. Furthermore, although method embodiments may be described in a particular order, various other method embodiments may be implemented in any logical order and may include fewer or more steps than those described herein. Source/drain regions may refer to either source or drain, either individually or collectively depending on the context.
Embodiments of the present disclosure provide a fork blade structure in a semiconductor device and a method of manufacturing the same. The fork strap structure according to embodiments of the present disclosure includes a dielectric wall disposed between two channel regions inside the gate structure and not extending through the sidewall spacers to the source/drain regions. In some embodiments, a Cut Metal Gate (CMG) dielectric structure is formed in the gate structure along with the dielectric wall. The gate dielectric layer is in contact with the dielectric wall. In some embodiments, the dielectric layer surrounds the semiconductor channel in the channel region. In other embodiments, the gate dielectric layer surrounds a portion of the semiconductor channel that is located in the channel region, such as forming a pi-shaped cross-sectional profile around the semiconductor channel.
Fig. 1 is a flow chart of a method 100 for fabricating a semiconductor device 10 according to an embodiment of the present disclosure. Fig. 2 is a schematic layout diagram of a semiconductor device 10 according to an embodiment of the present disclosure. Fig. 3 to 6, 7A to 7C, 8A to 8C, 9A to 9C, 10A to 10C, 11A to 11C, 12A to 12C, 13A to 13C, 14A to 14C, 15A to 15C, 16A to 16C, 17, 18A to 18C, 19A to 19C, 20A to 20G, 21A to 21B, and 22A to 22D schematically illustrate various stages of manufacturing the semiconductor device 10 according to embodiments of the present disclosure. Additional operations may be provided before, during, and after the operations/processes in method 100, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations/processes may be interchanged.
As shown in fig. 2, semiconductor device 10 may include a plurality of fin structures 20 along an x-axis and a plurality of gate structures 58 along a y-axis. Dielectric walls 51 may be formed between adjacent fin structures 20 and within gate structures 58 to form a fork-type structure. By forming dielectric wall 51 within the gate structure, semiconductor device 10 reduces fin structure distance FD, which is defined as the distance of the gap between two adjacent fin structures 20, as shown in fig. 2. In some embodiments, fin structure distance FD may be reduced by a percentage in the range between 25% and 35% using dielectric wall 51 described below.
The method 100 begins at operation 102, where fin structures 20a, 20b are formed over a substrate 12, as shown in fig. 3. Fig. 3 is a schematic cross-sectional view along line A-A in fig. 2. A substrate 12 is provided to form a semiconductor device 10 thereon. The substrate 12 may comprise single crystal semiconductor material such as, but not limited to Si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb and InP. The substrate 12 may include various doping configurations depending on the circuit design. For example, different doping profiles, e.g., n-well, p-well, may be formed in regions of substrate 12 designed for different device types, such as n-type field effect transistors (nfets) and p-type field effect transistors (pfets). In some embodiments, substrate 12 may be a silicon-on-insulator (SOI) substrate including a structure for enhanced insulators (not shown).
In the embodiment shown in fig. 3, the substrate 12 includes a p-doped region or p-well 12b and an n-doped region or n-well 12a. One or more n-type devices, such as nfets, will be formed over and/or within p-well 12 b. One or more p-type devices, such as pfets, will be formed over and/or within n-well 12a. Fig. 3 shows that p-well 12b is located in a doped localized region of the doped substrate, which is not limiting. In other embodiments, the p-well 12b and the n-well 12a may be separated by one or more insulators (e.g., shallow trench isolation ("STI")).
Semiconductor stack 18a may be formed and patterned over n-well 12a to form semiconductor fin 20a. Semiconductor stack 18a includes alternating semiconductor layers made of different materials to facilitate formation of a nanoflake channel, such as a nanoflake channel pFET, in a multi-gate n-type device. In some embodiments, the semiconductor stack 18a includes a first semiconductor layer 14a interposed by a second semiconductor layer 16 a. The first semiconductor layer 14a and the second semiconductor layer 16a have different compositions. In some embodiments, the two semiconductor layers 14a and 16a provide different oxidation rates and/or different etch selectivities. In a later stage of fabrication, portions of the second semiconductor layer 16a form nanoplate channels in the multi-gate device. As an example, three first semiconductor layers 14a and three second semiconductor layers 16a are alternately arranged, as shown in fig. 3. More or fewer semiconductor layers 14a and 16a may be included in semiconductor stack 18a, depending on the desired number of channels to be formed in the semiconductor device. In some embodiments, the number of semiconductor layers 14a and 16a is between 1 and 10.
In some embodiments, the first semiconductor layer 14a may include silicon germanium (SiGe). The first semiconductor layer 14a may be a SiGe layer including Ge in a molar ratio of more than 25%. For example, the first semiconductor layer 14a may be a SiGe layer including Ge in a molar ratio ranging between 25% and 50%. In some embodiments, the first semiconductor layer 14a and the second semiconductor layer 16a have substantially the same composition. The second semiconductor layer 16a may include: silicon, ge; compound semiconductors such as SiC, geAs, gaP, inP, inAs and/or InSb; alloy semiconductors such as SiGe, gaAsP, alInAs, alGaAs, inGaAs, gaInP and/or GaInAsP; or a combination thereof. In some embodiments, the second semiconductor layer 16a may be a Ge layer. The second semiconductor layer 16a may include a p-type dopant, boron, and the like.
Semiconductor stack 18b may be formed over p-well 12b and then patterned to form semiconductor fin 20b. Semiconductor stack 18b includes alternating semiconductor layers made of different materials to facilitate formation of a nanoflake channel, such as a nanoflake channel nFET, in a multi-gate n-type device. In some embodiments, the semiconductor stack 18b includes a third semiconductor layer 14b interposed by a fourth semiconductor layer 16 b. The third semiconductor layer 14b and the fourth semiconductor layer 16b have different compositions. In some embodiments, the two semiconductor layers 14b and 16b provide different oxidation rates and/or different etch selectivities. In a later stage of fabrication, portions of the fourth semiconductor layer 16b form nanoplate channels in the multi-gate device. As an example, three third semiconductor layers 14b and three fourth semiconductor layers 16b are alternately arranged, as shown in fig. 3. More or fewer semiconductor layers 14b and 16b may be included in semiconductor stack 18b, depending on the desired number of channels to be formed in the semiconductor device. In some embodiments, the number of semiconductor layers 14b and 16b is between 1 and 10.
In some embodiments, the third semiconductor layer 14b may include silicon germanium (SiGe). The third semiconductor layer 14b may be a SiGe layer including Ge in a molar ratio of more than 25%. For example, the third semiconductor layer 14b may be a SiGe layer including Ge in a molar ratio ranging between 25% and 50%. The fourth semiconductor layer 16b may include silicon (Si). In some embodiments, the fourth semiconductor layer 16b may include an n-type dopant, such As phosphorus (P), arsenic (As), and the like.
The semiconductor layers 14a, 14b, 16a, 16b may be formed by a Molecular Beam Epitaxy (MBE) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, and/or other suitable epitaxial growth process.
In some embodiments, each semiconductor layer 16a, 16b has a thickness in a range between about 5nm and about 30 nm. In other embodiments, each second semiconductor layer 16a, 16b has a thickness in a range between about 10nm and about 20 nm. In some embodiments, each semiconductor layer 16a, 16b has a thickness in a range between about 6nm and about 12 nm. In some embodiments, semiconductor layer 16a in semiconductor stack 18a and semiconductor layer 16b in semiconductor stack 18b are uniform in thickness.
The semiconductor layers 14a, 14b may eventually be removed and used to define the vertical distance between adjacent channel regions for subsequently formed multi-gate devices. In some embodiments, the thickness of the semiconductor layers 14a, 14b is equal to or greater than the thickness of the semiconductor layers 16a, 16 b. In some embodiments, each semiconductor layer 14a, 14b has a thickness in a range between about 5nm and about 50 nm. In other embodiments, each semiconductor layer 14a, 14b has a thickness in a range between about 10nm and about 30 nm.
The semiconductor stacks 18a, 18b may be formed separately. For example, the semiconductor stack 18a is first formed over the entire substrate, i.e., over the n-well 12a and the p-well 12b, then a recess is formed in the semiconductor stack 18a in the region over the p-well 12b to expose the p-well 12b, and then the semiconductor stack 18b is formed in the recess over the p-well 12b while the semiconductor stack 18a is covered by a mask layer.
In fig. 3, fin structures 20a, 20b are formed from portions of semiconductor stacks 18a, 18b and underlying n-well 12a, p-well 12b, respectively. Each semiconductor fin 20a, 20b has an active portion formed by the semiconductor stack 18a, 18b and a well portion formed in the n-well 12a, the p-well 12b, respectively. A trench 21 is formed between fin structures 20a, 20 b. The trench 21 has a width W1 along the y-axis. In some embodiments, the width W1 is in a range between about 30nm and about 46 nm. In some embodiments, dielectric walls are then formed in the portions of the trenches 21 between the fin structures 20a, 20b to form a fork-fin structure.
In operation 104, an isolation layer 22 or Shallow Trench Isolation (STI) layer is formed, as shown in fig. 4. Fig. 4 is a schematic cross-sectional view along line A-A in fig. 2. Isolation material fills in the trenches between the fin structures 20a, 20b and is then etched back to under the semiconductor stacks 18a, 18b of the fin structures 20a, 20 b. An isolation material is deposited over the substrate 12 to cover at least a portion of the well portion of the fin structures 20a, 20 b. The isolation material may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition process. In some embodiments, the isolation material may include silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), low-k dielectrics, combinations thereof. In some embodiments, the isolation material is formed by a suitable deposition process to fill the trenches between the fin structures 20a, 20b to cover the fin structures 20a, 20b, and then the recesses are etched using a suitable anisotropic etching process to expose the active portions of the fin structures 20a, 20b, thereby creating the isolation layer 22.
In operation 106, a sacrificial gate dielectric layer 26 is deposited over the exposed surfaces of the semiconductor device 10, as shown in fig. 5. Fig. 5 is a schematic cross-sectional view along line A-A in fig. 2. A sacrificial gate dielectric layer 26 may be conformally formed over fin structures 20a, 20b and isolation layer 22. In some embodiments, the sacrificial gate dielectric layer 26 may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, an FCVD process, an ALD process, a PVD process, or other suitable process. Sacrificial gate dielectric layer 26 may comprise one or more layers of dielectric material, such as SiO 2 SiN, high-k dielectric material, and/or other suitable dielectric material.
In operation 108, a sacrificial gate electrode layer 28 is deposited over the exposed surfaces of the semiconductor device 10, as shown in fig. 6. Fig. 6 is a schematic cross-sectional view along line A-A in fig. 2. Sacrificial gate electrode layer 28 may be blanket deposited over sacrificial gate dielectric layer 26. The sacrificial gate electrode layer 28 comprises silicon, such as polysilicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in a range between about 42nm and about 200 nm. In some embodiments, the sacrificial gate electrode layer 28 is subjected to a planarization operation. Sacrificial gate electrode layer 28 may be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes. Subsequently, a pad layer 30 and a mask layer 32 are formed over the sacrificial gate electrode layer 28. The pad layer 30 may comprise silicon nitride. Mask layer 32 may comprise silicon oxide.
In operation 110, a sacrificial gate structure 24 is formed, as shown in fig. 7A-7C and 8A-8C. Fig. 7A and 8A are schematic perspective sectional views taken along the line A-A in fig. 2. Fig. 7B and 8B are schematic cross-sectional views taken along line B-B in fig. 2. Fig. 7C and 8C are schematic cross-sectional views along the line C-C in fig. 2.
A sacrificial gate structure 24 is formed over the spacer layer 22 and over the exposed portions of the fin structures 20a, 20 b. A sacrificial gate structure 24 is formed over portions of the fin structures 20a, 20b that will become channel regions. Sacrificial gate structure 24 may include a sacrificial gate dielectric layer 26, a sacrificial gate electrode layer 28, a pad layer 30, and a mask layer 32. Patterning is performed on mask layer 32, pad layer 30, sacrificial gate electrode layer 28, and sacrificial gate dielectric layer 26 to form sacrificial gate structure 24.
In operation 112, sidewall spacers 34 and inner spacers 36 are formed as shown in fig. 9A-9C. Fig. 9A is a schematic perspective sectional view taken along the line A-A in fig. 2. Fig. 9B is a schematic cross-sectional view taken along line B-B in fig. 2. Fig. 9C is a schematic cross-sectional view along line C-C in fig. 2.
Sidewall spacers 34 are formed on the sidewalls of the sacrificial gate structure. After forming the sacrificial gate structure 24, the sidewall spacers 34 are formed by blanket depositing an insulating material and subsequent anisotropic etching to remove the insulating material from the horizontal surfaces. The sidewall spacers 34 may have a thickness in a range between about 4nm and about 7 nm. In some embodiments, the insulating material of the sidewall spacers 34 is a silicon nitride based material, such as SiN, siON, siOCN or SiCN and combinations thereof.
The exposed fin structures 20a, 20b are etched and internal spacers 36 are formed. Although described together in each operation, the process for the region of the p-type device (i.e., over n-well 12 a) and the region of the n-type device (i.e., over p-well 12 b) may be implemented separately using a patterned mask and different processing methods.
The fin structures 20a, 20b not covered by the sacrificial gate structure 24 are etched to expose well portions of the fin structures 20a, 20 b. In some embodiments, the semiconductor layers 14a, 14b, 16a, 16b may be removed together or separately using a suitable dry and/or wet etch.
After recess etching of the fin structures 20a, 20b, the inner spacers 36 are formed. To form the inner spacers 36, the semiconductor layers 14a, 14b under the sidewall spacers 34 are selectively etched from the semiconductor layers 16a, 16b in the horizontal or X direction to form spacer cavities. In some embodiments, the semiconductor layers 14a, 14b may be selectively etched by using a wet etchant, such as, but not limited to, ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution. In some embodiments, the etch thickness of semiconductor layers 14a, 14b is in a range between about 2nm and about 10nm along the X-direction.
After the spacer cavities are formed, the inner spacers 36 are formed in the spacer cavities by conformal deposition and then partial removal of the insulating layer. The insulating layer may be formed by ALD or any other suitable method. A subsequent etching process removes most of the insulating layer except inside the cavity, creating an internal spacer 36. The inner spacer 36 has a thickness in the X direction in the range from about 4nm to about 7 nm.
In operation 114, epitaxial source/drain regions 38, 40 are formed, as shown in fig. 10A-10C. Fig. 10A is a schematic perspective sectional view taken along the line A-A in fig. 2. Fig. 10B is a schematic cross-sectional view taken along line B-B in fig. 2. Fig. 10C is a schematic cross-sectional view along line C-C in fig. 2. As discussed above, the epitaxial source/drain regions 38 for p-type devices and the epitaxial source/drain regions 40 for n-type devices are formed using a patterned mask and different epitaxial processes.
For p-type devices, such as pfets, the epitaxial source/drain regions 38 for the p-type devices may include one or more layers of Si, siGe, ge with a p-type dopant, such as boron (B). In some embodiments, the epitaxial source/drain regions 38 may be a SiGeB material, wherein boron is a dopant. The epitaxial source/drain regions 40 for an n-type device may include one or more layers of Si, siP, siC and SiCP. The epitaxial source/drain regions 40 also include n-type dopants, such As phosphorus (P), arsenic (As), and the like. In some embodiments, the epitaxial source/drain regions 40 may be Si layers including phosphorus dopants.
The epitaxial source/drain regions 38, 40 shown in fig. 10A have a hexagonal shape. However, the epitaxial source/drain regions 38, 40 may be other shapes, depending on the design. The epitaxial source/drain regions 38 for p-type devices and the epitaxial source/drain regions 40 for n-type devices may have different shapes.
In operation 116, a Contact Etch Stop Layer (CESL) 42 and an interlayer dielectric (ILD) layer 44 are formed over the exposed surfaces, as shown in fig. 11A-11C. Fig. 11A is a schematic cross-sectional view taken along line A-A in fig. 2. Fig. 11B is a schematic perspective sectional view taken along line B-B in fig. 2. Fig. 11C is a schematic cross-sectional view along line C-C in fig. 2. CESL 42 is formed over epitaxial source/drain regions 38, 40, sidewall spacers 34 and isolation layer 22. In some embodiments, CESL 42 has a thickness in a range between about 4nm and about 7 nm. CESL 42 may include Si 3 N 4 SiON, siCN, or any other suitable material, and may be formed by CVD, PVD, or ALD.
An interlayer dielectric (ILD) layer 44 is formed over CESL 42. Materials for ILD layer 44 include compounds including Si, O, C, and/or H, such as silicon oxide, siCOH, and SiOC. An organic material (such as a polymer) may be used for ILD layer 44. The ILD layer 44 protects the epitaxial source/drain regions 38, 40 during removal of the sacrificial gate structure 24.
A planarization process may be performed after depositing ILD layer 44 to expose sacrificial gate structure 24. In some embodiments, ILD layer 44 may be etched back and capping layer 45 may be deposited over its ILD layer 44 to provide protection during subsequent processing.
In operation 118, an opening 46 is formed in the sacrificial gate electrode layer 28 to remove the sacrificial gate electrode layer 28 between the fin structures 20a, 20b within the sacrificial gate structure 24, as shown in fig. 12A-12C. Fig. 12A is a schematic cross-sectional view taken along line A-A in fig. 2. Fig. 12B is a schematic perspective sectional view taken along line B-B in fig. 2. Fig. 12C is a schematic cross-sectional view along line D-D in fig. 2.
The openings 46 may be formed using a suitable patterning and etching process. In some embodiments, the openings 46 are substantially aligned with the trenches between the fin structures 20a, 20b such that the sacrificial gate electrode layer 28 between the fin structures 20a, 20b may be selectively removed. In some embodiments, the sacrificial gate dielectric layer 26 formed on the sidewalls of the fin structures 20a, 20B is exposed by the opening 46, as shown in fig. 12B. The opening 46 may have a width W2 along the y-axis. In some embodiments, the width W2 may be substantially similar to or slightly greater than the width W1 of the trench 21 between the fin structures 20a, 20b to ensure that the sacrificial gate dielectric layer 26 formed on the sidewalls of the fin structures 20a, 20b is exposed by the opening 46. In the x-axis, openings 46 terminate at sidewall spacers 34 on both sides of sacrificial gate structure 24.
In operation 120, the sacrificial gate dielectric layer 26 exposed by the opening 46 is selectively removed, as shown in fig. 13A-13C. Fig. 13A is a schematic cross-sectional view taken along line A-A in fig. 2.
Fig. 13B is a schematic perspective sectional view taken along line B-B in fig. 2. Fig. 13C is a schematic cross-sectional view taken along line D-D in fig. 2. Portions of the second sacrificial dielectric layer 26 exposed to the openings 46 are selectively removed and the end surfaces of the semiconductor layers 14a, 14b, 16a, 16b of the fin structures 20a, 20b are exposed to the openings 46. After operation 120, isolation layer 22 may also be exposed to opening 46.
In operation 122, dielectric walls 51 are formed in openings 46, as shown in fig. 14A-14C. Fig. 14A is a schematic cross-sectional view taken along line A-A in fig. 2. Fig. 14B is a schematic perspective sectional view taken along line B-B in fig. 2. Fig. 14C is a schematic cross-sectional view along line D-D in fig. 2. Dielectric wall 51 may include one or more dielectric layers. In some embodiments, dielectric wall 51 may be formed from one or more layers of low-k dielectric material. For example, dielectric wall 51 may be formed of one or more materials having a dielectric constant of less than about 7The dielectric material layers are formed. In some embodiments, dielectric wall 51 is made of SiO 2 SiN, siCN, siOC, siOCN or one or more layers of other suitable dielectric materials having a dielectric value of less than 7.
As shown in fig. 14B and 14C, the dielectric wall 51 has two sides 51s1, 51s2 in contact with the fin structures 20a, 20B, respectively, and two sides 51s3, 51s3 in contact with the sidewall spacers 34, respectively. Dielectric walls 51 are disposed within the gate structure and terminate at sidewall spacers 34 along the x-axis.
In some embodiments, dielectric wall 51 includes a dielectric liner layer 48 and a dielectric fill layer 50. The dielectric liner layer 48 may be formed of a dielectric material that may be selectively removed from the dielectric fill layer 50. In some embodiments, the dielectric liner layer 48 may be a SiN layer and the dielectric fill layer 50 comprises SiO 2 . In some embodiments, the dielectric liner layer 48 may be conformally deposited over all exposed surfaces of the opening 46. In some embodiments, the dielectric liner layer 48 may be used to define a gate cap over the channel in the interdigitated structure. For example, the thickness T1 of the dielectric liner layer 48 on the end faces of the semiconductor layers 16a, 16b may be used to define the thickness of the gate cap. In some embodiments, the thickness T1 may be in a range between about 2nm and about 5 nm.
In some embodiments, the dielectric wall 51 may be formed from a single layer of dielectric material, and in the resulting fork blade structure, there is no gate structure between the semiconductor layers 16a, 16b and the dielectric wall 51.
After forming the dielectric wall 51, a replacement gate process may be performed to form gate structures on both sides of the dielectric wall 51. Operations 124 through 132 describe a replacement gate sequence in accordance with an embodiment of the present disclosure.
In operation 124, the sacrificial gate electrode layer 28 and the sacrificial gate dielectric layer 26 are sequentially removed, as shown in fig. 15A to 15C and fig. 16A to 16C. Fig. 15A/16A are schematic cross-sectional views taken along the line A-A in fig. 2. Fig. 15B/16B are schematic perspective sectional views taken along line B-B in fig. 2. Fig. 15C/16C are schematic cross-sectional views along the line D-D in fig. 2. The sacrificial gate electrode layer 28 may be removed using a plasma dry etch and/or a wet etch. When sacrificial gate electrode layer 28 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove sacrificial gate electrode layer 28 without removing the dielectric material of ILD layer 44, CESL 42, or dielectric wall 51. After removal of the sacrificial gate electrode layer, the sacrificial gate dielectric layer 26 may be removed using a suitable etching process.
In some embodiments, when the dielectric wall 51 includes the dielectric liner layer 48, an optional operation 126 may be performed to remove portions of the dielectric liner layer 48, as shown in fig. 17. Fig. 17 is a schematic perspective sectional view taken along line B-B in fig. 2. In some embodiments, an isotropic removal process may be performed to remove the dielectric liner layer 48 located over the fin structures 20a, 20 b. A wet etch or a chemical dry etch may be used to remove portions of the dielectric liner layer 48. After operation 126, the portion of the dielectric liner layer 48 between the fin structures 20a, 20b is exposed for subsequent processing.
In operation 128, the sacrificial semiconductor layers 14a, 14b are removed from the fin structures 20a, 20b, as shown in fig. 18A-18C. Fig. 18A is a schematic cross-sectional view taken along line A-A in fig. 2. Fig. 18B is a schematic perspective sectional view taken along line B-B in fig. 2. Fig. 18C is a schematic cross-sectional view along line D-D in fig. 2. In some embodiments, the semiconductor layers 14a, 14b may be removed during the same etching process or different processes. The semiconductor layers 14a, 14b may be selectively removed using a wet etchant such as, but not limited to, ammonium hydroxide (NH) 4 OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution. The removal of the semiconductor layers 14a, 14B creates nanoplatelets of the semiconductor layers 16a, 16B on both sides of the dielectric wall 51, as shown in fig. 18B. Portions of the dielectric liner layer 48 formed on the sidewalls of the fin structures 20a, 20b are also exposed.
In operation 130, an etching process is performed to remove at least portions of the dielectric liner layer 48 formed on the sidewalls of the fin structures 20a, 20b, as shown in fig. 19A-19C. Fig. 19A is a schematic perspective sectional view taken along line B-B in fig. 2. Fig. 19B to 19C are schematic cross-sectional views taken along the line B-B in fig. 2.
In some embodiments, the profile of the gate structure to be formed may be controlled by removing different amounts of the dielectric liner layer 48 in operation 130. In fig. 19B, a portion of the dielectric liner layer 48 remains between the semiconductor layers 16a/16B and the dielectric fill layer 50. The semiconductor layers 16a/16b may have a height H1 along the z-axis. The remaining dielectric liner layer 48 may have a height H2 along the z-axis. In some embodiments, the height H2 is less than the height H1, and then the gate structure may have a pi-shaped profile. In fig. 19C, the dielectric liner layer 48 is completely removed and the subsequent gate structure may surround all sides of the semiconductor layers 16a/16 b. In some embodiments, operation 130 may be omitted, and the subsequent gate structure may surround the semiconductor layers 16a, 16b from three sides. As more dielectric liner layer 48 is removed, the effective length of the subsequent gate structure increases, resulting in improved gate control performance. The low-k dielectric material in the dielectric liner layer 48 improves Average Capacitance (AC) performance as more of the dielectric liner layer 48 remains.
In operation 132, a replacement gate structure 58 is formed, as shown in fig. 20A-20D. Fig. 20A is a schematic cross-sectional view taken along line A-A in fig. 2. Fig. 20B is a schematic perspective sectional view taken along line B-B in fig. 2. Fig. 20C is a schematic cross-sectional view along line C-C in fig. 2. Fig. 20D is a schematic cross-sectional view taken along line D-D in fig. 2. Replacement gate structure 58 may include gate dielectric layer 52 and gate electrode layer 54. In some embodiments, replacement gate structure 58 also includes a conductive cap layer 56.
After the sacrificial gate structure 24 is removed, a gate dielectric layer 52 is formed on the exposed surface. In some embodiments, the gate dielectric layer 52 may have different compositions and dimensions for n-type and p-type devices and be formed separately using a patterned masking layer and different deposition methods. Gate dielectric layer 52 may include one or more layers of dielectric material such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric materials, and/or combinations thereof. Examples of high-k dielectric materials include HfO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zirconia, alumina, titania, hafnia-alumina (HfO 2 -Al 2 O 3 ) Alloys, other suitable high-k dielectric materials, and/or combinations thereof.
The gate dielectric layer 52 may be formed by CVD, ALD, or any suitable method. In some embodiments, the thickness of gate dielectric layer 52 is in a range between about 1nm and about 6 nm. In some embodiments, an interfacial layer may be formed between the semiconductor layers 16a, 16b and the gate dielectric layer 52. The gate dielectric layer 52 is in contact with the dielectric wall 51.
A gate electrode layer 54 is formed on the gate dielectric layer 52 to fill the gate cavity. Gate electrode layer 54 comprises one or more layers of conductive material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, tiN, WN, tiAl, tiAlN, taCN, taC, taSiN, metal alloys, other suitable materials, and/or combinations thereof. In some embodiments, the gate electrode layer 54 may be formed by CVD, ALD, electroplating, or other suitable methods. In some embodiments, a planarization process may be performed after forming the gate electrode layer 54. In some embodiments, a conductive capping layer 56 may be formed over the gate electrode layer 54. Conductive capping layer 56 may comprise tungsten.
As shown in fig. 20B, the semiconductor layers 16a, 16B, the gate dielectric layer 52, the gate electrode layer 54, and the dielectric wall 51 formed on the semiconductor layers 16a, 16B form a fork-shaped sheet structure 60. The semiconductor layer 16a forms a first channel region, and the semiconductor layer 16b forms a second channel region. A dielectric wall 51 is disposed between the first channel region and the second channel region.
The gate structure around each channel layer or semiconductor layer 16a, 16b may be tuned to achieve the desired performance. Fig. 20E, 20F, 20G are partial enlarged views of region a in fig. 20B to show different contours of the gate structure. In fig. 20E, the gate dielectric layer 52 surrounds all sides of the channel or semiconductor layers 16a, 16b. A gate dielectric layer 52 is formed in the space defined by the dielectric liner layer 48 of the dielectric wall 51. In some embodiments, the gate dielectric layer 52 may have a thickness T2 between the semiconductor layers 16a, 16b and the dielectric wall 51. In some embodiments, the thickness T2 is in a range between about 2nm and about 5 nm.
In fig. 20F, segments of the dielectric liner layer 48 remain on the end portions of the semiconductor layers 16a, 16b. The gate dielectric layer 52 surrounds the channel or semiconductor layers 16a, 16b that are not covered by the dielectric liner layer 48. As shown in fig. 20F, the gate dielectric layer 52 has a pi-shaped profile in the cross section of fig. 20B. There may be a portion of the gate electrode layer 54 between the semiconductor layers 16a, 16b and the dielectric wall 51. Portions of gate electrode layer 54 may have a thickness T3 between semiconductor layers 16a, 16b and dielectric wall 51 and a height H3 from the top surface of semiconductor layers 16a/16a and the top surface of dielectric layer 48, as shown in fig. 20F. In some embodiments, the thickness T3 may be less than about 1nm. The height H3 may be in a range between 0nm and about 3 nm.
In fig. 20G, the dielectric liner layer 48 remains on the entire end portions of the semiconductor layers 16a, 16b. The gate dielectric layer 52 surrounds the channel or semiconductor layers 16a, 16b on three sides.
In operation 134, a cut gate structure 62 may be formed within the gate structure 58 adjacent to the fork blade structure 60, as shown in fig. 21A. Fig. 21A is a schematic perspective cross-sectional view through four fin structures along line B-B in fig. 2. The gate electrode layer 54 and the conductive cap layer 56 may be patterned and the gate electrode layer 54 and the conductive cap layer 56 cut into two sections through the opening. The openings may then be filled with one or more dielectric materials to form the cut gate structures 62. The cut gate structure 62 electrically isolates two sections of the gate electrode layer 54 and the conductive cap layer 56. A channel region including the semiconductor layer 16a is disposed between the dielectric wall 51 for the fork blade structure 60 and the cut gate structure 62.
The cut gate structure 62 may include one or more dielectric layers. In some embodiments, the cut gate structure 62 may be formed from one or more layers of low-k dielectric material. For example, the cut gate structure 62 may be formed from one or more layers of dielectric material having a dielectric constant of less than about 7. In some embodiments, the dicing gate structure 62 is made of SiO 2 SiN, siCN, siOC, siOCN or one or more layers of other suitable dielectric materials having a dielectric value of less than 7.
As shown in fig. 21A, a portion of the gate electrode layer 54 is disposed between the semiconductor layer 16b and the dicing gate structure 62. The gate electrode layer 54 is disposed between the semiconductor layers 16b, and the cut gate structure 62 has a thickness T4. In some embodiments, the thickness T4 may be in a range between about 5nm and about 10 nm.
In some embodiments, the cut gate structure 62 may be formed prior to forming the replacement gate dielectric layer 52 and the gate electrode layer 54.
In some embodiments, a cut channel structure 64 may be formed between the dielectric wall 51 and the cut gate structure 62, as shown in fig. 21B. Dicing channel structure 64 may be formed by removing semiconductor layer 16b and its surrounding gate structure and then depositing one or more dielectric layers. A dicing channel structure 64 may be formed around the cell edges to achieve the desired circuit function.
In operation 136, source/drain contacts 70 and gate contacts 72 are formed as shown in fig. 22A-22D. Fig. 22A is a schematic cross-sectional view taken along line A-A in fig. 2. Fig. 22B is a schematic perspective sectional view taken along line B-B in fig. 2. Fig. 22C is a schematic cross-sectional view along line C-C in fig. 2. Fig. 22D is a schematic cross-sectional view along line D-D in fig. 2.
In some embodiments, a planarization process may be first performed to expose ILD layer 44 and conductive cap layer 56. In some embodiments, an etch stop layer 66 and an ILD layer 68 may be deposited sequentially over ILD layer 44 and conductive cap layer 56. Contact holes are formed through the various layers using suitable photolithographic and etching techniques to expose the source/drain regions 38 and 40. After the contact holes are formed, a silicide layer (not shown) is selectively formed over the exposed top surfaces of the epitaxial source/drain regions 38, 40 that are exposed by the contact holes. The source/drain contact features 70 are then formed by filling the contact holes with a conductive material. In some embodiments, the conductive material for the source/drain contacts may be formed by CVD, PVD, plating, ALD, or other suitable techniques. In some embodiments, the conductive material may include TiN, taN, ta, ti, hf, zr, ni, W, co, cu, ag, al, zn, ca, au, mg, mo, cr, or the like. Similarly, contact vias are formed through the various layers using suitable photolithographic and etching techniques to expose gate structure 58. A conductive material is then filled in the contact via to form the gate contact 72.
The source/drain contact means 70a is a shared contact means for connecting to the source/drain regions 38, 40 of the two channel regions of the fork blade structure 60. Because the dielectric wall 51 is not present between the source/drain regions 38 and 40, the dielectric wall 51 of the fork blade structure 60 is not damaged or impeded from exposing the source/drain regions 38, 40 during contact hole formation.
Fig. 23 is a flowchart of a method 100a for fabricating a semiconductor device according to an embodiment of the present disclosure. Fig. 24 to 34, 35A to 35B, 36A to 36E, and 37A to 37B schematically illustrate various stages of manufacturing a semiconductor device 10a using a method 100 a. The method 100a includes operations similar to those in the method 100 described above. The same reference numerals are used to denote these same operations.
Operations 102 and 104 of method 100a are similar to operations 102 and 104 of method 100, wherein semiconductor fin structures 20a, 20b are formed, as shown in fig. 24. Fig. 24 is a schematic perspective sectional view taken along line A-A in fig. 2.
In operation 106a, a first sacrificial gate dielectric layer 25 and a second sacrificial gate dielectric layer 26 are sequentially deposited over the exposed surfaces of the semiconductor device 10a, as shown in fig. 24. The first and second sacrificial gate dielectric layers 25, 26 may comprise one or more layers of dielectric material, such as SiO 2 SiN, high-k dielectric material, and/or other suitable dielectric material, and are etch selective with respect to each other. In some embodiments, the first sacrificial gate dielectric layer 25 and the second sacrificial gate dielectric layer 26 are formed of a low-k dielectric material, such as a dielectric material having a k value less than 7. In some embodiments, the first sacrificial gate dielectric layer 25 may be a SiN layer and the second sacrificial gate dielectric layer 26 comprises SiO 2 . In some embodiments, the first sacrificial gate dielectric layer 25 may be conformally deposited and then used to define the gate cap over the channel in the fork strap structure. For example, the thickness T5 of the first sacrificial gate dielectric layer 25 formed on the end portions of the semiconductor layers 16a, 16b may be used to define the thickness of the gate cap. In some embodimentsIn an example, the thickness T5 may be in a range between about 2nm and about 5 nm.
Operations 108, 110, 112, 114, and 116 of method 100a are similar to operations 108, 110, 112, 114, and 116 of method 100, with sacrificial gate structure 24, sidewall spacers 34, inner spacers 36, source/drain regions 38, 40, CESL layer 42, and ILD layer 44 being formed sequentially, as shown in fig. 24-28. Fig. 24 to 28 are schematic perspective sectional views along the line A-A in fig. 2 at different stages.
In operation 118a, a dielectric wall opening is formed within the sacrificial gate electrode layer 28, as shown in fig. 29. Fig. 29 is a schematic perspective sectional view along line B-B in fig. 2. The dielectric fill opening extends along the x-axis within the sacrificial gate structure 24 and terminates at the sidewall spacer 34. Along the y-axis, the dielectric fill opening has a width W3 that is less than the width W1 of the trench 21 between the semiconductor fin structures 20a, 20b, and leaves a gap volume 28g of the sacrificial gate electrode layer 28 between the dielectric fill layer 50a and the second sacrificial gate dielectric layer 26. The gap volume 28g ensures that the first sacrificial gate dielectric layer 25 is not damaged during the patterning process of the dielectric wall opening.
In operation 120a, a dielectric fill layer 50a is deposited in the dielectric fill opening, as shown in fig. 29. Dielectric fill layer 50a extends along the x-axis within sacrificial gate structure 24 and terminates at sidewall spacers 34. Along the y-axis, dielectric fill layer 50a has a width W3 that is less than the width W1 of trench 21. Dielectric fill layer 50a may be a low-k dielectric material such as SiO 2 SiN, siCN, siOC, siOCN or other suitable dielectric material having a dielectric value of less than 7. In some embodiments, dielectric fill layer 50a may be formed of a low-k dielectric material having etch selectivity with respect to second sacrificial gate dielectric layer 26 and first sacrificial gate dielectric layer 25.
In operation 122a, the sacrificial gate electrode layer 28 is removed, as shown in fig. 30. Fig. 30 is a schematic perspective sectional view along line B-B in fig. 2. The sacrificial gate electrode layer 28 may be removed using a plasma dry etch and/or a wet etch. When the sacrificial gate electrode layer 28 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the sacrificial gate electrode layer 28 without removing the dielectric material of the ILD layer 44, CESL 42, or dielectric wall 51 a. As shown in fig. 30, the gap volume 28g is removed, thereby forming an air gap between the dielectric fill layer 50a and the second sacrificial gate dielectric layer 26.
In operation 124a, a second dielectric fill layer 48a is filled in the air gap between the dielectric fill layer 50a and the second sacrificial gate dielectric layer 26, as shown in fig. 31. Fig. 31 is a schematic perspective sectional view along line B-B in fig. 2. In some embodiments, the second dielectric fill layer 48a may be conformally deposited. In some embodiments, the second dielectric fill layer 48a may be formed of a low-k dielectric material, such as SiO 2 SiN, siCN, siOC, siOCN or other suitable dielectric material having a dielectric value of less than 7. In some embodiments, the second dielectric fill layer 48a may be selectively removed from the sidewall spacers 34 and from the first dielectric fill layer 50 a. In some embodiments, the second sacrificial gate dielectric layer 26 and the second dielectric fill layer 48a may be formed of the same material.
In operation 126a, the second dielectric fill layer 48a, the second sacrificial gate dielectric layer 26, and the first sacrificial gate dielectric layer 25 are sequentially removed to expose the fin structures 20a, 20b, as shown in fig. 32 and 33. Fig. 32 and 33 are schematic perspective sectional views along the line B-B in fig. 2.
In fig. 32, the second dielectric fill layer 48a and the second sacrificial gate dielectric layer 26 are selectively removed. The second dielectric fill layer 48a and the sacrificial gate dielectric layer 26 may be removed using a suitable etching process. In some embodiments, an isotropic etching process, such as a wet etching process, may be used to remove the second dielectric fill layer 48a and the second sacrificial gate dielectric layer 26 from the exposed surface regions, leaving portions of the second dielectric fill layer 48a and the second sacrificial gate dielectric layer 26 between the dielectric fill layer 50a and the semiconductor fin structures 20a, 20 b. The first sacrificial gate dielectric layer 25 is exposed.
In fig. 33, a suitable etching process is used to selectively remove the first sacrificial gate dielectric layer 25. In some embodiments, an isotropic etching process, such as a wet etching process, may be used to remove the first sacrificial gate dielectric layer 25 from the exposed surface regions, leaving a portion of the first sacrificial gate dielectric layer 25 between the dielectric fill layer 50a and the semiconductor fin structures 20a, 20 b. The semiconductor layers 14a, 14b are exposed.
As shown in fig. 33, a dielectric wall 51a for a fork piece structure is formed. Dielectric wall 51a includes first dielectric fill layer 50a, second dielectric fill layer 48a, second sacrificial gate dielectric layer 26, and first sacrificial gate dielectric layer 25. A first dielectric fill layer 50a is disposed between the semiconductor fin structures 20a, 20b and extends over the semiconductor fin structures 20a, 20 b. The first dielectric fill layer 50a may be a substantially rectangular pillar having first and second surfaces in contact with the sidewall spacers 34 and terminating at the sidewall spacers 34 and third and fourth surfaces facing the semiconductor fin structures 20a, 20 b. The second dielectric fill layer 48a is disposed on lower portions of the first dielectric fill layer 50a on the third and fourth surfaces facing the semiconductor fin structures 20a, 20 b. The second sacrificial gate dielectric layer 26 is disposed on the bottom surface of the first dielectric fill layer 50a and on the second dielectric fill layer 48 a. At this stage, the first sacrificial gate dielectric layer 25 is disposed outside the second sacrificial gate dielectric layer 26 and surrounds the second sacrificial gate dielectric layer 26. Subsequently, portions of the first sacrificial gate dielectric layer 25 may be further removed to achieve a desired gate profile.
In operation 128, the sacrificial semiconductor layers 14a, 14b are removed from the fin structures 20a, 20b, as shown in fig. 34. Fig. 34 is a schematic perspective sectional view taken along line B-B in fig. 2. In some embodiments, the semiconductor layers 14a, 14b may be removed during the same etching process or different processes. The semiconductor layers 14a, 14b may be selectively removed using a wet etchant such as, but not limited to, ammonium hydroxide (NH) 4 OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution. The removal of the semiconductor layers 14a, 14b creates nanoplatelets of the semiconductor layers 16a, 16b over the third and fourth surfaces of the dielectric wall 51 a. Portions of the first sacrificial gate dielectric layer 25 formed on the sidewalls of the fin structures 20a, 20b are also exposed.
In operation 130a, an etching process is performed to remove at least a portion of the first sacrificial gate dielectric layer 25 formed on the sidewalls of the fin structures 20a, 20B, as shown in fig. 35A and 35B. Fig. 35A and 35B are schematic perspective sectional views along the line B-B in fig. 2.
In some embodiments, the profile of the gate structure to be formed may be controlled by removing a different amount of the first sacrificial gate dielectric layer 25 in operation 130 a. In fig. 35A, a portion of the first sacrificial gate dielectric layer 25 remains between the semiconductor layers 16a/16b and the second sacrificial gate dielectric layer 26. In fig. 35B, the first sacrificial gate dielectric layer 25 is completely removed and the subsequent gate structure may surround all sides of the semiconductor layers 16 a/16B. In some embodiments, operation 130a may be omitted, and the subsequent gate structure may surround the semiconductor layers 16a, 16b from three sides. When more of the first sacrificial gate dielectric layer 25 is removed, the effective length of the subsequent gate structure increases, resulting in improved gate control performance. The low-k dielectric material in the dielectric liner layer 48 improves the Average Capacitance (AC) performance while retaining more of the first sacrificial gate dielectric layer 25.
Operation 132 of method 100a is similar to operation 132 of method 100, wherein replacement gate structure 58 is formed, as shown in fig. 36A-36E. Fig. 36A is a schematic cross-sectional view taken along line A-A in fig. 2. Fig. 36B is a schematic perspective sectional view taken along line B-B in fig. 2. Fig. 36C is a schematic cross-sectional view along line C-C in fig. 2. Fig. 36D is a schematic cross-sectional view taken along line D-D in fig. 2. Replacement gate structure 58 may include gate dielectric layer 52 and gate electrode layer 54. In some embodiments, replacement gate structure 58 also includes a conductive cap layer 56. Fig. 36E is a partially enlarged view of the sectional view in the region B of fig. 36B. Fig. 36E includes details of pi gate profiles in accordance with an embodiment of the present disclosure.
As shown in fig. 36B, the semiconductor layers 16a, 16B, the gate dielectric layer 52, the gate electrode layer 54, and the dielectric wall 51a formed on the semiconductor layers 16a, 16B form a fork-shaped sheet structure 60a. The semiconductor layer 16a forms a first channel region, and the semiconductor layer 16b forms a second channel region. A dielectric wall 51a is disposed between the first channel region and the second channel region. In fig. 36E, a segment of the first sacrificial gate dielectric layer 25 remains on an end portion of the semiconductor layers 16a, 16b. The gate dielectric layer 52 surrounds the channel or semiconductor layers 16a, 16b which are not covered by the first sacrificial gate dielectric layer 25. The gate dielectric layer 52 has a pi-shaped profile in cross section. There may be a portion of the gate electrode layer 54 between the semiconductor layers 16a, 16b and the dielectric wall 51 a. Alternatively, the first sacrificial gate dielectric layer 25 may be completely removed or may be completely retained.
Operation 134 of method 100a is similar to operation 134 of method 100 in that a cut gate structure 62 may be formed within gate structure 58 adjacent to fork blade structure 60a, as shown in fig. 37A. Fig. 37A is a schematic perspective cross-sectional view through four fin structures along line B-B in fig. 2. The gate electrode layer 54 and the conductive cap layer 56 may be patterned and the gate electrode layer 54 and the conductive cap layer 56 cut into two sections through the opening. The openings may then be filled with one or more dielectric materials to form the cut gate structures 62. The cut gate structure 62 electrically isolates two sections of the gate electrode layer 54 and the conductive cap layer 56. A channel region including the semiconductor layer 16a is disposed between the dielectric wall 51a for the fork blade structure 60 and the cut gate structure 62.
In some embodiments, a cut channel structure 64 may be formed between the dielectric wall 51a and the cut gate structure 62, as shown in fig. 37B. Dicing channel structure 64 may be formed by removing semiconductor layer 16b and its surrounding gate structure and then depositing one or more dielectric layers. A dicing channel structure 64 may be formed around the cell edges to achieve the desired circuit function.
The method of forming a fork structure with dielectric walls within a gate structure provides flexibility in gate profile and also flexibility in allowing patterning overlay offset. Fig. 38A and 38B schematically show the shape of the dielectric wall 51 with a stack offset in operation 118. Although the opening 46 may not initially be aligned with the trench 21 between the semiconductor fin structures 20a, 20b, a lower portion of the dielectric wall 51 may be moved back to be aligned with the trench 21.
By confining the dielectric walls within the gate structure, the fork strap structure of embodiments of the present disclosure eliminates leakage problems, reduces source/drain spacing, and increases the volume of the source/drain regions, thus improving device performance. Embodiments of the present disclosure also provide flexibility in gate profile adjustment, thus adjusting capacitive performance or control. Furthermore, the dielectric walls of embodiments of the present disclosure may be formed of low-k materials and thus have improved capacitive performance.
Some embodiments provide a semiconductor device comprising: a first source/drain region; a second source/drain region disposed adjacent to the first source/drain region; fork piece structure includes: a first channel region in contact with the first source/drain region; a second channel region in contact with the second source/drain region; a dielectric wall disposed between the first channel region and the second channel region, wherein the dielectric wall has a first surface facing the first channel region, a second surface facing the second channel region, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface; a first sidewall spacer disposed on a first side of the fork blade structure, wherein the first sidewall spacer is disposed between the first and second source/drain regions and the first and second channel regions; and a second sidewall spacer disposed on a second side of the fork blade structure, wherein the dielectric wall is disposed between the first sidewall spacer and the second sidewall spacer.
Some embodiments provide a semiconductor device comprising: a first source/drain region; a second source/drain region; a first channel region disposed between and connected to the first and second source/drain regions; a first gate structure comprising: a first gate dielectric layer disposed on the first channel region; and a first gate electrode layer disposed on the first gate dielectric layer; a first sidewall spacer and a second sidewall spacer disposed on opposite sides of the first gate structure, wherein the first source/drain region is in contact with the first sidewall spacer and the second source/drain region is in contact with the second sidewall spacer; and a dielectric wall, wherein the dielectric wall has a first end, a second end, and a first surface connecting the first end and the second end, the first end of the dielectric wall terminates at the first sidewall spacer, the second end of the dielectric wall terminates at the second sidewall spacer, and the first gate dielectric layer is in contact with the first surface of the dielectric wall.
Some embodiments provide a method comprising: forming a first fin structure and a second fin structure along a first direction; forming a sacrificial gate structure along a second direction and across the first fin structure and the second fin structure; forming first and second sidewall spacers on opposite sidewalls of the sacrificial gate structure; etching back the first fin structure and the second fin structure to form source/drain openings on opposite sides of the sacrificial gate structure; forming epitaxial source/drain regions in the source/drain openings; forming a wall opening in the sacrificial gate structure between the first sidewall spacer and the second sidewall spacer; forming a dielectric wall in the wall opening between the first sidewall spacer and the second sidewall spacer; removing the sacrificial gate structure; and forming a first replacement gate structure and a second replacement gate structure, wherein the dielectric wall isolates the first replacement gate structure from the second replacement gate structure.
Some embodiments of the present application provide a semiconductor device including: a first source/drain region; a second source/drain region disposed adjacent to the first source/drain region; fork piece structure includes: a first channel region in contact with the first source/drain region; a second channel region in contact with the second source/drain region; a dielectric wall disposed between the first channel region and the second channel region, wherein the dielectric wall has a first surface facing the first channel region, a second surface facing the second channel region, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface; a first sidewall spacer disposed on a first side of the fork blade structure, wherein the first sidewall spacer is disposed between the first and second source/drain regions and the first and second channel regions; and a second sidewall spacer disposed on a second side of the fork blade structure, wherein the dielectric wall is disposed between the first sidewall spacer and the second sidewall spacer. In some embodiments, the semiconductor device further comprises: a first gate dielectric layer disposed on the first channel region; and a first gate electrode layer disposed on the first gate dielectric layer, wherein the first gate dielectric layer is in contact with the first surface of the dielectric wall. In some embodiments, the dielectric wall comprises one or more low-k dielectric materials. In some embodiments, the dielectric wall comprises: a dielectric liner layer; and a dielectric fill layer disposed over the dielectric liner layer, wherein the third and fourth surfaces of the dielectric wall comprise the dielectric liner layer. In some embodiments, the first surface and the second surface of the dielectric wall comprise the dielectric fill layer. In some embodiments, portions of the first and second surfaces of the dielectric wall include the dielectric liner layer. In some embodiments, the dielectric wall comprises: a first dielectric fill layer extending from the third surface to the fourth surface of the dielectric wall; and a second dielectric fill layer disposed on lower portions of the first and second surfaces of the dielectric wall. In some embodiments, the dielectric wall further comprises: and the sacrificial dielectric layer is arranged on the second dielectric filling layer. In some embodiments, the semiconductor device further comprises: a cut gate dielectric extending between the first sidewall spacer and the second sidewall spacer, wherein the cut gate dielectric and the dielectric wall are disposed on opposite sides of the first channel region.
Still further embodiments of the present application provide a semiconductor device comprising: a first source/drain region; a second source/drain region; a first channel region disposed between and connected to the first and second source/drain regions; a first gate structure comprising: a first gate dielectric layer disposed on the first channel region; and a first gate electrode layer disposed on the first gate dielectric layer; a first sidewall spacer and a second sidewall spacer disposed on opposite sides of the first gate structure, wherein the first source/drain region is in contact with the first sidewall spacer and the second source/drain region is in contact with the second sidewall spacer; and a dielectric wall, wherein the dielectric wall has a first end, a second end, and a first surface connecting the first end and the second end, the first end of the dielectric wall terminates at the first sidewall spacer, the second end of the dielectric wall terminates at the second sidewall spacer, and the first gate dielectric layer is in contact with the first surface of the dielectric wall. In some embodiments, the dielectric wall comprises: a dielectric liner layer; and a dielectric fill layer disposed over the dielectric liner layer, wherein the first surface includes the dielectric fill layer and a portion of the dielectric liner layer extending from the dielectric fill layer, and the portion of the dielectric liner layer is in contact with the first channel region. In some embodiments, the first channel region includes two or more semiconductor channels, and the first gate dielectric layer is formed on each of the semiconductor channels, and the portion of the dielectric liner layer has a height that is shorter than a height of the semiconductor channels. In some embodiments, the first gate dielectric layer has a pi-shaped profile. In some embodiments, the semiconductor device further comprises: a third source/drain region; a fourth source/drain region; a second channel region disposed between and connected to the third and fourth source/drain regions; and a second gate structure comprising: a second gate dielectric layer disposed on the second channel region; and a second gate electrode layer disposed on the second gate dielectric layer, wherein the dielectric wall has a second surface opposite the first surface and connecting the first end and the second end of the dielectric wall, and the second gate dielectric layer is in contact with the second surface of the dielectric wall.
Still further embodiments of the present application provide a method of manufacturing a semiconductor device, comprising: forming a first fin structure and a second fin structure along a first direction; forming a sacrificial gate structure along a second direction and across the first fin structure and the second fin structure; forming first and second sidewall spacers on opposite sidewalls of the sacrificial gate structure; etching back the first fin structure and the second fin structure to form source/drain openings on opposite sides of the sacrificial gate structure; forming epitaxial source/drain regions in the source/drain openings; forming a wall opening in the sacrificial gate structure between the first sidewall spacer and the second sidewall spacer; forming a dielectric wall in the wall opening between the first sidewall spacer and the second sidewall spacer; removing the sacrificial gate structure; and forming a first replacement gate structure and a second replacement gate structure, wherein the dielectric wall isolates the first replacement gate structure from the second replacement gate structure. In some embodiments, forming the sacrificial gate structure includes: depositing a sacrificial gate dielectric layer; depositing a sacrificial gate electrode layer over the sacrificial gate dielectric layer; and patterning the sacrificial gate electrode layer and the sacrificial gate dielectric layer to form the sacrificial gate structure, wherein the wall opening is formed through the sacrificial gate electrode layer and the sacrificial gate dielectric layer is exposed in the wall opening. In some embodiments, forming the dielectric wall comprises: removing the sacrificial gate dielectric layer from the first fin structure and the second fin structure; depositing a dielectric liner layer in the wall opening; and depositing a dielectric fill layer over the dielectric liner layer. In some embodiments, the first fin structure includes two or more first semiconductor layers stacked alternately with two or more second semiconductor layers, the method further comprising: removing the two or more second semiconductor layers from the first fin structure after removing the sacrificial gate structure; and removing at least a portion of the dielectric liner layer disposed between the two or more first semiconductor layers and the dielectric fill layer. In some embodiments, forming the sacrificial gate structure includes: depositing a first sacrificial gate dielectric layer; depositing a second sacrificial gate dielectric layer over the first sacrificial gate dielectric layer; depositing a sacrificial gate electrode layer over the second sacrificial gate dielectric layer; and patterning the sacrificial gate electrode layer, the second sacrificial gate dielectric layer, and the first sacrificial gate dielectric layer to form the sacrificial gate structure, wherein the wall opening is formed within the sacrificial gate electrode layer and a gap volume of the sacrificial gate electrode layer remains between the wall opening and the first fin structure. In some embodiments, forming the dielectric wall comprises: depositing a first dielectric fill layer in the wall opening; removing the sacrificial gate electrode layer and forming an air gap in the gap volume; and depositing a second dielectric fill layer in the air gap.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they may readily use the presently disclosed embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments presented herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims (10)

1. A semiconductor device, comprising:
a first source/drain region;
a second source/drain region disposed adjacent to the first source/drain region;
fork piece structure includes:
a first channel region in contact with the first source/drain region;
a second channel region in contact with the second source/drain region;
a dielectric wall disposed between the first channel region and the second channel region, wherein the dielectric wall has a first surface facing the first channel region, a second surface facing the second channel region, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface;
A first sidewall spacer disposed on a first side of the fork blade structure, wherein the first sidewall spacer is disposed between the first and second source/drain regions and the first and second channel regions; and
and a second sidewall spacer disposed on a second side of the fork blade structure, wherein the dielectric wall is disposed between the first sidewall spacer and the second sidewall spacer.
2. The semiconductor device of claim 1, further comprising:
a first gate dielectric layer disposed on the first channel region; and
and a first gate electrode layer disposed on the first gate dielectric layer, wherein the first gate dielectric layer is in contact with the first surface of the dielectric wall.
3. The semiconductor device of claim 2, wherein the dielectric wall comprises one or more low-k dielectric materials.
4. The semiconductor device of claim 3, wherein the dielectric wall comprises:
a dielectric liner layer; and
a dielectric fill layer disposed over the dielectric liner layer, wherein the third and fourth surfaces of the dielectric wall comprise the dielectric liner layer.
5. The semiconductor device of claim 4, wherein the first and second surfaces of the dielectric wall comprise the dielectric fill layer.
6. The semiconductor device of claim 5, wherein portions of the first and second surfaces of the dielectric wall comprise the dielectric liner layer.
7. The semiconductor device of claim 3, wherein the dielectric wall comprises:
a first dielectric fill layer extending from the third surface to the fourth surface of the dielectric wall; and
a second dielectric fill layer is disposed on lower portions of the first and second surfaces of the dielectric wall.
8. The semiconductor device of claim 7, wherein the dielectric wall further comprises:
and the sacrificial dielectric layer is arranged on the second dielectric filling layer.
9. A semiconductor device, comprising:
a first source/drain region;
a second source/drain region;
a first channel region disposed between and connected to the first and second source/drain regions;
a first gate structure comprising:
A first gate dielectric layer disposed on the first channel region; and
a first gate electrode layer disposed on the first gate dielectric layer;
a first sidewall spacer and a second sidewall spacer disposed on opposite sides of the first gate structure, wherein the first source/drain region is in contact with the first sidewall spacer and the second source/drain region is in contact with the second sidewall spacer; and
a dielectric wall, wherein the dielectric wall has a first end, a second end, and a first surface connecting the first end and the second end, the first end of the dielectric wall terminates at the first sidewall spacer, the second end of the dielectric wall terminates at the second sidewall spacer, and the first gate dielectric layer is in contact with the first surface of the dielectric wall.
10. A method of manufacturing a semiconductor device, comprising:
forming a first fin structure and a second fin structure along a first direction;
forming a sacrificial gate structure along a second direction and across the first fin structure and the second fin structure;
forming first and second sidewall spacers on opposite sidewalls of the sacrificial gate structure;
Etching back the first fin structure and the second fin structure to form source/drain openings on opposite sides of the sacrificial gate structure;
forming epitaxial source/drain regions in the source/drain openings;
forming a wall opening in the sacrificial gate structure between the first sidewall spacer and the second sidewall spacer;
forming a dielectric wall in the wall opening between the first sidewall spacer and the second sidewall spacer;
removing the sacrificial gate structure; and
a first replacement gate structure and a second replacement gate structure are formed, wherein the dielectric wall isolates the first replacement gate structure from the second replacement gate structure.
CN202311461422.4A 2022-11-05 2023-11-03 Semiconductor device and method for manufacturing the same Pending CN117637845A (en)

Applications Claiming Priority (3)

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US63/422,944 2022-11-05
US18/106,724 2023-02-07
US18/106,724 US20240154014A1 (en) 2022-11-05 2023-02-07 Semiconductor device and method for manufacturing thereof

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