CN117637824A - Semiconductor groove type voltage driving device and manufacturing method thereof - Google Patents
Semiconductor groove type voltage driving device and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
The application discloses a semiconductor groove type voltage driving device and a manufacturing method thereof, and relates to the field of semiconductor device manufacturing, wherein a device structure comprises a drain electrode substrate, an active layer, an interlayer film and a metal source electrode layer, and the drain electrode substrate is provided with first grooves which are parallel to each other; the isolation gate and the grid are arranged in the first groove, the isolation gate is arranged at the bottom of the first groove, a first gate oxide layer is arranged between the two sides and the bottom of the isolation gate and the inner wall of the first groove, the grid is arranged above the isolation gate, a second gate oxide layer is arranged between the grid and the inner wall of the first groove, a thickening structure is arranged at the corner position of the first groove, and the thickening structure is covered by the second gate oxide layer. An active layer is formed in the drain substrate, an interlayer film is formed on the first trench and the active layer, and a metal source layer is formed on the drain substrate and fills the second trench. The method has the effect of improving the reliability of the gate oxide by increasing the thickness of the gate oxide.
Description
Technical Field
The present disclosure relates to semiconductor device manufacturing, and more particularly, to a semiconductor trench type voltage driving device and a method for manufacturing the same.
Background
High reliability voltage driven devices are a common type of semiconductor device commonly used for high frequency and high power applications. These devices include Trench field effect transistors (Trench MOSFETs), high reliability bipolar transistors (Trench Bipolar Transistor), and the like, which play an important role in the power electronics field.
For a high-reliability voltage driven device, the reliability of gate oxide is a primary key factor for limiting the reliability of the device. The primary factors influencing the reliability of the gate oxide are that the upper and lower corners of the trench bear higher positive-negative maximum electric fields respectively due to the gate oxide quality defect caused by the difference of lattice crystal phases.
At present, two approaches for solving the reliability of the gate oxide layer are mainly adopted, one approach is to improve the quality of the gate oxide layer so that the gate oxide layer can bear a higher electric field, and only improvement can be made in terms of materials; the other is to protect the gate oxide layer without degrading the device performance, so that the electric field applied to the gate oxide layer is reduced, the on-resistance is increased by the method, and the effect is not obvious.
Therefore, how to provide a method for effectively improving the reliability of the gate oxide is a problem to be solved.
Disclosure of Invention
In order to solve the above problems, the present application provides a semiconductor trench type voltage driving device and a method of manufacturing the same.
In a first aspect, the present application provides a semiconductor trench type voltage driving device, comprising:
a drain electrode substrate provided with first grooves parallel to each other; an isolation gate and a grid are arranged in the first groove, the isolation gate is arranged at the bottom of the first groove, first grid oxide layers are arranged on the two sides and between the bottom of the isolation gate and the inner wall of the first groove, the grid is arranged above the isolation gate, a second grid oxide layer is arranged between the grid and the inner wall of the first groove, a thickening structure is arranged at the corner position of the first groove, and the thickening structure is covered by the second grid oxide layer;
the active layer is formed in the drain electrode substrate and comprises an N+ region and a P-region from top to bottom, a second groove is formed by the active layer and is positioned between the first grooves, the bottom of the second groove is the P+ region, and the depth of the second groove is larger than that of the N+ region but insufficient to penetrate through the active layer;
an interlayer film formed on the first trench and the active layer, wherein a portion on the first trench is directly connected to the gate electrode, and a portion on the active layer covers the second gate oxide layer;
and a metal source layer formed on the drain electrode substrate and filling the second trench, wherein the metal source layer is isolated from the active layer and the interlayer film by a metal barrier layer.
Optionally, the thickening structure symmetry set up in the top both sides corner position of first slot, bottom one side of thickening structure with the N+ field lug connection of active layer, the bottom opposite side with the grid passes through the second gate oxide layer keeps apart, the top of thickening structure passes through the second gate oxide layer with interlayer film keeps apart.
Optionally, the thickening structure symmetry set up in the bottom both sides corner position of first slot, the outside of thickening structure with inside lug connection of first slot, the grid is located thickening structure top and downwardly extending to the thickening structure centre is until the isolation gate, the grid with keep apart through the second gate oxide layer between the thickening structure, the bottom of thickening structure respectively with the isolation gate with first gate oxide layer is connected.
Optionally, the thickening structure comprises a first thickening structure and a second thickening structure,
the first thickening structures are symmetrically arranged at corner positions of two sides of the top of the first groove, one side of the bottom of each first thickening structure is directly connected with the N+ field of the active layer, the other side of the bottom of each first thickening structure is isolated from the grid electrode through the second grid oxide layer, and the top of each first thickening structure is isolated from the interlayer film through the second grid oxide layer;
the second thickening structure is symmetrically arranged at corner positions at two sides of the bottom of the first groove, the outer side of the second thickening structure is directly connected with the inside of the first groove, the grid electrode is arranged above the second thickening structure and extends downwards to the middle of the second thickening structure until the isolation grid is arranged between the second thickening structure, the grid electrode and the second thickening structure are isolated through the second grid oxide layer, and the bottom of the second thickening structure is respectively connected with the isolation grid and the first grid oxide layer.
Optionally, the thickened structure is formed by a LOCOS process.
In a second aspect, the present application provides a method for manufacturing a semiconductor trench type voltage driving device, comprising:
providing a drain electrode substrate, wherein the drain electrode substrate is provided with a processing surface, and after the first surface acidification, first grooves which are parallel to each other are formed by etching the processing surface;
forming an isolation gate in the first trench through first polysilicon deposition;
forming a thickening structure at the corner position of the first groove by using a lcos process;
forming a gate within the first trench, forming an active layer under the processing surface of the drain substrate;
an electrical connection structure is formed between the first trenches by etching the second trenches, and an electrode is formed over the active layer and the first trenches.
Optionally, the forming the isolation gate in the first trench by the first polysilicon deposition specifically includes:
forming a first gate oxide layer on the processing surface and in the first groove; depositing first polysilicon on the first gate oxide layer to enable the first polysilicon layer to fill the first groove;
removing other parts of the first polysilicon layer, which are positioned at the bottom of the first groove and are used for forming isolation gates, from the first polysilicon layer;
removing the rest part of the first gate oxide layer except the junction with the isolation gate;
the forming of the thickening structure at the corner position of the first groove by using a lcos process specifically includes:
performing secondary surface acidification and silicon nitride precipitation;
carrying out silicon nitride etching and removal of second surface acidification by using the outline of the thickened structure at the corner position of the first groove;
forming a thickening structure at the corner position of the first groove by using a lcos process;
forming a second gate oxide layer on the treatment surface, the thickening structure and the isolation gate;
forming a gate in the first trench and forming an active layer under the processing surface of the drain substrate, specifically including:
depositing second polysilicon on the second gate oxide layer to enable the second polysilicon layer to fill the first groove;
removing other parts of the second polysilicon layer, which are positioned in the bottom of the first trench and are used for forming a grid electrode;
forming an active layer below the processing surface of the drain electrode substrate in an energy injection mode, and forming an N+ field and a P-field from top to bottom;
the second trench formed by etching between the first trenches forms an electrical connection structure, and an electrode is formed over the active layer and the first trench, specifically including:
forming an interlayer film over the active layer and the first trench in a deposition coverage manner;
etching the interlayer film and the active layer to form a second groove, wherein the second groove is positioned between the first grooves, the depth of the second groove is larger than that of the N+ field but insufficient to penetrate the active layer, and a P+ field is formed at the bottom of the second groove;
and forming a metal barrier layer above the active layer, the first groove and the second groove in a deposition covering mode, forming a metal source layer above the metal barrier layer, and filling the second groove.
Optionally, the thickening structure symmetry set up in the top both sides corner position of first slot, bottom one side of thickening structure with the N+ field lug connection of active layer, the bottom opposite side with the grid passes through the second gate oxide layer keeps apart, the top of thickening structure passes through the second gate oxide layer with interlayer film keeps apart.
Optionally, the thickening structure symmetry set up in the bottom both sides corner position of first slot, the outside of thickening structure with inside lug connection of first slot, the grid is located thickening structure top and downwardly extending to the thickening structure centre is until the isolation gate, the grid with keep apart through the second gate oxide layer between the thickening structure, the bottom of thickening structure respectively with the isolation gate with first gate oxide layer is connected.
Optionally, the thickening structure comprises a first thickening structure and a second thickening structure,
the first thickening structures are symmetrically arranged at corner positions of two sides of the top of the first groove, one side of the bottom of each first thickening structure is directly connected with the N+ field of the active layer, the other side of the bottom of each first thickening structure is isolated from the grid electrode through the second grid oxide layer, and the top of each first thickening structure is isolated from the interlayer film through the second grid oxide layer;
the second thickening structure is symmetrically arranged at corner positions at two sides of the bottom of the first groove, the outer side of the second thickening structure is directly connected with the inside of the first groove, the grid electrode is arranged above the second thickening structure and extends downwards to the middle of the second thickening structure until the isolation grid is arranged between the second thickening structure, the grid electrode and the second thickening structure are isolated through the second grid oxide layer, and the bottom of the second thickening structure is respectively connected with the isolation grid and the first grid oxide layer.
In summary, the present application includes the following beneficial technical effects:
aiming at the problem that the reliability of the device is reduced due to the fact that the grooves bear higher positive negative maximum electric fields at the upper corner and the lower corner of the grooves of the groove type voltage driving device, a novel structure is provided, and a thickening structure is arranged at the corners of the grooves, so that the thickness of gate oxide at the corresponding positions is increased, the electric field of a gate oxide layer is reduced, and the reliability of the gate oxide of the device is improved.
The structure can be applied to various groove structure devices and is used for improving the reliability of the devices.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor trench type voltage driving device provided in an embodiment of the present application.
Fig. 2 is a schematic diagram of a drain substrate provided during the fabrication of a semiconductor trench-type voltage driven device according to an embodiment of the present application.
Fig. 3 is a schematic diagram of forming first trenches parallel to each other by etching a processing surface of a drain substrate in a process of manufacturing a semiconductor trench type voltage driving device according to an embodiment of the present application.
Fig. 4 is a schematic diagram of forming a first gate oxide layer and performing a first polysilicon deposition in the process of manufacturing a semiconductor trench type voltage driven device according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a process for partially removing a first polysilicon deposit to form an isolation gate in the process of manufacturing a semiconductor trench type voltage driving device according to an embodiment of the present application.
Fig. 6 is a schematic diagram of a partial removal of a first gate oxide layer in a process of manufacturing a semiconductor trench type voltage driving device according to an embodiment of the present application.
Fig. 7 is a schematic diagram of second surface acidification and silicon nitride deposition during fabrication of a semiconductor trench voltage driven device according to an embodiment of the present application.
Fig. 8 is a schematic diagram of the removal of silicon nitride etching and second surface acidification with the profile of the thickened structure at the corner position of the first trench in the process of manufacturing the semiconductor trench type voltage driven device according to the embodiment of the present application.
Fig. 9 is a schematic diagram of forming a thickened structure in the process of manufacturing a semiconductor trench type voltage driving device according to an embodiment of the present application.
Fig. 10 is a schematic diagram of forming a second gate oxide layer in the process of manufacturing a semiconductor trench type voltage driving device according to an embodiment of the present application.
Fig. 11 is a schematic diagram of forming a second polysilicon precipitate during the process of manufacturing a semiconductor trench type voltage driven device according to an embodiment of the present application.
Fig. 12 is a schematic diagram of removing a portion of the second polysilicon deposit in the process of manufacturing a semiconductor trench type voltage driven device according to an embodiment of the present application.
Fig. 13 is a schematic view of active layer formation in the process of manufacturing a semiconductor trench type voltage driving device according to an embodiment of the present application.
Fig. 14 is a schematic view of interlayer film formation in the process of manufacturing a semiconductor trench type voltage driven device provided in an embodiment of the present application.
Fig. 15 is a schematic diagram of Contact formation in the process of manufacturing a semiconductor trench type voltage driving device according to an embodiment of the present application.
Fig. 16 is a schematic diagram of electrode formation during the fabrication of a semiconductor trench type voltage driven device according to an embodiment of the present application.
Reference numerals:
drain substrate 10: a first trench 11; an isolation gate 12; a gate electrode 13; a first gate oxide layer 14; a second gate oxide layer 15; a second trench 16; a first polysilicon layer 17; a second polysilicon layer 18; a first thickening structure 21; a second thickening structure 22; thickened structure position 23; an active layer 30; an interlayer film 40; a metal barrier layer 41; a metal source layer 50.
Detailed Description
In order to make the technical solutions in the present specification better understood by those skilled in the art, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments.
In the description of embodiments of the present application, words such as "exemplary," "such as" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "illustrative," "such as" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "illustratively," "such as" or "for example," etc., is intended to present related concepts in a concrete fashion.
In the description of the embodiments of the present application, the term "plurality" means two or more unless otherwise indicated. For example, a plurality of systems means two or more systems, and a plurality of screen terminals means two or more screen terminals. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating an indicated technical feature. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
In order to facilitate understanding of the technical solution of the present invention, the semiconductor trench type voltage driving device and the manufacturing method thereof of the present invention are described and explained in further detail below, but are not intended to limit the scope of protection of the present invention. It should be understood by those skilled in the art that the source and drain referred to in this specification are relative concepts and not absolute concepts, and that in the specific application of the variant, the exemplary source may be used as a drain connection, the exemplary drain may be used as a source connection, the source described in this specification may be used as a source connection, the drain described in this specification may necessarily be used as a drain connection, the source described in this specification may be used as a drain connection, and the drain described in this specification may necessarily be used as a source connection.
Fig. 1 is a schematic diagram showing a partial structure of a semiconductor trench type voltage driving device according to some preferred embodiments of the present invention, and fig. 2 to 16 are schematic diagrams showing individual steps in the manufacturing process of the semiconductor trench type voltage driving device according to some preferred embodiments of the present invention. The drawings include portions common to many embodiments, and portions having differences or differences in the modified embodiments are described in a text manner. Thus, based on the industrial characteristics and technical essence, those skilled in the art should correctly and reasonably understand and determine whether individual features or any combination of several features described below can be characterized in the same embodiment or whether features mutually exclusive in technical essence can be characterized only in different variant embodiments.
Referring to fig. 1, a semiconductor trench voltage driving device according to an embodiment of the present invention mainly includes:
a drain substrate 10 provided with first trenches 11 parallel to each other; the isolation gate 12 and the grid 13 are arranged in the first groove 11, the isolation gate 12 is arranged at the bottom of the first groove 11, a first grid oxide layer 14 is arranged between two sides and the bottom of the isolation gate 12 and the inner wall of the first groove 11, the grid 13 is arranged above the isolation gate 12, a second grid oxide layer 15 is arranged between the grid 13 and the inner wall of the first groove 11, a thickening structure is arranged at the corner position of the first groove 11, and the thickening structure is covered by the second grid oxide layer 15.
An active layer 30 formed in the drain substrate 10, including an n+ region and a P-region from top to bottom, a second trench 16 formed by the active layer 30 and located between the first trenches 11, the bottom of the second trench 16 being the p+ region, the depth of the second trench 16 being greater than the n+ region but insufficient to penetrate the active layer 30;
an interlayer film 40 formed on the first trench 11 and the active layer 30, wherein a portion located on the first trench 11 is directly connected to the gate electrode 13, and a portion located on the active layer 30 is covered on the second gate oxide layer 15;
a metal source layer 50 formed on the drain substrate 10 and filling the second trench 16, and isolated from the active layer 30 and the interlayer film 40 by a metal barrier layer 41.
Specifically, the first trench 11 includes two corners at the top opening and two corners at the bottom, and the upper and lower corners of the device are subjected to a higher electric field during operation, so that the thickened structure is arranged in a manner corresponding to the positions of the corners.
As an implementation manner of the embodiment of the present invention, a thickening structure may be symmetrically disposed at corner positions on two sides of the top of the first trench 11, one side of the bottom of the thickening structure is directly connected to the n+ region of the active layer 30, the other side of the bottom of the thickening structure is isolated from the gate 13 by the second gate oxide layer 15, and the top of the thickening structure is isolated from the interlayer film 40 by the second gate oxide layer 15. Such an arrangement is mainly considered for reinforcement at the top corners.
As another implementation manner of the embodiment of the present invention, a thickening structure may be symmetrically disposed at corner positions on two sides of the bottom of the first trench 11, the outer side of the thickening structure is directly connected with the inside of the first trench 11, the gate 13 is located above the thickening structure and extends downward to the middle of the thickening structure until the isolation gate 12, the gate 13 is isolated from the thickening structure by the second gate oxide layer 15, and the bottom of the thickening structure is respectively connected with the isolation gate 12 and the first gate oxide layer 14. Such an arrangement is mainly considered for reinforcement at the bottom corners.
As a preferred implementation manner of the embodiment of the present invention, the two foregoing implementation manners may be combined, the thickening structure includes a first thickening structure 21 and a second thickening structure 22, the first thickening structure 21 is symmetrically disposed at corner positions on two sides of the top of the first trench 11, one side of the bottom of the first thickening structure 21 is directly connected to the n+ region of the active layer 30, the other side of the bottom is isolated from the gate 13 by the second gate oxide layer 15, and the top of the first thickening structure 21 is isolated from the interlayer film 40 by the second gate oxide layer 15; the second thickening structures 22 are symmetrically arranged at corner positions at two sides of the bottom of the first groove 11, the outer sides of the second thickening structures 22 are directly connected with the inside of the first groove 11, the grid 13 is located above the second thickening structures 22 and extends downwards to the middle of the second thickening structures 22 until the isolation grid 12 is arranged, the grid 13 is isolated from the second thickening structures 22 through the second grid oxide layer 15, and the bottoms of the second thickening structures 22 are respectively connected with the isolation grid 12 and the first grid oxide layer 14.
The principle of realizing the effect of improving the reliability of the gate oxide through the thickening structure is as follows:
definition of electric field E of gate oxide layer at corner based on trench
E=V/T
When the bias voltage V is unchanged, the thickness T of the gate oxide layer is increased, so that E can be reduced. Through the thickening structure arranged at the corner, and the second gate oxide layer 15 is covered on the thickening structure, the total thickness T is increased, and then the electric field E of the gate oxide layer is reduced, so that the gate oxide reliability of the device is improved.
The thickening structure is made of silicon oxide, and for the formation of the thickening structure, in the examples of the present application, a preferred embodiment thereof is formed by a LOCOS process. The LOCOS process has lower costs, it uses conventional oxidation and diffusion steps, does not require additional material or equipment investment, and is therefore more economical in the manufacturing process.
It should be noted that, as other embodiments, other processes for forming the thickened structure may be used, which are not particularly limited in the present invention.
The thickened structure provided in the embodiment of the invention can be used for not only the device structure shown in fig. 1, but also other voltage driving devices with a groove structure and the reliability of gate oxide at the corner of the groove.
On the basis of the above embodiments, referring to fig. 2 to 16, the method for manufacturing the semiconductor trench type voltage driving device according to the present invention, which is provided for other embodiments of the present invention, is used for manufacturing the semiconductor trench type voltage driving device according to any of the above combinations of technical solutions, and the process steps S2 to S16 are in the same corresponding manner as the reference numerals for easy understanding and description.
Referring first to fig. 2, a drain substrate 10 is provided in step S2, and the drain substrate 10 is typically in the form of a wafer, specifically a silicon wafer. The treated surface of the drain substrate 10 is provided with a surface acidification film after the first surface acidification, which has the function of a hard mask to facilitate the formation of the first trench 11 in the subsequent process.
Referring to fig. 3, in step S3, first trenches 11 parallel to each other are etched on the surface to be processed, and the surface acidification film is removed after the first trenches 11 are formed. The formation of the first trench 11 is realized by adopting a Deep Trench Etching process method.
The process illustrated in fig. 4-6 is to form isolation gates within the first trenches by a first polysilicon deposition.
Specifically, referring to fig. 4, a corresponding step S4 is to form a first gate oxide layer 14 on the processing surface and in the first trench 11; and a first polysilicon deposition is performed on the first gate oxide layer 14 such that the first polysilicon layer 17 fills the first trench.
The inner wall of the first trench 11 is insulated by a first gate oxide layer 14. The first gate oxide layer 14 may be a thermal oxide layer or/and a deposited oxide layer, but is not limited to these two.
Referring to fig. 5, in step S5, the first polysilicon layer 17 is removed and located at the bottom of the first trench 11 to form other parts except the isolation gate 12. By removing the excess polysilicon deposit, an isolation gate 12 is formed at the bottom of the first trench 11.
Referring to fig. 6, a corresponding step S6 is to remove the remaining portion of the first gate oxide layer 14 except at the junction with the isolation gate 12. The portion of the first gate oxide layer 14 remaining in the first trench 11 is not higher than the isolation gate 12, and the first gate oxide layer 14 and the top of the isolation gate 12 are in the same plane for supporting the second thickened structure 22 disposed at the bottom corner of the first trench 11.
The process illustrated in fig. 7-10 is to form a thickened structure at the corner location of the first trench using a lcos process.
Specifically, referring to fig. 7, in step S7, a second surface acidification and silicon nitride precipitation are performed to form a protective layer, so that the subsequent formation of a thickened structure is facilitated.
Referring to fig. 8, in step S8, a mask is used to cover the outline of the thickened structure at the corner of the first trench 11, and a silicon nitride etching is performed at the thickened structure 23 to expose the second surface acidification layer. Etching is performed on the surface of the silicon nitride precipitate in a Locos Photo mode, and the etched position corresponds to the position where a thickening structure needs to be formed.
Referring to fig. 9, in step S9, a thickened structure is formed at a corner of the first trench, the silicon nitride and the second surface acidification layer are removed, and a Locos acidification process is used to remove the second surface acidification layer at the thickened structure to obtain a thickened structure. The thickness of the thickened structure formed by LOCOS process is generally several hundred nanometers to several micrometers, which is far greater than the thickness of the gate oxide layer, and meanwhile, the thickened structure is only arranged at the corner of the first groove 11, so that the performance of the device is not reduced due to the too thick oxide layer.
Referring to fig. 10, a second gate oxide layer 15 is formed in step S10, and the second gate oxide layer 15 is formed on the processing surface, the thickened structure, and the isolation gate 12. The second gate oxide layer 15 is formed on the same principle as the first gate oxide layer 14.
The process shown in fig. 11-13 is to form a gate within the first trench and an active layer below the treated surface of the drain substrate.
Specifically, referring to fig. 11, a second polysilicon layer is deposited on the second gate oxide layer 15 corresponding to step S11, so that the second polysilicon layer 18 fills the first trench 11. The second polysilicon deposition is mainly used to form the gate 13.
Referring to fig. 12, corresponding step S12 is the formation of the gate 13. The second polysilicon layer 18 is removed and is located in the first trench 11 to form other parts except the gate 13, and the height of the gate 13 is lower than the processing plane.
Referring to fig. 13, a corresponding step S13 is to form an active layer 30, and form the active layer 30 under the processing surface of the drain substrate 10 by energy implantation, including an n+ region and a P-region from top to bottom.
In the present embodiment, the active layer 30 is formed by implanting energy into the drain substrate 10. As an optimized implementation of the present embodiment, the formation of the active layer 30 may be performed before the execution of the other steps described above, taking into consideration actual process production requirements.
As another embodiment, the active layer 30 may be formed by a deposition process, and it should be noted that, when another process is used, the execution time of the step needs to be adjusted correspondingly, and the step is performed before the execution of any of the other steps.
Fig. 14-16 show the process of forming an electrical connection between the first trenches by etching a second trench, forming an electrode over the active layer and the first trench.
Specifically, referring to fig. 14, an interlayer film 40 is formed in step S14, and the interlayer film 40 is formed over the active layer 30 and the first trench 11 in a deposition coverage manner. The interlayer film 40 is a thin film material for isolating and electrically insulating between different metal layers. The interlayer film 40 is typically made of a material having good electrical insulating properties, such as silicon dioxide (SiO 2), silicon nitride (Si 3N 4), low-k materials, or the like. The materials have higher electrical insulation performance, can effectively prevent the current from flowing, and have lower capacitive coupling effect. A common method of fabricating interlayer film 40 is to deposit a thin film of material between metal layers by Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) techniques. After the deposition is completed, photolithography, etching, and other process steps are typically performed to form the complete interlayer film 40 structure.
Referring to fig. 15, in response to step S15, contact is formed, the interlayer film 40 and the active layer 30 are etched to form the second trench 16, the second trench 16 is located between the first trenches 11, the depth of the second trench 16 is greater than the n+ region but insufficient to penetrate the active layer 30, and a p+ region is formed at the bottom of the second trench 16. The p+ region may also be formed by energy implantation. The p+ region is used to counteract the schottky effect while increasing the conductive effect.
Referring to fig. 16, in step S16, an electrode is formed, a metal barrier layer 41 is formed over the active layer 30, the first trench 11 and the second trench 16 in a deposition coverage manner, a metal source layer 50 is formed over the metal barrier layer 41, and the second trench 16 is filled with source metal.
The metal barrier layer 41 is used to prevent interdiffusion between the metal and the medium: the metal barrier layer 41 prevents diffusion of metal atoms into surrounding materials, avoiding unnecessary reactions and damage, thereby protecting the interface of metal and other materials. Meanwhile, the adhesion between the metal and the medium can be improved, the binding force between the metal and the medium is enhanced, and the peeling and fracture of the interface are reduced. Common materials for the metal barrier layer 41 include titanium (Ti), tungsten (W), molybdenum (Mo), and the like.
Through the steps S2-S16, the manufacturing of the device structure with the thickened structure and high gate oxide reliability is completed, and the thickened structure is arranged at the corner of the groove, so that the gate oxide thickness at the corresponding position is increased, the electric field of the gate oxide layer is further reduced, and the gate oxide reliability of the device is improved. The method is applicable to any trench-type voltage driving device with the requirement of reducing the electric field intensity at the corners of the trench.
The embodiments of the present invention are all preferred embodiments for easy understanding or implementation of the technical solution of the present invention, and are not limited in scope by the present invention, and all equivalent changes according to the structure, shape and principle of the present invention should be covered in the scope of the claimed invention.
Claims (10)
1. A semiconductor trench type voltage driving device, comprising:
a drain electrode substrate provided with first grooves parallel to each other; an isolation gate and a grid are arranged in the first groove, the isolation gate is arranged at the bottom of the first groove, first grid oxide layers are arranged on the two sides and between the bottom of the isolation gate and the inner wall of the first groove, the grid is arranged above the isolation gate, a second grid oxide layer is arranged between the grid and the inner wall of the first groove, a thickening structure is arranged at the corner position of the first groove, and the thickening structure is covered by the second grid oxide layer;
the active layer is formed in the drain electrode substrate and comprises an N+ region and a P-region from top to bottom, a second groove is formed by the active layer and is positioned between the first grooves, the bottom of the second groove is the P+ region, and the depth of the second groove is larger than that of the N+ region but insufficient to penetrate through the active layer;
an interlayer film formed on the first trench and the active layer, wherein a portion on the first trench is directly connected to the gate electrode, and a portion on the active layer covers the second gate oxide layer;
and a metal source layer formed on the drain electrode substrate and filling the second trench, wherein the metal source layer is isolated from the active layer and the interlayer film by a metal barrier layer.
2. The semiconductor trench type voltage driving device according to claim 1, wherein the thickening structure is symmetrically arranged at corner positions of two sides of the top of the first trench, one side of the bottom of the thickening structure is directly connected with the n+ region of the active layer, the other side of the bottom of the thickening structure is isolated from the gate electrode by the second gate oxide layer, and the top of the thickening structure is isolated from the interlayer film by the second gate oxide layer.
3. The semiconductor trench type voltage driving device according to claim 1, wherein the thickened structure is symmetrically arranged at corner positions at two sides of the bottom of the first trench, the outer side of the thickened structure is directly connected with the inside of the first trench, the grid electrode is located above the thickened structure and extends downwards to the middle of the thickened structure until the isolation grid, the grid electrode is isolated from the thickened structure through the second grid oxide layer, and the bottom of the thickened structure is respectively connected with the isolation grid and the first grid oxide layer.
4. The semiconductor trench voltage driven device of claim 1 wherein said thickening structure comprises a first thickening structure and a second thickening structure,
the first thickening structures are symmetrically arranged at corner positions of two sides of the top of the first groove, one side of the bottom of each first thickening structure is directly connected with the N+ field of the active layer, the other side of the bottom of each first thickening structure is isolated from the grid electrode through the second grid oxide layer, and the top of each first thickening structure is isolated from the interlayer film through the second grid oxide layer;
the second thickening structure is symmetrically arranged at corner positions at two sides of the bottom of the first groove, the outer side of the second thickening structure is directly connected with the inside of the first groove, the grid electrode is arranged above the second thickening structure and extends downwards to the middle of the second thickening structure until the isolation grid is arranged between the second thickening structure, the grid electrode and the second thickening structure are isolated through the second grid oxide layer, and the bottom of the second thickening structure is respectively connected with the isolation grid and the first grid oxide layer.
5. The semiconductor trench type voltage driven device according to any one of claims 2 to 4, wherein the thickened structure is formed by a LOCOS process.
6. A method of manufacturing a semiconductor trench type voltage driving device, comprising:
providing a drain electrode substrate, wherein the drain electrode substrate is provided with a processing surface, and after the first surface acidification, first grooves which are parallel to each other are formed by etching the processing surface;
forming an isolation gate in the first trench through first polysilicon deposition;
forming a thickening structure at the corner position of the first groove by using a lcos process;
forming a gate within the first trench, forming an active layer under the processing surface of the drain substrate;
an electrical connection structure is formed between the first trenches by etching the second trenches, and an electrode is formed over the active layer and the first trenches.
7. The method of manufacturing a semiconductor trench type voltage driven device according to claim 6, wherein,
forming an isolation gate in the first trench through first polysilicon deposition, specifically including:
forming a first gate oxide layer on the processing surface and in the first groove; depositing first polysilicon on the first gate oxide layer to enable the first polysilicon layer to fill the first groove;
removing other parts of the first polysilicon layer, which are positioned at the bottom of the first groove and are used for forming isolation gates, from the first polysilicon layer;
removing the rest part of the first gate oxide layer except the junction with the isolation gate;
the forming of the thickening structure at the corner position of the first groove by using a lcos process specifically includes:
performing secondary surface acidification and silicon nitride precipitation;
carrying out silicon nitride etching and removal of second surface acidification by using the outline of the thickened structure at the corner position of the first groove;
forming a thickening structure at the corner position of the first groove by using a lcos process;
forming a second gate oxide layer on the treatment surface, the thickening structure and the isolation gate;
forming a gate in the first trench and forming an active layer under the processing surface of the drain substrate, specifically including:
depositing second polysilicon on the second gate oxide layer to enable the second polysilicon layer to fill the first groove;
removing other parts of the second polysilicon layer, which are positioned in the bottom of the first trench and are used for forming a grid electrode;
forming an active layer below the processing surface of the drain electrode substrate in an energy injection mode, and forming an N+ field and a P-field from top to bottom;
the second trench formed by etching between the first trenches forms an electrical connection structure, and an electrode is formed over the active layer and the first trench, specifically including:
forming an interlayer film over the active layer and the first trench in a deposition coverage manner;
etching the interlayer film and the active layer to form a second groove, wherein the second groove is positioned between the first grooves, the depth of the second groove is larger than that of the N+ field but insufficient to penetrate the active layer, and a P+ field is formed at the bottom of the second groove;
and forming a metal barrier layer above the active layer, the first groove and the second groove in a deposition covering mode, forming a metal source layer above the metal barrier layer, and filling the second groove.
8. The method of manufacturing a semiconductor trench type voltage driven device according to claim 7, wherein the thickening structure is symmetrically arranged at corner positions of two sides of the top of the first trench, one side of the bottom of the thickening structure is directly connected with the n+ region of the active layer, the other side of the bottom of the thickening structure is isolated from the gate electrode by the second gate oxide layer, and the top of the thickening structure is isolated from the interlayer film by the second gate oxide layer.
9. The method according to claim 7, wherein the thickened structure is symmetrically arranged at corner positions at two sides of the bottom of the first trench, the outer side of the thickened structure is directly connected with the inside of the first trench, the gate is located above the thickened structure and extends downwards to the middle of the thickened structure until the isolation gate, the gate and the thickened structure are isolated by the second gate oxide layer, and the bottom of the thickened structure is respectively connected with the isolation gate and the first gate oxide layer.
10. The method of manufacturing a semiconductor trench voltage driven device according to claim 7, wherein said thickening structure comprises a first thickening structure and a second thickening structure,
the first thickening structures are symmetrically arranged at corner positions of two sides of the top of the first groove, one side of the bottom of each first thickening structure is directly connected with the N+ field of the active layer, the other side of the bottom of each first thickening structure is isolated from the grid electrode through the second grid oxide layer, and the top of each first thickening structure is isolated from the interlayer film through the second grid oxide layer;
the second thickening structure is symmetrically arranged at corner positions at two sides of the bottom of the first groove, the outer side of the second thickening structure is directly connected with the inside of the first groove, the grid electrode is arranged above the second thickening structure and extends downwards to the middle of the second thickening structure until the isolation grid is arranged between the second thickening structure, the grid electrode and the second thickening structure are isolated through the second grid oxide layer, and the bottom of the second thickening structure is respectively connected with the isolation grid and the first grid oxide layer.
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| CN202311736854.1A CN117637824A (en) | 2023-12-18 | 2023-12-18 | Semiconductor groove type voltage driving device and manufacturing method thereof |
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| CN202311736854.1A CN117637824A (en) | 2023-12-18 | 2023-12-18 | Semiconductor groove type voltage driving device and manufacturing method thereof |
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