CN117637598A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN117637598A
CN117637598A CN202210969697.8A CN202210969697A CN117637598A CN 117637598 A CN117637598 A CN 117637598A CN 202210969697 A CN202210969697 A CN 202210969697A CN 117637598 A CN117637598 A CN 117637598A
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China
Prior art keywords
diffusion barrier
layer
material layer
barrier material
interconnection
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CN202210969697.8A
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Inventor
张�杰
冯毅伟
费凡
闫冬
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202210969697.8A priority Critical patent/CN117637598A/en
Priority to PCT/CN2022/123956 priority patent/WO2024031816A1/en
Publication of CN117637598A publication Critical patent/CN117637598A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a first conductive layer and a dielectric layer, the dielectric layer is positioned on the first conductive layer, and an interconnection through hole exposing the first conductive layer is formed in the dielectric layer; forming a first diffusion barrier material layer on the inner wall of the interconnection through hole and above the dielectric layer; forming a second diffusion barrier material layer on the first diffusion barrier material layer above the dielectric layer; thinning the first diffusion barrier material layer positioned at the bottom of the interconnection through hole; and removing the first diffusion barrier material layer above the dielectric layer to form a first diffusion barrier layer and forming a conductive plug in the interconnection through hole. The embodiment of the application can effectively reduce the resistance between the conductive layer and the conductive plug.

Description

Semiconductor structure and preparation method thereof
Technical Field
The present disclosure relates to semiconductor technology, and in particular, to a semiconductor structure and a method for fabricating the same.
Background
In semiconductor manufacturing, conductive layers (e.g., metal layers) on both sides of a dielectric layer are typically conductively connected through interconnect vias in the dielectric layer. The interconnection through hole is filled with a conductive plug. The conductive plugs are typically made of a metallic material. And the metal material is easy to diffuse to the dielectric layer, thereby affecting the performance of the device. Therefore, a diffusion barrier layer is usually formed on the inner wall of the interconnect via to prevent metal diffusion.
However, the diffusion barrier layer has a higher resistivity at the same time, resulting in an increase in resistance between the conductive layer and the conductive plug, thereby easily causing an RC delay problem.
Disclosure of Invention
Based on this, the embodiment of the application provides a semiconductor structure and a preparation method thereof, so as to reduce the resistance between the conductive layer and the conductive plug.
A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first conductive layer and a dielectric layer, the dielectric layer is positioned on the first conductive layer, and an interconnection through hole exposing the first conductive layer is formed in the dielectric layer;
forming a first diffusion barrier material layer on the inner wall of the interconnection through hole and above the dielectric layer;
forming a second diffusion barrier material layer on the first diffusion barrier material layer above the dielectric layer;
thinning a first diffusion barrier material layer at the bottom of the interconnection through hole;
and removing the first diffusion barrier material layer above the dielectric layer to form a first diffusion barrier layer and forming a conductive plug in the interconnection through hole.
In one embodiment, the forming a second diffusion barrier material layer on the first diffusion barrier material layer above the dielectric layer includes:
And forming the second diffusion barrier material layer on the surface of the first diffusion barrier material layer above the dielectric layer and the surface of the first diffusion barrier material layer on the top of the side wall of the interconnection through hole.
In one embodiment, the second diffusion barrier material layer is formed by physical vapor deposition.
In one embodiment, the physical vapor deposition is a high deposition rate deposition, the deposition rate not less than 5nm/s and not greater than 10nm/s.
In one embodiment, the physical vapor deposition is performed at a deposition temperature of 180-220 ℃ and a deposition power of 1300-1700W, with a nitrogen flow of 55-65 sccm and an argon flow of 9-11 sccm.
In one embodiment, the first diffusion barrier material layer is formed by an atomic layer deposition mode, and the thickness of the formed first diffusion barrier material layer is 10nm-12nm; and/or
The thickness of the second diffusion barrier material layer formed in the physical vapor deposition mode is 10nm-15nm.
In one embodiment, the second diffusion barrier material layer is WNx, wherein x is greater than 0.9.
In one embodiment, the material of the second diffusion barrier material layer is the same as the material of the first diffusion barrier material layer.
In one of the embodiments, the sidewall of the interconnection via is at an angle of 86 ° to 90 ° to the horizontal direction.
In one embodiment, after the thinning, the thickness of the first diffusion barrier material layer is 3nm-5nm.
In one embodiment, the thinning the first diffusion barrier material layer located at the bottom of the interconnection via includes:
and performing physical bombardment treatment on the first diffusion barrier material layer at the bottom of the interconnection through hole.
In one embodiment, before forming the first diffusion barrier material layer on the inner wall of the interconnection through hole and the dielectric layer, the method further includes:
and carrying out reduction treatment on the first conductive layer at the bottom of the interconnection through hole.
In one embodiment, the reduction process is performed in the same process chamber as the physical bombardment process.
In one of the embodiments of the present invention,
when the reduction treatment is carried out, hydrogen and argon are introduced, the flow of the hydrogen is 18-22sccm, the flow of the argon is 90-110sccm, the bias power is set to be 180-200W, and the dissociation power is set to be 1800-2200W.
In one of the embodiments of the present invention,
when physical bombardment treatment is carried out, argon is introduced, the flow of the argon is 90-110sccm, the bias power is set to be 600-1000W, and the dissociation power is set to be 1800-2200W.
In one embodiment, the thinning the first diffusion barrier material layer located at the bottom of the interconnection via includes: and carrying out dry etching on the first diffusion barrier material layer at the bottom of the interconnection through hole.
In one embodiment, the removing the first diffusion barrier material layer above the dielectric layer to form a first diffusion barrier layer and forming a conductive plug in the interconnection via includes:
forming a conductive plug material layer within the interconnect via and over the second diffusion barrier material layer;
and performing chemical mechanical polishing treatment to remove the conductive plug material layer and the first diffusion barrier material layer above the second diffusion barrier material layer so as to form the conductive plug and the first diffusion barrier layer.
In one embodiment, after the performing the chemical mechanical polishing process to remove the conductive plug material layer and the first diffusion barrier material layer above the second diffusion barrier material layer, the method further includes:
and continuing chemical mechanical polishing treatment on the dielectric layer, the conductive plug in the interconnection through hole and the first diffusion barrier layer.
In one embodiment, after removing the first diffusion barrier material layer above the dielectric layer to form a first diffusion barrier layer and forming a conductive plug in the interconnection via, the method further includes:
And forming a second conductive layer on the dielectric layer, wherein the second conductive layer covers the conductive plug.
A semiconductor structure formed by the method of any of the preceding claims, the semiconductor structure comprising:
the substrate comprises a first conductive layer and a dielectric layer, wherein the dielectric layer is positioned on the first conductive layer, and an interconnection through hole is formed in the dielectric layer;
the first diffusion barrier layer is positioned on the inner wall of the interconnection through hole, and the thickness of the first diffusion barrier layer positioned at the bottom of the interconnection through hole is smaller than that of the first diffusion barrier layer positioned on the side wall of the interconnection through hole;
and a conductive plug positioned on the surface of the first diffusion barrier layer in the interconnection through hole and filling the interconnection through hole.
In one embodiment, the thickness of the first diffusion barrier layer at the bottom of the interconnection through hole is 3nm-5nm, and the thickness of the first diffusion barrier layer at the side wall of the interconnection through hole is 10nm-12nm.
In one embodiment, the semiconductor structure further comprises:
and the second conductive layer is positioned on the dielectric layer and covers the conductive plug.
According to the semiconductor structure and the preparation method thereof, the diffusion of metal in the conductive plug to the dielectric layer can be effectively prevented through the diffusion barrier layer on the side wall of the interconnection through hole. Meanwhile, the first diffusion barrier layer at the bottom of the interconnection through hole is thinned, so that the resistance between the conductive plug and the first conductive layer can be effectively reduced.
Meanwhile, in the preparation method of the semiconductor structure, after the first diffusion barrier material layer is formed, a second diffusion barrier material layer is formed on the first diffusion barrier material layer above the dielectric layer. The second diffusion barrier material layer may prevent the first diffusion barrier material layer above the dielectric layer from being significantly thinned or removed while the first diffusion barrier material layer at the bottom of the interconnect via is thinned. At this time, on the one hand, the dielectric layer can be protected in the thinning process, and the dielectric layer is prevented from being damaged in the thinning process. On the other hand, in the process of forming the conductive plug, the diffusion of the metal material to the dielectric layer can be effectively prevented, so that the performance of the device is ensured. Meanwhile, the second diffusion barrier material layer and the first diffusion barrier material layer are both film layers with the function of blocking metal diffusion, so that the second diffusion barrier material layer is formed without polluting the first diffusion barrier material layer.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;
fig. 2 to 7 are schematic cross-sectional views illustrating a process for fabricating a semiconductor structure according to an embodiment;
fig. 8 is a schematic cross-sectional view of a semiconductor structure according to an embodiment.
Reference numerals illustrate:
100-substrate, 110-first conductive layer, 120-dielectric layer, 120 a-interconnection via, 130-third diffusion barrier layer, 200-first diffusion barrier layer, 201-first diffusion barrier material layer, 202-second diffusion barrier material layer, 300-conductive plug, 301-conductive plug material layer, 400-second conductive layer.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
The relevant structures in the embodiments of the present application should not be limited to the specific shapes illustrated in the drawings of the specification, but include deviations in shapes that result, for example, from manufacturing techniques. The relevant structures shown in the figures are schematic in nature and their shapes do not represent the actual shape of a region of a device and are not intended to limit the scope of the present application.
In one embodiment, referring to fig. 1, a method for fabricating a semiconductor structure is provided, including the following steps:
in step S10, referring to fig. 2, a substrate 100 is provided, the substrate 100 includes a first conductive layer 110 and a dielectric layer 120, the dielectric layer 120 is disposed on the first conductive layer 110, and an interconnection via 120a exposing the first conductive layer 110 is formed in the dielectric layer 120;
Step S30, referring to fig. 3, a first diffusion barrier material layer 201 is formed on the inner wall of the interconnection via 120a and over the dielectric layer 120;
in step S40, referring to fig. 4, a second diffusion barrier material layer 202 is formed on the first diffusion barrier material layer 201 above the dielectric layer 120;
step S50, please refer to fig. 5, wherein the first diffusion barrier material layer 201 at the bottom of the interconnection via 120a is thinned;
in step S60, referring to fig. 7, the first diffusion barrier material layer 201 above the dielectric layer 120 is removed to form a first diffusion barrier layer 200, and a conductive plug 300 is formed in the interconnection via 120 a.
Specifically, in step S10, referring to fig. 2, the material of the first conductive layer 110 may be a metal material, including but not limited to. Specifically, the material of the first conductive layer 110 may include, but is not limited to, copper (Cu).
The first conductive layer 110 may be a conductive trace under the dielectric layer 120, which may be formed in an insulating layer (not shown) under the dielectric layer 120 by a damascene process. Specifically, a trench may be first formed in the insulating layer under the dielectric layer 120. Then, a third diffusion barrier 130 is formed at the sidewalls and bottom of the trench. Then, the first conductive layer 110 is formed on the surface of the third diffusion barrier 130 by electroplating or the like to fill the trench in the insulating layer under the dielectric layer 120.
Of course, the form of the first conductive layer 110 may also be different. For example, the first conductive layer 110 may not be formed on the surface of the third diffusion barrier 130. Alternatively, the first conductive layer 110 may not be formed by the damascene process. There is no limitation in this regard.
Dielectric layer 120 is located on first conductive layer 110. The material of the dielectric layer 120 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like.
As an example, after forming the first conductive layer 110 in the insulating layer under the dielectric layer 120 by a damascene process, the dielectric layer 120 is deposited to cover the first conductive layer 110 and the embedded insulating layer.
The interconnect via 120a within the dielectric layer 120 penetrates the dielectric layer 120 in a vertical direction, which may be formed by a dry etching process. The aperture of the interconnection via 120a is relatively small compared to the trench in which the first conductive layer 110 is filled. The interconnection via 120a exposes the first conductive layer 110 so that the conductive plug 300 formed therein may connect the first conductive layer 110.
In step S30, referring to fig. 3, the material of the first diffusion barrier material layer 201 may include, but is not limited to, tungsten nitride, titanium nitride, tantalum nitride, etc.
As an example, the first diffusion barrier material layer 201 may be deposited on the inner wall of the interconnect via 120a and over the dielectric layer 120 by Atomic Layer Deposition (ALD) or the like. The conditions for Atomic Layer Deposition (ALD) are known conditions and will not be described in detail herein.
It is understood that the inner wall of the interconnect via 120a includes the sidewall of the interconnect via 120a and the bottom of the interconnect via 120 a.
The thin film formed by the atomic layer deposition has good coverage, so that good coverage can be formed on the side wall and the bottom of the interconnection through hole 120a with relatively small aperture, and the first diffusion barrier material layer 201 has good function of blocking metal diffusion.
In step 40, referring to fig. 4, the second diffusion barrier material layer 202 covers the first diffusion barrier material layer 201 above the dielectric layer 120, so as to prevent the first diffusion barrier material layer 201 above the dielectric layer 120 from being significantly thinned or removed when the first diffusion barrier material layer 201 is thinned in a subsequent step.
Meanwhile, since the second diffusion barrier material layer 202 and the first diffusion barrier material layer 201 are both film layers having a function of blocking metal diffusion. Therefore, the second diffusion barrier material layer 202 is formed to effectively prevent the first diffusion barrier material layer 201 from being contaminated. Specifically, in forming the second diffusion barrier material layer 202, even if a small amount of the second diffusion barrier material layer 202 falls to the bottom of the interconnect via 120a due to process capability or the like, the first diffusion barrier material layer 201 at the bottom of the interconnect via 120a is not contaminated. At this time, the resistance between the conductive plug 300 and the first conductive layer 110 formed later is hardly affected.
As an example, the second diffusion barrier material layer 202 may be provided with the same material as the first diffusion barrier material layer 201. For example, both are tungsten nitride. Of course, the material of the second diffusion barrier material layer 202 may also be different. The material of the second diffusion barrier material layer 202 may be, for example, titanium nitride, tantalum nitride, or the like, which is not limited thereto.
In step 50, referring to fig. 5, the first diffusion barrier material layer 201 at the bottom of the interconnect via 120a may be thinned by vertical physical bombardment or anisotropic etching (e.g., dry etching), while the first diffusion barrier material layer 201 at the sidewall of the interconnect via 120a remains.
It should be noted that, after "thinning the first diffusion barrier material layer 201 at the bottom of the interconnect via 120 a" herein, the thickness of the first diffusion barrier material layer 201 at the bottom of the interconnect via 120a may be greater than or equal to zero. That is, "thinning the first diffusion barrier material layer 201 at the bottom of the interconnect via 120 a" may be such that the thickness of the first diffusion barrier material layer 201 at the bottom of the interconnect via 120a becomes smaller, but it still exists; the first diffusion barrier material layer 201 at the bottom of the interconnection via 120a may also be removed directly.
As an example, the angle of the sidewall of the interconnection via 120a to the horizontal direction may be controlled to 86 ° to 90 °, and further may be controlled to 88 ° to 90 °. At this time, the sidewall verticality of the interconnect via 120a is high, so that the first diffusion barrier material layer 201 located at the sidewall of the interconnect via 120a is hardly affected while the first diffusion barrier material layer 201 at the bottom of the interconnect via 120a is thinned.
Meanwhile, due to the protective effect of the second diffusion barrier material layer 202, the first diffusion barrier material layer 201 located above the dielectric layer 120 is not significantly thinned or removed at the same time as the first diffusion barrier material layer 201 at the bottom of the interconnection via 120a is thinned.
Specifically, while the first diffusion barrier material layer 201 at the bottom of the interconnection via 120a is thinned, the second diffusion barrier material layer 202 may be completely removed, or may have a remaining part of the thickness. While the first diffusion barrier material layer 201 located over the dielectric layer 120 may not be removed at all or may be removed only by a portion of the thickness.
At this time, in the process of thinning the first diffusion barrier material layer 201, the dielectric layer 120 may be always covered by the first diffusion barrier material layer 201 or the first diffusion barrier material layer 201 and the second diffusion barrier material layer 202, so as not to be damaged. Therefore, the device performance can be effectively ensured at this time.
If the second diffusion barrier material layer 202 is not formed, the first diffusion barrier material layer 201 located over the dielectric layer 120 may be thinned at the same time as the first diffusion barrier material layer 201 at the bottom of the interconnection via 120 a. Also, due to the positional relationship, the degree of thinning of the first diffusion barrier material layer 201 above the dielectric layer 120 may be greater relative to the degree of thinning of the first diffusion barrier material layer 201 at the bottom of the interconnect via 120a, or may even be completely removed. Therefore, the vicinity of the upper surface of the dielectric layer 120 may be damaged during the thinning process, thereby affecting the device performance.
As an example, the thickness of the first diffusion barrier material layer 201 formed in step S30 may be 10nm to 12nm. Then, in step S50, the first diffusion barrier material layer 201 at the bottom of the interconnection via 120a may be thinned to 3nm-5nm. At this time, the first diffusion barrier material layer 201 at the bottom of the interconnection via 120a is thinned by about 7nm to 8 nm. Accordingly, the thickness of the second diffusion barrier material layer 202 formed in step S40 may be set to be about 10nm to 15nm, thereby effectively protecting the first diffusion barrier material layer 201.
In step S60, referring to fig. 6, a conductive plug material layer 301 may be formed in the interconnect via 120a and above the dielectric layer 120. The material of the conductive plug material layer 301 may be a metal material, such as tungsten metal.
Specifically, as is apparent from the foregoing description, due to the protective effect of the second diffusion barrier material layer 202, while the first diffusion barrier material layer 201 at the bottom of the interconnect via 120a is thinned, the first diffusion barrier material layer 201 located above the dielectric layer 120 is not thinned, and may even have a partial thickness of the second diffusion barrier material layer 202 thereon; or the first diffusion barrier material layer 201 is only partially thinned, but it is not removed.
Accordingly, the conductive plug material layer 301 may be formed on the surface of the first diffusion barrier material layer 201 within the interconnect via 120a, the surface of the first diffusion barrier material layer 201 (or the second diffusion barrier material layer 202) over the dielectric layer 120.
In this process, the first diffusion barrier material layer 201 (or the second diffusion barrier material layer 202 and the first diffusion barrier material layer 201) above the dielectric layer 120 may prevent the metal in the conductive plug material layer 301 above the dielectric layer 120 from diffusing into the dielectric layer 120, thereby effectively ensuring the device performance.
Then, referring to fig. 7, the conductive plug material layer 301 and the first diffusion barrier material layer 201 (or the second diffusion barrier material layer 202 and the first diffusion barrier material layer 201) above the dielectric layer 120 may be removed to form the conductive plug 300 and the first diffusion barrier layer 200.
In the present embodiment, the diffusion of the metal in the conductive plug 300 to the dielectric layer 120 can be effectively prevented by the diffusion barrier layer 200 of the sidewall of the interconnect via 120 a. Meanwhile, by thinning the first diffusion barrier material layer 201 at the bottom of the interconnection via 120a, the resistance between the finally formed conductive plug 300 and the first conductive layer 110 can be effectively reduced.
Meanwhile, the present embodiment also forms the second diffusion barrier material layer 202 on the first diffusion barrier material layer 201 above the dielectric layer 120 after forming the first diffusion barrier material layer 201. The second diffusion barrier material layer 202 may prevent the first diffusion barrier material layer 201 above the dielectric layer 120 from being significantly thinned or removed while the first diffusion barrier material layer 201 at the bottom of the interconnect via 120a is thinned. At this time, on the one hand, the dielectric layer 120 can be protected during the thinning process, so as to prevent the dielectric layer 120 from being damaged during the thinning process. On the other hand, in the process of forming the conductive plugs 300, the diffusion of the metal material into the dielectric layer 120 can be effectively prevented, thereby ensuring the device performance.
Meanwhile, the second diffusion barrier material layer 202 and the first diffusion barrier material layer 201 are both film layers with a function of blocking metal diffusion, so that the formation of the second diffusion barrier material layer 202 does not pollute the first diffusion barrier material layer 201.
In one embodiment, step S40 includes:
in step S41, a second diffusion barrier material layer 202 is formed on the surface of the first diffusion barrier material layer 201 above the dielectric layer 120 and on the surface of the first diffusion barrier material layer 201 on the top of the sidewall of the interconnect via 120a, as shown in fig. 4.
In the subsequent step, when the first diffusion barrier material layer 201 is thinned in the vertical direction by physical bombardment or dry etching, etching particles generate a certain amount of heat in the process of mutually colliding and striking the surface of the sample, and the medium layer 120 is easily damaged due to the excessive heat.
After the interconnect via 120a is formed in the dielectric layer 120, corners of the dielectric layer 120 are formed at intersections of the upper surface of the dielectric layer 120 and sidewalls of the interconnect via 120 a.
In the present embodiment, the second diffusion barrier material layer 202 is formed not only on the surface of the first diffusion barrier material layer 201 above the dielectric layer 120 but also on the surface of the first diffusion barrier material layer 201 on top of the sidewall of the interconnect via 120 a. Thus, the corners of the dielectric layer 120 may be effectively masked by the second diffusion barrier material layer 202. Therefore, when the first diffusion barrier material layer 201 is thinned in the vertical direction in the subsequent step, the corners of the dielectric layer 120 can be well protected.
In one embodiment, in step S40, the second diffusion barrier material layer 202 is formed by physical vapor deposition.
As an example, in performing physical vapor deposition, the deposition temperature may be set to 180-220 ℃ and the deposition power may be set to 1300-1700W. Simultaneously, nitrogen and argon can be introduced. The nitrogen flow rate can be controlled to be 55sccm-65sccm. The argon flow can be controlled to be 9sccm-11sccm.
Also, at this time, the first diffusion barrier material layer 201 may be formed by atomic layer deposition, and has a thickness of 10nm to 12nm, as an example. Meanwhile, the thickness of the second diffusion barrier material layer 202 formed by physical vapor deposition is 10nm-15nm. At this time, the second diffusion barrier material layer 202 may effectively protect the first diffusion barrier material layer 201 and the dielectric layer 120 thereunder during the thinning process.
The physical vapor deposition method forms a film with poor coverage, and the deposited second diffusion barrier material layer 202 mostly falls on the horizontal surface. Meanwhile, since the aperture of the interconnection via 120a is relatively small, the second diffusion barrier material layer 202 may be formed little or not at all at the bottom of the interconnection via 120a by physical vapor deposition.
Therefore, in the present embodiment, the formation of the second diffusion barrier material layer 202 on the surface of the first diffusion barrier material layer 201 above the dielectric layer 120 can be simply and effectively achieved by physical vapor deposition.
Furthermore, by controlling deposition conditions such as deposition rate of physical vapor deposition, it is also convenient to form the second diffusion barrier material layer 202 on the surface of the first diffusion barrier material layer 201 on top of the sidewall of the interconnect via 120a at the same time.
In one embodiment, physical vapor deposition is performed at a high deposition rate, not less than 5nm/s.
The deposition rate is not less than 5nm/s, and a high deposition rate deposition mode can be effectively realized.
The higher the deposition rate of physical vapor deposition, the poorer the coverage fill of the film layer formed. When the high deposition rate deposition manner is adopted, it is possible to facilitate making the second diffusion barrier material layer 202 hardly formed at the bottom of the interconnect via 120 a.
In one embodiment, the deposition rate of physical vapor deposition is controlled to be not less than 5nm/s while the deposition rate of physical vapor deposition is controlled to be not more than 10nm/s.
In physical vapor deposition, too high a deposition rate can make it difficult to precisely control the thickness of the deposited film.
In the present embodiment, the deposition rate of the physical vapor deposition is not less than 5nm/s but not more than 10nm/s, so that the thickness of the second diffusion barrier material layer 202 above the dielectric layer 120 can be precisely controlled while making the bottom of the interconnection via 120a hardly form the second diffusion barrier material layer 202.
In addition, when the second diffusion barrier material layer 202 is formed by physical vapor deposition, the formed second diffusion barrier material layer 202 may be controlled to have a high nitrogen atom content, so that it is not easy to be removed during the thinning process, and thus the dielectric layer 120 may be effectively protected. Specifically, for example, when the second diffusion barrier material layer 202 is tungsten nitride (WN x ) When the value of x can be controlled to be greater than 0.9.
In one embodiment, step S50 includes:
in step S51, the first diffusion barrier material layer 201 located at the bottom of the interconnection via 120a is subjected to a physical bombardment treatment.
Specifically, argon may be introduced during the physical bombardment treatment. The flow rate of argon gas may be controlled to be 90sccm to 110sccm. Meanwhile, the bias power can be controlled to be 600W-1000W. Meanwhile, the dissociation power is set to 1800W-2200W. At dissociation power, argon gas may dissociate to form argon ions. The argon ions may move downward under the bias power to bombard the first diffusion barrier material layer 201 at the bottom of the interconnect via 120 a. At the same time, the dielectric layer 120 over the interconnect via 120a is also bombarded with argon ions. At this time, the second diffusion barrier material layer 202 is formed over the dielectric layer 120, so that the dielectric layer 120 and the first diffusion barrier material layer 201 thereabove can be effectively protected.
After the first diffusion barrier material layer 201 at the bottom of the interconnection via 120a is thinned by physical bombardment, a polymer which is difficult to remove is not generated, so that the surface of the thinned first diffusion barrier material layer 201 is ensured to be clean. Meanwhile, after physical bombardment, the first diffusion barrier material layer 201 sputtered from the bottom can further increase the thickness of the first diffusion barrier material layer 201 on the sidewall of the interconnection via 120a, thereby improving the metal diffusion barrier capability thereof.
Of course, in other embodiments, step S50 may also include:
in step S52, the first diffusion barrier material layer 201 located at the bottom of the interconnection via 120a is dry etched.
At this time, after the thinning, polymers and the like which may be generated during the etching process may be cleaned, so that the surface of the thinned first diffusion barrier material layer 201 is cleaned.
In one embodiment, before step S30, the method further includes:
in step S20, the first conductive layer 110 at the bottom of the interconnection via 120a is subjected to a reduction process.
After the interconnection via 120a is formed in the dielectric layer 120 of the substrate 100, a portion of the surface of the first conductive layer 110 is exposed by the interconnection via 120a, and thus may be oxidized by air.
For example, when the first conductive layer 110 is copper, a portion thereof exposed by the interconnection via 120a may be oxidized, thereby forming a copper oxide layer on a surface thereof.
In step S20, the substrate 100 after the interconnection via 120a is formed may be placed in a pre-cleaning chamber. Then, a reducing gas is introduced into the chamber to be cleaned, so that the oxidized portion of the first conductive layer 110 is effectively reduced. For example, the copper oxide layer is reduced.
In one embodiment, the reduction process in step S20 is performed in the same process chamber as the physical bombardment in step S50.
As an example, in step S20, the substrate 100 may be subjected to a reduction process in the pre-cleaning chamber. In step S30, the substrate 100 may be transferred to an atomic layer deposition chamber, thereby forming the first diffusion barrier material layer 201. In step S34, the substrate 100 formed with the first diffusion barrier material layer 201 may be transferred to a physical vapor deposition chamber, thereby forming the second diffusion barrier material layer 202. In step S50, the substrate 100 after the first diffusion barrier material layer 201 and the second diffusion barrier material layer 202 are formed may be turned back into the pre-cleaning chamber again, so that the second diffusion barrier material layer 202 and the first diffusion barrier material layer 201 at the bottom of the interconnection via 120a are subjected to a physical bombardment treatment to thin the first diffusion barrier material layer 201 at the bottom of the interconnection via 120 a.
At this time, both the reduction treatment and the physical bombardment are performed in the pre-cleaning chamber, so that the process equipment system can be simplified.
As an example, in step S20, when the reduction treatment is performed in the pre-cleaning chamber, hydrogen gas and argon gas may be introduced into the pre-cleaning chamber. Hydrogen is used as the reducing gas. Argon was used as carrier gas. The hydrogen flow rate can be 18-22sccm, and the argon flow rate can be 90-110sccm. Meanwhile, the bias power can be controlled to be 180W-200W. Meanwhile, the dissociation power is set to 1800W-2200W. Under the dissociation power, the hydrogen gas dissociates to form hydrogen ions, thereby subjecting the first conductive layer 110 at the bottom of the interconnect via 120a to a reduction treatment.
It will be appreciated that argon is now primarily used as the carrier gas. Even if dissociated into argon ions, the bias power is small, so that physical bombardment effect is not formed, and sputtering phenomenon is not generated.
In step S50, argon may be introduced into the pre-cleaning chamber during the physical bombardment treatment in the pre-cleaning chamber. Meanwhile, the bias power can be controlled to be 600W-1000W. Meanwhile, the dissociation power is set to 1800W-2200W. Under the dissociation power, the argon gas dissociates to form hydrogen ions, thereby physically bombarding and thinning the first diffusion barrier material layer 201 at the bottom of the interconnect via 120 a.
Of course, in other embodiments, the reduction in step S20 and the physical bombardment in step S50 may or may not be performed in the same process chamber, which is not limited herein.
In one embodiment, referring to fig. 6 and fig. 7, step S60 includes:
step S61, forming a conductive plug material layer 301 in the interconnection via 120a and above the dielectric layer 120;
in step S62, a Chemical Mechanical Polishing (CMP) process is performed to remove the conductive plug material layer 301 and the first diffusion barrier material layer 201 above the dielectric layer 120, i.e. above the second diffusion barrier material layer, so as to form the conductive plug 300 and the first diffusion barrier layer 200.
In step S61, the conductive plug material layer 301 may be formed by Chemical Vapor Deposition (CVD) or electroplating, or the like. Conditions for Chemical Vapor Deposition (CVD) or electroplating are conventional in the art, and will not be described in detail herein.
In step S62, the conductive plug material layer 301 and the first diffusion barrier material layer 201 above the dielectric layer 120 may be effectively removed by a CMP process.
It will be appreciated that when the thinning process in step S50 is completed, the second diffusion barrier material layer 202 may be removed during CMP while the second diffusion barrier material layer 202 still has a partial thickness over the dielectric layer 120.
Meanwhile, as an example, after step S62, it may further include:
in step S63, the cmp process is continued for the dielectric layer 120 and the conductive plugs 300 and the first diffusion barrier 200 in the interconnect vias 120 a. The thickness of the dielectric layer 120 is removed by the chemical mechanical polishing process by an amount of 70-90nm.
At this time, the dielectric layer 120 is thinned, so that the surface of the dielectric layer 120 is effectively prevented from being contaminated by metal particles in the conductive plug material layer 301 during the CMP process, and thus, a good insulating and isolating effect is achieved.
In one embodiment, after step S60, further comprising:
in step S70, a second conductive layer 400 is formed on the dielectric layer 120, and the second conductive layer 400 covers the conductive plugs 300, as shown in fig. 8.
Specifically, the second conductive layer 400 may be formed on the surfaces of the dielectric layer 120 and the conductive plugs 300 and the first diffusion barrier layer 200 within the interconnection via 120 a. The material of the second conductive layer 400 may include, but is not limited to, a metal material. For example, the material of the second conductive layer 400 may be aluminum.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
In one embodiment, a semiconductor structure formed according to any of the methods described above is also provided. Referring to fig. 8, the semiconductor structure includes a substrate 100, a first diffusion barrier 200, and a conductive plug 300.
The substrate 100 includes a first conductive layer 1110 and a dielectric layer 120.
The material of the first conductive layer 110 may be, but is not limited to, a metal material. Specifically, the material of the first conductive layer 110 may include, but is not limited to, copper (Cu). The first conductive layer 110 may be a conductive trace under the dielectric layer 120, which may be formed in an insulating layer (not shown) under the dielectric layer 120 by a damascene process. Specifically, a trench may be provided in the insulating layer under the dielectric layer 120. The sidewalls and bottom of the trench may be formed with a third diffusion barrier 130. The first conductive layer 110 may be located on the surface of the third diffusion barrier 130.
Of course, the form of the first conductive layer 110 may also be different. For example, the first conductive layer 110 may not be formed on the surface of the third diffusion barrier 130.
Dielectric layer 120 is located on first conductive layer 110. The material of the dielectric layer 120 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like.
And, an interconnection via 120a is formed in the dielectric layer 120. The interconnect via 120a within the dielectric layer 120 penetrates the dielectric layer 120 in a vertical direction. The aperture of the interconnection via 120a is relatively small compared to the trench in which the first conductive layer 110 is filled.
The first diffusion barrier 200 is located on the inner wall of the interconnection via 120a, i.e., on the sidewall and bottom of the interconnection via 120a. And, the thickness of the first diffusion barrier layer 200 at the bottom of the interconnection via 120a is smaller than the thickness of the first diffusion barrier layer 200 at the sidewall of the interconnection via 120a.
The conductive plug 300 is located on the first diffusion barrier surface within the interconnect via 120a and fills the interconnect via 120a. The material of conductive plug 300 may include, but is not limited to, a metallic material such as metallic tungsten.
At this time, the metal in the conductive plug 300 may be effectively prevented from diffusing to the dielectric layer 120 by the diffusion barrier 200 of the sidewall of the interconnection via 120a. Meanwhile, the thickness of the first diffusion barrier layer 200 at the bottom of the interconnection via 120a is reduced, so that the resistance between the conductive plug 300 and the first conductive layer 110 can be effectively reduced.
It should be noted that, herein, "the thickness of the first diffusion barrier layer 200 at the bottom of the interconnection via 120 a" may be greater than zero or equal to zero.
When the "thickness of the first diffusion barrier layer 200 located at the bottom of the interconnection via 120 a" is greater than zero, the first diffusion barrier layer 200 continuously covers the sidewall and the bottom of the interconnection via 120a, so that the diffusion of metal in the conductive plug 300 to the dielectric layer 120 can be more effectively prevented, and the device performance can be effectively ensured.
As an example, the thickness of the first diffusion barrier layer 200 at the bottom of the interconnection via 120a may be 3nm to 5nm, and the thickness of the first diffusion barrier layer 200 at the sidewall of the interconnection via 120a may be 10nm to 12nm.
In one embodiment, the semiconductor structure further includes a second conductive layer 400. The material of the second conductive layer 400 may include, but is not limited to, a metal material. For example, the material of the second conductive layer 400 may be aluminum.
The second conductive layer 400 is located on the dielectric layer 120 and covers the conductive plugs 300.
In particular, the second conductive layer 400 may be located on the surfaces of the conductive plugs 300 and the first diffusion barrier layer 200 within the dielectric layer 120 and the interconnect via 120 a.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (19)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first conductive layer and a dielectric layer, the dielectric layer is positioned on the first conductive layer, and an interconnection through hole exposing the first conductive layer is formed in the dielectric layer;
forming a first diffusion barrier material layer on the inner wall of the interconnection through hole and above the dielectric layer;
forming a second diffusion barrier material layer on the first diffusion barrier material layer above the dielectric layer;
thinning a first diffusion barrier material layer at the bottom of the interconnection through hole;
and removing the first diffusion barrier material layer above the dielectric layer to form a first diffusion barrier layer and forming a conductive plug in the interconnection through hole.
2. The method of claim 1, wherein forming a second diffusion barrier material layer over the first diffusion barrier material layer over the dielectric layer, comprises:
and forming the second diffusion barrier material layer on the surface of the first diffusion barrier material layer above the dielectric layer and the surface of the first diffusion barrier material layer on the top of the side wall of the interconnection through hole.
3. The method of claim 1 or 2, wherein the second diffusion barrier material layer is formed by physical vapor deposition.
4. A method of fabricating a semiconductor structure according to claim 3, wherein the physical vapor deposition is a high deposition rate deposition, the deposition rate being not less than 5nm/s and not more than 10nm/s.
5. The method of claim 3, wherein the physical vapor deposition is performed at a deposition temperature of 180-220 ℃ and a deposition power of 1300-1700W, a nitrogen flow of 55-65 sccm, and an argon flow of 9-11 sccm.
6. The method of manufacturing a semiconductor structure according to claim 3, wherein,
the first diffusion barrier material layer is formed in an atomic layer deposition mode, and the thickness of the formed first diffusion barrier material layer is 10nm-12nm; and/or
The thickness of the second diffusion barrier material layer formed in the physical vapor deposition mode is 10nm-15nm.
7. The method of claim 3, wherein the second diffusion barrier material layer is WN x Wherein x is greater than 0.9.
8. The method of manufacturing a semiconductor structure according to claim 1 or 7, wherein a material of the second diffusion barrier material layer is the same as a material of the first diffusion barrier material layer.
9. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein,
the angle between the side wall of the interconnection through hole and the horizontal direction is 86-90 degrees; and/or
After thinning, the thickness of the first diffusion barrier material layer is 3nm-5nm.
10. The method for manufacturing a semiconductor structure according to claim 1 or 9, wherein the thinning the first diffusion barrier material layer located at the bottom of the interconnection via hole comprises:
and carrying out physical bombardment treatment or dry etching on the first diffusion barrier material layer at the bottom of the interconnection through hole.
11. The method of claim 10, wherein before forming the first diffusion barrier material layer over the inner wall of the interconnect via and the dielectric layer, further comprising:
and carrying out reduction treatment on the first conductive layer at the bottom of the interconnection through hole.
12. The method of claim 11, wherein the reducing and the physically bombarding are performed in the same process chamber.
13. The method of manufacturing a semiconductor structure as claimed in claim 12, wherein,
when the reduction treatment is carried out, hydrogen and argon are introduced, the flow of the hydrogen is 18-22sccm, the flow of the argon is 90-110sccm, the bias power is set to be 180-200W, and the dissociation power is set to be 1800-2200W; and/or
When physical bombardment treatment is carried out, argon is introduced, the flow of the argon is 90-110sccm, the bias power is set to be 600-1000W, and the dissociation power is set to be 1800-2200W.
14. The method of claim 1, wherein removing the first diffusion barrier material layer over the dielectric layer to form a first diffusion barrier layer and forming a conductive plug in the interconnect via comprises:
forming a conductive plug material layer within the interconnect via and over the second diffusion barrier material layer;
and performing chemical mechanical polishing treatment to remove the conductive plug material layer and the first diffusion barrier material layer above the second diffusion barrier material layer so as to form the conductive plug and the first diffusion barrier layer.
15. The method of claim 14, wherein after performing a chemical mechanical polishing process to remove the conductive plug material layer and the first diffusion barrier material layer over the second diffusion barrier material layer, further comprising:
And continuing chemical mechanical polishing treatment on the dielectric layer, the conductive plug in the interconnection through hole and the first diffusion barrier layer.
16. The method of claim 14 or 15, wherein after removing the first diffusion barrier material layer above the dielectric layer to form a first diffusion barrier layer and forming a conductive plug in the interconnect via, further comprising:
and forming a second conductive layer on the dielectric layer, wherein the second conductive layer covers the conductive plug.
17. A semiconductor structure formed by the method of any of claims 1-16, the semiconductor structure comprising:
the substrate comprises a first conductive layer and a dielectric layer, wherein the dielectric layer is positioned on the first conductive layer, and an interconnection through hole is formed in the dielectric layer;
the first diffusion barrier layer is positioned on the inner wall of the interconnection through hole, and the thickness of the first diffusion barrier layer positioned at the bottom of the interconnection through hole is smaller than that of the first diffusion barrier layer positioned on the side wall of the interconnection through hole;
and a conductive plug positioned on the surface of the first diffusion barrier layer in the interconnection through hole and filling the interconnection through hole.
18. The semiconductor structure of claim 17, wherein the thickness of the first diffusion barrier layer at the bottom of the interconnect via is 3nm-5nm and the thickness of the first diffusion barrier layer at the sidewall of the interconnect via is 10nm-12nm.
19. The semiconductor structure of claim 17 or 18, wherein the semiconductor structure further comprises:
and the second conductive layer is positioned on the dielectric layer and covers the conductive plug.
CN202210969697.8A 2022-08-12 2022-08-12 Semiconductor structure and preparation method thereof Pending CN117637598A (en)

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