CN117636950A

CN117636950A - Data access processing structure, data access processing method and memory

Info

Publication number: CN117636950A
Application number: CN202210956139.8A
Authority: CN
Inventors: 赵北游
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-08-10
Filing date: 2022-08-10
Publication date: 2024-03-01

Abstract

The present disclosure relates to the field of semiconductor circuit design, and in particular, to a data access processing structure, a data access processing method, and a memory, where the data access processing structure includes: n storage units, wherein N is a positive integer greater than or equal to 3; each storage unit is connected with a corresponding local data line, and the local data line is used for storing write-in data into the storage unit or reading out the storage data of the storage unit; the data processing module is characterized in that the input end of the data processing module is connected with all local data lines, the output end of the data processing module is connected with a data transmission line, the data transmission line is connected with the local data lines, and the data transmission line is used for transmitting write-in data and read-out data; the data processing module is configured to adjust output levels transmitted by local data lines corresponding to the N storage units so as to generate read data with the same level as the write data; the accuracy and stability of the memory work are improved by adjusting the number of the memory units for storing 1bit data.

Description

Data access processing structure, data access processing method and memory

Technical Field

The present disclosure relates to the field of semiconductor circuit design, and in particular, to a data access processing structure, a data access processing method, and a memory.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is widely used in modern electronic systems due to its high storage density and high transfer speed. With the development of semiconductor technology, DRAM technology is more advanced, and the integration level of memory cells is higher; meanwhile, various applications are also increasingly demanding on performance, power consumption, reliability, etc. of the DRAM.

At present, the data storage modes of the common memory are as follows: 1bit data storage is independently carried out based on an independent storage unit, namely 1bit data is stored by adopting a storage unit; in this storage mode, if data is suddenly changed during transmission or storage, errors occur in the 1bit data read out by the corresponding storage unit, so that the accuracy and stability of the operation of the memory are affected.

Disclosure of Invention

The embodiment of the disclosure provides a data access processing structure, a data access processing method and a memory, which improve the accuracy and stability of the work of the memory by adjusting the number of memory cells for storing 1bit data.

An embodiment of the present disclosure provides a data access processing structure, including: n storage units, wherein N is a positive integer greater than or equal to 3; each storage unit is connected with a corresponding local data line, and the local data line is used for storing write-in data into the storage unit or reading out the storage data of the storage unit; the data processing module is characterized in that the input end of the data processing module is connected with all local data lines, the output end of the data processing module is connected with a data transmission line, the data transmission line is connected with the local data lines, and the data transmission line is used for transmitting write-in data and read-out data; the data processing module is configured to adjust output levels transmitted by the local data lines corresponding to the N memory cells to generate read data of the same level as the write data.

The data access processing structure provided by the embodiment stores 1bit data through N storage units in the data writing process by adjusting the number of the storage units for storing 1bit data; in the data reading process, the data is checked through the data processing module so as to output the read data with the same level as the written data, thereby avoiding the possible data errors of the memory and further ensuring the accuracy and stability of the operation of the memory.

In addition, the data processing module includes: each first logic circuit comprises N-1 input ends, each input end is correspondingly connected with different local data lines, and the combination of the local data lines connected with each first logic circuit is different; the second logic circuit is provided with N input ends, each input end is correspondingly connected with the output end of the first logic circuit, and the output end is used for outputting read data.

In addition, the first logic circuit and the second logic circuit are set based on nand logic circuits.

In addition, the first logic circuit and the second logic circuit are set based on nor logic circuits.

In addition, the N memory cells include: a first storage unit, a second storage unit, and a third storage unit; the data access processing structure further includes: a judging module that acquires difference data based on the write data and read-out levels of the first, second, and third memory units, and generates a first control signal or a second control signal based on the number of the difference data; if the number of the difference data is smaller than or equal to 1, the judging module generates a first control signal, and if the number of the difference data is larger than or equal to 2, the judging module generates a second control signal; the third logic circuit is provided with N input ends, each input end is correspondingly connected with the output end of the first logic circuit, and the output end is used for outputting read data; wherein if the first logic circuit is set based on the NAND logic circuit, the third logic circuit is set based on the AND logic circuit, and if the first logic circuit is set based on the NOR logic circuit, the third logic circuit is set based on the OR logic circuit; and a selection unit connected to the judgment module and configured to control the second logic circuit to output the read data based on the first control signal or control the third logic circuit to output the read data based on the second control signal. Based on the judgment module and the selection unit, the second logic circuit and the third logic circuit are selected as output circuits of the data processing module, no matter the number of error data in the first storage unit, the second storage unit and the third storage unit, the read data of the data processing module are the same as the write data, and possible data errors of the memory are avoided.

In addition, the judging module includes: an input register configured to store write data transmitted to the memory cell by the data transmission line; a signal detector configured to detect an output level of a local data line to which the first, second, and third memory units are connected; and a signal processing unit connected to the input register and the signal detector, configured to acquire the number of difference data based on the write data and the output level, and generate the first control signal or the second control signal based on the number of difference data.

In addition, the selection unit includes: and a gate configured to turn on a path in which the second logic circuit is located based on the first control signal or turn on a path in which the third logic circuit is located based on the second control signal.

In addition, a selection conduction unit is further arranged on the transmission path of the local data line, and the selection conduction unit is configured to conduct the local data line based on the selection signal. When a plurality of data access processing structures are arranged by arranging the selection conducting unit, the plurality of data access control structures can share the same data processing module so as to save layout area required by arranging the plurality of data access processing structures; in addition, the local data line is selectively conducted through the selective conduction unit, and the storage of the written data by partial storage units in the N storage units can be selected, so that the power consumption of the memory is saved.

In addition, the data access processing structure further includes: n-1 write control units for connecting adjacent local data lines configured to be turned on based on a write control signal to electrically connect the adjacent local data lines; the data transmission line is connected with the local data line, and comprises: the data transmission line is connected with at least one local data line corresponding to the memory unit. In the data writing stage, the data transmission line is connected with the local data line corresponding to at least one storage unit, and N-1 writing control units are used for connecting adjacent local data lines, so that the local data line corresponding to each storage unit is connected with the data transmission line; in the data reading stage, N-1 writing control units are closed, so that the read data of each local data line is prevented from being transmitted to the data transmission line, and the possibility of errors of the read data on the data transmission line is reduced.

In addition, a driver is also arranged on a data path of the data transmission line connected with the local data line. By providing the driver, write data is prevented from being attenuated at the data transferred from the data transfer line to the local data line; in addition, the driver is also arranged to prevent the read data from being directly output by the data paths of the data transmission line and the local data line, thereby causing the read error of the memory.

Another embodiment of the present disclosure further provides a data storage processing method, which is applied to the data access processing structure provided in the foregoing embodiment, including: acquiring write data and storing the write data into N storage units based on a data transmission line; reading data stored in N storage units; the output levels of the N memory cells are adjusted based on the data processing module to generate corresponding read data, and the read data is output based on the data transmission line, the level of the read data being the same as the level of the write data.

In the data storage processing method provided by the embodiment, 1bit data is stored through N storage units in the data writing process; in the data reading process, the data is checked through the data processing module so as to output the read data with the same level as the written data, thereby avoiding the possible data errors of the memory and further ensuring the accuracy and stability of the operation of the memory.

In addition, storing write data into N memory cells based on the data transmission line includes: transmitting write data based on the data transmission line; providing a write control signal to store write data into N memory cells

In addition, the N memory cells include: a first storage unit, a second storage unit, and a third storage unit; adjusting the output levels of the N memory cells based on the data processing module to generate corresponding read data, comprising: acquiring difference data based on the write data and read levels of the first, second, and third memory cells; generating a first control signal or a second control signal based on the difference data; the data processing path that generates the read data is adjusted based on the first control signal or the second control signal.

The further embodiment of the present disclosure further provides a memory, which is applied to the data access processing structure provided in the foregoing embodiment to complete data writing and data reading of the memory units, and by adjusting the number of the memory units storing 1bit data, the accuracy and stability of the memory operation are improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a schematic diagram of a data access processing structure according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a data access processing structure with a write control unit according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram illustrating a data processing module in a data access processing structure according to an embodiment of the disclosure;

FIG. 4 is a schematic diagram of a data access processing structure with three memory cells according to an embodiment of the disclosure;

fig. 5 is a schematic diagram of a specific structure of a data access processing structure provided with a judging module, a selecting unit and a third logic circuit according to an embodiment of the disclosure.

Detailed Description

As known from the background art, the data storage manner of the common memory is: 1bit data storage is independently carried out based on an independent storage unit, namely 1bit data is stored by adopting a storage unit; in this storage mode, if data is suddenly changed during transmission or storage, errors occur in the 1bit data read out by the corresponding storage unit, so that the accuracy and stability of the operation of the memory are affected.

An embodiment of the present disclosure provides a data access processing structure, which improves accuracy and stability of memory operation by adjusting the number of memory cells storing 1bit data.

Those of ordinary skill in the art will understand that in various embodiments of the present disclosure, numerous technical details are set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not be construed as limiting the specific implementation of the disclosure, and the embodiments can be combined with each other and cited with each other without contradiction.

Fig. 1 is a schematic structural diagram of a data access processing structure provided in this embodiment, fig. 2 is a schematic structural diagram of a data access processing structure provided in this embodiment and including a writing control unit, fig. 3 is a schematic structural diagram of a data processing module in the data access processing structure provided in this embodiment, fig. 4 is a schematic structural diagram of a data access processing structure provided in this embodiment and including three memory units, fig. 5 is a schematic structural diagram of a data access processing structure provided in this embodiment and including a judging module, a selecting unit and a third logic circuit, and the data access processing structure provided in this embodiment is described in detail with reference to the accompanying drawings, in which:

referring to fig. 1, a data access processing structure includes:

n memory cells 10, N is a positive integer greater than or equal to 3, each memory cell 10 is connected to a corresponding local data line 201, and the local data line 201 is used for storing write data into the memory cell 10 or reading out the data of the memory cell 10.

It should be noted that fig. 1 illustrates 3 memory units 10 as an example, which is only for understanding the data access processing structure provided in the present embodiment, and is not limited to the present embodiment; in a specific application, N may be set to a positive integer of 5, 7, or 9, etc.

For the memory cells 10 provided in this embodiment, each memory cell 10 includes a capacitor 12 and a sense amplifier 11, where the capacitor 12 characterizes that 1bit data stored in the memory cell 10 is "1" or "0" by the stored charge amount, the charge and discharge processes of the capacitor 12 are controlled by the transistors correspondingly connected, and the memory selects the corresponding bit line and word line based on the selection of the corresponding memory cell, thereby selecting the corresponding crystalThe body tube controls the corresponding capacitor 12 to charge or discharge through the conduction of the transistor so as to complete the data writing or the data reading of the memory cell; in addition, the sense amplifier 11 is based on the precharge level V _REF The precharge is performed, and the sense amplifier 11 after the precharge is used to amplify the read data of the capacitor 12, and the amplified data is outputted based on the local data line 201.

The data processing module 300 has an input end connected to all the local data lines 201, an output end connected to the data transmission line 202, and the data transmission line 202 connected to the local data lines 201, wherein the data transmission line 202 is used for transmitting write data and read data, i.e. the data transmission line is connected to each local data line 201, and the data processing module 300 is configured to adjust output levels transmitted by the local data lines 201 corresponding to the N memory cells 10 to generate read data with the same level as the write data.

With the data access processing structure provided in the present embodiment, in the data writing stage, since the data transmission line 202 is connected to the local data line 201, writing data transmitted based on the data transmission line 202 is written into the N memory cells 10 based on the local data line 201; in addition, the write data is buffered based on the ring circuit formed by the data processing module 300, the data transmission line 202 and the local data line 201, so as to continuously and stably provide the write data, thereby reducing the possibility of errors occurring in the write data during the process of writing into the memory unit 10; in the data reading stage, the memory cells 10 are connected to the data processing module 300 through the local data lines 201, the data processing module 300 generates read data based on the output levels transmitted by the N local data lines 201, specifically, since the N memory cells 10 perform data writing based on the same write data in the data writing stage, if no data error occurs in the data reading process, the N memory cells 10 output N identical output levels, if a data error occurs in one of the memory cells, the N memory cells 10 output N-1 identical output levels, and the data processing module 300 outputs the read data based on the identical levels transmitted by at least the N-1 local data lines 201, thereby ignoring the error data read by the memory cells 10 having the error. Namely, the data access processing structure provided in this embodiment stores 1bit data through N storage units in the data writing process by adjusting the number of storage units storing 1bit data; in the data reading process, the data is checked through the data processing module so as to output the read data with the same level as the written data, thereby avoiding the possible data errors of the memory and further ensuring the accuracy and stability of the operation of the memory.

In some embodiments, referring to fig. 2, the data access processing structure further comprises: n-1 write control units 200 for connecting adjacent local data lines 201, configured to be turned on based on a write control signal to connect the adjacent local data lines 201, the data transmission lines 202 connected to the local data lines 201, comprising: the data transmission line is connected to at least one local data line 201 corresponding to the memory cell 10. In the data writing stage, since the data transmission line 202 is connected with the local data line 201 corresponding to at least one memory cell 10, and N-1 writing control units 200 are used for connecting adjacent local data lines 201, so that the local data line 201 corresponding to each memory cell 10 is connected with the data transmission line 202, and the consistency of writing data into each memory cell 10 is ensured; in the data reading stage, the N-1 write control units 201 are turned off, so that the read data of each local data line 201 is prevented from being transmitted to the data transmission line 202, and the possibility of errors of the read data on the data transmission line 202 is reduced.

It should be noted that, the data transmission line 202 shown in fig. 2 is only connected to one local data line 201, which is only used for understanding the data access processing structure provided in the present embodiment by those skilled in the art, and is not limited to the present embodiment.

In this embodiment, referring to fig. 3, a data processing module 300 includes: n first logic circuits 301, each first logic circuit 301 includes N-1 input terminals, each input terminal is correspondingly connected to a different local data line 201, and the combination of the local data lines connected to each first logic circuit 301 is different; the second logic circuit 302 has N input terminals, each input terminal is correspondingly connected to the output terminal of the first logic circuit 301, and the output terminal is used for outputting readout data.

In some embodiments, the first logic 301 and the second logic 302 are based on a nand logic setting; in some embodiments, the first logic 301 and the second logic 302 are based on nor logic settings; in the following description of the present embodiment, the first logic circuit 301 and the second logic circuit 302 are illustrated as nand logic circuits, and the present embodiment is not limited thereto, and those skilled in the art may replace the illustrated nand gates with nor gates.

In one example, if the first logic circuit 301 and the second logic circuit 302 are set based on a nand logic circuit, and N is set to be C1, C2, C3, C4, and C5 for the input signals corresponding to the 5,5 memory cells, respectively, the first logic circuit 301 is set to be 5, and the numbers of the 5 first logic circuits 301 are A1, A2, A3, A4, and A5, where the input terminal of A1 is connected to C1, C2, C3, and C4, the input terminal of A2 is connected to C2, C3, C4, and C5, the input terminal of A3 is connected to C3, C4, C5, and C1, C2, and C3, respectively, and the truth table of the data processing module 300 is shown in table 1 below:

in one example, if the first logic circuit 301 and the second logic circuit 302 are set based on nor logic circuits, and N is set to be C1, C2, C3, C4, and C5 for the corresponding input signals of the 5,5 memory cells, respectively, the first logic circuit 301 is 5, and the numbers of the 5 first logic circuits 301 are A1, A2, A3, A4, and A5, where the input terminal of A1 is connected to C1, C2, C3, and C4, the input terminal of A2 is connected to C2, C3, C4, and C5, the input terminal of A3 is connected to C3, C4, C5, and C1, and the input terminal of A4 is connected to C5, C1, C2, and C3, respectively, the truth table of the data processing module 300 is shown in table 2 below:

writing data	C1	C2	C3	C4	C5	A1	A2	A3	A4	A5	Reading out data
												0	0	0	0	0	0	1	1	1	1	1	0
1	1	1	1	1	1	0	0	0	0	0	1
												0	0	0	1	0	0	0	0	0	1	0	0
1	1	1	0	1	1	0	0	0	0	0	1

It should be noted that the 1bit error shown in table 1 and table 2 occurs in the memory cell 10 connected to C3, and is not limited to the present embodiment, and is only used for understanding the working principle of the data processing module 300 in the present embodiment by those skilled in the art; as can be seen from the contents of tables 1 and 2, when the output levels of C1-C5 are not wrong or 1-bit errors exist, the read data are consistent with the write data, and the possible data errors of the memory are avoided.

In one example, referring to fig. 4, if the first logic circuit 301 and the second logic circuit 302 are set based on a nand logic circuit, and N is set to 3, N memory cells include a first memory cell, a second memory cell, and a third memory cell, assuming that output data of the local data line 201 connected to the first memory cell is C1, output data of the local data line 201 connected to the second memory cell is C2, output data of the local data line 201 connected to the third memory cell is C3, and accordingly, the first logic circuit 301 is 3, assuming that numbers of the 3 first logic circuits 301 are A1, A2, and A3, wherein input terminals of A1 are connected to C1 and C2, input terminals of A2 are connected to C2 and C3, and input terminals of A3 are connected to C3 and C1, a truth table of the data processing module 300 is shown in table 3 below:

in one example, if the first logic circuit 301 and the second logic circuit 302 are set based on nor logic circuits, and N is set to 3, where N storage units include a first storage unit, a second storage unit, and a third storage unit, it is assumed that output data of the local data line 201 connected to the first storage unit is C1, output data of the local data line 201 connected to the second storage unit is C2, output data of the local data line 201 connected to the third storage unit is C3, and accordingly, the first logic circuit 301 is 3, it is assumed that numbers of the 3 first logic circuits 301 are A1, A2, and A3, where an input terminal of A1 is connected to C1 and C2, an input terminal of A2 is connected to C2 and C3, and an input terminal of A3 is connected to C3 and C1, and a truth table of the data processing module 300 is shown in table 4 below:

writing data	C1	C2	C3	A1	A2	A3	Reading out data
								0	0	0	0	1	1	1	0
1	1	1	1	0	0	0	1
								0	0	0	1	1	0	0	0
1	1	1	0	0	0	0	1

It should be noted that, the 1bit error shown in table 3 and table 4 occurs in the memory cell 10 connected to C3, and is not limited to the present embodiment, and is only used for understanding the working principle of the data processing module 300 in the present embodiment by those skilled in the art; as can be seen from the contents of tables 3 and 4, when the output levels of C1 to C3 are not wrong or 1bit error exists, the read data is consistent with the write data, and the possible data error of the memory is avoided.

In some embodiments, referring to fig. 5, the data access processing structure further comprises: the judging module 601 obtains difference data based on the write data and read levels of the first storage unit, the second storage unit and the third storage unit, and generates a first control signal or a second control signal based on the number of the difference data, wherein if the number of the difference data is less than or equal to 1, the judging module generates the first control signal, and if the number of the difference data is greater than or equal to 2, the judging module generates the second control signal.

Specifically, the difference data is used for representing the number of error data of the read-out level from the first storage unit, the second storage unit and the third storage unit, and if the number of the difference data is less than or equal to 1, namely the read-out level of the first storage unit, the second storage unit and the third storage unit is not wrong or the read-out level of one storage unit is wrong; if the number of the difference data is greater than or equal to 2, namely the read-out level of two memory cells in the read-out levels of the first memory cell, the second memory cell and the third memory cell is wrong or all the read-out levels are wrong.

Accordingly, the data access processing structure further includes: the selection unit 602 is connected to the judging module 601 and configured to control the second logic circuit 302 to output the read data based on the first control signal or control the third logic circuit 303 to output the read data based on the second control signal, where the third logic circuit 303 has N input terminals, each input terminal is correspondingly connected to an output terminal of the first logic circuit 301, and the output terminal is used for outputting the read data, where if the first logic circuit 301 is set based on the nand logic circuit, the third logic circuit 303 is set based on the and logic circuit, and if the first logic circuit 301 is set based on the nor logic circuit, the third logic circuit is set based on the or logic circuit.

If the first logic circuit 301 is set based on the nand logic circuit, the truth table of the data processing module 300 is as follows in table 5:

writing data	C1	C2	C3	A1	A2	A3	Output circuit	Reading out data
									0	0	0	0	1	1	1	Second logic circuit 302	0
1	1	1	1	0	0	0	Second logic circuit 302	1
									0	0	0	1	1	1	1	Second logic circuit 302	0
1	1	1	0	0	1	1	Second logic circuit 302	1
									0	0	1	1	1	0	1	Third logic circuit 303	0
1	1	0	0	1	1	1	Third logic circuit 303	1
									0	1	1	1	0	0	0	Third logic circuit 303	0
1	0	0	0	1	1	1	Third logic circuit 303	1

If the first logic circuit 301 is set based on the nor logic circuit, the truth table of the data processing module 300 is as follows in table 6:

it should be noted that, the occurrence positions of the error signals shown in table 5 and table 6 are only for illustration, and are not limited to the present embodiment, and only used for understanding the working principle of the data processing module 300 in the present embodiment by those skilled in the art; as can be seen from the contents of tables 5 and 6, based on the judgment module 601 and the selection unit 602, the second logic circuit 302 or the third logic circuit 303 is selected as the output circuit of the data processing module 300, and the read data of the data processing module 300 is identical to the write data regardless of the number of error data in the first memory unit, the second memory unit and the third memory unit, so that possible data errors in the memory are avoided.

In the above example, the nand logic circuit is implemented by a nand gate, and the and logic circuit is implemented by an and gate, which is not limited to the present embodiment; in other embodiments, the nand logic circuit may be implemented by an and gate connected to an inverter, and the and logic circuit may be implemented by an nand gate connected to an inverter.

For the judgment module 601 provided in the present embodiment, the judgment module 601 includes: an input register configured to store write data transmitted to the memory cell 10 by the data transmission line 202; a signal detector configured to detect an output level of the local data line 201 to which the first, second, and third memory units are connected; and a signal processing unit connected to the input register and the signal detector, configured to acquire the number of difference data based on the write data and the output level, and generate the first control signal or the second control signal based on the number of difference data.

For the selection unit 602 provided in the present embodiment, the selection unit 602 includes: the gate is configured to turn on a path in which the second logic circuit 302 is located based on the first control signal, or to turn on a path in which the third logic circuit 303 is located based on the second control signal.

With continued reference to fig. 1, in some embodiments, a selective turn-on unit 401 is further disposed on the transmission path of the local data line 201, where the selective turn-on unit 401 is configured to turn on the local data line 201 based on the selection signal. By setting the selection conducting unit 401, when a plurality of data access processing structures are set, the plurality of data access control structures can share the same data processing module 300, so as to save layout area required by setting the plurality of data access processing structures; in addition, by selectively turning on the local data line 201 by the selection on unit 401, the storage of the write data by some memory cells 10 of the N memory cells 10 can be selected, thereby saving the power consumption of the memory.

With continued reference to fig. 1, in some embodiments, a driver 400 is further provided on the data path of the data transmission line 202 connecting the local data line 201, and by providing the driver 400, write data is prevented from being attenuated in the data transmitted from the data transmission line 202 to the local data line 201; in addition, the set driver 400 is also used to prevent the read data from being directly output from the data path with the data transmission line 202 and the local data line 201, thereby causing a read error of the memory.

It should be noted that the features disclosed in the data access processing structure provided in the foregoing embodiments may be arbitrarily combined without collision, so as to obtain a new data access processing structure embodiment.

It should be noted that, each unit referred to in this embodiment is a logic unit, and in practical application, one logic unit may be one physical unit, or may be a part of one physical unit, or may be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present application, elements that are not so close to solving the technical problem presented in the present application are not introduced in the present embodiment, but it does not indicate that other elements are not present in the present embodiment.

Another embodiment of the present disclosure provides a data access processing method, which is applied to the data access processing structure provided in the foregoing embodiment, and improves the accuracy and stability of the memory operation by adjusting the number of memory cells storing 1bit data, where the data access processing method provided in the present embodiment is described in detail below, specifically as follows:

the data access processing method comprises the following steps:

step S1, obtaining write-in data, and storing the write-in data into N storage units based on a data transmission line.

In some embodiments, step S1 comprises: step S1-1: transmitting write data based on the data transmission line; step S1-2: and providing a write control signal to store the write data into the N storage units.

Step S2, reading out the data stored in the N storage units.

In some embodiments, if the write control signal is provided in step S1, step S2 further includes stopping providing the write control signal.

And step S3, adjusting the output levels of the N storage units based on the data processing module to generate corresponding read data, and outputting the read data based on the data transmission line.

Wherein the level of the read data is the same as the level of the write data.

In one example, if the first logic circuit and the second logic circuit are set based on a nand logic circuit, and N is set to be C1, C2, C3, C4, and C5 for the input signals corresponding to the 5,5 memory cells, respectively, the first logic circuit is 5, and the numbers of the 5 first logic circuits are A1, A2, A3, A4, and A5, where the input terminal of A1 is connected to C1, C2, C3, and C4, the input terminal of A2 is connected to C2, C3, C4, and C5, the input terminal of A3 is connected to C3, C4, C5, and C1, and the input terminal of A4 is connected to C5, C1, C2, and C3, respectively, the truth table of the data processing module is referred to table 1 provided in the above embodiment; in one example, if the first logic circuit and the second logic circuit are set based on nor logic circuits, and N is set to be C1, C2, C3, C4, and C5 for the input signals corresponding to the 5,5 memory cells, respectively, the first logic circuit is 5, and the numbers of the 5 first logic circuits are A1, A2, A3, A4, and A5, where the input terminal of A1 is connected to C1, C2, C3, and C4, the input terminal of A2 is connected to C2, C3, C4, and C5, the input terminal of A3 is connected to C3, C4, C5, and C1, the input terminal of A4 is connected to C4, C5, C1, C2, and C3, respectively, and the truth table of the data processing module is referred to table 2 provided in the above embodiment.

In one example, if the first logic circuit and the second logic circuit are set based on a nand logic circuit, and N is set to 3, where N storage units include a first storage unit, a second storage unit, and a third storage unit, it is assumed that output data of a local data line connected to the first storage unit is C1, output data of a local data line connected to the second storage unit is C2, output data of a local hand limitation connected to the third storage unit is C3, and accordingly, the first logic circuit is 3, it is assumed that numbers of the 3 first logic circuits are A1, A2, and A3, where an input end of A1 is connected to C1 and C2, an input end of A2 is connected to C3 and C1, and a truth table of the data processing module refers to table 3 provided in the foregoing embodiment; in one example, if the first logic circuit and the second logic circuit are set based on nor logic circuits, and N is set to 3, where N storage units include a first storage unit, a second storage unit, and a third storage unit, the output data of the local data line connected to the first storage unit is assumed to be C1, the output data of the local data line connected to the second storage unit is assumed to be C2, the output data of the local data line connected to the third storage unit is assumed to be C3, and accordingly, the first logic circuits are assumed to be 3, and the numbers of the 3 first logic circuits are assumed to be A1, A2, and A3, where the input terminal of A1 is connected to C1 and C2, and the input terminal of A2 is connected to C3 and C1, the truth table of the data processing module refers to table 4 provided in the foregoing embodiment.

As can be seen from the contents of tables 1 to 4, when the output level of the local data line is not wrong or 1bit error exists, the read data is consistent with the write data, thereby avoiding possible data errors of the memory.

In some embodiments, if the N storage units include a first storage unit, a second storage unit, and a third storage unit, step S3 includes:

step S3-1, acquiring difference data based on the write data and the read level of the first, second and third memory cells.

And step S3-2, generating a first control signal and a second control signal based on the difference data.

Step S3-3, adjusting a data processing path for generating read data based on the first control signal or the second control signal.

Specifically, the path of the second logic circuit is conducted based on the first control signal, or the path of the third logic circuit is conducted based on the second control signal.

Based on the contents of table 5 and table 6 provided in the foregoing embodiments, the second logic circuit and the third logic circuit are selected as the output circuits of the data processing module, and the read data of the data processing module is the same as the write data regardless of the number of error data in the first memory cell, the second memory cell and the third memory cell, so that possible data errors of the memory are avoided.

Since the above-described embodiment corresponds to the present embodiment, the present embodiment can be implemented in cooperation with the above-described embodiment. The related technical details mentioned in the foregoing embodiments are still valid in this embodiment, and the technical effects that can be achieved in the foregoing embodiments may also be achieved in this embodiment, so that the repetition is reduced, and details are not repeated here. Accordingly, the related technical details mentioned in the present embodiment can also be applied to the above-described embodiments.

It should be noted that, features disclosed in the data access processing method provided in the foregoing embodiments may be arbitrarily combined without collision, so as to obtain a new data access processing method embodiment.

Yet another embodiment of the present disclosure provides a memory, in which data writing and data reading to a memory cell are completed based on the data access processing structure provided in the foregoing embodiment, so as to improve accuracy and stability of operation of the memory.

In particular, the memory may be a memory cell or device based on a semiconductor device or component. For example, the memory device may be a volatile memory such as dynamic random access memory DRAM, synchronous dynamic random access memory SDRAM, double data rate synchronous dynamic random access memory DDR SDRAM, low power double data rate synchronous dynamic random access memory LPDDR SDRAM, graphics double data rate synchronous dynamic random access memory GDDR SDRAM, double data rate type double synchronous dynamic random access memory DDR2SDRAM, double data rate type triple synchronous dynamic random access memory DDR3SDRAM, double data rate fourth generation synchronous dynamic random access memory DDR4SDRAM, thyristor random access memory TRAM, etc.; or may be a non-volatile memory such as a phase change random access memory PRAM, MRAM, resistive random access memory RRAM, etc.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific embodiments for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A data access processing structure, comprising:

n storage units, wherein N is a positive integer greater than or equal to 3;

each storage unit is connected with a corresponding local data line, and the local data line is used for storing write-in data into the storage unit or reading out the storage data of the storage unit;

the input end of the data processing module is connected with all the local data lines, the output end of the data processing module is connected with a data transmission line, the data transmission line is connected with the local data lines, and the data transmission line is used for transmitting the writing data and the reading data;

the data processing module is configured to adjust output levels transmitted by local data lines corresponding to the N memory cells to generate the read data at the same level as the write data.

2. The data access processing architecture of claim 1, wherein the data processing module comprises:

each first logic circuit comprises N-1 input ends, each input end is correspondingly connected with different local data lines, and the combination of the local data lines connected with each first logic circuit is different;

the second logic circuit is provided with N input ends, each input end is correspondingly connected with the output end of the first logic circuit, and the output end is used for outputting the read data.

3. The data access processing structure of claim 2, wherein the first logic circuit and the second logic circuit are based on a nand logic circuit arrangement.

4. The data access processing structure of claim 2, wherein the first logic circuit and the second logic circuit are based on a nor logic circuit arrangement.

5. A data access processing structure according to claim 3 or 4, comprising:

the N memory cells include: a first storage unit, a second storage unit, and a third storage unit;

the data access processing structure further includes: a judging module that acquires difference data based on the write data and read-out levels of the first, second, and third memory units, and generates a first control signal or a second control signal based on the number of the difference data;

the judging module generates the first control signal if the number of the difference data is less than or equal to 1, and generates the second control signal if the number of the difference data is greater than or equal to 2;

the third logic circuit is provided with N input ends, each input end is correspondingly connected with the output end of the first logic circuit, and the output end is used for outputting the read data;

wherein if the first logic circuit is set based on a NAND logic circuit, the third logic circuit is set based on an AND logic circuit, and if the first logic circuit is set based on a NOR logic circuit, the third logic circuit is set based on an OR logic circuit;

and a selection unit connected to the judgment module and configured to control the second logic circuit to output the readout data based on the first control signal or control the third logic circuit to output the readout data based on the second control signal.

6. The data access processing structure of claim 5, wherein the determining module comprises:

an input register configured to store write data transmitted to the memory cell by the data transmission line;

a signal detector configured to detect an output level of the local data line to which the first, second, and third memory units are connected;

and a signal processing unit connected to the input register and the signal detector, configured to acquire the number of the difference data based on the write data and the output level, and generate the first control signal or the second control signal based on the number of the difference data.

7. The data access processing structure according to claim 5, wherein the selecting unit includes: and the gating device is configured to conduct a channel where the second logic circuit is located based on the first control signal or conduct a channel where the third logic circuit is located based on the second control signal.

8. The data access processing structure according to claim 1, wherein a selective turn-on unit is further provided on a transmission path of the local data line, the selective turn-on unit being configured to turn on the local data line where the local data line is located based on a selection signal.

9. The data access processing structure of claim 1, further comprising:

n-1 write control units for connecting adjacent local data lines configured to be turned on based on a write control signal to electrically connect adjacent local data lines;

the data transmission line is connected with the local data line, and comprises: the data transmission line is connected with at least one local data line corresponding to the storage unit.

10. The data access processing structure according to claim 1 or 9, wherein a driver is further provided on a data path where the data transmission line connects the local data line.

11. A data access processing method applied to the data access processing structure according to any one of claims 1 to 10, characterized by comprising:

acquiring write data and storing the write data into N storage units based on a data transmission line;

reading out the data stored by the N storage units;

and adjusting the output levels of the N storage units based on the data processing module to generate corresponding read data, and outputting the read data based on the data transmission line, wherein the level of the read data is the same as the level of the write data.

12. The data access processing method according to claim 11, wherein the storing the write data into N memory cells based on a data transmission line includes:

transmitting the write data based on the data transmission line;

and providing a write control signal, and storing the write data into N storage units.

13. The data access processing method according to claim 11, characterized by comprising:

the adjusting the output levels of the N memory cells based on the data processing module to generate corresponding read data includes:

acquiring difference data based on the write data and read levels of the first, second, and third memory cells;

generating a first control signal or a second control signal based on the difference data;

a data processing path generating the read data is adjusted based on the first control signal or the second control signal.

14. A memory, characterized in that data writing and data reading to a memory cell are completed based on the data access processing structure of any one of claims 1 to 10.