CN117634414B - Fly line interconnection method between different components, electronic equipment and storage medium - Google Patents
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Abstract
The invention relates to the technical field of Electronic Design Automation (EDA), in particular to a flying lead interconnection method between different components, electronic equipment and a storage medium. The method comprises the steps of obtaining a first component D1 and a second component D2 to be connected; designating a mapping relation between K pairs of network names of the first component and network names of the second component; calculating the shortest distance between pins in the mapping relation of each pair of network names, and creating a flying line by taking two pins of the shortest distance as endpoints; wherein the calculating step of the shortest distance comprises the following steps: searching all pins with the same name as the appointed network in the D1 to obtain a pin set S1; searching all pins with the same name as the appointed network in the D2 to obtain a pin set S2; and calculating the shortest distance from all pins in S1 to all pins in S2 to obtain the shortest distance between pins in the kth pair of mapping relations. The method can create the flying line during design and visualize the layout of the flying line in real time.
Description
Technical Field
The invention relates to the technical field of Electronic Design Automation (EDA), in particular to a flying lead interconnection method between different components, electronic equipment and a storage medium.
Background
In the circuit board design process, circuit elements which cannot be connected through wiring sometimes occur, and the design is required in a flying lead mode. Flying leads are also wires that are not integrated into the interior of the component. After the production of the components is finished, the related pins of the two components are required to be connected during the assembly, and the connection line between any two pins is a flying wire, and the flying wire can be a conductive metal connection line or a connection line generated on a circuit diagram during the circuit design.
When the conventional EDA tools are used for collaborative design, the design of flying leads cannot be simultaneously considered when a plurality of designs are laid out, so that the flying leads have no reasonable layout, and therefore, a method for simultaneously designing the flying leads is needed.
Disclosure of Invention
Aiming at the technical problems, the invention adopts the following technical scheme: a flying lead interconnection method between different components, the method comprising the steps of:
s200, acquiring a first component D1 and a second component D2 to be connected, wherein the first component D1 and the second component D2 are provided with N pins, the D2 is provided with M pins, and the D1 and the D2 respectively comprise a plurality of pins with the same network name.
S400, appointing the mapping relation { PP ] between the network name of the K pairs of the first component and the network name of the second component 1 ,PP 2 ,…,PP k ,…,PP K }，PP k The value range of K is 1 to K for the mapping relation of the kth pair of network names; PP (Polypropylene) k The ith network name net with the mapping relation of D1 D1,i J-th network name net with D2 D2,j And (3) connecting, wherein i and j are equal to or greater than 1.
S600, calculating the shortest distance between pins in the mapping relation of each pair of network names, and creating a flying line by taking two pins of the shortest distance as endpoints; wherein PP is k The calculating step of the shortest distance between the pins comprises the following steps:
s620, find the and net in D1 D1,i All pins are identical, resulting in a pin set S1.
S640, find the net in D2 D2,j All pins are identical, resulting in a pin set S2.
S660, calculating the shortest distance between all pins in S1 and all pins in S2 to obtain the shortest distance between pins in the kth pair of mapping relations.
The present invention also provides a non-transitory computer readable storage medium having stored therein at least one instruction or at least one program loaded and executed by a processor to implement the above-described method.
Furthermore, the invention also provides an electronic device comprising a processor and the non-transitory computer readable storage medium.
The invention has at least the following beneficial effects:
the embodiment of the invention provides a fly line interconnection method, electronic equipment and a storage medium between different components, which are used for designating the mapping relation of network names between two different components; the method can simultaneously create the flying leads in design and visualize the flying lead layout in real time, and solves the problem that a plurality of designs cannot consider the flying lead layout design in the prior art.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a fly-line interconnection method between different components provided in a first embodiment of the invention;
fig. 2 is a flowchart of a method for acquiring a shortest flying line path according to a second embodiment of the present invention;
fig. 3 is a flowchart of an optimization method for obtaining a shortest flying-line path according to a third embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
When the conventional EDA tools are used for collaborative design, the design of flying leads cannot be simultaneously considered when a plurality of designs are laid out, so that the flying leads have no reasonable layout, and therefore, a method for simultaneously designing the flying leads is needed. In order to solve the technical problem, the present invention provides a first embodiment.
Example 1
Referring to fig. 1, a flowchart of a method for fly-line interconnection between different components is shown, the method includes the following steps:
s200, acquiring a first component D1 and a second component D2 to be connected, wherein the first component D1 and the second component D2 are provided with N pins, the D2 is provided with M pins, and the D1 and the D2 respectively comprise a plurality of pins with the same network name. It should be noted that, multiple different pins with the same network name in the same component are physically connected to each other.
Wherein D1 and D2 are components with different designs respectively.
S400, appointing the mapping relation { PP ] between the network name of the K pairs of the first component and the network name of the second component 1 ,PP 2 ,…,PP k ,…,PP K }，PP k The value range of K is 1 to K for the mapping relation of the kth pair of network names; PP (Polypropylene) k The ith network name net with the mapping relation of D1 D1,i J-th network name net with D2 D2,j And (3) connecting, wherein i and j are equal to or greater than 1.
Wherein, the specified mapping relationship is a mapping relationship between network names and network names. A fly line connection needs to be created between two network names that specify a mapping relationship. When the mapping relationship is specified, the mapping relationship of K pairs can be specified, and the mapping relationship is specified by a user.
S600, calculating the shortest distance between pins in the mapping relation of each pair of network names, and creating a flying line by taking two pins of the shortest distance as endpoints. By this step, all network names of the specified mapping relationship can be created into flyers. By creating the flying leads, the user can intuitively see the flying lead layout among the devices, and the user can adjust the devices through moving, overturning and other operations so as to update the flying lead layout in real time, so that the user can intuitively compare and select more reasonable layout.
Further, PP k Shortest distance between middle pinsThe calculating step of the separation comprises the following steps:
s620, find the and net in D1 D1,i All pins are identical, resulting in a pin set S1.
S640, find the net in D2 D2,j All pins are identical, resulting in a pin set S2.
S660, calculating the shortest distance between all pins in S1 and all pins in S2 to obtain the shortest distance between pins in the kth pair of mapping relations.
Specifically, when all pins in S1 are { P S1,1 ,P S1,2 ,…,P S1,q …,P S1,Q }，P S1,q Q is the total number of pins in S1, and the value range of Q is 1 to Q; when all pins in S2 are { P S2,1 ,P S2,2 ,…,P S2,e, …,P S2,E }，P S2,e E is the total number of pins in S2, and the value range of E is 1 to E; shortest distance D from all pins in S1 to all pins in S2 min The calculation steps of (1) adopt an exhaustion method, comprising: respectively calculate P S1,1 Distance sequence D is obtained from the distances between the pins in S2 and all pins S1,1 The method comprises the steps of carrying out a first treatment on the surface of the Calculation of P S1,2 Distance sequence D is obtained from the distances between the pins in S2 and all pins S1,2 And by analogy, respectively calculating the distance between each pin in the S1 and all pins in the S2 to obtain a distance sequence corresponding to each pin in the S1; and (3) sequencing the distance sequences of all the pins in the S1 to obtain the shortest distance. Other algorithms for calculating the shortest distance in the prior art fall within the scope of the present invention.
As a preferred embodiment, the algorithm for calculating the shortest distance is further optimized. The calculating step of the shortest distance from all pins in S1 to all pins in S2 comprises the following steps:
s662, a reference difference coordinate and a reference distance DD are obtained, wherein the reference difference coordinate comprises an abscissa reference difference dx and an ordinate reference difference dy. Alternatively, the initial values of the reference difference coordinates and the reference distance DD may be specified by the user.
As a preferred embodiment, S662 further includes the step of acquiring initial values of the reference difference coordinate and the reference distance DD:
s6622, obtain the first pin pair CP by exhaustion method 1,1 。
It should be noted that the exhaustion method is to combine all pins in S1 and all pins in S2 two by two to obtain different pin pairs. Wherein S1 and S2 are two arrays respectively, two layers of traversal are performed according to index numbers of the arrays, the first layer of traversal is to traverse each pin in S1, the second layer of traversal is to traverse each pin in S2, and the second layer of traversal is nested when any pin in S1 is traversed. Thus, the first pin pair of the traversal is the first pin of the first-tier traversal and the first pin of the second-tier traversal.
S6624, obtain CP 1,1 The difference coordinates include the difference dx of the abscissa of the pin pair 1,1 Difference dy from the ordinate 1,1 . As an example, when the coordinates of the pin pair are (x 11 ,y 11 ) And (x) 21 ,y 21 ) When dx=x 11 -x 21 ,dy=y 11 -y 21 。
S6626 according to CP 1,1 Obtaining a candidate distance DD by calculating the square value of the distance between the pin pairs according to the difference coordinates 1,1 . Wherein DD is provided with 1,1 The method meets the following conditions: DD (DD) 1,1 = dx 1,1 2 +dy 1,1 2 。
S6628, CP 1,1 Is designated as the initial value of the reference difference coordinate, DD 1,1 Designated as an initial value of the reference distance DD.
And after the difference coordinate of the first pin pair is used as the initial value of the reference difference coordinate and the candidate distance is used as the initial value of the reference distance DD, traversing the next pin pair, comparing the data of the next pin pair with the reference value, and updating the reference value in real time can reduce the calculation complexity and improve the calculation efficiency.
S664, sequentially processing each pin pair by an exhaustion method to obtain the shortest distance; wherein, when the pin pair CP consisting of the w-th pin in the S1 and the v-th pin in the S2 is obtained w,v When the method comprises the following processing steps:
s6642 obtaining CP w,v The difference coordinates include the difference dx of the abscissa of the pin pair w,v Difference dy from the ordinate w,v 。
S6644 when dx w,v Greater than dx and dy w,v When the number is greater than dy, ending calculation, and acquiring the next pin pair through an exhaustion method; when dx w,v Less than dx and dy w,v When less than dy, according to CP w,v Obtaining a candidate distance DD by calculating the square value of the distance between the pin pairs according to the difference coordinates w,v When DD w,v When the DD is smaller than the DD, the DD is updated to DD w,v And updating the reference difference coordinates to CP w,v Is a difference coordinate of (c).
When dx w,v Greater than dx and dy w,v When dy is larger than dy, calculation is finished, most pin pairs can be screened out, candidate distances can be screened out without further calculation, and a large amount of hardware calculation resources are saved. Furthermore, the shortest distance can be obtained while the exhaustion method is completed by updating the reference difference coordinate and the reference distance DD in real time, so that the calculation efficiency is further improved.
The calculating step can avoid the traditional calculation of the distance between two pins through the root number, and improves the calculating efficiency; meanwhile, as most of pin pairs are shielded through the reference value, the calculation efficiency can be further improved.
As a preferred embodiment, the present invention further includes S300, obtaining a mapping table of pins and network names, including:
s320, obtaining a mapping table PN of pins and network names in D1 D1 ={PN D1,1 ,PN D1,2 ,…,PN D1,f ,…,PN D1,F }，PN D1,f For the f network name net in D1 D1,f And all of D1 have net D1,f Wherein F is the number of network names in D1, and F is the number of network names in D1.
S620, according to PN D1 Find the AND net in D1 D1,i All pins are identical, resulting in a pin set S1. It should be noted that searching PN by using network name as index D1 Obtaining a mapping to a current network nameAnd (3) regarding the relation, wherein all pins in the mapping relation are S1.
S340, obtaining a mapping table PN of pins and network names in D2 D2 ={PN D2,1 ,PN D2,2 ,…,PN D2,h ,…,PN D2,H }，PN D2,h For the h network name net in D2 D2,h And all of D2 have net D2,h Wherein the value range of H is 1 to H.
S640 according to PN D2 Find the AND net in D2 D2,j All pins are identical, resulting in a pin set S2.
Alternatively, the step of S300 may be performed before S200, or may be performed after S200 and before S600, or may be performed synchronously with S200.
Because the network names of the pins in the component are already specified in design, when in use, the network names of each pin in the component are determined, so that the mapping table of the pins and the network names is obtained before calculating the shortest distance, the corresponding pins can be obtained by searching the mapping table by taking the network names as indexes after each time of moving, overturning and other operations are performed, and all pins corresponding to each network name do not need to be searched again each time, thereby saving hardware computing resources.
As a preferred embodiment, the invention further comprises S500, S300 being performed after S400 and before S600, alternatively S500 or S300 being used, i.e. S300 and S500 are not present simultaneously in the method steps provided by the invention. S500, obtaining a mapping table of pins and network names, comprising:
s520, obtaining a mapping table PPN of pins and network names in D1 D1 ={PPN D1,1 ,PPN D1,2 ,…,PPN D1,r ,…,PPN D1,R }，PPN D1,r The r-th network name net in the designated D1 D1,r And all of D1 have net D1,r Wherein R has a value ranging from 1 to R.
S620, according to PPN D1 Find the AND net in D1 D1,i All pins are identical, resulting in a pin set S1. It should be noted that searching PN by using network name as index D1 Obtaining the current and the currentAnd the mapping relation of the front network name is that all pins in the mapping relation are S1.
S540, obtaining a mapping table PPN of pins and network names in D2 D2 ={PPN D2,1 ,PPN D2,2 ,…,PPN D2,t ,…,PPN D2,T }，PPN D2,r The t-th network name net in the designated D2 D2,t And all of D2 have net D2,t Wherein T has a value ranging from 1 to T.
S640 according to PPN D2 Find the AND net in D2 D2,j All pins are identical, resulting in a pin set S2.
It should be noted that, the network names in the mapping tables of the pins and the network names acquired in S500 are the network names specified in S400, and the mapping relationship of the unspecified network names is not established. This step can further save hardware computing resources and cache space.
As a preferred embodiment, S500, when the position of D1 or D2 is moved, S600 is performed according to the pin coordinates after the movement.
The embodiment of the invention provides a fly line interconnection method between different components, which comprises the steps of obtaining a first component D1 and a second component D2, and designating a mapping relation of network names, wherein the D1 and the D2 are respectively provided with a plurality of pins; the method can be used for creating the flying lead layout in real time, and can be used for simultaneously creating the flying lead layout in design, so that the problem that a plurality of designs cannot be designed in the prior art. And the flying line layout can be checked in real time after the operations such as moving and overturning are performed each time, so that the user can visually compare and select a more reasonable layout.
Embodiments of the present invention also provide a non-transitory computer readable storage medium that may be disposed in an electronic device to store at least one instruction or at least one program for implementing one of the methods embodiments, the at least one instruction or the at least one program being loaded and executed by the processor to implement the methods provided by the embodiments described above.
Embodiments of the present invention also provide an electronic device comprising a processor and the aforementioned non-transitory computer-readable storage medium.
Embodiments of the present invention also provide a computer program product comprising program code for causing an electronic device to carry out the steps of the method according to the various exemplary embodiments of the invention as described in the specification, when said program product is run on the electronic device.
An embodiment one implements how to create the shortest fly between two modules. After the shortest flying line is obtained, how to obtain the shortest flying line paths among all modules becomes a technical problem to be solved, and in the prior art, the shortest path is generated by a greedy algorithm, namely searching another node Pk closest to the current node, then searching another node closest to the current node again by taking the Pk as the current node, and so on. The greedy algorithm can ensure that the flying line between two adjacent nodes is shortest, but cannot ensure that the resulting flying line path is shortest, and therefore, a method capable of generating the shortest flying line path is needed. In order to solve the problem that the finally generated flying line path is shortest, the invention provides a second embodiment.
Example two
Referring to fig. 2, a flowchart of a method for acquiring a shortest fly-line path is shown, and the method includes the following steps:
and T100, acquiring N1 flying lines which are sequentially connected with all the nodes.
All nodes connected by the N1 flying lines are respectively different components or are respectively different pins with the same network name in the same component.
When the plurality of nodes connected by the N1 flying lines are respectively different components, each flying line is the shortest distance flying line of two components. It should be noted that, each component includes a plurality of pins, and each pin is configured with a network name. And each component comprises L pins with the same network name, wherein L is more than or equal to 0. Pins of the same network name are physically interconnected between different components. Therefore, after the mapping relation is configured between the network names of different components, the different components are connected through the pins in a flying line interconnection mode, and a plurality of flying line interconnection schemes exist, wherein one flying line can be acquired so that the distance between two pins connected through the flying line is shortest.
As a preferred embodiment, when a plurality of nodes connected by N1 flying leads are different components, the flying leads between the components are generated by the scheme provided in the first embodiment. The shortest distance flying line created by the first embodiment makes the flying line between any two components shortest, and the shortest flying line path is obtained again on the basis, so that the final flying line path finally obtained is the actual shortest flying line path.
As a preferred embodiment, N1 flying lines are generated by taking two points from all nodes at will, so the number relation between the nodes and the flying lines satisfies the following conditions: n1=n (N-1)/2, where N is the number of nodes.
And T200, sequencing all the flying lines according to the length to obtain a flying line ordered set. Optionally, the flyers are traversed in the order of length from small to large, and in T400.
T300, obtaining a target flying lead number M of the shortest flying lead path connecting all nodes, wherein M satisfies the following conditions: m=n-1, where n is the number of nodes. The target flying line number is the flying line number contained in the shortest flying line path and is used for constraining the flying line number to be sequentially traversed according to the flying line length, so that the redundant flying lines are prevented from being traversed and the calculation resources are wasted.
T400, traversing the flying lines in sequence according to the sequence of the flying lines in the flying line ordered set, and processing to obtain all selected flying lines, wherein all selected flying lines form a shortest flying line path; the processing steps when traversing the ith flying line comprise:
and T410, marking a branch index for the target node connected with the two ends of the ith flying line, and determining whether the flying line is selected according to the branch index.
Further, T410 further includes: when two target nodes connected with two ends of the ith flying line are not marked with branch indexes, selecting the ith flying line, and marking the two target nodes as the same new branch index. When two target nodes are marked as branch indexes of two different path branches, selecting an ith flying line, and unifying all branch indexes of the two path branches into the same branch index. When one of the target nodes is not marked with the branch index, the ith flying line is selected, and the target node which is not marked with the branch index is marked with the branch index of the other target node. When the branch indexes of the two target nodes are the same, the ith flying line is not selected.
Before traversing, the branch indexes of all nodes are default values, and when the branch indexes of the nodes are default values, the node is not marked in the traversing process.
Alternatively, when two target nodes are marked as the same new branch index, the new branch index is different from the branch index mark that has been used.
Alternatively, when all the branch indexes of the two path branches are unified into the same branch index, the unified same branch index may be any one branch index of the two path branches, or may be a new branch index, where the new branch index is different from the used branch index mark. For example, there are two path branches, one path branch connecting J nodes, each node having a branch index val1; the other path branch is communicated with G nodes, and the branch index of each node is val2; at this time, all val1 and val2 are unified as val1, or unified as val2, or unified as another unused new branch index.
The flying lines traversed each time can be the shortest flying line in the remaining flying lines which are not marked by the way of marking the branch index, and the paths obtained by final marking can be the shortest flying line paths after all the shortest flying line paths are traversed and communicated.
And T420, updating the selected flying lead number H, and stopping traversing when the selected flying lead number H is equal to M.
The shortest flying lines in the rest flying lines can be traversed in sequence through marking the branch index marks, and the shortest flying line path formed by the shortest flying lines is obtained when the selected flying lines are equal to the target flying line number M of the shortest flying line path.
The invention provides a method for acquiring shortest flying line paths, which comprises the steps of sorting flying lines among nodes to obtain a flying line ordered set, traversing the flying lines in the flying line ordered set in sequence, marking branch indexes for target nodes connected with two ends of each flying line when traversing each flying line, and stopping traversing when the number H of the selected nodes is equal to M to obtain the shortest flying line paths. The shortest flying lines are sequentially increased to traverse in the traversing process, and the traversing is stopped when the number of the selected flying lines is equal to the number of the target flying lines, so that the finally obtained flying line path is the shortest flying line path, is the most efficient traversing mode, and does not traverse redundant flying lines.
The second embodiment provides how to obtain the shortest flying line path connecting multiple nodes, but in practical application, more flying lines exist, for example, 40000 can be obtained for 4 ten thousand pins by adopting the method provided in the first embodiment39999 flying lines, about 8 hundred million flying lines, and the shortest path obtaining time for traversing 8 hundred million flying lines is 104s, and the time for obtaining the flying lines is longer. In order to improve the calculation efficiency of acquiring the fly line and reduce hardware calculation resources, the invention provides a third embodiment.
A second embodiment of the present invention also provides a non-transitory computer readable storage medium, which may be provided in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment, where the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the foregoing embodiment.
A second embodiment of the present invention also provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.
A second embodiment of the invention also provides a computer program product comprising program code for causing an electronic device to carry out the steps of the method according to various exemplary embodiments of the invention as described in the specification, when said program product is run on the electronic device.
Example III
Referring to fig. 3, a flowchart of an optimization method for obtaining a shortest fly-line path is shown, the method includes:
p200, applying for a memory space according to the number of flying lines connecting any two nodes, wherein the memory space SM satisfies the following conditions: sm=n (n-1)/2, where n is the number of nodes.
Any two nodes are selected from the n nodes, and the selected two nodes are connected by the flying leads, and the total number of the flying leads to be connected is n (n-1)/2. N (n-1)/2 memory spaces are required to store the n (n-1)/2 flyers with memory. The size of the allocated memory space is thus equal to the number of flyers.
The nodes are pins or components, and the meaning of the nodes is the same as that of the nodes in the first embodiment, and are not described again.
P400, obtain the ordered flyer group of goal according to node and SM, including:
p420, the intermediate reference value ref is acquired. The middle reference value is used for dividing flying lines of all design modules into a flying line group larger than the reference value and a flying line group smaller than the reference value.
Optionally, the intermediate reference value ref satisfies: ref=d/2, d= [ (x) max -x min ) 2 +(y max -y min ) 2 ] 1/2 Wherein x is min X is the minimum abscissa of all nodes max For the maximum abscissa of all nodes, y min Y is the minimum ordinate of all nodes max Is the maximum ordinate of all nodes.
As a preferred embodiment, in order to improve the computational efficiency, the intermediate reference value ref satisfies: ref=d 2 /4，D 2 =(x max -x min ) 2 +(y max -y min ) 2 。
P440, traversing all nodes to calculate the flying line length between any two nodes, and when the flying line length is smaller than ref, sequentially storing the flying line length according to the positive sequence of the memory space to obtain a target flying line group; and when the flying line length is greater than ref, sequentially storing according to the reverse order of the memory space to obtain candidate flying line groups.
The positive sequence is a sequence in which the minimum addresses in the memory space are sequentially increased. I.e. when traversing a flying lead length smaller than ref, the flying leads are put into the memory in sequence according to the increasing sequence of the memory space. The reverse order is an order sequentially decreasing from the maximum address of the memory space. Because the number of the flying lines is equal to the size of the memory space, the addresses with the increased positive sequence and the addresses with the decreased negative sequence eventually get close to each other, and finally are converged, so that the flying line data can be stored in each address in the memory space. Finally, the effect of dividing the data stored in the memory space into two different groups by ref is achieved.
And P460, sorting the target flying line groups according to the flying line length to obtain target ordered flying line groups. It should be noted that, if the number of elements in the target ordered flyer group is KK, the time spent for ordering is the square of KK, where KK is smaller than SM, and compared with the square of time SM that needs to be spent for directly ordering all flyer lengths without grouping, the ordering efficiency is improved, and the consumption of hardware computing resources is reduced.
And P600, traversing the flying line length in sequence according to the sequence of elements in the target ordered flying line group and processing to obtain the shortest flying line path.
As a preferred embodiment, P400 further comprises:
p470, when the number of elements in the target flying lead group is smaller than a preset number threshold, not updating the target flying lead group; and updating the target flying line group when the number of elements in the target flying line group is greater than or equal to a preset number threshold. The preset quantity threshold is used for limiting the quantity of elements in the target flying line group, the quantity of the elements is too large, for example hundreds of millions of elements, the calculation amount of sequencing is large, and the sequencing efficiency is low, so that the calculation efficiency can be improved through the preset quantity threshold.
Further, the updating step includes:
and P472, obtaining a new reference value according to the average value of the maximum length and the minimum length of the flying lines in the target flying line group. Optionally, a new reference value ref 1 The method meets the following conditions: ref (ref) 1 = (min+max)/2, where min is the minimum length of the flying leads in the target flying lead set and max is the maximum length of the flying leads in the target flying lead set. In the prior art, other ways for obtaining the median, the mean, the median or other values of the flying lines in the target flying line group as the reference values are also within the scope of the present invention.
P474 comparing the length of each flying line in the target flying line group with a new reference value in turn according to the positive sequence, comparing the length of the jth flying line in the target flying line group with the new reference value in turn according to the reverse sequence when the length of the kth flying line is greater than the new reference value, and exchanging the storage positions of the jth flying line and the kth flying line in the memory space when the length of the kth flying line is less than the new reference value, thereby finally obtaining the new target flying line group and the new candidate flying line group. It should be noted that, in this step, the flying leads in the target flying lead group are shifted into two groups again according to the new reference value, so that all the flying leads smaller than the new reference value are located in the new target flying lead group and are stored in the first half part of the memory space. So that all the reference values greater than the new reference value are located in the new candidate flying lead group and stored in the second half of the memory space.
P476, when the number of flying leads in the new target flying lead set is greater than the preset number threshold, P470 is performed again.
As a preferred embodiment, P600 further comprises:
and P620, marking a branch index for the target node connected with the two ends of the ith flying line, and determining whether the flying line is selected according to the branch index.
P640, updating the selected flying lead number H, and stopping traversing when the selected flying lead number H is equal to the target flying lead number M, wherein M satisfies the following conditions: m=n-1.
It should be noted that the steps of P620-P640 are the same as the steps of S410-S420 in the first embodiment, and will not be repeated.
As a preferred embodiment, P600 further comprises:
p660, when the number H of traversals is smaller than M, sequencing the flying lines in the candidate flying line groups according to the flying line length to obtain candidate ordered flying line groups; P620-P660 is again performed with the candidate ordered flight line group as the new target ordered flight line group.
As an example, when all flyers are saved in memory space as target flyer group A 1 And candidate flying lead group B 1 When in use; if A 1 If the number of flying lines in the system is larger than the preset number threshold value, then A is carried out 1 Saved as new target flying lead group A again in accordance with step P470 11 And candidate flying lead group B 11 The method comprises the steps of carrying out a first treatment on the surface of the If A 11 If the number of flying lines in the system is still greater than the preset number threshold value, then A is carried out 11 Saved as new target flying lead group A again in accordance with step P470 111 And candidate flying lead group B 111 . In pair A 111 When the shortest fly-line path is obtained by processing according to P600 after sequencing, if A 111 When the number of flying leads in the system is smaller than H, then the system is corresponding to B 111 After sorting, traversing according to P600; if A 111 And B 111 If the total number of the flying lines is still smaller than H, then the candidate flying line group B 11 As a processing object, the traversal is stopped until the number of flying lines traversed by P600 is equal to M, and so on.
The method provided by the third embodiment of the invention has much higher efficiency of acquiring the shortest path than the second embodiment of the invention. For example, for 4 ten thousand pins, 40000 can be obtained by the method provided in embodiment two39999 flying lines, about 8 hundred million flying lines, and the time for traversing 8 hundred million flying lines to obtain the shortest path is 104s. And 12s when the method provided by the third embodiment of the invention is adopted to obtain the time of the shortest path.
The embodiment of the invention provides an optimization method for acquiring a shortest flying line path, which comprises the steps of storing flying lines into a memory space with the same size, dividing the flying lines stored in the memory space into two groups through a reference value, sequencing the flying lines in a target flying line group smaller than the reference value, traversing the sequencing flying lines to obtain a target ordered flying line group, traversing the flying line length in sequence according to the sequence of elements in the target ordered flying line group, and processing the traversed flying lines to obtain the shortest flying line path, thereby improving the efficiency of acquiring the shortest flying line path.
A third embodiment of the present invention also provides a non-transitory computer readable storage medium that may be provided in an electronic device to store at least one instruction or at least one program related to implementing one method of the method embodiments, where the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided by the above embodiments.
A third embodiment of the present invention also provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.
A third embodiment of the invention also provides a computer program product comprising program code for causing an electronic device to carry out the steps of the method according to various exemplary embodiments of the invention as described in the specification, when said program product is run on the electronic device.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. Those skilled in the art will also appreciate that many modifications may be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (10)
1. The fly line interconnection method between different components is characterized by comprising the following steps:
s200, acquiring a first component D1 and a second component D2 to be connected, wherein the first component D1 and the second component D2 are provided with N pins, the D2 is provided with M pins, and the D1 and the D2 respectively comprise a plurality of pins with the same network name;
s400, appointing the mapping relation { PP ] between the network name of the K pairs of the first component and the network name of the second component 1 ,PP 2 ,…,PP k ,…,PP K }，PP k The value range of K is 1 to K for the mapping relation of the kth pair of network names; PP (Polypropylene) k The ith network name net with the mapping relation of D1 D1,i J-th network name net with D2 D2,j A connection, wherein i and j are each 1 or more;
s600, calculating the shortest distance between pins in the mapping relation of each pair of network names, and creating a flying line by taking two pins of the shortest distance as endpoints; wherein PP is k The calculating step of the shortest distance between the pins comprises the following steps:
s620, find the and net in D1 D1,i All the same pins obtain a pin set S1;
s640, find the net in D2 D2,j All the same pins obtain a pin set S2;
s660, calculating the shortest distance between all pins in S1 and all pins in S2 to obtain the shortest distance between pins in the kth pair of mapping relations.
2. The method of claim 1, wherein S660 further comprises:
s662, acquiring a reference difference coordinate and a reference distance DD, wherein the reference difference coordinate comprises an abscissa reference difference dx and an ordinate reference difference dy;
s664, sequentially processing each pin pair by an exhaustion method to obtain the shortest distance; wherein, when the pin pair CP consisting of the w-th pin in the S1 and the v-th pin in the S2 is obtained w,v When the method comprises the following processing steps:
s6642 obtaining CP w,v The difference coordinates include the difference dx of the abscissa of the pin pair w,v Difference dy from the ordinate w,v ；
S6644 when dx w,v Greater than dx and dy w,v When the value is greater than dy, ending the calculation; when dx w,v Less than dx and dy w,v When less than dy, according to CP w,v Obtaining a candidate distance DD by calculating the square value of the distance between the pin pairs according to the difference coordinates w,v When DD w,v When the DD is smaller than the DD, the DD is updated to DD w,v And updating the reference difference coordinates to CP w,v Is the difference coordinates of (2)。
3. The method of claim 2, wherein S662 further comprises the step of obtaining initial values of the reference difference coordinates and the reference distance DD.
S6622, obtain the first pin pair CP by exhaustion method 1,1 ；
S6624, obtain CP 1,1 The difference coordinates include the difference dx of the abscissa of the pin pair 1,1 Difference dy from the ordinate 1,1 ；
S6626 according to CP 1,1 Obtaining a candidate distance DD by calculating the square value of the distance between the pin pairs according to the difference coordinates 1,1 ；
S6628, CP 1,1 Is designated as the initial value of the reference difference coordinate, DD 1,1 Designated as an initial value of the reference distance DD.
4. The method of claim 1, wherein S400 is preceded by:
s300, obtaining a mapping table of pins and network names, comprising:
s320, obtaining a mapping table PN of pins and network names in D1 D1 ={PN D1,1 ,PN D1,2 ,…,PN D1,f ,…,PN D1,F }，PN D1,f For the f network name net in D1 D1,f And all of D1 have net D1,f Wherein F is the number of network names in D1, and F is the number of pins of the circuit board;
s620, according to PN D1 Find the AND net in D1 D1,i All pins are identical, resulting in a pin set S1.
5. The method of claim 4, wherein S300 further comprises:
s340, obtaining a mapping table PN of pins and network names in D2 D2 ={PN D2,1 ,PN D2,2 ,…,PN D2,h ,…,PN D2,H }，PN D2,h For the h network name net in D2 D2,h And all of D2 have net D2,h The mapping relation between pins of (1) and (H), wherein the value range of H is 1 to H;
s640 according to PN D2 Find the AND net in D2 D2,j All pins are identical, resulting in a pin set S2.
6. The method of claim 1, wherein S400 further comprises, after:
s500, obtaining a mapping table of pins and network names, comprising:
s520, obtaining a mapping table PPN of pins and network names in D1 D1 ={PPN D1,1 ,PPN D1,2 ,…,PPN D1,r ,…,PPN D1,R }，PPN D1,r The r-th network name net in the designated D1 D1,r And all of D1 have net D1,r Wherein the value range of R is 1 to R;
s620, according to PPN D1 Find the AND net in D1 D1,i All pins are identical, resulting in a pin set S1.
7. The method of claim 6, wherein S500 further comprises:
s540, obtaining a mapping table PPN of pins and network names in D2 D2 ={PPN D2,1 ,PPN D2,2 ,…,PPN D2,t ,…,PPN D2,T }，PPN D2,r The t-th network name net in the designated D2 D2,t And all of D2 have net D2,t Wherein the value range of T is 1 to T;
s640 according to PPN D2 Find the AND net in D2 D2,j All pins are identical, resulting in a pin set S2.
8. The method of claim 1, wherein S500 is performed according to the pin coordinates after the movement when the position of D1 or D2 is moved.
9. A non-transitory computer readable storage medium having stored therein at least one instruction or at least one program, wherein the at least one instruction or the at least one program is loaded and executed by a processor to implement the method of any one of claims 1-8.
10. An electronic device comprising a processor and the non-transitory computer readable storage medium of claim 9.
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