CN117634412A - Level shifter unit, power supply wiring method and device thereof, and storage medium - Google Patents

Abstract

A level shifter unit, a power supply wiring method and device thereof, and a storage medium, the method comprising: when the chip is designed, a level shifter unit library is called to generate a level shifter unit, wherein the level shifter unit comprises at least one power pin to be wired, which is positioned on an I-th metal layer, I is more than or equal to 1, and a power wire corresponding to the power pin to be wired is positioned on an N-th metal layer, I is less than N, and N is more than or equal to 5; invoking a pre-stored wiring unit to generate a power wiring structure of a power supply pin to be wired, wherein the wiring unit comprises power supply connecting wires sequentially distributed from an (I+1) th metal layer to an (N-2) th metal layer, the power supply connecting wires of the I th metal layer are connected with the power supply connecting wires of the (I-1) th metal layer, the power supply connecting wires of the (I+1) th metal layer are connected with the power supply pin to be wired, the equivalent wiring width of the power supply connecting wires in the (I+1) th metal layer to the K th metal layer is larger than the initial design width of the corresponding metal layer, I is not less than (I+2) is not more than (N-2), and K is not more than N-2.

Description

Level converter unit, power supply wiring method and device, and storage medium thereof

Technical field

The present disclosure relates to, but is not limited to, the technical field of integrated circuit design, and in particular, to a level converter unit, its power supply wiring method and device, and storage medium.

Background technique

In the chip design and manufacturing process, voltage drop (IR Drop) has a very large impact, which may cause the performance of the chip to decline. In serious cases, the chip may not work. Therefore, the IR Drop must be reduced to Within the controllable range. Due to the continuous evolution of technology, the width of metal interconnect lines is getting narrower and narrower, the resistance value is getting larger and larger, the supply voltage is getting smaller and smaller, and the effect of IR Drop is becoming more and more obvious.

Contents of the invention

The following is an overview of the topics described in detail in this article. This summary is not intended to limit the scope of the claims.

Embodiments of the present disclosure provide a level converter unit power supply wiring method. The method includes: during chip design, calling a level converter unit library to generate a level converter unit. The level converter unit includes at least A power supply pin to be wired, the power supply pin to be wired is located on the Ith metal layer of the chip, I≥1, and the power line corresponding to the power supply pin to be wired is located on the Nth metal layer of the chip, I< N, N≥5; call the pre-stored wiring unit to generate the power wiring structure of the power pin to be wired, the wiring unit includes from the (I+1)th metal layer to the (N-2)th metal layer The power connection lines are arranged in layers, the power connection line of the i-th metal layer is connected to the power connection line of the (i-1)-th metal layer, and the power connection line of the (I+1)-th metal layer is connected to the power connection line to be The power pins of the wiring are connected, and the equivalent trace width of the power connection lines in the (I+1)-th metal layer to the K-th metal layer is greater than the initial design width of the corresponding metal layer, (I+2)≤ i≤(N-2), K≤N-2.

An embodiment of the present disclosure also provides a level converter unit power supply wiring device, including a memory; and a processor connected to the memory, where the memory is used to store instructions, and the processor is configured to store instructions based on the The instructions in the memory are used to execute the steps of the level converter unit power supply wiring method according to any embodiment of the present disclosure.

An embodiment of the present disclosure also provides a level converter unit. The power supply wiring structure of at least one power supply pin in the level converter unit is generated by calling a pre-stored wiring unit; the power supply pin is located on the third side of the chip. I metal layer, I≥1, the power line corresponding to the power pin is located in the Nth metal layer of the chip, I<N, N≥5, the wiring unit includes from the (I+1)th metal layer to the ((I+1)th metal layer N-2) The power supply connection lines arranged in the metal layers in sequence, the power supply connection lines of the i-th metal layer are connected to the power supply connection lines of the (i-1)th metal layer, and the power supply connection lines of the (I+1)th metal layer are connected The line is connected to the power pin, and the equivalent trace width of the power connection line in the (I+1)-th metal layer to the K-th metal layer is greater than the initial design width of the corresponding metal layer, (I+2 )≤i≤(N-2), K≤N-2.

An embodiment of the present disclosure also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the level converter unit power supply wiring method as described in any embodiment of the present disclosure is implemented.

The level converter unit, its power supply wiring method and device, and the storage medium in the embodiment of the present disclosure generate a level converter unit by calling a level converter unit library during chip design. The level converter unit includes at least one to-be-used level converter unit. The power pins to be routed are located on the Ith metal layer of the chip, I≥1, and the power lines corresponding to the power pins to be routed are located on the Nth metal layer of the chip, I<N, N≥5; Call the pre-stored wiring unit to generate the power wiring structure of the power pin to be routed. The wiring unit includes power connection lines arranged sequentially from the (I+1)th metal layer to the (N-2)th metal layer. The power connection line of the i metal layer is connected to the power connection line of the (i-1)th metal layer, the power connection line of the (I+1)th metal layer is connected to the power pin to be routed, and the (I+1)th The equivalent trace width of the power connection line from the metal layer to the Kth metal layer is greater than the initial design width of the corresponding metal layer, (I+2)≤i≤(N-2), K≤N-2, which can be reduced The IR Drop of the level converter unit improves the design efficiency of integrated circuits, allowing integrated circuits to be quickly commercialized and meet sign-off standards. After testing in actual photo design projects, this method can reduce the IR_Drop of the level converter unit to less than 6%, greatly reducing the risk of chip failure.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the application. Other advantages of the application can be realized and obtained by the solutions described in the specification and drawings.

Description of drawings

The drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. They are used to explain the technical solution of the present disclosure together with the embodiments of the present disclosure and do not constitute a limitation of the technical solution of the present disclosure.

Figure 1 is a schematic diagram of the layout and wiring of a level converter unit generated through a script;

Figure 2 is a schematic flowchart of a level converter unit power supply wiring method according to an exemplary embodiment of the present disclosure;

Figure 3A is a schematic diagram of the power supply pin distribution (first metal layer) of a level converter unit according to an exemplary embodiment of the present disclosure;

Figure 3B is a schematic diagram of the power connection line of the second metal layer designed for the power pin to be routed in Figure 3A;

Figure 3C is a schematic diagram of the power connection line of the third metal layer designed for the power pin to be routed in Figure 3A;

Figure 3D is a schematic diagram of the power connection line of the fourth metal layer designed for the power pin to be routed in Figure 3A;

Figure 3E is a schematic diagram of the power connection line of the fifth metal layer designed for the power pin to be routed in Figure 3A;

Figure 3F is a schematic diagram of the power connection line of the sixth metal layer designed for the power pin to be routed in Figure 3A;

Figure 4 is a schematic diagram of a wiring unit designed for the power pins to be routed in Figure 3A;

Figure 5 is a schematic diagram of the power connection line of the seventh metal layer of a level converter unit design provided by an embodiment of the present disclosure;

Figure 6 is a schematic diagram of the power connection line of the seventh metal layer designed for multiple level converter units at different positions provided in Figure 5 according to the embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of a power supply wiring device for a level converter unit according to an exemplary embodiment of the present disclosure.

Detailed ways

This application describes multiple embodiments, but the description is illustrative rather than restrictive, and it is obvious to those of ordinary skill in the art that within the scope of the embodiments described in this application, There are many more examples and implementations. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Unless expressly limited, any feature or element of any embodiment may be used in combination with, or may be substituted for, any other feature or element of any other embodiment.

This application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features and elements that have been disclosed in this application may also be combined with any conventional features or elements to form unique inventive solutions as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution as defined by the claims. Therefore, it should be understood that any feature shown and/or discussed in this application may be implemented individually or in any suitable combination. Accordingly, the embodiments are not to be limited except by those appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Additionally, in describing representative embodiments, the specification may have presented methods and/or processes as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of steps described herein, the method or process should not be limited to the specific order of steps described. As one of ordinary skill in the art will appreciate, other sequences of steps are possible. Therefore, the specific order of steps set forth in the specification should not be construed as limiting the claims. Furthermore, claims directed to the method and/or process should not be limited to steps performing them in the order written, as those skilled in the art can readily understand that these orders may be varied and still remain within the spirit and scope of the embodiments of the present application. Inside.

Unless otherwise defined, the technical terms or scientific terms used in the disclosure of the embodiments of the present disclosure shall have the usual meanings understood by those with ordinary skill in the art to which the disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "include" mean that the elements or things preceding the word include the elements or things listed after the word and their equivalents, without excluding other elements or things.

Chip design is divided into front-end design and back-end design. Front-end design is also called logic design. The result of front-end design is the gate-level netlist circuit of the chip. Back-end design is also called physical design, including layout planning, wiring, and layout physical verification. etc., where wiring includes wiring between various standard units (basic logic gate circuits). During the wiring process, gate-level circuits need to be routed based on the netlist and constraint files synthesized by logic and using various standard cell libraries provided by manufacturers.

The standard unit library includes layout library, symbol library, circuit logic library, etc., including combinational logic, sequential logic, functional units and special type units. It is a basic part of the back-end design process of integrated circuit chips. Using pre-designed and optimized standard cell libraries for automatic logic synthesis and layout layout can greatly improve design efficiency and speed up the time for products to enter the market. Generally, each process manufacturer will provide corresponding standard units for each process. The following description takes a standard unit as a level shift cell (LVL cell) as an example. However, those skilled in the art will know based on the principles of the present disclosure that the power supply wiring method provided by the embodiment of the present disclosure is suitable for various applications. types of standard units, not limited to level converter units.

In a design using multi-supply voltage technology, we generally need level converter units to convert due to the different voltages between different voltage domains. The level converter unit acts like a buffer connecting a voltage domain output port and a voltage domain input port. Its main function is to convert the logic signal from one voltage to another voltage with minimal delay. The information on level converter units in the standard unit library generally includes the following aspects: (1) Level conversion type: generally can be divided into level converter units from low level to high level and from high level There are two types of level converter units to low levels; (2) the size of the supported voltage; (3) the pin connected to a specific voltage. The physical design implementation EDA tool can find the appropriate level converter unit in the standard unit library according to the specific situation, insert the appropriate level converter into the netlist, and then place it reasonably and connect the corresponding connections to complete the design. .

In a chip design process, the level converter unit provided by the wafer factory passes through the first metal layer (in the embodiment of the present disclosure, the first metal layer to the Nth metal layer are arranged in sequence in the direction away from the base substrate, Among them, N is a natural number greater than 1) leads to the power pin, and winding needs to be designed from the power pin of the first metal layer to the power line of the upper layer to complete the power supply connection. However, in the current design process, due to the imperfection of the script, more low-level routing resources are automatically occupied when designing the power routing of some power pins within the level converter unit. As shown in Figure 1, assuming that the power supply pin to be routed in the example in Figure 1 is the VDDQ power supply pin (in this disclosure, the power supply pin to be routed is the data bus power supply voltage (Voltage Data Drain Quiescent, VDDQ)). The power supply pin is Example is introduced. In other examples, the power pin can be any other type of power pin). M1 indicates that the power pin is located on the first metal layer. After the winding design is completed, the power pin passes through the first connection in turn. line (power connection line located in the second metal layer M2), second connection line (power connection line located in the third metal layer M3), third connection line (power connection line located in the fourth metal layer M4), fourth The connection line (the power connection line located at the fifth metal layer M5), the fifth connection line (the power connection line located at the sixth metal layer M6) and the sixth connection line (the power connection line located at the seventh metal layer M7) are connected to As can be seen from the figure of the power line located on the eighth metal layer M8, the length of the second connecting line is longer than the length of the other connecting lines. Due to the low-layer winding (the second connecting line belongs to the low-layer winding), the wiring width is usually narrow. , using more low-layer wiring resources will increase the resistance value, which also increases the risk of IR Drop violations in the level converter unit. The actual measured IR Drop of the level converter unit can reach 15% or even higher. The industry generally believes that the acceptable IR Drop level is 10%. Therefore, it is necessary and meaningful to consider how to reduce the voltage drop of the level converter unit.

As shown in Figure 2, an embodiment of the present disclosure provides a level converter unit power supply wiring method, including:

Step 201. During chip design, a level converter unit library is called to generate a level converter unit. The level converter unit includes at least one power pin to be routed. The power pin to be routed is located on the first metal of the chip. layer, I≥1, the power line corresponding to the power pin to be routed is located on the Nth metal layer of the chip, I<N, N≥5;

Step 202: Call the pre-stored wiring unit to generate the power wiring structure of the power pin to be routed. The wiring unit includes power supplies arranged sequentially from the (I+1)th metal layer to the (N-2)th metal layer. Connection lines, the power connection line of the i-th metal layer is connected to the power connection line of the (i-1)th metal layer, the power connection line of the (I+1)th metal layer is connected to the power pin to be routed, and the (i-th) metal layer power connection line is connected to the power pin to be routed, and the (i-1)th metal layer power connection line is connected to The equivalent trace width of the power connection line from the metal layer I+1 to the Kth metal layer is greater than the initial design width of the corresponding metal layer, (I+2)≤i≤(N-2), K≤N- 2.

The level converter unit power supply wiring method in the embodiment of the present disclosure generates a level converter unit by calling a level converter unit library during chip design. The level converter unit includes at least one power pin to be routed. The wired power pin is located on the Ith metal layer of the chip, I≥1, and the power line corresponding to the power pin to be wired is located on the Nth metal layer of the chip, I<N, N≥5; call the pre-stored wiring unit, To generate a power wiring structure for the power pins to be routed, the wiring unit includes power connection lines arranged in sequence from the (I+1)th metal layer to the (N-2)th metal layer, and the power connection lines of the i-th metal layer It is connected to the power connection line of the (i-1)th metal layer, the power connection line of the (I+1)th metal layer is connected to the power pin to be routed, and the metal layer (I+1) to the Kth layer The equivalent trace width of the power connection lines in the layer is greater than the initial design width of the corresponding metal layer, (I+2)≤i≤(N-2), K≤N-2, which can reduce the IR of the level converter unit Drop improves the design efficiency of integrated circuits, enabling integrated circuits to be quickly commercialized and meet sign-off standards. After testing in actual photo design projects, this method can reduce the IR_Drop of the level converter unit to less than 6%, greatly reducing the risk of chip failure.

In the embodiment of the present disclosure, the initial design width corresponding to the metal layer may be the width of the metal trace specified for the corresponding metal layer in the initialization design file, or may be the metal width corresponding to the metal layer automatically generated by the design script when designing the power supply winding. The width of the trace.

In some exemplary implementations, the method further includes: generating and saving the wiring unit in an automatic placement and routing tool.

In the embodiment of the present disclosure, the power pin to be wired is located on the Ith metal layer of the chip. For example, I=1, that is, the power pin of the level converter unit to be wired is located on the first metal layer of the chip. The power line corresponding to the power pin to be wired is located on the Nth metal layer of the chip. For example, N=8, that is, the power line corresponding to the power pin to be wired is located on the eighth metal layer of the chip. Hereinafter, I= 1 and N=8 are taken as an example for introduction. However, the embodiment of the present disclosure does not limit this.

In the embodiment of the present disclosure, the automatic placement and routing tool may be Innovus, however, the embodiment of the present disclosure does not limit this.

Innovus is an electronic design automation (Electronic Design Automation, EDA) software tool provided by Cadence Design Systems for the physical implementation of integrated circuits. It is one of the key tools for semiconductor design and is used to optimize and realize the physical layout of integrated circuits (ICs), including layout placement, routing, timing optimization and power consumption analysis.

In some exemplary implementations, generating and saving wiring units includes:

Import the basic information of the level converter unit library. The basic information includes the size of the level converter unit library and the shape and location of the power pins;

Design the power wiring structure from the (I+1)th metal layer to the (N-2)th metal layer corresponding to the power pins to be routed;

Extract the power wiring structure from the (I+1)th metal layer to the (N-2)th metal layer and save it as a wiring unit.

In the embodiment of the present disclosure, the basic information of the level converter unit library refers to the basic information about the level converter unit in the netlist and constraint files, including the size of the level converter unit and the shape and shape of the power pin. Location etc.

For example, importing the basic information of the level converter unit library includes: deleting all content except the basic information in the current netlist and constraint files, leaving only the basic information; using the netlist and constraint files containing the basic information. The constraint file executes the initial design process and generates a database (DB) file; open the database file, add a level converter unit and rename it. A chip can include multiple level converter units, and each level converter unit can be processed in a similar way. This disclosure takes one of the level converter units as an example to introduce the level converter unit that is turned on. The structure of the power supply pins of the converter unit is shown in Figure 3A. In Figure 3A, it is assumed that the power supply pin to be routed is the VDDQ power supply pin. Other unmarked power supply pins may include chip working positive voltage (VDD), chip working negative voltage (VSS) and other power supply pins. Since the VDD power supply When the power wiring structure of VDD power pins and VSS power pins is automatically generated by tools, the problem of IR Drop generally does not occur. Therefore, the power wiring structures of VDD power pins and VSS power pins can be automatically generated by tools. Of course, in In other examples, the power pins to be routed may also be other types of power pins, which are not limited in the embodiments of the present disclosure.

In some exemplary embodiments, when designing the power wiring structure of the (I+1)th metal layer to the (N-2)th metal layer corresponding to the power pin to be routed, the (I+1)th metal layer can be Layers to the (N-2)th metal layer are designed in sequence. Taking I=1 and N=8 as an example, as shown in Figure 3B, the power connection line (i.e. the first connection line) of the second metal layer M2 is connected to the power pin of the first metal layer M1; as shown in Figure 3C , the power connection line (i.e., the second connection line) of the third metal layer M3 is connected to the power connection line (i.e., the first connection line) of the second metal layer M2; as shown in Figure 3D, the power connection line of the fourth metal layer M4 The power connection line (i.e., the third connection line) of the third metal layer M3 is connected to the power connection line (i.e., the second connection line) of the third metal layer M3; as shown in Figure 3E, the power connection line (i.e., the fourth connection line) of the fifth metal layer M5 is connected to The power connection line of the fourth metal layer M4 (i.e., the third connection line) is connected; as shown in Figure 3F, the power connection line of the sixth metal layer M6 (i.e., the fifth connection line) is connected to the power connection line of the fifth metal layer M5 (i.e. the fourth connecting line) connection. Since the equivalent trace width of the power connection lines of each layer is large, the problem of IRDrop violation will not occur in this power wiring structure. Due to the wide spacing between multiple power connection lines on each layer, the power wiring structure will not cause design rule check (DRC) violations.

After designing the power wiring structure of the (I+1)th metal layer to the (N-2)th metal layer corresponding to the power pin to be routed, as shown in Figure 4, extract the second metal layer M2 to the sixth metal layer The power routing structure of layer M6 (extract its Library Exchange Format (LEF), Design Exchange Format (DEF), Graphic Database System (GDS), Netlist (NETLIST) and other files , for subsequent design call) and saved as a routing unit.

In some exemplary embodiments, as shown in FIG. 4 , the power connection lines of each metal layer in the wiring unit are located within the level converter unit to prevent DRC violations.

In some exemplary embodiments, from the (I+2)th metal layer to the (N-2)th metal layer, the number of power connection lines in each layer is greater than or equal to 2, and the plurality of power connection lines in each layer The power connection lines are connected in parallel by connecting the power connection lines of the previous layer. The equivalent trace width of the power connection lines is equal to the sum of the trace widths of multiple power connection lines connected in parallel.

In the embodiment of the present disclosure, by arranging multiple power connection lines connected in parallel in each metal layer from the (I+2)th metal layer to the (N-2)th metal layer, the wiring resistance can be reduced, thereby reducing the IR Drop Risk of Violation.

For example, the number of power connection lines of the (I+1)th metal layer is 1, and from the (I+2)th metal layer to the (N-2)th metal layer, the number of power connection lines of each layer is The number of items is 2. However, the embodiment of the present disclosure does not limit this. The number of power connection lines of each layer can be set as needed. For example, the number of power connection lines of the (I+1)th metal layer can be set to 2, and the number of power connection lines of the (I+1)th metal layer can be set to 2. From the (I+2) metal layer to the (N-2) metal layer, the number of power connection lines of a certain layer or multiple layers can be set to 3, 4, 5, etc.

In the embodiment of the present disclosure, the metal traces (power lines or power connection lines) of the second metal layer, the fourth metal layer, the sixth metal layer, and the eighth metal layer all extend in the horizontal direction, and the third metal layer, the fifth metal layer, and the fifth metal layer all extend in the horizontal direction. The metal traces (power connection lines) of the metal layer and the seventh metal layer all extend in the vertical direction.

In the embodiment of the present disclosure, the generated wiring unit is used to automatically set the power wiring structure of the I+1th metal layer to the (N-2)th metal layer in the level converter unit, and the (N-1)th metal layer The power supply routing structure needs to be set according to the location of each level converter unit and the location of the nearest power line.

In some exemplary embodiments, the method further includes:

Determine the power line closest to the location of each level converter unit among the power lines corresponding to the power pins to be routed;

Design the power connection line of the (N-1)th metal layer corresponding to each level converter unit, and connect the power connection line of the (N-1)th metal layer corresponding to each level converter unit to each level conversion The power connection line of the (N-2)th metal layer corresponding to the converter unit itself and the power line closest to each level converter unit itself.

As shown in Figure 5 and Figure 6, a chip can include multiple level converter units and multiple power lines corresponding to power pins to be routed. The location of the nearest power line to the location of different level converter units may be Different, therefore, when we design the power connection line of the (N-1)th metal layer, we can first determine the power line closest to the location of each level converter unit, and then design the corresponding power line of each level converter unit. The power connection line of the (N-1)th metal layer of each level converter unit is connected to the (N-1)th metal layer corresponding to each level converter unit. 2) The power connection lines of the metal layer and the power lines closest to each level converter unit itself.

An embodiment of the present disclosure also provides a level converter unit power supply wiring device, including a memory; and a processor connected to the memory, where the memory is used to store instructions, and the processor is configured to store instructions based on the The instructions in the memory are used to execute the steps of the level converter unit power supply wiring method according to any embodiment of the present disclosure.

As shown in Figure 7, in one example, the level converter unit power supply wiring device may include: a processor 710, a memory 720, and a bus system 730, wherein the processor 710 and the memory 720 are connected through the bus system 730, and the memory 720 is For storing instructions, the processor 710 is used to execute the instructions stored in the memory 720 . Specifically, during chip design, the processor 710 calls a level converter unit library to generate a level converter unit. The level converter unit includes at least one power supply pin to be wired. The power supply pin to be wired is Located on the Ith metal layer of the chip, I≥1, the power line corresponding to the power pin to be routed is located on the Nth metal layer of the chip, I<N, N≥5; call the pre-stored wiring unit to generate all Describe the power wiring structure of the power pins to be wired, the wiring unit includes power connection lines arranged sequentially from the (I+1)th metal layer to the (N-2)th metal layer, and the power connection of the i-th metal layer The line is connected to the power connection line of the (i-1)th metal layer, the power connection line of the (I+1)th metal layer is connected to the power pin to be routed, and the (I+1)th The equivalent trace width of the power connection line from the metal layer to the Kth metal layer is greater than the initial design width of the corresponding metal layer, (I+2)≤i≤(N-2), K≤N-2.

It should be understood that the processor 710 can be a central processing unit (Central Processing Unit, CPU), and the processor 710 can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASICs), and off-the-shelf programmable gate arrays. (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

Memory 720 may include read-only memory and random access memory and provides instructions and data to processor 710 . A portion of memory 720 may also include non-volatile random access memory. For example, memory 720 may also store device type information.

In addition to the data bus, the bus system 730 may also include a power bus, a control bus, a status signal bus, etc. However, for the sake of clarity, the various buses are labeled bus system 730 in FIG. 3 .

During implementation, the processing performed by the processing device may be completed by instructions in the form of hardware integrated logic circuits or software in the processor 710 . That is to say, the method steps of the embodiments of the present disclosure may be implemented by a hardware processor, or may be executed by a combination of hardware and software modules in the processor. Software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media. The storage medium is located in the memory 720. The processor 710 reads the information in the memory 720 and completes the steps of the above method in combination with its hardware. To avoid repetition, it will not be described in detail here.

An embodiment of the present disclosure also provides a level converter unit. The power supply wiring structure of at least one power supply pin in the level converter unit is generated by calling a pre-stored wiring unit; the power supply pin is located on the third side of the chip. I metal layer, I≥1, the power line corresponding to the power pin is located in the Nth metal layer of the chip, I<N, N≥5, the wiring unit includes from the (I+1)th metal layer to the ((I+1)th metal layer N-2) The power supply connection lines arranged in the metal layers in sequence, the power supply connection lines of the i-th metal layer are connected to the power supply connection lines of the (i-1)th metal layer, and the power supply connection lines of the (I+1)th metal layer are connected The line is connected to the power pin, and the equivalent trace width of the power connection line in the (I+1)-th metal layer to the K-th metal layer is greater than the initial design width of the corresponding metal layer, (I+2 )≤i≤(N-2), K≤N-2.

An embodiment of the present disclosure also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the level converter unit power supply wiring method as described in any embodiment of the present disclosure is implemented. The method of driving the power supply wiring of the level converter unit by executing executable instructions is basically the same as the power supply wiring method of the level converter unit provided by the above embodiments of the present disclosure, and will not be described again here.

In some possible implementations, various aspects of the level converter unit power wiring method provided by the present disclosure can also be implemented in the form of a program product, which includes program code. When the program product is run on a computer device , the program code is used to cause the computer device to execute the steps in the level converter unit power supply wiring method according to various exemplary embodiments of the present disclosure described above in this specification. For example, the computer device can execute the present disclosure. The level converter unit power supply wiring method described in the embodiment.

The program product may take the form of any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to: electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: electrical connection with one or more conductors, portable disk, hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.

Those of ordinary skill in the art can understand that all or some steps, systems, and functional modules/units in the devices disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may consist of several physical components. Components execute cooperatively. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As is known to those of ordinary skill in the art, the term computer storage media includes volatile and nonvolatile media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. removable, removable and non-removable media. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disk (DVD) or other optical disk storage, magnetic cassettes, tapes, disk storage or other magnetic storage devices, or may Any other medium used to store the desired information and that can be accessed by a computer. Additionally, it is known to those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

It should be noted that the above-described embodiments or implementations are only illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions or omissions may be made in the form and details of the implementation without departing from the scope of the present disclosure.

Claims (10)

1. A level shifter cell power supply wiring method, comprising:

when a chip is designed, a level shifter unit library is called to generate a level shifter unit, wherein the level shifter unit comprises at least one power pin to be wired, the power pin to be wired is positioned on an I-th metal layer of the chip, I is more than or equal to 1, a power wire corresponding to the power pin to be wired is positioned on an N-th metal layer of the chip, and I is less than N, and N is more than or equal to 5;

invoking a pre-stored wiring unit to generate a power wiring structure of the power pin to be wired, wherein the wiring unit comprises power connecting wires sequentially distributed from an (I+1) th metal layer to an (N-2) th metal layer, the power connecting wires of the I th metal layer are connected with the power connecting wires of the (I-1) th metal layer, the power connecting wires of the (I+1) th metal layer are connected with the power pin to be wired, and the equivalent wiring width of the power connecting wires in the (I+1) th metal layer to the K th metal layer is larger than the initial design width of the corresponding metal layer, I is not less than (N-2), and K is not more than N-2.

2. The method according to claim 1, wherein the method further comprises:

determining the power line closest to the position of each level shifter unit in the power lines corresponding to the power pins to be wired;

designing a power supply connecting wire of an (N-1) th metal layer corresponding to each level shifter unit, wherein the power supply connecting wire of the (N-1) th metal layer corresponding to each level shifter unit is connected with the power supply connecting wire of an (N-2) th metal layer corresponding to each level shifter unit and the nearest power supply wire of each level shifter unit.

3. The method according to claim 1, characterized in that the method is preceded by: in the automatic layout wiring tool, the wiring units are generated and saved.

4. A method according to claim 3, wherein said generating and saving said wiring unit comprises:

importing basic information of the level shifter unit library, wherein the basic information comprises the size of the level shifter unit library and the shape and the position of a power pin;

designing a power wiring structure from the (I+1) th metal layer to the (N-2) th metal layer corresponding to the power pin to be wired;

and extracting the power wiring structures from the (I+1) th metal layer to the (N-2) th metal layer and storing the power wiring structures as the wiring units.

5. The method of claim 1, wherein the power connection lines of each metal layer in the wiring unit are located within the level shifter unit.

6. The method according to claim 1, wherein the number of the power connection lines of each layer is greater than or equal to 2 from the (i+2) th metal layer to the (N-2) th metal layer, and the plurality of power connection lines of each layer are connected in parallel by the power connection lines of the previous layer, and the equivalent wiring width of the power connection lines is equal to the sum of the wiring widths of the plurality of power connection lines connected in parallel.

7. The method of claim 6, wherein the number of power connection lines of the (i+1) th metal layer is 1, and the number of power connection lines of each layer is 2 from the (i+2) th metal layer to the (N-2) th metal layer.

8. A level shifter unit power supply wiring device, comprising a memory; and a processor connected to the memory, the memory for storing instructions, the processor configured to perform the steps of the level shifter unit power supply wiring method of any one of claims 1 to 7 based on the instructions stored in the memory.

9. A storage medium having stored thereon a computer program which when executed by a processor implements the level shifter unit power supply wiring method of any one of claims 1 to 7.

10. A level shifter unit, wherein a power supply wiring structure of at least one power supply pin in the level shifter unit is generated by calling a wiring unit stored in advance; the power supply pin is positioned on an I-th metal layer of the chip, I is more than or equal to 1, a power supply wire corresponding to the power supply pin is positioned on an N-th metal layer of the chip, I is less than N, N is more than or equal to 5, the wiring unit comprises power supply connecting wires sequentially distributed from the (I+1) -th metal layer to the (N-2) -th metal layer, the power supply connecting wires of the I-th metal layer are connected with the power supply connecting wires of the (I-1) -th metal layer, the power supply connecting wires of the (I+1) -th metal layer are connected with the power supply pin, and the equivalent wiring width of the power supply connecting wires from the (I+1) -th metal layer to the K-th metal layer is larger than the initial design width of the corresponding metal layer, I is less than or equal to (N-2), and K is less than or equal to N-2.