CN117623211A

CN117623211A - MEMS sensor and preparation method thereof

Info

Publication number: CN117623211A
Application number: CN202311605668.4A
Authority: CN
Inventors: 戴维·L·马克斯; 森克·阿卡尔; 苏迪尔·斯里达拉穆蒂
Original assignee: Shanghai Sirui Technology Co ltd
Current assignee: Shanghai Sirui Technology Co ltd
Priority date: 2023-11-28
Filing date: 2023-11-28
Publication date: 2024-03-01

Abstract

The application relates to a MEMS sensor and a preparation method thereof, wherein the method comprises the following steps: generating a first oxide layer on a substrate wafer, performing patterning etching on the first oxide layer, and depositing and doping the patterned etched first oxide layer to form a first polysilicon layer; patterning and etching the first polysilicon layer to form wiring, and depositing a second oxide layer on the first polysilicon layer; after patterning etching is carried out on the second oxide layer, depositing and doping are carried out to form a second polysilicon layer; patterning and etching the second polysilicon layer to form a bonding anchor point and a capacitor plate with lower height relative to the bonding anchor point; bonding the device wafer with the bonding anchor point, and performing patterning etching on the device wafer to generate a movable structure so as to obtain a device layer; and bonding the side of the device wafer away from the substrate wafer with the cover layer. The movable structure is released without etching holes, the induction capacitance for out-of-plane induction is higher, and the use reliability is higher.

Description

MEMS sensor and preparation method thereof

Technical Field

The application relates to the technical field of MEMS devices, in particular to an MEMS sensor and a preparation method thereof.

Background

MEMS (Micro-Electro Mechanical System, microelectromechanical systems) technology is the integration of sensor structures and corresponding electronics into a small housing. Compared with the sensor manufactured by the traditional processing method, the MEMS sensor is manufactured based on an integrated circuit process and a micromachining process, has the advantages of small volume, light weight, low power consumption and the like, and has wide application prospect in the aspects of dual-purpose of army and civil use.

MEMS sensors, such as IMUs (inertial measurement units), MEMS gyroscopes, MEMS accelerometers, etc., include a cap layer, a device layer, and a substrate layer, wherein the device layer includes a device wafer on which a movable structure is formed, and the substrate layer includes a capacitive plate, and an inductive capacitor is formed by the movable structure and the capacitive plate in cooperation for sensing a corresponding physical quantity. In traditional manufacturing mode, set up the oxide layer between electric capacity polar plate and device wafer, after carrying out patterning etching to the device wafer and forming movable structure, need carry out the punching to the device wafer and let etching gas pass through, utilize etching gas etching to get rid of at least partial oxide layer in order to release movable structure, this kind of manufacturing mode can influence the induction capacitance who is used for the face induction, and the MEMS sensor of preparation has the shortcoming that the reliability in use is low.

Disclosure of Invention

In view of the above, it is desirable to provide a MEMS sensor and a method for manufacturing the same that can improve the reliability of use.

A method of fabricating a MEMS sensor, comprising:

generating a first oxide layer on a substrate wafer, performing patterning etching on the first oxide layer, and depositing and doping the first oxide layer after patterning etching to form a first polysilicon layer;

patterning and etching the first polysilicon layer to form wiring, and depositing a second oxide layer on the first polysilicon layer;

after the second oxide layer is subjected to patterning etching, depositing and doping to form a second polysilicon layer;

patterning and etching the second polysilicon layer to form a bonding anchor point and a capacitor polar plate with lower height relative to the bonding anchor point;

bonding a device wafer with the bonding anchor point, and performing patterning etching on the device wafer to generate a movable structure so as to obtain a device layer;

and bonding one side of the device wafer, which is away from the substrate wafer, with a cover layer.

In one embodiment, the performing patterned etching on the second polysilicon layer to form a bonding anchor point and a capacitor plate with a lower height relative to the bonding anchor point includes:

flattening the second polysilicon layer, and forming a third oxide layer on the flattened second polysilicon layer;

and carrying out patterning etching on the third oxide layer and the second polysilicon layer to form a bonding anchor point and a capacitor plate with a first bulge, and reserving the part of the third oxide layer covering the bonding anchor point.

In one embodiment, after the patterning etching is performed on the third oxide layer and the second polysilicon layer to form a bonding anchor point and a capacitor plate with a first bump, and the third oxide layer is reserved to cover a portion of the bonding anchor point, the method further includes:

generating a fourth oxide layer covering the third oxide layer and the capacitor plate;

patterning and etching the third oxide layer and the fourth oxide layer to expose the bonding anchor points.

In one embodiment, the bonding the device wafer to the bonding anchor point, and performing patterned etching on the device wafer to generate a movable structure, so as to obtain a device layer, including:

bonding the device wafer with the bonding anchor point;

carrying out planarization treatment on the device wafer;

patterning and etching the device wafer to generate a movable structure, and obtaining a device layer after etching is completed;

and removing the fourth oxide layer covering the capacitor plate.

In one embodiment, after the flattening treatment is performed on the device wafer, performing patterned etching on the device wafer to generate a movable structure, and before the device layer is obtained after the etching is completed, the method further includes: and performing metal deposition on the device wafer to obtain a welding spot and a first bonding part.

In one embodiment, after the bonding the device wafer to the cap layer on the side facing away from the substrate wafer, the method further includes: the cap layer is patterned such that the device layer portion is exposed.

In one embodiment, before the bonding the device wafer to the cap layer on the side of the device wafer facing away from the substrate wafer, the method further includes:

providing a cap layer wafer;

and depositing a second bonding metal layer on the cover layer wafer, and performing patterning etching on the second bonding metal layer to obtain a second bonding part.

In one embodiment, after the providing the cap layer wafer, the depositing a second bonding metal layer on the cap layer wafer, and performing patterned etching on the second bonding metal layer to obtain a second bonding portion, the method further includes: and generating a fifth oxide layer on the cover layer wafer, and performing patterned etching on the fifth oxide layer to form a second protrusion.

In one embodiment, after depositing the second bonding metal layer on the cap layer wafer and performing patterned etching on the second bonding metal layer to obtain the second bonding portion, the method further includes: and performing patterned etching on the cover layer wafer to generate a cover layer chamber and a third protrusion arranged in the cover layer chamber.

In one embodiment, the second oxide layer has a thickness of 1 micron to 5 microns.

In one embodiment, the first oxide layer has a thickness of 1 micron to 3 microns and/or the second oxide layer has a thickness of 1 micron to 5 microns and/or the first polysilicon layer has a thickness of 1 micron to 5 microns and/or the second polysilicon layer has a thickness of 5 microns to 10 microns.

In one embodiment, the substrate wafer has a thickness of 150 microns to 500 microns.

A MEMS sensor comprising a substrate wafer, a first oxide layer, a first polysilicon layer, a second oxide layer, a second polysilicon layer, a device layer, and a cap layer, the MEMS sensor being prepared by the method of any one of the above.

According to the MEMS sensor and the preparation method thereof, the bonding anchor point and the capacitor electrode plate are formed on the second polycrystalline silicon layer, and after the device wafer is bonded with the bonding anchor point, a cavity is formed between the device wafer and the capacitor electrode plate because the height of the capacitor electrode plate is lower than that of the bonding anchor point. Therefore, after the device wafer is subjected to patterning etching to generate the movable structure, an etching hole is not needed to release the movable structure, so that the induction capacitance for out-of-plane induction is higher, and the use reliability is higher.

Drawings

FIG. 1 is a flow chart of a method of fabricating a MEMS sensor in one embodiment;

FIGS. 2 to 31 are schematic structural views showing a process for manufacturing a MEMS sensor portion in one embodiment;

FIG. 32 is a flow chart of a method of fabricating a MEMS sensor in another embodiment;

fig. 33 to 35 are schematic structural views of a MEMS sensor portion manufacturing process in one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.

In one embodiment, as shown in fig. 1, there is provided a MEMS sensor manufacturing method, comprising:

step S101: and generating a first oxide layer on the substrate wafer, performing patterning etching on the first oxide layer, and depositing and doping the patterned etched first oxide layer to form a first polysilicon layer.

As shown in fig. 2, a substrate wafer 110, specifically a silicon wafer, is first provided. A global alignment mark (not shown) may also be provided on the substrate wafer 110 to facilitate subsequent processing alignment.

As shown in fig. 3 and 4, the first oxide layer 120 is generated by performing oxide deposition (e.g., thermal oxide deposition) on one or both sides of the substrate wafer 110, and the first oxide layer 120 on one side is patterned to etch away a portion of the oxide to form an etch trench, exposing a portion of the substrate wafer 110. The first oxide layer 120 may be any dielectric film, and in this embodiment, the first oxide layer 120 is a silicon oxide layer. The first oxide layer 120 is used to shield the substrate wafer 110 during subsequent deposition and doping, and prevent deposition and doping to undesired locations. As shown in fig. 5, after the patterning etching is performed on the first oxide layer 120, silicon deposition and doping are performed to form a first polysilicon layer 130, and the first polysilicon layer 130 covers the first oxide layer 120 after the patterning etching and fills the etching groove of the first oxide layer 120 to contact the substrate wafer 110.

Step S102: and carrying out patterned etching on the first polysilicon layer to form a wiring, and depositing a second oxide layer on the first polysilicon layer.

As shown in fig. 6 and 7, after the first polysilicon layer 130 is patterned and etched to form the wiring, an oxide may be deposited by a plasma enhanced chemical vapor deposition process to form the second oxide layer 140. The second oxide layer 140 may be formed by vapor deposition using any dielectric material, for example, the second oxide layer 140 may be a silicon oxide layer.

Step S103: and after the second oxide layer is subjected to patterning etching, depositing and doping to form a second polysilicon layer.

Specifically, as shown in fig. 8 and 9, chemical mechanical polishing may be performed on the second oxide layer 140 first, and after planarization is completed, patterning etching is performed on the second oxide layer 140, so that a portion of the oxide is etched to form an etching groove, and a portion of the first polysilicon layer 130 is exposed. As shown in fig. 10, after the patterning etching of the second oxide layer 140 is completed, silicon deposition and doping are performed to form a second polysilicon layer 150, and the second polysilicon layer 150 covers the patterned etched second oxide layer 140 and fills the etched trench of the second oxide layer 140 to be in contact with the first polysilicon layer 130.

Step S104: and carrying out patterned etching on the second polysilicon layer to form a bonding anchor point and a capacitor polar plate with lower height relative to the bonding anchor point.

Specifically, in one embodiment, step S104 includes steps 41 through 42.

Step 41: and carrying out planarization treatment on the second polysilicon layer, and forming a third oxide layer on the planarized second polysilicon layer. As shown in fig. 11 and 12, the planarization process may be accomplished by performing chemical mechanical polishing on the second polysilicon layer 150. An oxide is then deposited on the second polysilicon layer 150 by a plasma enhanced chemical vapor deposition process to form a third oxide layer 160.

Step 42: and carrying out patterning etching on the third oxide layer and the second polysilicon layer to form a bonding anchor point and a capacitor plate with the first bulge, and reserving the part of the third oxide layer covering the bonding anchor point. Specifically, the patterned etching of the third oxide layer and the second polysilicon layer may be completed in multiple steps. As shown in fig. 13, in the first step of etching, the third oxide layer 160 and the second polysilicon layer 150 are simultaneously subjected to patterned etching such that a plurality of bonding anchor points are formed on the second polysilicon layer 150, while for the third oxide layer 160, only a portion of the third oxide layer 160 covering the bonding anchor points remains to protect the surfaces of the bonding anchor points before the bonding anchor points are used for protecting the surfaces of the bonding anchor points in the subsequent steps. In the first etching step, the etching depth of the second polysilicon layer 150 determines the gap between the first bump and the device layer that are formed later. As shown in fig. 14, in the second etching step, a part of the area is covered on the basis of the first etching area, the etching is continued on the second polysilicon layer 150, the first protrusion 152 is formed on the second polysilicon layer 150, and the first protrusion 152 is used for limiting the downward movement amplitude of the movable structure in the subsequently generated device layer and providing a restoring force for the movable structure, so that the adhesion is avoided. As shown in fig. 15, the third etching step continues to etch the second polysilicon layer 150 to form a capacitor plate 154 with a first bump 152.

In this embodiment, the bonding anchor point, the first bump 152 and the capacitor plate 154 are obtained by performing patterned etching on the same polysilicon layer (the second polysilicon layer 150), which is beneficial to reducing process steps and simplifying the preparation process. In addition, the capacitor plate 154 and the wiring are arranged on different polysilicon layers, specifically, the capacitor plate 154 is arranged on the second polysilicon layer 150, and the wiring is arranged on the first polysilicon layer 130, so that the design of the induction capacitor and the wiring is more flexible, in addition, the first polysilicon layer 130 and the second polysilicon layer 150 are contacted with each other through the step S103 to form electric connection, and the electric connection mode enables the design to be more compact. The first polysilicon layer 130 and the second polysilicon layer 150 are low resistance polysilicon, it being understood that in other embodiments refractory metals or alloys may also be employed.

The electrode layer is formed up to this point through steps S101 to S104.

Step S105: and bonding the device wafer with the bonding anchor point, and performing patterning etching on the device wafer to generate a movable structure, thereby obtaining the device layer.

The device wafer may be a silicon wafer. Because a complete wafer that has not been etched to a specific structure and/or pattern is bonded to the second polysilicon layer 150, bonding tolerances need not be considered during bonding and specific point-to-point alignment bonding is not required. Precise alignment may be based on image tolerances rather than bonding tolerances. Further, the bonding anchor on the second polysilicon layer 150 also does not need to be increased in size in order to take into account bonding tolerances, i.e., the anchor size can be reduced, thereby enabling a more compact device structure.

The device layer manufacturing mode of the traditional MEMS sensor comprises a sacrificial release process, specifically, an oxide layer is arranged between a capacitor plate and a device wafer, and after patterning etching is performed on the device wafer to form a movable structure, the movable structure is in a state locked by the oxide layer. The device wafer is perforated to allow etching gas to pass through, and at least a portion of the oxide layer is etched away using the etching gas to release the movable structure. The sensing capacitor formed by the movable structure and the capacitor plate is used for sensing the change of external physical quantity, such as acceleration or angular velocity. Punching holes in the device wafer can affect the sensing capacitance of the sensor. In this application, the bonding anchor point and the capacitor plate 154 are both formed on the second polysilicon layer 150, after the device wafer is bonded with the bonding anchor point, the height of the capacitor plate 154 is lower than that of the bonding anchor point, so that a cavity is formed between the device wafer and the capacitor plate 154, and after the device wafer is patterned and etched to generate the movable structure, the movable structure is released without etching holes, and the cavity provides a movable space for the movable structure. The induced capacitance for out-of-plane sensing is higher than for the sacrificial release process because no etched holes are needed to release the movable structure. In addition, since etching holes are not required, the Q value of the out-of-plane induction is lower compared to the sacrificial release process—ringing is reduced and influence is reduced in the event of impact or drop, drift and stability change due to impact or drop are lower, and use reliability is higher.

In one embodiment, as shown in fig. 16-18, to avoid adversely affecting the capacitor plate 154 during the patterned etching of the device wafer when performing step S105, and to enable timely stopping of the etching after the formation of the movable structure, to avoid over-etching, an oxide patch protection process is further performed after performing step 42 and before performing step S105, and specifically includes:

step 43: a fourth oxide layer is formed overlying the third oxide layer and the capacitor plate. As shown in fig. 16, after the capacitor plate 154 is etched, a plasma enhanced chemical vapor deposition process is performed to deposit oxide, forming a fourth oxide layer 170. The fourth oxide layer 170 covers the capacitor plate 154, as well as the remaining third oxide layer 160. The material of the fourth oxide layer 170 is not limited, and specifically, any dielectric film that can be removed by vapor phase hydrogen fluoride may be used for the fourth oxide layer 170, so that the fourth oxide layer 170 is removed after the movable structure is formed. In this embodiment, the fourth oxide layer 170 is a silicon oxide layer.

Step 44: the third oxide layer and the fourth oxide layer are patterned and etched to expose the bonding anchor points. As shown in fig. 17, the fourth oxide layer 170 is first patterned to expose the third oxide layer 160 covering the bond anchor and leave the fourth oxide layer 170 covering the capacitor plate 154. As shown in fig. 18, the third oxide layer 160 is patterned and etched to remove the third oxide layer 160 covering the bonding anchor, so that the bonding anchor is exposed to facilitate subsequent fusion bonding. The remaining fourth oxide layer 170 serves to protect the capacitor plate 154 from undesired etching later in the fabrication of the movable structure and to provide endpoint detection for the device wafer etch, i.e., etch stop at the point of encountering the fourth oxide layer 170.

Specifically, in one embodiment, step S105 includes steps 51 through 55.

Step 51: and bonding the device wafer with the bonding anchor point. As shown in fig. 19, the device wafer 210 is fusion bonded to the exposed bonding anchor. In step 41 and step 42, the second polysilicon layer is planarized, and then a bonding anchor is formed, that is, the bonding anchor has a flat surface, which is favorable for performing fusion bonding. In addition, the fusion bonding is not limited by temperature, and can be performed at a higher temperature, so that higher bonding strength is obtained, and the electrode layer and the device layer are firmly connected.

Step 52: and carrying out planarization treatment on the device wafer. As shown in fig. 20, the device wafer 210 is polished and polished to complete the planarization process.

Step 54: and performing patterning etching on the device wafer to generate a movable structure, and obtaining a device layer after etching is completed. As shown in fig. 23, the device wafer 210 is subjected to patterning etching, and a movable structure is generated through the device wafer 210. Specifically, after etching through the device wafer 210, the etching is terminated until the fourth oxide layer 170, and the fourth oxide layer 170 provides endpoint detection for etching, preventing over-etching. The fourth oxide layer 170 overlying the capacitor plate 154 provides protection for the capacitor plate 154 from undesired etching of the capacitor plate 170. The plurality of movable structures 212 formed by etching are used for detecting in cooperation with the capacitor plate 154, and the first protrusion 152 can limit the maximum downward movement amplitude of the movable structures 212 and provide restoring force for the movable structures 212 to avoid adhesion.

In addition, the thickness of the movable structure 212 manufactured in this embodiment is determined by the initial thickness of the device wafer 210 and the thickness of the polishing, and the thickness of the polishing can be selected according to actual needs. It will be appreciated that the maximum thickness of the movable structure 212 may be the initial thickness of the device wafer 210, whereby thicker movable structures 212 may be fabricated to achieve higher planar capacitance. Compared with a device layer generated by a traditional film deposition process, the thickness of the movable structure 212 is determined by grinding and polishing on the basis of the initial device wafer 210, so that the manufacturing is more convenient and the accuracy is higher.

Step 55: and removing the fourth oxide layer covering the capacitor plate. After the patterning etch of the device wafer 210 to form the movable structure 212 is completed, the remaining fourth oxide layer 170 may be etched away by vapor phase hydrogen fluoride to expose the capacitor plate 154, as shown in fig. 24.

Step S106: and bonding the side of the device wafer away from the substrate wafer with the cover layer.

In one embodiment, the side of the device wafer facing away from the substrate wafer is eutectic bonded to the cap layer.

Specifically, after performing step 52, and before performing step 54, the method further includes:

step 53: performing metal deposition on the device wafer to obtain a welding spot and a first bonding part, wherein the metal deposition comprises the following steps: depositing a first bond metal layer on the device wafer; and carrying out patterning etching on the first bonding metal layer to obtain a welding spot and a first bonding part. Specifically, as shown in fig. 21, metal deposition is performed on the device wafer 210 to obtain the first bonding metal layer 220, where the material of the first bonding metal layer 220 may be any eutectic metal capable of wire bonding, for example, aluminum. As shown in fig. 22, the first bond metal layer 220 is patterned etched to form a solder joint 222 and a first bond 224. Wherein the solder joint 222 is used for electrical connection through a wire, and the first bonding portion 224 is used for bonding with a cap layer. In this way, by depositing and etching the first bonding metal layer 220, the solder points 222 for wire bonding and the first bonding portions 224 for eutectic bonding can be formed, which is advantageous in terms of reducing process steps and simplifying the manufacturing process.

The preparation steps of the cover layer comprise:

step 61: a cap layer wafer is provided. As shown in fig. 25, a cap wafer 310 is provided, and a silicon wafer may be used for the cap wafer 310. Alternatively, the cap wafer 310 may be provided with a global alignment flag (not shown) to facilitate subsequent processing alignment.

Step 63: and depositing a second bonding metal layer on the cover layer wafer, and performing patterning etching on the second bonding metal layer to obtain a second bonding part. As shown in fig. 28, metal deposition is performed on the cap wafer 310 to obtain a second bond metal layer 330, and as shown in fig. 29, the second bond metal layer 330 is subjected to patterned etching to obtain a second bond 332. The material of the second bonding metal layer 330 may be any eutectic metal, such as germanium or gold.

In step S106, the device wafer 210 is eutectic bonded to the cap layer by the first bonding portion 224 and the second bonding portion 332 on the side facing away from the substrate wafer 110, in combination with step 53, step 61 and step 63. It will be appreciated that the bonding means may be any type of eutectic bonding, but other types of bonding means may be used, such as thermocompression bonding, transient liquid phase bonding, solder bonding, glass fusion bonding, etc.

Further, after performing step 61, and before performing step 63, the method further includes:

step 62: and generating a fifth oxide layer on the cover layer wafer, and performing patterning etching on the fifth oxide layer to form a second protrusion. As shown in fig. 26 and 27, the fifth oxide layer 320 is formed by performing oxide deposition on one or both sides of the cap wafer 310, and the fifth oxide layer 320 on one side thereof is patterned to form the second protrusions 322. The fifth oxide layer 320 may be any dielectric film, and in this embodiment, the fifth oxide layer 320 is a silicon oxide layer.

As can be seen from the combination of step 63 and step S105, the second bonding portion 332 obtained in step 63 is adjacent to the second protrusion 322. The second bonding portion 332 may be in contact with the second protrusion 322, or may have a gap, and the gap may be variable, and the second protrusions 322 may be disposed on both sides of the second bonding portion 332, or the second protrusions 322 may be disposed on one side of the second bonding portion 332, and the specific manner of disposition may be adjusted according to actual needs. Specifically, a second bonding portion 332 located at the edge of the cap wafer 310, and having a second protrusion 322 disposed on the side thereof near the middle region of the cap wafer 310; the second bonding portion 332 located at the middle region of the cap wafer 310 is provided with second protrusions 322 on both sides thereof. When the second bonding portion 332 is subsequently bonded to the first bonding portion 224, a eutectic fluid is generated during the bonding process, and the second protrusion 322 is used to prevent the eutectic fluid from overflowing during the bonding process.

Further, the preparation step of the cover layer further comprises:

step 64: and performing patterned etching on the cover layer wafer to generate a cover layer chamber and a third protrusion arranged in the cover layer chamber. As shown in fig. 30, the cap layer wafer 310 is patterned and etched to avoid the second bonding portion 332 and the second bump 322, so as to generate a cap layer chamber and a third bump 312 disposed in the cap layer chamber. In combination with step S106, after the device wafer 210 is eutectic bonded to the cap layer through the first bonding portion 224 and the second bonding portion 332 on the side facing away from the substrate wafer 110, the cap layer chamber provides a moving space for the movable structure 212, and the third protrusion 312 is used to limit the maximum upward movement of the movable structure 212 and provide a restoring force for the movable structure 212, so as to avoid adhesion. The movement of the movable structure 212 in the vertical direction is restricted by the engagement of the third protrusion 312 with the first protrusion 152. In this embodiment, the third bump 322 is integrated into the cap layer, which also improves device compactness.

Further, the preparation step of the cover layer further comprises:

step 65: a getter is generated in a cap layer chamber of the cap layer wafer. Specifically, the MEMS sensor is an IMU (inertial measurement unit) and includes a gyroscope and an accelerometer, as shown in fig. 31 and 34, where a region X is used to fabricate the gyroscope, a region Y is used to fabricate the accelerometer, and a getter 340 is disposed in a cap layer chamber corresponding to the region X on the cap layer wafer 310. A getter 340 is provided in the cap layer chamber for maintaining a vacuum in the gyroscope.

In one embodiment, as shown in fig. 32, after performing step S106, the method further includes:

step S107: the cap layer is patterned such that the device layer portion is exposed. Specifically, as shown in fig. 33 to 35, after bonding is completed, the cap layer wafer 310 is ground and polished, the thickness of the cap layer wafer 310 is reduced, and the flatness of the cap layer wafer 310 is improved. The portion of cap wafer 310 that obstructs bond pads 222 is patterned to expose bond pads 222. On the one hand, the bonding pads 222 are exposed to facilitate connection, on the other hand, the positions of the bonding pads 222 are lower than the cover wafer 310, and after the bonding pads 222 are connected with the leads, the heights of the leads can be lower than the cover wafer 310, so that the package size can be reduced in the subsequent package of the shell.

It is understood that the specific thicknesses of the substrate wafer 110, the first oxide layer 120, the first polysilicon layer 130, the second oxide layer 140, and the second polysilicon layer 150 are not unique and may be designed according to actual needs.

In one embodiment, the thickness of the substrate wafer 110 is 150 microns-500 microns. The thickness of the substrate wafer 110 may be selected to be 150 microns, 200 microns, 300 microns, 500 microns, etc. By designing the thicker substrate wafer 110, the capacitive plates of the MEMS sensor have better stability.

In one embodiment, the thickness of the second oxide layer 140 is 1 micron to 5 microns. The thickness of the planarized second oxide layer 140 may be designed to be 1 micron, 2 microns, 3 microns, 5 microns, etc. The thickness of the second oxide layer 140 between the two polysilicon layers, the first polysilicon layer 130 and the second polysilicon layer 150, can be adjusted to control the distance between the vertical direction wiring and the capacitor plate 154. In this embodiment, by reasonably selecting the thickness of the second oxide layer 140 between the two polysilicon layers, the parasitic capacitance of the MEMS sensor can be effectively reduced.

In one embodiment, the first oxide layer 120 has a thickness of 1 micron to 3 microns, and/or the second oxide layer 140 has a thickness of 1 micron to 5 microns, and/or the first polysilicon layer 130 has a thickness of 1 micron to 5 microns, and/or the second polysilicon layer 150 has a thickness of 5 microns to 10 microns. The thickness of the first oxide layer 120 may be 1 micron, 1.5 micron, 2 micron, 3 micron, etc., the thickness of the planarized second oxide layer 140 may be 1 micron, 2 micron, 3 micron, 5 micron, etc., the thickness of the first polysilicon layer 130 may be 1 micron, 2 micron, 3 micron, 5 micron, etc., and the thickness of the planarized second polysilicon layer 150 may be 5 micron, 6 micron, 8 micron, 10 micron, etc. The distance between the substrate wafer 110 and the device wafer 210 may be controlled by adjusting the thickness of at least one of the first polysilicon layer 130, the second polysilicon layer 150, the first oxide layer 120, and the second oxide layer 140. In this embodiment, by reasonably adjusting the thickness of at least one of the first polysilicon layer 130, the second polysilicon layer 150, the first oxide layer 120, and the second oxide layer 140 between the substrate wafer 110 and the device wafer 210, the parasitic capacitance of the MEMS sensor can be effectively reduced.

In one embodiment, a MEMS sensor is further provided, including a substrate wafer, a first oxide layer, a first polysilicon layer, a second oxide layer, a second polysilicon layer, a device layer, and a cap layer, where the MEMS sensor may further include a getter and the like, and the MEMS sensor is manufactured by the above method.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. A method of manufacturing a MEMS sensor, comprising:

2. The method of claim 1, wherein the patterning the second polysilicon layer to form a bond anchor and a capacitor plate having a lower height relative to the bond anchor comprises:

3. The method of claim 2, wherein after the patterning etching the third oxide layer and the second polysilicon layer to form a bond anchor and a capacitor plate with a first bump, and leaving a portion of the third oxide layer covering the bond anchor, further comprising:

4. The method of claim 3, wherein bonding the device wafer to the bonding anchor and performing patterned etching on the device wafer to generate a movable structure, and obtaining a device layer comprises:

bonding the device wafer with the bonding anchor point;

carrying out planarization treatment on the device wafer;

and removing the fourth oxide layer covering the capacitor plate.

5. The method of claim 4, wherein after the planarizing the device wafer, performing a patterned etching on the device wafer to generate a movable structure, and before the etching is completed, obtaining a device layer, further comprising: and performing metal deposition on the device wafer to obtain a welding spot and a first bonding part.

6. The method of any of claims 1-5, further comprising, after bonding the device wafer to the cap layer on a side of the device wafer facing away from the substrate wafer: the cap layer is patterned such that the device layer portion is exposed.

7. The method of claim 5, wherein prior to bonding the side of the device wafer facing away from the substrate wafer with the cap layer, further comprising:

providing a cap layer wafer;

8. The method of claim 7, wherein after providing the cap wafer, the depositing a second bonding metal layer on the cap wafer and performing a patterned etching on the second bonding metal layer to obtain a second bonding portion, further comprising: and generating a fifth oxide layer on the cover layer wafer, and performing patterned etching on the fifth oxide layer to form a second protrusion.

9. The method of claim 7, wherein after depositing a second bonding metal layer on the cap wafer and performing patterned etching on the second bonding metal layer to obtain a second bonding portion, further comprising: and performing patterned etching on the cover layer wafer to generate a cover layer chamber and a third protrusion arranged in the cover layer chamber.

10. The method of any one of claims 1-5, wherein the second oxide layer has a thickness of 1 micron to 5 microns.

11. The method according to any of claims 1-5, wherein the first oxide layer has a thickness of 1 micrometer to 3 micrometers and/or the second oxide layer has a thickness of 1 micrometer to 5 micrometers and/or the first polysilicon layer has a thickness of 1 micrometer to 5 micrometers and/or the second polysilicon layer has a thickness of 5 micrometers to 10 micrometers.

12. The method of any of claims 1-5, wherein the substrate wafer has a thickness of 150 microns to 500 microns.

13. A MEMS sensor comprising a substrate wafer, a first oxide layer, a first polysilicon layer, a second oxide layer, a second polysilicon layer, a device layer, and a cap layer, the MEMS sensor being prepared by the method of any one of claims 1-12.