CN117614396A - Current sense amplifier circuit and input offset voltage correction method thereof - Google Patents

Abstract

A current sense amplifier circuit and a method for correcting input offset voltage thereof. The current sense amplifier circuit includes: the amplifier is used for generating an output voltage related to a current to be sensed according to a first input voltage of the first input end and a second input voltage of the second input end in a normal operation mode; the current source circuit is used for generating a correction current according to the first input voltage and the reference voltage in a correction mode and providing the correction current to correct the input offset voltage generated by the current sense amplifier circuit in a normal operation mode; the current source circuit is coupled to: between the first resistor and the non-inverting input, between the second resistor and the output voltage, between the third resistor and the non-inverting input, or between the fourth resistor and the inverting input.

Description

Current sense amplifier circuit and input offset voltage correction method thereof

Technical Field

The present invention relates to a current sense amplifier circuit and an input offset voltage correction method thereof, and more particularly, to a current sense amplifier circuit and an input offset voltage correction method thereof capable of correcting an input offset voltage by supplying a correction current.

Background

Referring to fig. 1A and 1B, fig. 1A is a flowchart illustrating steps of a method 10 for correcting an input offset voltage of a prior art current sense amplifier circuit. Fig. 1B is a schematic diagram showing a prior art current sense amplifier circuit 11 with input offset voltage correction. In the current sense amplifier circuit 11 of the prior art, the gain of the current sense amplifier circuit 11 cannot be matched due to the input offset voltage (offset referred to input, RTI) generated by the errors in the manufacturing process of the resistors R11, R21, R31, and the gain is wrong with the design value, thereby causing the error of the current sensing result. As shown in fig. 1A and referring to fig. 1B, the current sense amplifier circuit 11 of the prior art has two input terminals Ni1 and Ni2, and a reference voltage Vref is added to enable the current sense amplifier circuit 11 to sense bidirectional current. The current sense amplifier circuit 11 of the prior art adjusts the resistance value of the built-in programmable feedback resistor chain Rcr to correct the input offset voltage; as shown in fig. 1B, through the correction procedure, the current sense amplifier circuit 11 selects a part of resistors R41, R42 with relatively small resistance values, which are connected in series to the output terminal, to correct the input offset voltage as required.

Compared to other prior art current sense amplifier circuits (not shown), the current sense amplifier circuit 11 further comprises a resistor R31 coupled to the reference voltage Vref, wherein one end of the resistor R31 is coupled to the reference voltage Vref, and the other end is electrically connected to the non-inverting input terminal of the amplifier. Providing the resistor R31 coupled to the reference voltage Vref has the following two reasons.

First, if no reference voltage Vref is applied to the non-inverting input of the amplifier through the resistor R31, the common mode voltage of the inverting input and the non-inverting input of the amplifier is electrically connected to a relatively high voltage, for example, when the current sense amplifier circuit 11 is applied to an upper bridge circuit in a power conversion circuit, the current sense amplifier circuit 11 without the resistor R31 coupled to the reference voltage Vref is not provided, and the inverting input and the non-inverting input of the amplifier are electrically connected to the relatively high voltage, so that the amplifier is damaged, or the amplifier must use a high voltage tolerant element to increase the manufacturing cost. After the resistor R31 coupled to the reference voltage Vref is set, the common mode voltage of the inverting input terminal and the non-inverting input terminal of the amplifier can be adjusted to be relatively low, so that the amplifier can use a low voltage element without using a high voltage resistant element to reduce the cost and avoid the damage of the amplifier.

Second, in the normal operation mode, the relationship between the input voltage (Vin+ and Vin-) and the output voltage Vout of the current sense amplifier circuit 11 is as follows:

Vout＝Vref+(Vin ₊ -Vin _- )*k

where k is a preset constant.

When the input voltage vin+ of the input terminal Ni1 is smaller than the input voltage Vin-of the input terminal Ni2, if no reference voltage Vref is applied to the non-inverting input terminal of the amplifier (i.e., reference voltage vref=0), the output voltage Vout should be negative according to the above, but in the case of supplying the amplifier with the voltage drop from the internal supply voltage to the ground potential as the power supply, the amplifier cannot actually generate the negative output voltage Vout. Therefore, only zero potential can be output if the output voltage Vout should be negative. The reference voltage Vref is applied to the non-inverting input terminal of the amplifier, so that the output voltage Vout can be shifted to a positive level, which is suitable for the case that the input voltage Vin+ of the input terminal Ni1 is smaller than the input voltage Vin-of the input terminal Ni 2.

In detail, referring to fig. 1A, an input offset voltage correction method 10 is used to correct an input offset voltage of a current sense amplifier circuit 11 according to the prior art, and includes the following steps. In step 101, the programmable feedback resistor chain Rcr (comprising the series resistances of resistors R4a, R41, R42, is shorted). In step 101, the short-circuit programmable feedback resistor chain Rcr means that the switch SW4a is turned on to short-circuit the output voltage Vout with the inverting input terminal of the amplifier. Next, in step 102, two different common-mode voltages (i.e., the input terminal Ni1 and the input terminal Ni 2) are applied to the input terminal, and the output voltages Vout of the amplifiers at the two different common-mode voltages are measured respectively, and the difference between the two output voltages Vout is calculated to obtain a first output voltage difference. Thereafter, in step 103, the short circuit (referred to as turning off the switch SW4 a) is removed and the unmodified feedback chain resistance value in the programmable feedback resistor chain Rcr is measured. Next, in step 104, under the condition of the unmodified feedback chain resistance value of the programmable feedback resistor chain Rcr, the two different common-mode voltages are applied to the input ends (i.e. the input end Ni1 and the input end Ni 2), and the output voltages Vout of the amplifiers at the two different common-mode voltages are measured again respectively, and the difference between the two output voltages is calculated to obtain the second output voltage difference. Next, in step 105, a linear equation is derived based on the first output voltage difference, the second output voltage difference, and the unmodified feedback chain resistance values (0 and Rcr). Then, in step 106, a feedback resistance target is obtained based on the linear equation. Next, in step 107, the programmable feedback resistor chain Rcr is modified (trim) to the programmable resistor combination closest to the feedback resistor target for the feedback chain. Then, in step 108, in normal operation, the current flowing through the two inputs of the amplifier is sensed based on the corrected feedback chain resistance value of the programmable feedback resistor chain Rcr. The above-mentioned prior art input offset voltage correction method 10 is cumbersome in steps and if there are two loops, all steps are repeated again.

Although the prior art current sense amplifier circuit 11 shown in fig. 1B can sense current bi-directionally, i.e. sense current when the input voltage vin+ is smaller than the input voltage Vin-and the input voltage Vin-is smaller than the input voltage vin+, the equivalent input offset voltage will vary with the changes of the input voltages vin+ and Vin-and/or the reference voltage Vref. Therefore, the current sense amplifier circuit 11 of the prior art performs correction of the input offset voltage under a specific condition (for example, a combination of the input voltage and the reference voltage with a specific level), so as to obtain a fixed correction value, and when the resistance value of the programmable feedback resistor chain Rcr is adjusted to the corresponding resistance value according to the combination, the corresponding input offset voltage under the specific condition can be truly compensated, so that no output offset voltage (i.e. the output offset voltage is 0) exists between the actual output voltage and the corresponding output voltage expected value.

However, when the input voltage and/or the reference voltage are changed (e.g., the second combination of the input voltage and the reference voltage), the input offset voltage is changed accordingly, so that in another combination, the output offset voltage between the output voltage of the current sense amplifier circuit 11 and the corresponding output voltage expected value of the prior art is not negligible (i.e., the output offset voltage is not 0), resulting in an error of the current sensing result. It should be noted that the "output offset voltage" is equal to the "input offset voltage" multiplied by the gain of the amplifier.

It should be noted that the above situation occurs when other prior art current sense amplifier circuits are modified with a fixed correction current, both the "output offset voltage" and the "input offset voltage" are related to the input voltages vin+ and Vin-and/or the reference voltage Vref, that is, when the input voltages vin+ and Vin- (i.e., the input common mode voltage of the input voltages vin+ and Vin-is changed) and/or the reference voltage Vref is changed, the "output offset voltage" and the "input offset voltage" are changed, which also causes a current sense error. Thus, if the input offset voltage is modified with only a fixed modification current (rather than a modification current proportional to the input voltage vin+ and Vin-and the reference voltage Vref), only a certain combination of the input voltage vin+ and Vin-and the reference voltage Vref can be aligned (because of the modification current obtained with this combination).

Other related prior Art techniques such as p.horowitz and w.hill, the Art of Electronics.Cambridge, U.K.: cambridge Univ. Press,1989, which is a conventional current detector, uses three sets of op-amps for integration, and the benefit of using this architecture is that it provides a high common-mode rejection ratio (common-mode rejection ratio, CMRR) and a common instrumentation amplifier circuit that balances high input impedance, can be split into two parts. The input stage acts mainly as a buffer and the output stage is a differential amplifier, providing a high differential gain. The differential gain of the instrumentation amplifier may also be adjusted by adjusting the resistance value of the individual resistors. Because the single resistor is different from the other resistors in the circuit, the resistance value of the single resistor need not be matched to any other resistor. But this architecture is not applicable with respect to system offsets and at high common mode voltage inputs.

Another related art, such as Razvan Puscasu, pavl Brinzoi, & Laurentiu Creosteanu, "A High Voltage Current Sense Amplifier With Extended Input Common Mode Range Based On A Low Voltage Operational Amplifier Cell", is a current detection circuit developed to overcome the problem of current detectors that can perform bi-directional current detection at a wide range of common mode voltage inputs and whose input common mode voltage is independent of power supply. However, the input offset voltage generated by the error of the resistor in the manufacturing process causes that the overall gain cannot be matched and has an error with the design value, thereby causing the error of the current sensing result.

Another related art such as r.c. yi and p.r.gray, "a MOS switch-capacitor instrumentation amplifier," IEEE j.solid-State Circuits, vol.sc-17, pp.1008-1013, dec.1982, in which the input range of the common mode voltage can be increased, but the input offset voltage of the integral operational amplifier is indirectly caused to be different under different common mode voltage inputs, and the accuracy of the output voltage will be reduced under consideration of the phenomenon of process offset, so that in order to overcome this, the current detector adopts the design of input offset voltage suppression by adopting the capacitive switching technology (Chopper).

Other related prior art such as "TI: INA213 Voltage Output, low-or High-Side Measurement, bidirectionnal, zero-Drift Series, current-Shift Monitors "," On Semiconductor: NCS199A1R, current-Shift Monitors, voltage Output, bidirectionnal, zero-Drift, low-or High-Side Current Sensing "," SGMICRO: SGM8199 Voltage Output, high-or Low-Side Measurement, bi-Directional Current Shunt Monitor AND 3PEAK: TP181, zero-Drift, bi-directional Current Sense Amplifier).

In view of the above, the present invention provides a current sense amplifier circuit and a method for correcting an input offset voltage thereof.

Disclosure of Invention

In one aspect, the present invention provides a current sense amplifier circuit for sensing a current to be sensed flowing through a sense resistor, wherein two ends of the sense resistor are correspondingly coupled to a first input terminal and a second input terminal of the current sense amplifier circuit, the current sense amplifier circuit comprising: an amplifier for generating an output voltage related to the current to be sensed according to a first input voltage of the first input terminal and a second input voltage of the second input terminal in a normal operation mode; the first resistor is coupled between a reference voltage and a non-inverting input end of the amplifier, wherein the resistance value of the first resistor is a first resistance value plus a first error resistance value; the second resistor is coupled between the output voltage and an inverting input end of the amplifier, wherein the resistance value of the second resistor is the first resistance value minus the first error resistance value; the third resistor is coupled between the first input end and the non-inverting input end, wherein the resistance value of the third resistor is a second resistance value minus a second error resistance value; a fourth resistor coupled between the second input terminal and the inverting input terminal, wherein the resistance of the fourth resistor is the second resistance plus the second error resistance; and a current source circuit for generating a correction current according to the first input voltage, the second input voltage or an input common mode voltage and the reference voltage in a correction mode, and providing the correction current to correct an input offset (offset referred to input, RTI) voltage generated by the first error resistance and the second error resistance in the normal operation mode; wherein, this current source circuit is coupled to: between the first resistor and the non-inverting input terminal, between the second resistor and the output voltage, between the third resistor and the non-inverting input terminal, or between the fourth resistor and the inverting input terminal; in the correction mode, the first input terminal is electrically connected to the second input terminal, so that the first input voltage and the second input voltage have the same potential.

In one embodiment, the current source circuit includes: a first voltage-to-current circuit for converting the first input voltage, the second input voltage or the input common mode voltage to generate a first current; a second voltage-to-current circuit for converting the reference voltage to generate a second current; and a correction current generating circuit for generating the correction current according to the first current and the second current in the correction mode so that the output voltage is equal to or closest to the reference voltage.

In one embodiment, the correction current generating circuit includes: a first current copying circuit for copying the first current to generate a first copying current; a second current copying circuit for copying the second current to generate a second copying current; a first adder for performing a subtraction operation to subtract the second replica current from the first replica current to generate a first subtraction result; a second adder for performing a subtraction operation to subtract the first replica current from the second replica current to generate a second subtraction result; a judging circuit for generating a first enabling signal when the first replication current is higher than the second replication current, and generating a second enabling signal when the second replication current is higher than the first replication current; a first current correction circuit for correcting the first subtraction result by being enabled by the first enable signal to generate a first correction current; a second current correction circuit for correcting the second subtraction result by being enabled by the second enable signal to generate a second correction current; and a third adding circuit for performing an adding operation on the first and second correction currents to generate the correction current.

In one embodiment, the first current replication circuit and the second current replication circuit respectively include at least one current mirror circuit.

In one embodiment, the reference voltage is used to adjust an input common mode voltage of the amplifier so that the current sense amplifier circuit has a bidirectional current sense function.

In one embodiment, the current sense amplifier circuit further includes a capacitive switch circuit (chopper) coupled between the non-inverting input terminal and the inverting input terminal for suppressing input offset voltage variations caused by different input common mode voltages.

In one embodiment, the input offset voltage corresponds to a compensation term associated with the correction current, and the compensation term does not affect a gain error (gain error) of the amplifier.

In one embodiment, the correction current is proportional to a difference between the first input voltage and the reference voltage, a difference between the second input voltage and the reference voltage, or a difference between an input common mode voltage of the first input voltage and the second input voltage and the reference voltage.

In one embodiment, the first error resistance is less than half of the first resistance and the second error resistance is less than half of the second resistance.

In an embodiment, the current source circuit generates the correction current according to the first input voltage and the reference voltage in the correction mode by a binary approximation method, a single slope approximation method or a successive approximation method.

In another aspect, the present invention provides an input offset voltage correction method for correcting an input offset (offset referred to input, RTI) voltage of a current sense amplifier circuit, the input offset voltage correction method comprising: electrically connecting a first input end and a second input end of the current sense amplifier circuit so that a first input voltage of the first input end and a second input voltage of the second input end have the same potential; converting the first input voltage, the second input voltage or an input common mode voltage to generate a first current; converting a reference voltage to generate a second current; and generating a correction current according to the first current and the second current so that an output voltage of the current sense amplifier circuit is equal to or closest to the reference voltage; wherein a first resistor of the current sense amplifier circuit is coupled between the reference voltage and a non-inverting input of an amplifier of the current sense amplifier circuit; wherein in a normal operation mode, the correction current is provided to correct the input offset voltage generated by the current sense amplifier circuit.

In one embodiment, the step of generating the correction current to make the output voltage of the current sense amplifier circuit equal to or closest to the reference voltage according to the first current and the second current includes: copying the first current to generate a first copying current; copying the second current to generate a second copying current; performing a subtraction operation to subtract the second replica current from the first replica current to generate a first subtraction result; performing a subtraction operation to subtract the first replica current from the second replica current to generate a second subtraction result; generating a first enabling signal when the first replication current is higher than the second replication current, and generating a second enabling signal when the second replication current is higher than the first replication current; correcting the first subtraction result according to the first enabling signal to generate a first correction current; correcting the second subtraction result according to the second enabling signal to generate a second correction current; and performing an addition operation on the first correction current and the second correction current to generate the correction current.

In one embodiment, the input offset voltage correction method further includes: a capacitive switch circuit (chopper) is coupled between the non-inverting input terminal and an inverting input terminal of the current sense amplifier circuit for suppressing input offset voltage variations caused by different input common mode voltages.

In one embodiment, the resistance of the first resistor is a first resistance plus a first error resistance; the second resistor of the current sensing amplifier circuit is coupled between the output voltage and an inverting input end of the amplifier, wherein the resistance value of the second resistor is the first resistance value minus the first error resistance value; the third resistor of the current sense amplifier circuit is coupled between the first input end and the non-inverting input end, wherein the resistance value of the third resistor is a second resistance value minus a second error resistance value; a fourth resistor of the current sense amplifier circuit is coupled between the second input terminal and the inverting input terminal, wherein the resistance value of the fourth resistor is the second resistance value plus the second error resistance value; the input offset voltage is related to the first error resistance and the second error resistance.

The invention has the advantages that the current sensing amplifier circuit has a bidirectional current sensing function, and the accuracy of gain can be improved by correcting current so as to reduce the unmatched resistors caused by the resistor process.

The objects, technical contents, features and effects achieved by the present invention will be more readily understood from the following detailed description of specific embodiments.

Drawings

FIG. 1A is a flow chart showing the steps of a prior art input offset voltage correction method for a current sense amplifier circuit.

FIG. 1B is a schematic diagram showing a prior art current sense amplifier circuit with input offset voltage correction.

Fig. 2A is a circuit schematic diagram showing a current sense amplifier circuit according to an embodiment of the invention.

Fig. 2B is a circuit schematic diagram showing a current sense amplifier circuit according to another embodiment of the invention.

Fig. 3 is a block diagram showing a current source circuit according to an embodiment of the invention.

Fig. 4 is a circuit block diagram showing a current source circuit and a correction current generating circuit therein according to an embodiment of the present invention.

Fig. 5 is a circuit block diagram showing a correction current generating circuit according to another embodiment of the present invention.

Fig. 6 is a circuit block diagram showing a current source circuit according to another embodiment of the present invention.

Fig. 7 is a circuit diagram showing a current correction circuit according to an embodiment of the present invention.

FIG. 8 is a graph showing the difference between the reference voltage and the input voltage of the current sense amplifier circuit according to the present invention relative to the input offset voltage and the difference between the reference voltage and the input voltage of the current sense amplifier circuit according to the prior art relative to the input offset voltage according to an embodiment of the present invention.

FIG. 9 is a graph showing the difference between the reference voltage and the input voltage at different temperatures of the current sense amplifier circuit according to the present invention with respect to the correction current according to an embodiment of the present invention.

FIG. 10 is a graph showing the difference between the reference voltage and the input voltage versus the input offset voltage for different temperatures of the current sense amplifier circuit according to an embodiment of the present invention.

FIG. 11 is a graph showing correction codes used by the current sense amplifier circuit of the present invention versus input offset voltage at different temperatures according to an embodiment of the present invention.

FIG. 12 is a graph showing the correction code used by the current sense amplifier circuit of the present invention versus differential nonlinearity at different temperatures, according to an embodiment of the present invention.

FIG. 13 is a graph showing correction codes used by the current sense amplifier circuit of the present invention versus output voltage at different temperatures according to an embodiment of the present invention.

Fig. 14 is a flowchart showing steps of the input offset voltage correction method according to the present invention, according to an embodiment of the present invention.

FIG. 15 is a flowchart showing steps of generating a correction current according to an embodiment of the present invention.

Fig. 16 is a flowchart showing the steps of the capacitive switching circuit of the present invention to suppress input offset voltage variations at different input common mode voltages, according to an embodiment of the present invention.

Description of the symbols in the drawings

10: input offset voltage correction method

11: current sense amplifier circuit

101-108: step 20: current sense amplifier circuit

201: current source circuit

20111 a, 20111 b: voltage-to-current circuit

2012: correction current generating circuit

20121 20121a,20121b: current replica circuit

20122a,20122b,20122c: addition circuit

20123 20123a,20123b: judging circuit

20124a,20124b: current correction circuit

20125a,20125b,20126a,20126b: current source

202: amplifier

203: first resistor

204: second resistor

205: third resistor

206: fourth resistor

207: capacitive switching circuit

30: input offset voltage correction method

301-306, 3041-3048: step (a)

dR1: first error resistance value

dR2: second error resistance value

En1, en2: enable signal

Idn, iup: electric current

-Ig1: negative first current

Ig2: second current

-Ig2: negative second current

Igc1: first replication current

Igc2: second replication current

Imo1: the result of the first subtraction

Imo2: second subtraction result

Is: current to be sensed

Itrim: correction current

Itim+: first correction current

Itim-: second correction current

Nd1: first node

Nd2: second node

Nd3: third node

Nd4: fourth node

Ni1: a (first) input terminal

Ni2: (second) input terminal

Np1, np2, np3, ns: node

Q1 to Qn, qj1, qj2, qj3: switch

Qm1, qm2: transistor with a high-voltage power supply

R1: first resistance value

R1b, R2b, R3b, R4b, RT, R11, R21, R31, R41, R42, R4a: resistor

R2: second resistance value

Rcr: programmable feedback resistor chain

Rs: sensing resistor

SW1 to SWn-1, SW4a: switch

Vcom: input common mode voltage

VDDA: high potential

Vgs1, vgs2: gate-source voltage

Vin +: (first) input voltage

Vin-: (second) input voltage

Vout: output voltage

Vref: reference voltage

VSSA: low potential

Detailed Description

The drawings in the present invention are schematic and are mainly intended to represent coupling relationships between circuits and relationships between signal waveforms, which are not drawn to scale.

Fig. 2A is a circuit schematic diagram showing a current sense amplifier circuit according to an embodiment of the invention. As shown in fig. 2A, the current sense amplifier circuit 20 of the present invention Is used to sense the current Is to be sensed flowing through the sense resistor Rs. Both ends of the sense resistor Rs are correspondingly coupled to the first input terminal Ni1 and the second input terminal Ni2 of the current sense amplifier circuit 20. The current sense amplifier circuit 20 includes a current source circuit 201, an amplifier 202, a first resistor 203, a second resistor 204, a third resistor 205, and a fourth resistor 206. The amplifier 202 Is configured to generate an output voltage Vout related to the current Is to be sensed according to a first input voltage vin+ of the first input terminal Ni1 and a second input voltage Vin-of the second input terminal Ni2 in a normal operation mode.

The first resistor 203 is coupled between the reference voltage Vref and the non-inverting input terminal of the amplifier 202. The resistance value of the first resistor 203 is the first resistance value R1 plus the first error resistance value dR1. The second resistor 204 is coupled between the output voltage Vout and the inverting input terminal of the amplifier 202. The resistance of the second resistor 204 is the first resistance R1 minus the first error resistance dR1. The third resistor 205 is coupled between the first input terminal Ni1 and the non-inverting input terminal of the amplifier 202. The resistance value of the third resistor 205 is the second resistance value R2 minus the second error resistance value dR2. The fourth resistor 206 is coupled between the second input terminal Ni2 and the inverting input terminal of the amplifier 202. The resistance of the fourth resistor 206 is the second resistance R2 plus the second error resistance dR2.

Referring to fig. 2A and 3, the current source circuit 201 is configured to generate a correction current Itrim according to the first input voltage vin+, the second input voltage Vin-, or the input common mode voltage Vcom and the reference voltage Vref in the correction mode, and to provide the correction current Itrim to correct the input offset (offset referred to input, RTI) voltage of the current sense amplifier circuit 20 generated by the first error resistance dR1 and the second error resistance dR2 in the normal operation mode. In one embodiment, the current source circuit 201 is coupled to: a first node Nd1 between the first resistor 203 and the non-inverting input terminal, a second node Nd2 between the second resistor 204 and the output voltage Vout, a third node Nd3 between the third resistor 205 and the non-inverting input terminal, or a fourth node Nd4 between the fourth resistor 206 and the inverting input terminal.

In one embodiment, as shown in fig. 2A, the resistors R1b, R2b, R3b and R4b are selectively coupled between the non-inverting input terminal of the amplifier 202 and the current source circuit 201, between the output voltage Vout and the current source circuit 201, between the non-inverting input terminal of the amplifier 202 and the current source circuit 201, and between the inverting input terminal of the amplifier 202 and the current source circuit 201, respectively. In the correction mode, the first input terminal Ni1 is electrically connected to the second input terminal Ni2, such that the first input voltage Vin+ and the second input voltage Vin have the same potential. The reference voltage Vref is used for adjusting the input common-mode voltage of the amplifier 202, so that the current sense amplifier circuit 20 has a bidirectional current sense function.

Referring to fig. 2A and 6, in the correction mode, for example, when the current source circuit 201 is coupled to the second node Nd2 between the second resistor 204 and the output voltage Vout and the resistor R2b is coupled between the output voltage Vout and the current source circuit 201, the output voltage Vout is shown in formula (1) because the first input voltage vin+ is equal to the second input voltage Vin-:

where m is the multiplying power of all current mirrors and current correction circuits 20124a and 20124 b. In the formula (1)To input offset voltage- >To correct the compensation term of current Itrim, which corresponds to the input offset voltage, the compensation term does not affect the gain error (gain error) of amplifier 202.

As shown in the compensation term of the correction current Itrim, the correction current Itrim is proportional to the difference between the first input voltage Vin+ and the reference voltage Vref. Referring to fig. 7, in the correction mode, under specific conditions (i.e. selecting a reference voltage Vref and selecting a combination of the first input voltage vin+, according to the difference between the output voltage Vout and the reference voltage Vref, the ratio of the respective turned-on transistors in the current correction circuits 20124a and 20124b is gradually adjusted (i.e. using various approximations) to adjust the m value in the equation (1), and the m value obtained when the output voltage Vout is equal to or closest to the reference voltage Vref is the m value that can make the compensation term of the input offset voltage and the correction current Itrim in the equation (1) equal to or closest to each other. In the normal operation mode, the current source circuit 201 is enabled to provide the correction current Itrim to correct the input offset voltage generated by the first error resistance dR1 and the second error resistance dR2 by setting the ratio of the turned-on transistors in the current correction circuits 20124a and 20124b to the obtained m value. And because the current correction circuits 20124a and 20124b according to the present invention are configured for the m value, the current source circuit 201 can provide the correct correction current Itrim to compensate the input offset voltage without entering the correction mode again, no matter how the first input voltage vin+ and the reference voltage Vref change.

The input offset voltage corrected by the present invention refers to the input offset voltage of the current sense amplifier circuit, and not to the input offset voltage of the amplifier therein. The invention is particularly based on input offset voltages in current sense amplifier circuits due to errors in the manufacturing process of the resistors therein.

In one embodiment, the correction current Itrim is proportional to the difference between the first input voltage vin+ and the reference voltage Vref, the difference between the second input voltage Vin-and the reference voltage Vref, or the difference between an input common-mode voltage of the first input voltage vin+ and the second input voltage Vin-and the reference voltage Vref.

In one embodiment, the first error resistance dR1 is much smaller than the first resistance R1, e.g., the first error resistance dR1 is at least half smaller than the first resistance R1; and the second error resistance dR2 is much smaller than the second resistance R2, for example, the second error resistance dR2 is at least half smaller than the second resistance R2. In the ideal current sense amplifier circuit 20, the first error resistance dR1 and the second error resistance dR2 are zero, that is, in the ideal current sense amplifier circuit 20, the resistance of the first resistor 203 and the second resistor 204 have the same resistance (i.e., the first resistance R1); the third resistor 205 has the same resistance as the fourth resistor 206 (i.e., the second resistance R2). Because of the errors in the manufacturing process of the first resistor 203 and the second resistor 204, the resistance value of the first resistor 203 is the first resistance value R1 plus the first error resistance value dR1 and the resistance value of the second resistor 204 is the first resistance value R1 minus the first error resistance value dR1. In addition, because of the errors in the manufacturing process of the third resistor 205 and the fourth resistor 206, the resistance value of the third resistor 205 is the second resistance value R2 minus the second error resistance value dR2 and the resistance value of the fourth resistor 206 is the second resistance value R2 plus the second error resistance value dR2.

In one embodiment, the current source circuit 201 generates the correction current Itrim according to the first input voltage vin+, the second input voltage Vin-, or the input common-mode voltage Vcom and the reference voltage Vref by a binary approximation, a single slope approximation, or a successive approximation in the correction mode.

It should be noted that, the input common-mode voltage Vcom is an average of the first input voltage vin+ and the second input voltage Vin-, and in a general application, the levels of the first input voltage vin+, the second input voltage Vin-, or the input common-mode voltage Vcom are very close, so that the correction current Itrim can be generated.

Fig. 2B is a circuit schematic diagram showing a current sense amplifier circuit according to another embodiment of the invention. This embodiment is similar to the embodiment of fig. 2A, except that this embodiment further includes a capacitive switch circuit (chopper) 207 coupled between the non-inverting input terminal and the inverting input terminal of the amplifier 202 to suppress input offset voltage variations caused at different input common mode voltages.

Fig. 3 is a block diagram showing a current source circuit according to an embodiment of the invention. As shown in fig. 3, the current source circuit 201 includes a voltage-to-current circuit 2011a, a voltage-to-current circuit 2011b, and a correction current generating circuit 2012. The voltage-to-current circuit 2011a is used for converting the first input voltage vin+, the second input voltage Vin-, or the input common-mode voltage Vcom to generate a first current Ig1. The voltage-to-current circuit 2011b is used for converting the reference voltage Vref to generate a second current Ig2. In the correction mode, the correction current generation circuit 2012 generates the correction current Itrim according to the first current Ig1 and the second current Ig2 so that the output voltage Vout is equal to or closest to the reference voltage Vref.

Fig. 4 is a circuit block diagram showing a current source circuit and a correction current generating circuit therein according to an embodiment of the present invention. The voltage-to-current circuits 2011a and 2011b of the present embodiment are similar to the voltage-to-current circuits 2011a and 2011b of fig. 3, so a detailed description thereof is omitted. As shown in fig. 4, the correction current generating circuit 2012 includes current replica circuits 20121a and 20121b, an adding circuit 20122a, an adding circuit 20122b, an adding circuit 20122c, a judging circuit 20123, and current correction circuits 20124a and 20124b. The current replication circuit 20121a is configured to replicate the first current Ig1 to generate a first replication current Igc1, and the current replication circuit 20121b is configured to replicate the second current Ig2 to generate a second replication current Igc2. The adder 20122a performs a subtraction operation to subtract the second replica current Igc2 from the first replica current Igc1 to generate a first subtraction result Imo. The adder 20122b performs a subtraction operation to subtract the first replica current Igc1 from the second replica current Igc2 to generate a second subtraction result Imo.

The determining circuit 20123 is configured to generate an enable signal En1 when the first replica current Igc1 is higher than the second replica current Igc2, and generate the enable signal En2 when the second replica current Igc2 is higher than the first replica current Igc 1. The current correction circuit 20124a is configured to be enabled by the enable signal En1 to correct the first subtraction result Imo1 to generate a first corrected current itrim+. The current correction circuit 20124b is configured to be enabled by the enable signal En2 to correct the second subtraction result Imo to generate a second corrected current Itrim-. The adder 20122c is configured to add the first correction current itrim+ and the second correction current Itrim to generate the correction current Itrim. In one embodiment, the current replication circuits 20121a and 20121b each include at least one current mirror circuit. The specific implementation of the determining circuit 20123 is well known to those skilled in the art, and is not described herein.

Fig. 5 is a circuit block diagram showing a correction current generating circuit according to another embodiment of the present invention. The determination circuit 20123 of the present embodiment is similar to the determination circuit 20123 of fig. 4, so a detailed description thereof is omitted. As shown in fig. 5, in the present embodiment, the adding circuits 20122a, 20122b, and 20122c are respectively implemented in such a manner that the circuits are directly coupled to the nodes Np1, np2, and Np 3. One end of the adder 20122a is coupled to a current source 20125a between the ground potential and one end thereof, thereby providing a second current Ig2 flowing from the node Np1 to the ground potential, which corresponds to a negative second current-Ig 2 flowing from the ground potential to the node Np1, and the other end of the adder 20122a is coupled to a current source 20125b, thereby providing a first current Ig1 flowing into the node Np1, and further performing an addition operation by the adder 20122a, thereby obtaining a first subtraction result Imo1. One end of the adder 20122b is coupled to a current source 20126a, thereby providing a first current Ig1 flowing from the node Np2 to the ground potential, which corresponds to a negative first current-Ig 1 flowing from the ground potential to the node Np2, and the other end of the adder 20122b is coupled to the current source 20126b, thereby providing a second current Ig2 flowing into the node Np2, and the adder 20122b performs the addition operation to obtain a second subtraction result Imo2.

The current replica circuit 20121 in this embodiment is implemented as a current mirror. The current correction circuits 20124a and 20124b are implemented with a switch having a correction ratio of 1:1, so that the obtained first correction current itrim+ has a value obtained by subtracting the second current Ig2 from the first current Ig1, and the obtained second correction current Itrim-has a value obtained by subtracting the first current Ig1 from the second current Ig2 and is discharged out of the node Np3, which corresponds to a negative second correction current Itrim-flowing into the node Np3, i.e. has a value obtained by subtracting the negative value of the first current Ig1 from the second current Ig2, and then the addition circuit 20122c performs the addition operation to generate the correction current Itrim. It should be noted that one or both of the current correction circuits 20124a and 20124b may also be implemented with a combination of multiple switches of any other magnification.

Fig. 6 is a circuit block diagram showing a current source circuit according to another embodiment of the present invention. In the present embodiment, as shown in fig. 6, the voltage-to-current circuit 2011a includes a resistor RT, and the voltage-to-current circuit 2011b includes a resistor RT. The current replication circuits 20121a and 20121b each include at least one current mirror. In this embodiment, the adding circuits 20122a and 20122b are implemented by transistors, and the adding circuit 20122c is implemented by a circuit directly coupled method. In this embodiment, the determining circuits 20123a and 20123b include at least one switch Qj1 and Qj2. As shown in fig. 6, the first current Ig1 is shown in formula (2):

Where RT is the resistance value of resistor RT and Vgs1 is the gate-source voltage of transistor Qm 1. Similarly, the second current Ig2 is represented by formula (3):

where Vgs2 is the gate-source voltage of transistor Qm 2. As shown in fig. 6, by the subtraction of the adder 20122a, the first current Ig1 minus the second current Ig2 is equal to the current Iup, which is shown in the formula (4) assuming that the gate-source voltage Vgs1 is equal to the gate-source voltage Vgs 2:

the current Iup is corrected by the current correction circuit 20124a to obtain a first corrected current itrim+. As shown in fig. 6, by the subtraction operation of the adder circuit 20122b, the second current Ig2 minus the first current Ig1 is equal to the current Idn, which is shown as equation (5) assuming that the gate-source voltage Vgs1 is equal to the gate-source voltage Vgs 2:

the current Idn is corrected by the current correction circuit 20124b to obtain a second corrected current Itrim-. As in the embodiment of FIG. 5, the first correction current itrim+ and the second correction current Itrim are added by an adder 20122c to generate a correction current Itrim. It should be noted that one or both of the current correction circuits 20124a and 20124b may be implemented with a 1:1 correction factor or a combination of one or more switches of any other correction factor. In the present embodiment, assuming that the correction magnification is m and assuming that the magnification of all the current mirrors is 1, the first correction current itrim+ and the second correction current Itrim-are respectively as shown in equations (6) and (7):

In one embodiment, when the value of the first current Ig1 minus the second current Ig2 is greater than 0, the gate signal of the switch Qj1 is switched to the disable level and the gate signal of the switch Qj2 is switched to the enable level, so that the switch Qj2 is turned on to generate the first correction current itrim+. Since the gate signal of the switch Qj1 is switched to the disable level, the switch Qj1 is turned off, so that the node Ns is coupled to the ground potential, and the gate signal of the switch Qj3 is caused to be switched to the disable level, so that the switch Qj3 is turned off, thereby ensuring that the second correction current Itrim is zero when the first correction current itrim+ is positive.

Fig. 7 is a circuit diagram showing a current correction circuit according to an embodiment of the present invention. This embodiment is an exemplary embodiment of the current correction circuit 20124b of fig. 4 and 6. The current correction circuit 20124a of fig. 4 and 6 may also be implemented in a similar manner. As shown in fig. 7, the current correction circuit 20124b includes one or more switches Q1-Qn with gates coupled to each other. The current correction circuit 20124b adjusts the number of on switches among the switches SW1 to SWn-1 according to a predetermined correction rate, and further adjusts the number of active switches among the switches Q1 to Qn-1, so that the generated correction current Itrim can make the output voltage Vout equal to or closest to the reference voltage Vref in the correction mode. The number of the switches SW1 to SWn-1 to be turned on may be determined by, for example, a binary approximation, a single slope approximation, or a successive approximation, so as to generate the correction current Itrim, so that the output voltage Vout may be equal to or closest to the reference voltage Vref. The binary approximation, the single slope approximation and the successive approximation are well known to those skilled in the art and are not described here.

FIG. 8 is a graph showing the difference between the reference voltage and the input voltage of the current sense amplifier circuit according to the present invention relative to the input offset voltage and the difference between the reference voltage and the input voltage of the current sense amplifier circuit according to the prior art relative to the input offset voltage according to an embodiment of the present invention. As can be seen from fig. 8, the present invention significantly improves the correction of the input offset voltage over the prior art.

FIG. 9 is a graph showing the difference between the reference voltage and the input voltage at different temperatures of the current sense amplifier circuit according to the present invention with respect to the correction current according to an embodiment of the present invention. FIG. 10 is a graph showing the difference between the reference voltage and the input voltage versus the input offset voltage for different temperatures of the current sense amplifier circuit according to an embodiment of the present invention. As can be seen from fig. 9 and 10, the input offset voltage can be stably corrected by the correction current Itrim generated at different temperatures.

FIG. 11 is a graph showing correction codes used by the current sense amplifier circuit of the present invention versus input offset voltage at different temperatures according to an embodiment of the present invention. FIG. 12 is a graph showing the correction code used by the current sense amplifier circuit of the present invention versus differential nonlinearity at different temperatures, according to an embodiment of the present invention. FIG. 13 is a graph showing correction codes used by the current sense amplifier circuit of the present invention versus output voltage at different temperatures according to an embodiment of the present invention. Fig. 11 to 13 show compensation results at different correction currents (expressed by correction codes, and different correction codes represent different correction magnifications) when the first input voltage vin+ is 26V and the reference voltage Vref is 1V.

Fig. 14-16 are flowcharts showing steps of an input offset voltage correction method according to an embodiment of the present invention. As shown in fig. 14, the input offset voltage correction method 30 of the present invention includes at step 301, electrically connecting a first input terminal and a second input terminal of the current sense amplifier circuit such that a first input voltage of the first input terminal and a second input voltage of the second input terminal have the same potential. Next, in step 302, the first input voltage is converted to generate a first current. Then, in step 303, a reference voltage is converted to generate a second current. Then, in step 304, a correction current is generated according to the first current and the second current, so that an output voltage of the current sense amplifier circuit is equal to or closest to the reference voltage. Next, in step 305, in a normal operation mode, the correction current is provided to correct the input offset voltage generated by the current sense amplifier circuit.

In one embodiment, as shown in FIG. 15, step 304 includes steps 3041-3048. In step 3041, the first current is replicated to generate a first replicated current. Then, in step 3042, the second current is replicated to generate a second replicated current. Next, in step 3043, a subtraction operation is performed to subtract the second replica current from the first replica current, thereby generating a first subtraction result. Then, in step 3044, a subtraction operation is performed to subtract the first replica current from the second replica current, thereby generating a second subtraction result. Then, in step 3045, a first enable signal is generated when the first replica current is higher than the second replica current, and a second enable signal is generated when the second replica current is higher than the first replica current. Then, in step 3046, the first subtraction result is modified according to the first enable signal to generate a first modified current. Next, in step 3047, the second subtraction result is modified according to the second enable signal to generate a second modified current. Then, in step 3048, an addition operation is performed on the first correction current and the second correction current to generate the correction current. In one embodiment, the input offset voltage correction method 30 of the present invention may further include a step 306, as shown in fig. 16, of using a capacitive switch circuit coupled between the non-inverting input terminal and an inverting input terminal of the current sense amplifier circuit to suppress the input offset voltage variation caused by different input common mode voltages.

As described above, the present invention provides a current sense amplifier circuit and an input offset voltage correction method thereof, which can enable the current sense amplifier circuit to have a bidirectional current sensing function, and can improve the accuracy of gain by adjusting the correction current to reduce the resistance mismatch caused by the resistance process.

The present invention has been described in terms of the preferred embodiments, but the above description is only for the purpose of easily understanding the present invention by those skilled in the art, and is not intended to limit the scope of the claims of the present invention. The embodiments described are not limited to single applications but may be combined, for example, two or more embodiments may be combined, and portions of one embodiment may be substituted for corresponding components of another embodiment. In addition, various equivalent changes and various combinations will be apparent to those skilled in the art, and for example, the term "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the processing or calculating based on the signal itself, but includes performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling conversion of the signal, if necessary, and then processing or calculating based on the converted signal to generate an output result. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described herein, embody the principles of the invention and are thus equally well suited to the particular use contemplated. Accordingly, the scope of the invention should be assessed as that of the above and all other equivalent variations.

Claims (19)

1. A current sense amplifier circuit for sensing a current to be sensed flowing through a sense resistor, wherein two ends of the sense resistor are correspondingly coupled to a first input terminal and a second input terminal of the current sense amplifier circuit, the current sense amplifier circuit comprising:

an amplifier for generating an output voltage related to the current to be sensed according to a first input voltage of the first input terminal and a second input voltage of the second input terminal in a normal operation mode;

the first resistor is coupled between a reference voltage and a non-inverting input end of the amplifier, wherein the resistance value of the first resistor is a first resistance value plus a first error resistance value;

the second resistor is coupled between the output voltage and an inverting input end of the amplifier, wherein the resistance value of the second resistor is the first resistance value minus the first error resistance value;

the third resistor is coupled between the first input end and the non-inverting input end, wherein the resistance value of the third resistor is a second resistance value minus a second error resistance value;

a fourth resistor coupled between the second input terminal and the inverting input terminal, wherein the resistance of the fourth resistor is the second resistance plus the second error resistance; and

A current source circuit for generating a correction current according to the first input voltage, the second input voltage or an input common mode voltage and the reference voltage in a correction mode, and providing the correction current to correct the input offset voltage generated by the first error resistance and the second error resistance in the normal operation mode;

wherein, this current source circuit is coupled to: a first node between the first resistor and the non-inverting input terminal, a second node between the second resistor and the output voltage, a third node between the third resistor and the non-inverting input terminal, or a fourth node between the fourth resistor and the inverting input terminal;

in the correction mode, the first input terminal is electrically connected to the second input terminal, so that the first input voltage and the second input voltage have the same potential.

2. The current sense amplifier circuit of claim 1 wherein the current source circuit comprises:

a first voltage-to-current circuit for converting the first input voltage, the second input voltage or the input common mode voltage to generate a first current;

a second voltage-to-current circuit for converting the reference voltage to generate a second current; and

And a correction current generating circuit for generating the correction current according to the first current and the second current in the correction mode so that the output voltage is equal to or closest to the reference voltage.

3. The current sense amplifier circuit of claim 2 wherein the modified current generating circuit comprises:

a first current copying circuit for copying the first current to generate a first copying current;

a second current copying circuit for copying the second current to generate a second copying current;

a first adder for performing a subtraction operation to subtract the second replica current from the first replica current to generate a first subtraction result;

a second adder for performing a subtraction operation to subtract the first replica current from the second replica current to generate a second subtraction result;

a judging circuit for generating a first enabling signal when the first replication current is higher than the second replication current, and generating a second enabling signal when the second replication current is higher than the first replication current;

a first current correction circuit for correcting the first subtraction result by being enabled by the first enable signal to generate a first correction current;

A second current correction circuit for correcting the second subtraction result by being enabled by the second enable signal to generate a second correction current; and

a third adding circuit for performing an adding operation on the first and second correction currents to generate the correction current.

4. The current sense amplifier circuit of claim 3, wherein the first current replica circuit and the second current replica circuit each comprise at least one current mirror circuit.

5. The current sense amplifier circuit of claim 1, wherein the reference voltage is used to adjust the input common mode voltage of the amplifier to provide the current sense amplifier circuit with a bi-directional current sense function.

6. The current sense amplifier circuit of claim 5, further comprising a capacitive switch circuit coupled between the non-inverting input terminal and the inverting input terminal for suppressing input offset voltage variations caused by different input common mode voltages.

7. The current sense amplifier circuit of claim 1, wherein the input offset voltage corresponds to a compensation term associated with the correction current, and the compensation term does not affect the gain error of the amplifier.

8. The current sense amplifier circuit of claim 1, wherein the correction current is proportional to a difference between the first input voltage and the reference voltage, a difference between the second input voltage and the reference voltage, or a difference between the input common mode voltage and the reference voltage.

9. The current sense amplifier circuit of claim 1, wherein the first error resistance is less than half of the first resistance and the second error resistance is less than half of the second resistance.

10. The current sense amplifier circuit of claim 1, wherein the current source circuit generates the correction current in the correction mode according to the first input voltage and the reference voltage by a binary approximation, a single slope approximation, or a successive approximation.

11. An input offset voltage correction method for correcting an input offset voltage of a current sense amplifier circuit, the input offset voltage correction method comprising:

electrically connecting a first input end and a second input end of the current sense amplifier circuit so that a first input voltage of the first input end and a second input voltage of the second input end have the same potential;

converting the first input voltage, the second input voltage or an input common mode voltage to generate a first current;

Converting a reference voltage to generate a second current; and

generating a correction current according to the first current and the second current so that an output voltage of the current sense amplifier circuit is equal to or closest to the reference voltage;

wherein a first resistor of the current sense amplifier circuit is coupled between the reference voltage and a non-inverting input of an amplifier of the current sense amplifier circuit;

wherein in a normal operation mode, the correction current is provided to correct the input offset voltage generated by the current sense amplifier circuit.

12. The method of claim 11, wherein generating the correction current to make the output voltage of the current sense amplifier circuit equal to or closest to the reference voltage according to the first current and the second current comprises:

copying the first current to generate a first copying current;

copying the second current to generate a second copying current;

performing a subtraction operation to subtract the second replica current from the first replica current to generate a first subtraction result;

performing a subtraction operation to subtract the first replica current from the second replica current to generate a second subtraction result;

Generating a first enabling signal when the first replication current is higher than the second replication current, and generating a second enabling signal when the second replication current is higher than the first replication current;

correcting the first subtraction result according to the first enabling signal to generate a first correction current;

correcting the second subtraction result according to the second enabling signal to generate a second correction current; and

an addition operation is performed on the first correction current and the second correction current to generate the correction current.

13. The method of claim 11, wherein the reference voltage is used to adjust the input common mode voltage of the amplifier to provide the current sense amplifier circuit with bi-directional current sensing.

14. The input offset voltage correction method as claimed in claim 11, further comprising: a capacitance switch circuit is coupled between the non-inverting input terminal and an inverting input terminal of the current sense amplifier circuit for suppressing input offset voltage variation caused by different input common mode voltages.

15. The method of claim 11, wherein the input offset voltage corresponds to a compensation term associated with the correction current, and the compensation term does not affect the gain error of the amplifier.

16. The method of claim 11, wherein the first resistor has a resistance value of a first resistance value plus a first error resistance value; the second resistor of the current sensing amplifier circuit is coupled between the output voltage and an inverting input end of the amplifier, wherein the resistance value of the second resistor is the first resistance value minus the first error resistance value; the third resistor of the current sense amplifier circuit is coupled between the first input end and the non-inverting input end, wherein the resistance value of the third resistor is a second resistance value minus a second error resistance value; a fourth resistor of the current sense amplifier circuit is coupled between the second input terminal and the inverting input terminal, wherein the resistance value of the fourth resistor is the second resistance value plus the second error resistance value; the input offset voltage is related to the first error resistance and the second error resistance.

17. The method of claim 11, wherein the correction current is proportional to a difference between the first input voltage and the reference voltage, a difference between the second input voltage and the reference voltage, or a difference between the input common mode voltage and the reference voltage.

18. The method of claim 16, wherein the first error resistance is less than half of the first resistance and the second error resistance is less than half of the second resistance.

19. The method of claim 11, wherein the step of generating a correction current according to the first current and the second current such that an output voltage of the current sense amplifier circuit is equal to or closest to the reference voltage generates the correction current by a binary approximation, a single slope approximation, or a successive approximation.