CN117613132A

CN117613132A - Semiconductor structure, sensor device and method for forming photoelectric detector

Info

Publication number: CN117613132A
Application number: CN202310993119.2A
Authority: CN
Inventors: 刘柏均
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-11-01
Filing date: 2023-08-08
Publication date: 2024-02-27

Abstract

Various embodiments of the present invention relate to a sensor device including a photodetector with a simplified manufacturing process. A semiconductor structure for a photodetector includes a semiconductor substrate including an avalanche region where a p-type region and an n-type region form a PN junction. The inner absorber layer is recessed into the semiconductor substrate, wherein the inner absorber layer has a bottom protrusion protruding toward the avalanche region. The peripheral absorbent layer is located on the side wall of the inner absorbent layer and the bottom of the inner absorbent layer and also extends from the side wall to the bottom projection. The inner absorber layer and the peripheral absorber layer share a common semiconductor material and have a smaller bandgap than the semiconductor substrate. Furthermore, the peripheral absorber layer has a doping concentration that is elevated relative to the doping concentration of the inner absorber layer. Embodiments of the invention also provide sensor devices and methods of forming photodetectors.

Description

Semiconductor structure, sensor device and method for forming photoelectric detector

Technical Field

Embodiments of the present invention relate to semiconductor structures, sensor devices, and methods of forming photodetectors.

Background

Single Photon Avalanche Diodes (SPADs) are solid state photodetectors based on semiconductor p-n junctions. During operation, photo-generated carriers are accelerated by the electric field in the bulk material of the SPAD to kinetic energy sufficient to overcome the ionization energy of the bulk material, thereby knocking electrons out of the atoms of the bulk material. A large number of avalanche of current carriers occurs and grows exponentially to produce short duration trigger pulses. Thus, SPADs can be used to detect as few carriers as a single photo-generated carrier. Furthermore, due to the high speed of avalanche stacking, the leading edge of the pulse can be used to obtain the arrival time of photo-generated carriers.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor structure for a photodetector, the semiconductor structure comprising: a semiconductor substrate including an avalanche region where the p-type region and the n-type region form a PN junction; an inner absorber layer recessed into the semiconductor substrate, wherein the inner absorber layer has a bottom protrusion protruding toward the avalanche region; and a peripheral absorbent layer located on the sidewall of the inner absorbent layer and the bottom of the inner absorbent layer and also extending from the sidewall to the bottom protrusion; wherein the inner absorber layer and the peripheral absorber layer share a common semiconductor material and have a smaller bandgap than the semiconductor substrate, and the peripheral absorber layer has a doping concentration that is elevated relative to the doping concentration of the inner absorber layer.

Further embodiments of the present invention provide a sensor device comprising: a silicon substrate; a first well buried in the silicon substrate and having a first doping type; a second well located above and directly on the first well in the silicon substrate, wherein the second well has a second doping type opposite to the first doping type; a germanium structure located above the second well and recessed into the silicon substrate; undoped regions in the germanium structure; and a doped region in the germanium structure; wherein the doped region surrounds a bottom corner of the undoped region to separate the bottom corner from the silicon substrate, and the first and second wells and the germanium structure form a photodetector.

Still further embodiments of the present invention provide a method of forming a photodetector, the method comprising: forming a first well buried in the semiconductor substrate, and the first well having a first doping type; performing a first etch on the semiconductor substrate to form a trench, the trench being located above and spaced apart from the first well; doping the semiconductor substrate through the trench to form a second well on the first well, wherein the second well has a second doping type opposite to the first doping type; epitaxially growing a peripheral absorber layer on the exposed surface of the semiconductor substrate in the trench, the peripheral absorber layer having a second doping type; and epitaxially growing an inner absorber layer to fill the remainder of the trench over the peripheral absorber layer; wherein the peripheral absorber layer and the inner absorber layer are semiconductive and have a smaller bandgap than the semiconductor substrate.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It is noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of some embodiments of a sensor device including a photodetector in accordance with aspects of the present disclosure.

Fig. 2A and 2B illustrate top layout views of various embodiments of the sensor device of fig. 1.

Fig. 3A-3C illustrate doping profiles of various embodiments of a peripheral absorber layer in the sensor device of fig. 1.

Fig. 4A to 4E show cross-sectional views of various alternative embodiments of the sensor device of fig. 1.

FIG. 5 illustrates a cross-sectional view of some embodiments of the sensor device of FIG. 1 in which the sensor device includes a plurality of Integrated Circuit (IC) chips.

Fig. 6A and 6B show cross-sectional views of various alternative embodiments of the sensor device of fig. 5.

Fig. 7 illustrates a top layout view of some embodiments of the sensor device of fig. 6B.

Fig. 8-26 illustrate a series of cross-sectional views of some embodiments of methods of forming a sensor device including a photodetector, in accordance with aspects of the present disclosure.

Fig. 27 shows a block diagram of some embodiments of the methods of fig. 8-26.

Fig. 28-32 illustrate a series of cross-sectional views of some alternative embodiments of the method of fig. 8-26 in which the peripheral absorber layer has square ends on top of the semiconductor substrate.

Fig. 33-36 show a series of cross-sectional views of some alternative embodiments of the method of fig. 8-26 in which the peripheral absorber layer has square ends at the second avalanche well.

Fig. 37-41 show a series of cross-sectional views of some alternative embodiments of the method of fig. 8-26 in which the peripheral absorber layer has square ends at the top of the semiconductor substrate and at the second avalanche well.

Detailed Description

The instant disclosure provides many different embodiments, or examples, of the different components used to implement the instant disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "under …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Short Wave Infrared (SWIR) sensor devices typically include Single Photon Avalanche Diodes (SPADs) for indirect time of flight (iToF) depth sensing. iToF depth sensing applications include three-dimensional (3D) imaging and ranging on Advanced Driving Assistance Systems (ADAS), among others. Such SPADs may include a germanium absorbing structure located above and recessed into a silicon substrate, and an avalanche region located below the germanium absorbing structure in the silicon substrate.

Germanium absorbing structures provide enhanced absorption of SWIR radiation compared to silicon due to their smaller bandgap than silicon. However, germanium absorbing structures may result in high dark currents, which may result in high Dark Count Rates (DCR), and may thus adversely affect performance. The high dark current dominates at the interface between the germanium absorbing structure and the silicon substrate and may be due to: 1) A small band gap; 2) Crystal defects in the germanium absorbing structure; and 3) an interface state between the silicon substrate and the germanium absorber structure. Due to lattice mismatch, crystal defects and interface states may occur when epitaxially growing germanium absorber structures on silicon substrates.

To reduce dark current, SPADs may be formed with a p-type interface region in the silicon substrate at or near the interface between the germanium absorber structure and the silicon substrate. In addition, the SPAD may be formed with a p-type guard ring in the germanium absorber structure, the p-type guard ring extending along a periphery of the germanium absorber structure. Because of the p-type doping, the p-type interface region and the p-type guard ring are hole rich and passivate crystal defects and interface states to suppress dark current. However, the p-type interface region and the p-type guard ring are formed by selective ion implantation using photolithography, which increases manufacturing complexity. Furthermore, ion implantation during the formation of the p-type interface region can cause damage to the silicon substrate and rely on thermal processing for repair, further increasing manufacturing complexity.

Various embodiments of the present disclosure are directed to SWIR sensor devices including SPADs with reduced manufacturing complexity. As shown below, the reduction in manufacturing complexity stems from the omission of the p-type interface region in the silicon substrate and the p-type guard ring in the germanium absorber structure. The germanium absorber structure includes an inner germanium layer and a peripheral absorber layer.

The inner germanium layer is recessed into the silicon substrate and has a bottom protrusion protruding through the peripheral germanium layer toward the avalanche region. A peripheral germanium layer is located at an interface between the germanium absorber structure and the silicon substrate. Further, the peripheral germanium layer is located on the sidewalls of the inner germanium layer and the bottom of the inner germanium layer and further extends from the sidewalls to the bottom protrusion. The inner germanium layer is intrinsic or lightly doped, while the outer germanium layer is highly doped with a p-type dopant. Thus, the peripheral germanium layer is rich in holes and passivates crystal defects and interface states to suppress dark current.

Because the peripheral germanium layer suppresses dark current, the peripheral germanium layer acts as a substitute for the p-type interface region and the p-type guard ring. Further, since the number of regions/structures for suppressing dark current is reduced from two to one, manufacturing complexity is reduced. For example, photolithography and ion implantation to form the p-type guard ring may be omitted.

Unlike the p-type interface region, the peripheral germanium layer may be formed by a self-aligned epitaxial growth process in which the peripheral germanium layer is simultaneously grown and doped on the silicon substrate. Because the peripheral germanium layer is grown and doped simultaneously, its formation does not involve ion implantation into the silicon substrate and therefore does not damage the silicon substrate. Thus, ion implantation and heat treatment to form the p-type interface region can be omitted.

Referring to fig. 1, a cross-sectional view 100 of some embodiments of a sensor device including a photodetector 102 in accordance with aspects of the present disclosure is provided. The photodetector 102 includes an absorbing structure 104 above the semiconductor substrate 106 and recessed into the semiconductor substrate 106, and the photodetector 102 further includes an avalanche region 108 below the absorbing structure 104 in the semiconductor substrate 106. For example, the photodetector 102 may be a SPAD, avalanche Photodiode (APD), or the like.

The avalanche region 108 corresponds to a region where photo-generated carriers from the absorbing structure 104 are multiplied by the avalanche effect. Therefore, the avalanche region 108 may also be referred to as a multiplication region or the like. The avalanche region 108 is formed by a PN junction located where the first avalanche well 110 and the second avalanche well 112 are in direct contact. The first avalanche well 110 and the second avalanche well 112 are disposed below the absorber structure 104 in the semiconductor substrate 106 and have opposite doping types. For example, the first avalanche well 110 may be n-type, while the second avalanche well 112 may be p-type, and vice versa. Further, a second avalanche well 112 is disposed above the first avalanche well 110 and extends from the first avalanche well 110 to the absorption structure 104.

The absorber structure 104 is semiconductive and is a different semiconductor material than the semiconductor substrate 106. Furthermore, the absorbing structure 104 has a higher absorption coefficient for the target radiation than the semiconductor substrate 106. In some embodiments, the higher absorption coefficient results from the absorption structure 104 having a smaller bandgap than the semiconductor substrate 106. Because of the high absorption coefficient, the absorbing structure 104 is used to absorb radiation incident on the photodetector 102. The absorbing structure 104 may be or comprise, for example, germanium, a germanium tin alloy (e.g., geSn), etc., and the semiconductor substrate 106 may be or comprise, for example, silicon, etc., at least when the target radiation is long wave radiation.

As used herein, long wave radiation may be or include, for example, radiation having a wavelength greater than about 1310 nanometers, about 2000 nanometers, about 3000 nanometers, or some other suitable value, and/or long wave radiation may be or include, for example, radiation having a wavelength of about 1310-3000 nanometers, about 1310-2155 nanometers, about 2155-3000 nanometers, or some other suitable value. Furthermore, the long wave radiation may be or comprise SWIR radiation, for example.

The absorbent structure 104 includes an inner absorbent layer 114 and a peripheral absorbent layer 116. The inner absorber layer 114 is recessed into the semiconductor substrate 106 and has a bottom protrusion 114p protruding through the outer peripheral absorber layer 116 to the second avalanche well 112. A peripheral absorber layer 116 is located at the interface between the semiconductor substrate 106 and the absorber structure 104. In addition, the peripheral absorber layer 116 is located on the sidewall of the inner absorber layer 114 and the bottom of the inner absorber layer 114, and also extends from the sidewall to the bottom protrusion 114p. Thus, the peripheral absorber layer 116 separates the inner absorber layer 114 from the semiconductor substrate 106 except at the bottom protrusion 114p. In addition, the peripheral absorber layer 116 surrounds the bottom corner of the inner absorber layer 114 to separate the bottom corner from the semiconductor substrate 106.

The inner absorber layer 114 is intrinsic or lightly doped compared to the outer absorber layer 116, while the outer absorber layer 116 is highly doped compared to the inner absorber layer 114. Thus, the inner absorber layer 114 has a smaller doping concentration than the outer absorber layer 116. Furthermore, the peripheral absorption layer 116 is doped with a dopant having the same doping type as the second avalanche well 112 and having a doping type opposite to that of the first avalanche well 110.

Because the absorber structure 104 is a different semiconductor material than the semiconductor substrate 106, the absorber structure 104 and the semiconductor substrate 106 may have mismatched lattice constants, coefficients of thermal expansion, and the like. This may cause crystal defects in the absorber structure 104 and/or interface states between the semiconductor substrate 106 and the absorber structure 104. In addition, defects and interface states may cause dark currents at the interface between the semiconductor substrate 106 and the absorber structure 104. However, because the peripheral absorption layer 116 is highly doped, the peripheral absorption layer 116 is rich in carriers and passivates crystal defects and interface states at the interface to suppress dark current.

In addition, as shown below, the peripheral absorption layer 116 allows the formation of the photodetector 102 with reduced complexity compared to other similar photodetectors. For example, the photodetector 102 may be formed without a guard ring in the absorbing structure 104, thereby eliminating the photolithography process and the ion implantation process. As another example, the peripheral absorption layer 116 may be formed without ion implantation, and thus the peripheral absorption layer 116 may be formed without damaging the semiconductor substrate 106. Thus, the heat treatment and ion implantation process for repairing the damage can be omitted.

With continued reference to fig. 1, the inner absorber layer 114 and the outer absorber layer 116 are semi-conductive and have a higher absorption coefficient for the target radiation than the semiconductor substrate 106. In some embodiments, the inner absorber layer 114 and the peripheral absorber layer 116 also have a smaller bandgap than the semiconductor substrate 106. The smaller band gap enhances absorption of long wave radiation. The smaller bandgap may be, for example, about 0.66 electron volts (eV) or some other suitable value, and/or the smaller bandgap may be, for example, less than about 1eV, 0.7eV, or some other suitable value.

In some embodiments, the inner absorber layer 114 and the outer absorber layer 116 are or include a common semiconductor material in addition to doping. For example, the inner absorber layer 114 and the outer absorber layer 116 may be or include germanium, germanium tin alloys, and the like. In alternative embodiments, the inner absorber layer 114 and the peripheral absorber layer 116 are or comprise different semiconductor materials in addition to doping. For example, the inner absorber layer 114 may be or include germanium or the like, while the outer absorber layer 116 may be or include germanium tin alloy or the like, and vice versa. In some embodiments, the atomic percent of tin atoms is less than about 1% or some other suitable percentage, as far as the inner absorber layer 114 is or comprises a germanium tin alloy and/or the outer absorber layer 116 is or comprises a germanium tin alloy. Germanium tin alloys have higher quantum efficiency compared to germanium because tin has a smaller bandgap than germanium.

In some embodiments, the internal absorber layer 114 and the semiconductor substrate 106 have a lattice mismatch of about 3% or more, about 4% or more, or about some other suitable percentage. For example, the inner absorber layer 114 and the semiconductor substrate 106 may have separate values of lattice constants, and the difference between the separate values may be about 4% or some other suitable percentage of the separate values. Further, in some embodiments, the peripheral absorber layer 116 and the semiconductor substrate 106 have a lattice mismatch of about 3% or more, about 4% or more, or about some other suitable percentage.

In some embodiments, the inner absorber layer 114 and the semiconductor substrate 106 have a difference in coefficient of thermal expansion of about 50% or more, about 55% or more, or about some other suitable percentage. Further, in some embodiments, the peripheral absorber layer 116 and the semiconductor substrate 106 have a difference in coefficient of thermal expansion of about 50% or more, about 55% or more, or about some other suitable percentage.

The inner absorber layer 114 is intrinsic (e.g., undoped) or is otherwise lightly doped with a smaller doping concentration than the outer absorber layer 116. In some embodiments, the inner absorbent layer 114 has a thickness of about 0-5e16 atoms/cc (atoms/cm) ³ ) About 0 to 2.5e16 atoms/cm ³ About 2.5e16-5e16 atoms/cm ³ Or some other suitable value of doping concentration. Further, in some embodiments, the peripheral absorbent layer 116 has about 5e16-5e19 atoms/cm ³ About 5e16-2.5e19 atoms/cm ³ About 2.5e19-5e19 atoms/cm ³ Or some other suitable value of doping concentration.

The bottom protrusion 114p of the inner absorber layer 114 has a width W that decreases toward the second avalanche well 112 _p . In some embodiments, width W _p About 0.5-2 microns, about 0.5-1.25 microns, about 1.25-2 microns, or some other suitable value. Further, in some embodiments, the bottom protrusion 114p and the second avalanche well 112 have the same width or substantially the same width at the interface where the bottom protrusion 114p and the second avalanche well 112 are in direct contact.

As described above, the peripheral absorber layer 116 is highly doped. For example, to the extent that the peripheral absorber layer 116 is p-type germanium or the like, the peripheral absorber layer 116 may be doped with boron or the like. Furthermore, the peripheral absorption layer 116 has tapered ends at the second avalanche well 112 and also at the top corners of the absorption structure 104. Accordingly, the thickness T of the peripheral absorbent layer 116 _pal Gradually decreasing to about zero at each tapered end. Further, the peripheral absorbent layer 116 has an inclined surface at each tapered end. The inclined surface at the second avalanche well 112 faces the bottom protrusion 114p, while the inclined surface at the top corner of the absorption structure 104 faces the cover layer 118 on top of the absorption structure 104.

In some embodiments, the thickness T of the peripheral absorbent layer 116 _pal About 0-500 nanometers, about 0-250 nanometers, about 250-500 nanometers, or some other suitable value. In some embodiments, thickness T _pal Is uniform or substantially uniform from the bottom corner of the absorbent structure 104 to each tapered end. Example(s)E.g. thickness T _pal May have a first uniform thickness value from the bottom corner of the absorbent structure 104 to the tapered end at the top corner of the absorbent structure 104. As another example, thickness T _pal May have a second uniform thickness value from the bottom corner of the absorbing structure 104 to the tapered end at the second avalanche well 112. The first uniform thickness value and/or the second uniform thickness value may be, for example, about 50-500 nanometers, about 50-275 nanometers, about 275-500 nanometers, or some other suitable value. Further, although shown as being different, in alternative embodiments, the first uniform thickness value and the second uniform thickness value may be the same.

The cover layer 118 covers the absorbing structure 104 to protect the absorbing structure 104 during manufacture of the photodetector 102. The cover layer 118 is semiconductive and is a different semiconductor material than the absorbent structure 104. In addition, the cap layer 118 is intrinsic or otherwise lightly doped. For example, the light doping may correspond to less than about 5e16 atoms/cm ³ Or some other suitable value of doping concentration.

In some embodiments, the cover layer 118 has a smaller absorption coefficient for the target radiation than the absorbing structure 104, and/or the cover layer 118 has a larger bandgap than the absorbing structure 104. In some embodiments, the cap layer 118 is or includes the same semiconductor material as the semiconductor substrate 106. In some embodiments, the capping layer 118 has the same absorption coefficient for the target radiation as the semiconductor substrate 106 and/or the capping layer 118 has the same band gap as the semiconductor substrate 106.

In some embodiments, thickness T of cover layer 118 _cap About 10-100 nanometers, about 10-55 nanometers, about 55-100 nanometers, or some other suitable value. In some embodiments, thickness T _cap Is uniform or substantially uniform.

In some embodiments, the absorber structure 104 is or includes germanium, germanium tin alloy, or the like, while the semiconductor substrate 106 and the cap layer 118 are or include silicon, or the like. Such an embodiment may occur, for example, when the photodetector 102 is directed at long wavelength radiation. As described above, the long wave radiation may, for example, include SWIR radiation or the like, and/or may, for example, be radiation having a wavelength greater than about 1310 nanometers or the like.

The vertical connecting well 120 is located in the semiconductor substrate 106 and has the same doping type as the first avalanche well 110. The vertical connecting well 120 extends from the first avalanche well 110 to the top of the semiconductor substrate 106 to provide an electrical coupling from the top of the semiconductor substrate 106 to the first avalanche well 110. Further, the vertical connection well 120 surrounds the absorbing structure 104 in a pair of sections, between which the absorbing structure 104 is arranged.

The first contact region 122 is located on top of the vertical connection well 120 in the semiconductor substrate 106 and the second contact region 124 is located in the capping layer 118 and the absorber structure 104. The first contact region 122 has the same doping type as the first avalanche well 110 and the vertical link well 120, but a higher doping concentration. Further, the first contact region 122 has a pair of sections located on opposite sides of the absorbent structure 104, respectively. The second contact region 124 has the same doping type as the second avalanche well 112 and the peripheral absorption layer 116, but a higher doping concentration. Thus, the second contact region 124 has a doping type opposite to that of the first contact region 122.

In some embodiments, the bulk of the semiconductor substrate 106 is intrinsic or lightly doped. The bulk of the semiconductor substrate 106 corresponds to the portion of the semiconductor substrate 106 surrounding the first avalanche well 110, the second avalanche well 112, the vertically connected well 120 and the first contact region 122. For example, the light doping may correspond to less than about 5e16 atoms/cm ³ Or some other suitable value of doping concentration. In some embodiments where the bulk of the semiconductor substrate 106 is lightly doped, the bulk has the same doping type as the second avalanche well 112.

An interconnect structure 126 (partially shown) overlies the photodetector 102 and is electrically coupled to the photodetector 102. Interconnect structure 126 includes a plurality of conductive features including contacts 128 and wires 130. The contacts 128 are located in an interlayer dielectric (ILD) layer 132, which ILD layer 132 separates the wires 130 from the photodetectors 102. Further, contacts 128 extend from wires 130 to first contact region 122 and second contact region 124, respectively.

During operation of the photodetector 102, one of the first contact region 122 and the second contact region 124 corresponds to an anode of the photodetector 102 and a cathode of the photodetector 102. For example, to the extent that the second contact region 124 is p-type, the second contact region 124 corresponds to an anode and the first contact region 122 corresponds to a cathode. In addition, the photodetector 102 is reverse biased through the interconnect structure 126. To the extent that photodetector 102 is an APD, for example, photodetector 102 can be reverse biased slightly below the reverse breakdown voltage. To the extent that the photodetector 102 is SPAD, for example, the photodetector 102 may be reverse biased above a reverse breakdown voltage. In some embodiments, the photodetector 102 is reverse biased at hundreds of volts, tens of volts, or some other suitable voltage. For example, the photodetector 102 may be reverse biased at about 0-20 volts, about 10-20 volts, or some other suitable voltage.

When the photodetector 102 is reverse biased, the photodetector 102 is exposed to target radiation (e.g., long wave radiation, SWIR radiation, etc.). Due to its high absorption coefficient, radiation is absorbed at the absorbing structure 104 with high quantum efficiency. Absorption causes photo-generated carriers to migrate to the avalanche region 108 and be accelerated at the avalanche region 108 by a high electric field across the photodetector 102. The photo-generated carriers migrate to the avalanche region 108 via the second avalanche well 112, whereby the second avalanche well 112 can also be regarded as a carrier channel or the like. For example, the second avalanche well 112 can be considered as an electron channel in terms of electron migration into the avalanche region 108. At the avalanche region 108, the photo-generated carriers are accelerated to kinetic energy that overcomes the ionization energy of the semiconductor substrate 106 and knocks out electrons from atoms of the semiconductor substrate 106. This causes an avalanche of current carriers that can be measured.

Referring to fig. 2A and 2B, top layouts 200A, 200B of various embodiments of the sensor device of fig. 1 are provided. For example, the cross-sectional view 100 of fig. 1 may be taken along line B in fig. 2A and 2B.

In fig. 2A, the vertically connected wells 120 extend in a closed path around the absorbing structure 104. Further, the first contact region 122 has a pair of discrete sections that are located on opposite sides of the absorbent structure 104 and overlap the vertical connecting well 120, respectively.

In fig. 2B, the vertical connecting well 120 has two discrete sections located on opposite sides of the absorbent structure 104, respectively. Furthermore, the first contact region 122 has two discrete sections, which are located on opposite sides of the absorbent structure 104, respectively, and overlap with the discrete sections of the vertical connection well 120, respectively.

In both fig. 2A and 2B, the second contact region 124 and the second avalanche well 112 (shown in phantom) overlap the inner absorber layer 114 at the center of the inner absorber layer 114. In addition, the peripheral absorbent layer 116 extends in a closed path around the inner absorbent layer 114.

Referring to fig. 3A-3C, doping profiles 300A-300C are provided for various different embodiments of the peripheral absorber layer 116. As described above, the peripheral absorption layer 116 is highly doped to suppress dark current along the interface between the peripheral absorption layer 116 and the semiconductor substrate 106. The thickness T of the peripheral absorption layer 116 is along the doping profile 300A-300C _pal Extends, and may be, for example, taken along line a in any of fig. 1, 2A, and 2B.

In fig. 3A, the doping concentration of the peripheral absorber layer 116 is uniform from the semiconductor substrate 106 to the inner absorber layer 114. A uniform doping profile may have better process control than a variable doping profile.

In fig. 3B, the doping concentration decreases continuously and linearly from the semiconductor substrate 106 to the internal absorption layer 114. Furthermore, the doping concentration decreases to a non-zero value at the inner absorber layer 114. For example, the doping concentration may be from about 5e19 atoms/cm ³ Reduced to about 5e16 atoms/cm at the inner absorber layer 114 ³ . However, other suitable values are also acceptable. In an alternative embodiment, the doping concentration is reduced to zero at the inner absorber layer 114. Furthermore, in alternative embodiments, the doping concentration decreases discretely and/or non-linearly from the semiconductor substrate 106 to the inner absorber layer 114. The reduced doping profile may be compared to a uniform doping profile (e.g., as in fig. 3A) in the absorber structure 104 and the semiconductor substrate 106The dark current is better reduced at the interface between and thus the quantum efficiency of the photodetector 102 can be better enhanced.

In fig. 3C, the doping concentration of the peripheral absorber layer 116 is uniform from the semiconductor substrate 106 to a midpoint M, which is midway between the semiconductor substrate 106 and the inner absorber layer 114. Furthermore, the doping concentration decreases continuously and linearly from the midpoint M to the inner absorber layer 114 and has a non-zero value at the inner absorber layer 114. In an alternative embodiment, the doping concentration is reduced to zero at the inner absorber layer 114. Furthermore, in alternative embodiments, the doping concentration decreases discretely and/or non-linearly from the midpoint M to the inner absorber layer 114.

Referring to fig. 4A-4E, cross-sectional views 400A-400E of various alternative embodiments of the sensor device of fig. 1 are provided in which the constituent parts of the photodetector 102 (e.g., the peripheral absorption layer 116) are varied.

In fig. 4A, the peripheral absorbent layer 116 has square ends at the top corners of the absorbent structure 104 instead of tapered ends as in fig. 1. Accordingly, the thickness T of the peripheral absorbent layer 116 _pal Is uniform at the square ends. Further, at each square end, the peripheral absorber layer 116 has a surface facing the cap layer 118 and extending parallel to the top surface of the semiconductor substrate 106. The square end reduces dark current at the top corner better than the tapered end at the top corner.

In fig. 4B, the peripheral absorption layer 116 has a square end at the second avalanche well 112 instead of a tapered end as in fig. 1. Accordingly, the thickness T of the peripheral absorbent layer 116 _pal Is uniform at the square end and the width Wp of the bottom protrusion 114p is uniform. Further, at each square end, the peripheral absorption layer 116 has a surface facing the bottom protrusion 114p and extending perpendicular to the top surface of the semiconductor substrate 106. The square end reduces dark current at the second avalanche well 112 better than the tapered end at the second avalanche well 112.

In fig. 4C, the peripheral absorber layer 116 has square ends at the top corners of the absorber structure 104 and at the second avalanche well 112 instead of tapered ends as in fig. 1. The square end at the top corner of the absorbing structure 104 is as in fig. 4A, while the square end at the second avalanche well 112 is as in fig. 4B. The square end shows a better reduction of dark current than the tapered end.

In fig. 4D, the bottom protrusion 114p is separated from the second avalanche well 112 by the body of the semiconductor substrate 106. As described above, the bulk of the semiconductor substrate 106 may be intrinsic or otherwise lightly doped.

In fig. 4E, the vertical connecting well 120 and the first contact region 122 are positioned on a single side of the absorbing structure 104.

Although fig. 2A and 2B are described with respect to the sensor device in fig. 1, fig. 2A and 2B are also applicable to the sensor device in fig. 4A to 4D. Thus, the sensor device in any of fig. 4A to 4D may have the same top layout as in any of fig. 2A and 2B. Although fig. 3A to 3C are described with respect to the sensor device in fig. 1, fig. 3A to 3C are also applicable to the sensor device in fig. 4A to 4E. Thus, the peripheral absorber layer 116 in any of fig. 4A-4E may have the same doping profile as in any of fig. 3A-3C.

Referring to fig. 5, a cross-sectional view 500 of some embodiments of the sensor device of fig. 1 is provided, wherein the sensor device includes a plurality of Integrated Circuit (IC) chips. The plurality of IC chips includes a first IC chip 502a and a second IC chip 502b located below the first IC chip 502a and bonded to the first IC chip 502 a. The first IC chip 502a houses the photodetector 102, while the second IC chip 502b houses the logic device 504.

The photodetector 102 is located on the front side of the first semiconductor substrate 106, surrounded by a first trench isolation structure 506. Furthermore, the photodetector 102 is as in fig. 1, but may alternatively be as in any one or any combination of fig. 2A, 2B, 3A-3C, and 4A-4E. The first trench isolation structure 506 extends through the first semiconductor substrate 106 and has a pair of trench sections between which the photodetector 102 is disposed. The first trench isolation structure 506 provides electrical and optical isolation between the photodetector 102 and adjacent structures (e.g., other photodetectors).

In some embodiments, the first semiconductor substrate 106 has a thickness of about 3 microns, about 2.5-3.5 microns, about 2.5-3 microns, or about 3-3.5 microns. However, other suitable values are also possible.

On the backside of the first semiconductor substrate 106, a conductive layer 508 is disposed on the first semiconductor substrate 106. The conductive layer 508 has an isolation section that extends through the first semiconductor substrate 106 to partially form the first trench isolation structure 506. The isolation section is spaced apart from the first semiconductor substrate 106 and accommodates a void 510, which void 510 may also be referred to as an air gap or the like. In an alternative embodiment, void 510 is omitted. The conductive layer 508 also has a ground region 508g that extends to the first semiconductor substrate 106. The ground region 508g may be used for grounding or otherwise biasing the body of the first semiconductor substrate 106.

In some embodiments, the thickness of conductive layer 508 is about 0-5 kiloangstroms, about 0-2.5 kiloangstroms, about 2.5-5 kiloangstroms, or some other suitable value. In some embodiments, conductive layer 508 is or includes tungsten, some other suitable metal and/or conductive material, or any combination of the preceding.

A plurality of backside dielectric layers and conductive layers 508 are stacked on the backside of the first semiconductor substrate 106. The plurality of backside dielectric layers includes a first backside dielectric layer 512a, a second backside dielectric layer 512b, and a third backside dielectric layer 512c under the conductive layer 508. The first and third backside dielectric layers 512a and 512c line the conductive layer at the first trench isolation structure 506 to partially form the first trench isolation structure 506, and the second backside dielectric layer 512b separates the first and third backside dielectric layers 512a and 512c outside the first trench isolation structure 506. The plurality of backside dielectric layers further includes a fourth backside dielectric layer 512d and a fifth backside dielectric layer 512e that overlie the conductive layer 508.

In some embodiments, the first and second backside dielectric layers 512a and 512b are or comprise high-k dielectrics, and the third, fourth and fifth backside dielectric layers 512c, 512d and 512e are or comprise silicon oxide or the like. The high-k dielectric may be or include, for example, hafnium oxide (e.g., hfO ₂ ) Tantalum oxide (e.g. Ta ₂ O ₅ ) Etc.

In some embodiments, the thickness of the fourth backside dielectric layer 512d is about 3.7-5.7 kiloangstroms, about 3.7-4.7 kiloangstroms, about 4.7-5.7 kiloangstroms, or some other suitable value. In some embodiments, the thickness of fifth backside dielectric layer 512e is about 1.5-2.5 kiloangstroms, about 1.5-2 kiloangstroms, about 2-2.5 kiloangstroms, or some other suitable value. The third backside dielectric layer 512c has a different thickness directly above the photodetector 102 and at the ground region 508g of the conductive layer 508. In some embodiments, the thickness of the third backside dielectric layer 512c directly over the photodetector 102 is about 0.5-1.5 kiloangstroms, about 0.5-1.0 kiloangstroms, about 1.0-1.5 kiloangstroms, or some other suitable value. In some embodiments, the thickness of the third backside dielectric layer 512c at the ground region 508g is about 2-3 kiloangstroms, about 2-2.5 kiloangstroms, about 2.5-3 kiloangstroms, or some other suitable value.

On top of the plurality of backside dielectric layers, microlenses 514 are disposed directly above the photodetectors 102. The microlenses 514 are configured to focus radiation on the photodetector 102 to enhance quantum efficiency. In an alternative embodiment, color filters (not shown) are interposed in the plurality of backside dielectric layers between the microlenses 514 and the photodetectors 102 to selectively pass the target radiation. For example, the color filter may pass long wave radiation while blocking other wavelengths of radiation.

Logic devices 504 are located on the front side of second semiconductor substrate 516 and are separated from each other by second trench isolation structures 518. The second trench isolation structure 518 is or includes a dielectric material and may be, for example, a Shallow Trench Isolation (STI) structure or the like. For example, logic device 504 may be or include a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a fin field effect transistor (FinFET), a full-gate field effect transistor (GAA FET), a nanoflake field effect transistor, or the like, or any combination of the preceding.

Logic device 504 includes a separate gate electrode 520, a separate gate dielectric layer 522, a separate sidewall spacer 524, and a separate pair of source/drain regions 526. The gate electrodes 520 are stacked with gate dielectric layers 522, respectively, the gate dielectric layers 522 separating the gate electrodes 520 from the second semiconductor substrate 516. Sidewall spacers 524 are located on the sidewalls of gate electrode 520 and the sidewalls of gate dielectric layer 522, respectively. The sidewall spacers 524 are dielectric and may be or comprise, for example, silicon nitride or the like, or any combination of the foregoing. Pairs of source/drain regions 526 are located in the second semiconductor substrate 516, and the gate electrodes 520 are each located between the source/drain regions of a corresponding pair of source/drain regions 526.

With continued reference to the sensor device of fig. 5, the first and second IC chips 502a and 502b include first and second interconnect structures 126 and 528, respectively. The first interconnect structure 126 and the second interconnect structure 528 are located between the first semiconductor substrate 106 and the second semiconductor substrate 516. The first interconnect structure 126 is located on the front side of the first semiconductor substrate 106 and is electrically coupled to the photodetector 102. The second interconnect structure 528 is located on the front side of the second semiconductor substrate 516 and is electrically coupled to the logic device 504.

The first interconnect structure 126 and the second interconnect structure 528 each include a level contact 128, a multilevel conductive line 130, and a multilevel via 530. The contacts 128 of the first IC chip 502a extend from the photodetector 102, while the contacts 128 of the second IC chip 502b extend from the logic device 504. In addition, contacts 128 are located in respective ILD layer 132 and Contact Etch Stop Layer (CESL) 532. The wires 130 and vias 530 are alternately stacked from the corresponding contacts 128 to the bonding structures 534 between the first and second interconnect structures 126 and 528. In addition, the conductive lines 130 and vias 530 are located in corresponding interconnect dielectric layers 536.

The bonding structure 534 facilitates bonding the first and second IC chips 502a, 502b together by a combination of metal-to-metal bonding and dielectric-to-dielectric bonding. The bonding structure 534 includes a bonding dielectric layer 538, the bonding dielectric layer 538 being independent of the first and second IC chips 502a and 502b and being in direct contact at a bonding interface. In addition, the bonding structure 534 includes a bonding pad 540, the bonding pad 540 being independent of the first and second IC chips 502a, 502b and being in direct contact at the bonding interface. Bond pads 540 are inserted into the bond dielectric layers 538, respectively, and are electrically coupled to the first interconnect structure 126 and the second interconnect structure 528, respectively, through bond vias 542 in the bond dielectric layers 538, respectively.

Referring to fig. 6A and 6B, cross-sectional views 600A, 600B of various alternative embodiments of the sensor device of fig. 5 are provided.

In fig. 6A, the void 510 at the first trench isolation structure 506 is omitted. In alternative embodiments, the photodetector 102 is as in any one or any combination of fig. 2A, 2B, 3A-3C, and 4A-4E.

In fig. 6B, the sensor device includes a plurality of photodetectors 102, each of which has its counterpart shown and described in fig. 5. In alternative embodiments, void 510 is omitted as in fig. 6A, and/or photodetector 102 is as in any one or any combination of fig. 2A, 2B, 3A-3C, and 4A-4E.

Referring to fig. 7, a top layout 700 of some embodiments of the sensor device of fig. 6B is provided. For example, the cross-sectional view 600B of fig. 6B may be taken along line C. The sensor device includes a plurality of photodetectors 102 arranged in a plurality of rows R1-R6 and a plurality of columns C1-C6. Although six rows and six columns are shown, more or fewer rows and/or more or fewer columns are acceptable. The photodetector 102 may be as in any one or combination of fig. 1, 2A, 2B, 3A-3C, and 4A-4E, alone.

The first trench isolation structure 506 has a grid-like layout that individually surrounds the photodetectors 102 to separate the photodetectors 102. In addition, the first trench isolation structure 506 has a void 510 (shown in phantom). In alternative embodiments, the first trench isolation structure 506 has alternative layouts, and/or the void 510 is omitted.

Referring to fig. 8-26, a series of cross-sectional views 800-2600 of some embodiments of methods of forming a sensor device including a photodetector according to aspects of the present disclosure are provided. For example, the sensor device may correspond to the sensor device of fig. 1 or some other suitable sensor device.

As shown in cross-sectional view 800 of fig. 8, a first sacrificial layer 802 is deposited on a base substrate 804. The first sacrificial layer 802 is dielectric and may be or include, for example, silicon oxide and/or some other suitable dielectric material. Furthermore, first sacrificial layer 802 may be deposited, for example, by thermal oxidation, vapor deposition, some other suitable deposition process, or any combination of the preceding.

The base substrate 804 is semiconductive and may be, for example, a bulk silicon substrate or some other suitable type of substrate. In addition, the base substrate 804 is intrinsic or lightly doped. For example, the light doping may correspond to less than about 5e16 atoms/cm ³ Or some other suitable value of doping concentration.

As shown in the cross-sectional view 900 of fig. 9, the base substrate 804 is selectively doped by the first sacrificial layer 802 to form a first avalanche well 110 in the base substrate 804 along the top of the base substrate 804. In some embodiments, performing the selectively doping process includes: 1) Forming a first mask 902 over the first sacrificial layer 802 using photolithography; 2) With the first mask 902 in place, ion implantation 904 is performed on the base substrate 804; and 3) removing the first mask 902. In alternative embodiments, the selective doping is performed by some other suitable process. For example, the first mask 902 may be or include photoresist or some suitable material.

As shown in the cross-sectional view 1000 of fig. 10, the first sacrificial layer 802 is removed, thereby exposing the base substrate 804. The removal may be performed, for example, by an etching process and/or some other suitable type of removal process.

As shown in cross-sectional view 1100 of fig. 11, a semiconductor layer 1102 is epitaxially deposited on a base substrate 804. The base substrate 804 and the semiconductor layer 1102 together form the semiconductor substrate 106. The semiconductor layer 1102 may be or include, for example, silicon and/or some other suitable material. In some embodiments, the semiconductor layer 1102 is the same material as the base substrate 804. For example, both the semiconductor layer 1102 and the base substrate 804 may be silicon. In addition, the semiconductor layer 1102 is intrinsic or lightly doped. For example, the light doping may correspond to less than about 5e16 atoms/cm ³ Or some other suitable value of doping concentration.

As shown in the cross-sectional view 1200 of fig. 12, a second sacrificial layer 1202 is deposited over the semiconductor substrate 106. The second sacrificial layer 1202 is dielectric and may be or include, for example, silicon oxide and/or some other suitable dielectric material. Further, the second sacrificial layer 1202 may be deposited, for example, by thermal oxidation, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), some other suitable deposition process, or any combination of the preceding.

As shown in the cross-sectional view 1300 of fig. 13, the semiconductor substrate 106 is selectively doped by a second sacrificial layer 1202 to form the vertical connection well 120 and the first contact region 122. The vertically connected well 120 has a pair of sections located on opposite ends of the first avalanche well 110, respectively, and each section extends from the first avalanche well 110 to the top of the semiconductor substrate 106. The first contact region 122 has a pair of sections respectively located above the sections of the vertical connecting well 120. The vertical connecting well 120 and the first contact region 122 have the same doping type as the first avalanche well 110, but the first contact region 122 has a higher doping concentration than the vertical connecting well 120 and the first avalanche well 110.

In some embodiments, the vertically connected well 120 and the first contact region 122 have a top geometry as in fig. 2A. In other embodiments, the vertical connection well 120 and the first contact region 122 have a top geometry as in fig. 2B. In still other embodiments, the vertical connection well 120 has some other suitable top geometry, and/or the first contact region 122 has some other suitable top geometry.

In some embodiments, performing the selectively doping process includes: 1) Forming a second mask 1302 on the second sacrificial layer 1202 using photolithography; 2) With the second mask 1302 in place, performing ion implantation 1304 on the semiconductor substrate 106; and 3) removing the second mask 1302. In alternative embodiments, the selective doping is performed by some other suitable process. For example, the second mask 1302 may be or include photoresist or some suitable material.

As shown in the cross-sectional view 1400 of fig. 14, the second sacrificial layer 1202 is removed, thereby exposing the semiconductor substrate 106. The removal may be performed, for example, by an etching process and/or some other suitable type of removal process.

As shown in cross-section 1500 of fig. 15, a hard mask layer 1502 is deposited over the semiconductor substrate 106. The hard mask layer 1502 is dielectric and may be or include, for example, silicon oxide and/or some other suitable dielectric material. Furthermore, the hard mask layer 1502 may be deposited, for example, by thermal oxidation, CVD, PVD, some other suitable deposition process, or any combination of the preceding.

As shown in cross-sectional view 1600 of fig. 16, hard mask layer 1502 and semiconductor substrate 106 are selectively etched to form trenches 1602. The trench 1602 is formed at a region surrounded by the vertical connection well 120 and the first contact region 122. For example, trenches 1602 are located between sections of vertical connecting well 120, sections of vertical connecting well 120 being located on opposite ends of first avalanche well 110. Further, a trench 1602 is formed above the first avalanche well 110 and is spaced apart from the first avalanche well 110.

In some embodiments, performing the selectively etching process includes: 1) Forming a third mask 1604 on the hard mask layer 1502 using photolithography; 2) With the third mask 1604 in place, etching 1606 is performed on the hard mask layer 1502 and the semiconductor substrate 106; and 3) removing the third mask 1604. In alternative embodiments, the selective etching is performed by some other suitable process. For example, the third mask 1604 may be or include photoresist or some suitable material.

As shown in cross-section 1700 of fig. 17, a third sacrificial layer 1702 is deposited to line the trench 1602. The third sacrificial layer 1702 is dielectric and may be or include, for example, silicon oxide and/or some other suitable dielectric material. Further, third sacrificial layer 1702 may be deposited, for example, by thermal oxidation, CVD, PVD, some other suitable deposition process, or any combination of the preceding.

As shown in cross-sectional view 1800 of fig. 18, semiconductor substrate 106 is selectively doped by third sacrificial layer 1702 and trench 1602 to form second avalanche well 112. The second avalanche well 112 is disposed above the first avalanche well 110 and directly above the first avalanche well 110. In addition, a second avalancheWell 112 has an opposite doping type as first avalanche well 110. For example, the second avalanche well 112 may be p-type, while the first avalanche well may be n-type, and vice versa. Accordingly, the first avalanche well 110 and the second avalanche well 112 form a PN junction. Width W of the second avalanche well 112 _saw Less than the width of the grooves 1602, and may be, for example, about 0.5-2 microns, about 0.5-1.25 microns, about 1.25-2 microns, or some other suitable value.

The first avalanche well 110 and the second avalanche well 112 together form the avalanche region 108. Avalanche region 108 corresponds to a region where photo-generated carriers from subsequently formed absorbing structures are multiplied by the avalanche effect. Therefore, the avalanche region 108 may also be referred to as a multiplication region or the like.

In some embodiments, performing the selectively doping process includes: 1) Forming a fourth mask 1802 on the third sacrificial layer 1702 using photolithography; 2) With the fourth mask 1802 in place, performing ion implantation 1804 on the semiconductor substrate 106; and 3) removing the fourth mask 1802. In alternative embodiments, the selective doping is performed by some other suitable process. For example, the fourth mask 1802 may be or include a photoresist or some suitable material.

As shown in the cross-sectional view 1900 of fig. 19, the third sacrificial layer 1702 is selectively etched to clear the third sacrificial layer 1702 from the trench 1602, except at the second avalanche well 112. As a result, the sidewalls of the semiconductor substrate 106 in the trench 1602 are removed from the third sacrificial layer 1702. In addition, the recessed surface of semiconductor substrate 106 in trench 1602 is partially cleared of third sacrificial layer 1702 at a location laterally offset from second avalanche well 112.

In some embodiments, performing the selectively etching process includes: 1) Forming a fifth mask 1902 over the third sacrificial layer 1702 using photolithography; 2) With fifth mask 1902 in place, an etch 1904 is performed on third sacrificial layer 1702; and 3) removing the fifth mask 1902. In alternative embodiments, the selective etching is performed by some other suitable process. For example, fifth mask 1902 may be or include a photoresist or some suitable material.

With the third sacrificial layer 1702 in place, the peripheral absorber layer 116 is epitaxially grown, as shown in cross-section 2000 of fig. 20. The peripheral absorber layer 116 is preferentially grown on the semiconductor surface rather than the dielectric surface. Thus, peripheral absorber layer 116 is grown on the sidewalls of semiconductor substrate 106 in trench 1602. Further, peripheral absorber layer 116 is grown on the recessed surface of semiconductor substrate 106 in trench 1602 except at second avalanche well 112 masked by third sacrificial layer 1702.

Because the peripheral absorber layer 116 is preferentially grown on the semiconductor surface, the peripheral absorber layer 116 is deposited by a self-aligned process. In addition, because the peripheral absorption layer 116 is not grown at the second avalanche well 112, the peripheral absorption layer 116 has an opening 2002 above the peripheral absorption layer 116. In some embodiments, the width W of the opening 2002 _op About 0.5-2 microns, about 0.5-1.25 microns, about 1.25-2 microns, or some other suitable value.

The peripheral absorption layer 116 is further grown with tapered ends at the second avalanche well 112 and also at the top of the semiconductor substrate 106. Accordingly, the peripheral absorbent layer 116 has an inclined surface at each tapered end, and also has a thickness T _pal Thickness T _pal Gradually decreasing to about zero at each tapered end. In some embodiments, between the tapered ends, a thickness T _pal About 50-500 nanometers, about 50-275 nanometers, about 275-500 nanometers, or some other suitable value.

The peripheral absorber layer 116 is semiconductive and has a different semiconductor material than the semiconductor substrate 106. Furthermore, the peripheral absorber layer 116 has a higher absorption coefficient for the target radiation than the semiconductor substrate 106, and in some embodiments, the peripheral absorber layer 116 has a smaller bandgap than the semiconductor substrate 106. When the target radiation is long wave radiation, the peripheral absorption layer 116 may be or include germanium, germanium tin alloy (e.g., geSn), or the like, for example, and the semiconductor substrate 106 may be or include silicon, or the like, for example. Germanium tin alloys have higher quantum efficiency than germanium because tin has a smaller bandgap than germanium. The long wave radiation may, for example, be or include radiation having a wavelength greater than about 1310 nanometers or some other suitable value.

The peripheral absorption layer 116 is doped with a dopant having the same doping type as the second avalanche well 112 and having a doping type opposite to that of the first avalanche well 110. For example, as far as the second avalanche well 112 has p-type doping, the peripheral absorption layer 116 may also have p-type doping. In some embodiments where peripheral absorber layer 116 has p-type doping and is or includes germanium, the dopant may be or include boron or some other suitable dopant. In some embodiments, the peripheral absorber layer 116 has a high doping concentration of about 5e16-5e19 atoms/cm ³ About 5e16-2.5e19 atoms/cm ³ About 2.5e19-5e19 atoms/cm ³ Or some other suitable value, and/or the high doping concentration is greater than about 5e16-5e19 atoms/cm ³ About 5e16-2.5e19 atoms/cm ³ About 2.5e19-5e19 atoms/cm ³ Or some other suitable value. In some embodiments, the peripheral absorber layer 116 has a doping profile as in any of fig. 3A-3C. For example, the doping profile may correspond to line a in fig. 20.

For example, the peripheral absorber layer 116 may be epitaxially grown by Molecular Beam Epitaxy (MBE), CVD, or some other suitable process. In some embodiments where peripheral absorber layer 116 is or includes p-type germanium, the process is performed by CVD at 1) germane (e.g., geH ₄ ) And diborane (e.g., B ₂ H ₄ ) A precursor; 2) A temperature of about 350-700 degrees celsius; and 3) performing epitaxial growth at a pressure of about 5-50 Torr. In such embodiments, the ratio of germane to diborane may be adjusted to control the doping profile. For example, increasing the flow rate of diborane may increase the doping concentration. In some embodiments where peripheral absorber layer 116 is or includes a germanium tin alloy, in addition to additional tin chloride (e.g., snCl ₄ ) The epitaxial growth is performed by a CVD process as described above, except for the precursor. In such embodiments, the ratio of precursors may be adjusted to limit the atomic percent of tin to less than 1% or some other suitable value. For example, reducing the flow rate of tin chloride may reduce the atomic percent. Although the CVD process describes specific precursors, temperatures, and pressures, in alternative embodiments, other suitableThe precursor, temperature and pressure of (a) are possible.

As shown in cross-sectional view 2100 of fig. 21, third sacrificial layer 1702 is removed, thereby exposing hard mask layer 1502 and second avalanche well 112. The removal may be performed, for example, by an etching process and/or some other suitable type of removal process.

As shown in cross-sectional view 2200 of fig. 22, inner absorber layer 114 is epitaxially grown to fill the remainder of trench 1602. The inner absorber layer 114 preferentially grows on the semiconductor surface rather than on the dielectric surface. Thus, the inner absorber layer 114 grows from the outer absorber layer 116 and the second avalanche well 112, but does not grow from the hard mask layer 1502.

The inner absorber layer 114 is semiconductive and has a different semiconductor material than the semiconductor substrate 106. Furthermore, the inner absorber layer 114 has a higher absorption coefficient for the target radiation than the semiconductor substrate 106, and in some embodiments, the inner absorber layer 114 has a smaller bandgap than the semiconductor substrate 106. When the target radiation is long wave radiation, the internal absorption layer 114 may be or comprise germanium, a germanium tin alloy (e.g., geSn), etc., for example, and the semiconductor substrate 106 may be or comprise silicon, etc., for example.

In some embodiments, the inner absorber layer 114 and the outer absorber layer 116 are or comprise the same semiconductor material in addition to doping. For example, the inner absorber layer 114 and the outer absorber layer 116 may be or include germanium, germanium tin alloys, and the like. In other embodiments, the inner absorber layer 114 and the outer absorber layer 116 are or include different semiconductor materials in addition to doping. For example, the inner absorber layer 114 may be or include germanium or the like, while the outer absorber layer 116 may be or include germanium tin alloy or the like, and vice versa.

The inner absorber layer 114 is intrinsic (e.g., undoped) or otherwise lightly doped. The light doping is a doping concentration less than that of the peripheral absorber layer 116, and may be, for example, about 0-5e16 atoms/cm ³ About 0 to 2.5e16 atoms/cm ³ About 2.5e16-5e16 atoms/cm ³ Or some other suitable value.

For example, it may be by MBE, CVD, or some otherAn appropriate process is used to epitaxially grow the inner absorber layer 114. In some embodiments where the inner absorber layer 114 is or includes germanium, the inner absorber layer is formed by a CVD process on 1) germane (e.g., geH ₄ ) A precursor; 2) A temperature of about 350-700 degrees celsius; and 3) performing epitaxial growth at a pressure of about 5-50 Torr. In some embodiments in which the inner absorber layer 114 is or includes a germanium tin alloy, in addition to additional tin chloride (e.g., snCl ₄ ) The epitaxial growth is performed by a CVD process as described above, except for the precursor. In such embodiments, the ratio of precursors may be adjusted to limit the atomic percent of tin to less than 1% or some other suitable value. While the CVD process describes specific precursors, temperatures, and pressures, in alternative embodiments, other suitable precursors, temperatures, and pressures are possible.

The inner absorber layer 114 and the peripheral absorber layer 116 together form the absorber structure 104, the absorber structure 104 having a higher absorption coefficient for the target radiation than the semiconductor substrate 106. The higher absorption coefficient may be, for example, due to the absorption structure 104 having a smaller bandgap than the semiconductor substrate 106. The absorbing structure 104 and the avalanche region 108 together form a photodetector 102, and the photodetector 102 may be, for example, a SPAD, an Avalanche Photodiode (APD), or the like. During use of the photodetector 102, the absorption structure 104 enhances absorption of radiation and generation of photo-generated carriers due to the higher absorption coefficient. In addition, the avalanche region 108 multiplies photo-generated carriers.

Because the absorber structure 104 is a different semiconductor material than the semiconductor substrate 106, lattice mismatch, etc. causes dark current at the interface between the absorber structure 104 and the semiconductor substrate 106. This may be exacerbated by the small band gaps of the inner absorber layer 114 and the outer absorber layer 116 relative to the band gap of the semiconductor substrate 106. However, because the peripheral absorber layer 116 is highly doped, it is rich in carriers and passivates interface states and crystal defects to suppress dark current. For example, to the extent that peripheral absorber layer 116 has a p-type doping, peripheral absorber layer 116 may be hole-rich and may passivate interface states and defects to suppress dark current from electrons.

As shown in the cross-sectional view 2300 of fig. 23, planarization is performed on the top of the inner absorber layer 114 to planarize the top of the inner absorber layer 114. Planarization may be performed, for example, by Chemical Mechanical Polishing (CMP) or some other suitable planarization process.

As shown in cross-sectional view 2400 of fig. 24, a capping layer 118 is epitaxially grown on top of the absorber structure 104. The capping layer 118 is preferentially grown over the semiconductor surface rather than the dielectric surface. Thus, the capping layer 118 grows from the absorber structure 104, but not from the hard mask layer 1502. The cap layer 118 may be epitaxially grown, for example, by MBE, CVD, or some other suitable process.

In some embodiments, thickness T of cover layer 118 _cap Is about 10-100 nanometers, about 10-55 nanometers, about 55-100 nanometers, or some other suitable value. In some embodiments, thickness T _cap Is uniform or substantially uniform.

The cover layer 118 is semiconductive and has a semiconductor material that is different from the inner absorber layer 114 and a semiconductor material that is different from the outer absorber layer 116. Furthermore, the cover layer 118 has a lower absorption coefficient for the target radiation than the inner and outer absorption layers 114, 116, and in some embodiments, the cover layer 118 has a larger band gap than the inner and outer absorption layers 114, 116. The capping layer 118 may be or include, for example, silicon or the like, and the inner absorber layer 114 and the outer absorber layer 116 may be or include germanium, germanium tin alloy, or the like. In some embodiments, cap layer 118 and semiconductor substrate 106 are or comprise the same semiconductor material, except for doping. For example, the capping layer 118 and the semiconductor substrate 106 may be or include silicon or the like.

The cap layer 118 is intrinsic (e.g., undoped) or otherwise lightly doped. The light doping may be, for example, about 0-5e16 atoms/cm ³ About 0 to 2.5e16 atoms/cm ³ About 2.5e16-5e16 atoms/cm ³ Or some other suitable value of doping concentration.

As shown in cross-section 2500 of fig. 25, cap layer 118 and inner absorber layer 114 are selectively doped to form a second contact region 124 overlying second avalanche well 112. The second contact region 124 has the same doping type as the second avalanche well 112 and the peripheral absorption layer 116.

In some embodiments, performing the selectively doping process includes: 1) Forming a sixth mask 2502 over the hard mask layer 1502 and the cap layer 118 using photolithography; 2) With the sixth mask 2502 in place, ion implantation 2504 is performed on the cap layer 118 and the inner absorber layer 114; and 3) removing the sixth mask 2502. In alternative embodiments, the selective doping is performed by some other suitable process. For example, sixth mask 2502 may be or include photoresist or some suitable material.

As shown in cross-section 2600 of fig. 26, the hard mask layer 1502 is removed. The removal may be performed, for example, by an etching process and/or some other suitable type of removal process.

As also shown in cross-section 2600 of fig. 26, an interconnect structure 126 (partially shown) is formed to cover photodetector 102 and electrically coupled to photodetector 102. Interconnect structure 126 includes a plurality of conductive features including contacts 128 and wires 130. Contacts 128 are located in ILD layer 132, which ILD layer 132 separates wires 130 from photodetectors 102. Further, contacts 128 extend from wires 130 to first contact region 122 and second contact region 124, respectively.

During operation of the photodetector 102, one of the first contact region 122 and the second contact region 124 corresponds to an anode of the photodetector 102 and a cathode of the photodetector 102. Further, during operation of the photodetector 102, the photodetector 102 is reverse biased through the interconnect structure 126. To the extent that photodetector 102 is an APD, for example, photodetector 102 can be reverse biased slightly below the reverse breakdown voltage. To the extent that the photodetector 102 is SPAD, for example, the photodetector 102 may be reverse biased above a reverse breakdown voltage.

When the photodetector 102 is reverse biased, the photodetector 102 is exposed to target radiation (e.g., long wave radiation, SWIR radiation, etc.). Due to its high absorption coefficient, radiation is absorbed at the absorbing structure 104 with high quantum efficiency. Absorption causes photo-generated carriers to migrate to the avalanche region 108 and be accelerated at the avalanche region 108 by a high electric field across the photodetector 102. The photo-generated carriers are accelerated to kinetic energy that overcomes the ionization energy of the semiconductor substrate 106 and knocks electrons out of atoms of the semiconductor substrate 106. This causes an avalanche of current carriers that can be measured.

As described above, because the peripheral absorber layer 116 is highly doped, it passivates interface states and crystal defects to suppress dark current at the interface between the semiconductor substrate 106 and the absorber structure 104. Further, as described above, the peripheral absorption layer 116 may be formed by a self-aligned epitaxial growth process of simultaneously growing and doping the peripheral absorption layer 116 on the silicon substrate. This allows the photodetector 102 to be formed with reduced complexity compared to other similar photodetectors. For example, the photodetector 102 may be formed without a guard ring in the absorbing structure 104, thereby eliminating the photolithography process and the ion implantation process. As another example, the peripheral absorption layer 116 may be formed without ion implantation, and thus the peripheral absorption layer 116 may be formed without damaging the semiconductor substrate 106. Thus, the heat treatment and ion implantation for repairing the damage can be omitted.

Although fig. 8 to 26 are described with reference to a method, it will be understood that the structures shown in these figures are not limited to the method, but may be independent of the method. While fig. 8-26 are described as a series of acts, it will be appreciated that the order of the acts may be varied in other embodiments. While fig. 8-26 are illustrated and described as a particular set of acts, some acts illustrated and/or described may be omitted in other embodiments. Moreover, acts not shown and/or described may be included in other embodiments.

Referring to fig. 27, a block diagram 2700 of some embodiments of the methods of fig. 8-26 is provided.

At 2702, a first avalanche well buried in the semiconductor substrate and having a first doping type is formed. See, for example, fig. 8-11.

At 2704, the semiconductor substrate is doped to form a vertical connection region and a first contact region in the semiconductor substrate, wherein the vertical connection region and the first contact region each have a first doping type and a pair of regions respectively located on opposite sides of the first avalanche well. See, for example, fig. 12-14.

At 2706, the semiconductor substrate is etched to form a trench between the regions of the vertical connection region over the first avalanche well. See, for example, fig. 15 and 16.

At 2708, the semiconductor substrate is doped by the trench to form a second avalanche well having a second doping type opposite the first doping and located between the first avalanche well and the trench. See, for example, fig. 17 and 18.

At 2710, a peripheral absorber layer is epitaxially grown on the exposed surface of the semiconductor substrate in the trench, wherein the peripheral absorber layer has a second doping type and a higher absorption coefficient than the semiconductor substrate. See, for example, fig. 19-21.

At 2712, an inner absorber layer is epitaxially grown to fill the remainder of the trench, wherein the inner absorber layer has a smaller doping concentration than the peripheral absorber layer and also has a higher absorption coefficient than the semiconductor substrate. See, for example, fig. 22.

At 2714, the top of the inner absorbent layer is flattened. See, for example, fig. 23.

At 2716, a capping layer is epitaxially grown on top of the inner and outer absorber layers, wherein the capping layer has a lower absorption coefficient than the inner and outer absorber layers. See, for example, fig. 24.

At 2718, the capping layer and the internal absorber layer are doped to form a second contact region having a second doping type. See, for example, fig. 25.

At 2720, an interconnect structure is formed overlying and electrically coupled to the first contact region and the second contact region. See, for example, fig. 26.

While the block diagram 2700 of fig. 27 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more acts illustrated herein may occur in one or more separate acts and/or phases.

Referring to fig. 28-32, a series of cross-sectional views 2800-3200 of some alternative embodiments of the methods of fig. 8-26 are provided, wherein at the top of the semiconductor substrate 106, the peripheral absorber layer 116 has square ends instead of tapered ends. For example, the sensor device may correspond to the sensor device of fig. 4A or some other suitable sensor device.

As shown in cross-section 2800 of fig. 28, the actions described with respect to fig. 8-19 are performed. For example, these actions form first avalanche well 110, second avalanche well 112, vertical link well 120, first contact region 122, trench 1602, hard mask layer 1502, and third sacrificial layer 1702.

As also shown in cross-sectional view 2800 of fig. 28, the actions described with respect to fig. 20 are performed to epitaxially grow peripheral absorber layer 116 in trench 1602. Unlike fig. 20, however, epitaxial growth continues until peripheral absorber layer 116 grows out of trench 1602.

As shown in the cross-sectional view 2900 of fig. 29, the actions described with respect to fig. 21 are performed to remove the third sacrificial layer 1702.

As shown in cross-sectional view 3000 of fig. 30, the actions described with respect to fig. 22 are performed to epitaxially grow inner absorber layer 114 to fill the remainder of trench 1602.

As shown in the cross-sectional view 3100 of fig. 31, the actions described with respect to fig. 23 are performed to planarize the top of the inner absorber layer 114 and flatten the top of the inner absorber layer 114. Because peripheral absorber layer 116 is epitaxially grown to extend out of trench 1602, the planarization extends further into inner absorber layer 114 and squares the ends of peripheral absorber layer 116 at the top of peripheral absorber layer 116. The square end reduces dark current at the top of the peripheral absorber layer 116 better than the tapered end.

As shown in cross-section 3200 of fig. 32, the actions described with respect to fig. 24-26 are performed. For example, these actions form the cap layer 118, the second contact region 124, and the interconnect structure 126, and further remove the hard mask layer 1502.

While fig. 28-32 are described with reference to a method, it will be appreciated that the structures shown in these figures are not limited to this method, but may be independent of the method. While fig. 28-32 are described as a series of acts, it will be appreciated that the order of the acts may be varied in other embodiments. While fig. 28-32 are illustrated and described as a particular set of acts, some acts illustrated and/or described may be omitted in other embodiments. Moreover, acts not shown and/or described may be included in other embodiments.

Referring to fig. 33-36, a series of cross-sectional views 3300-3600 of some alternative embodiments of the method of fig. 8-26 are provided, wherein at the second avalanche well 112, the peripheral absorption layer 116 has square ends. For example, the sensor device may correspond to the sensor device of fig. 4B or some other suitable sensor device.

As shown in the cross-sectional view 3300 of fig. 33, the actions described with respect to fig. 8 to 18 are performed. For example, these actions form first avalanche well 110, second avalanche well 112, vertical link well 120, first contact region 122, trench 1602, hard mask layer 1502, and third sacrificial layer 1702.

As also shown in cross-sectional view 3300 of fig. 33, the actions described with respect to fig. 19 are performed to selectively etch third sacrificial layer 1702 and remove portions of third sacrificial layer 1702 in trench 1602. However, unlike fig. 19, the selective etch further removes the third sacrificial layer 1702 from on top of the second avalanche well 112. As a result, in at least some embodiments, the selective etching completely removes the third sacrificial layer 1702 from the trench 1602.

As shown in cross-sectional view 3400 of fig. 34, the actions described with respect to fig. 20 are performed to epitaxially grow peripheral absorber layer 116 in trench 1602. However, unlike fig. 20, because third sacrificial layer 1702 does not mask second avalanche well 112, peripheral absorption layer 116 is grown on second avalanche well 112. Thus, the peripheral absorbent layer 116 has a U-shaped profile or the like.

As shown in cross-section 3500 of fig. 35, peripheral absorber layer 116 is selectively etched to form an opening 2002 exposing second avalanche well 112. In some embodiments, the width W of the opening 2002 _op About 0.5-2 microns, about 0.5-1.25 microns, about 1.25-2 microns, or some other suitable value.

In some embodiments, performing the selectively etching process includes: 1) Forming a seventh mask 3502 on the third sacrificial layer 1702 and the peripheral absorption layer 116 using photolithography; 2) With the seventh mask 3502 in place, performing an etch 3504 to the peripheral absorber layer 116; and 3) removing the seventh mask 3502. In alternative embodiments, the selective etching is performed by some other suitable process. For example, seventh mask 3502 may be or include photoresist or some suitable material.

Because the end of the peripheral absorption layer 116 at the second avalanche well 112 is formed by selective etching, the end is square instead of tapered. The square end reduces dark current at the second avalanche well 112 better than the tapered end.

As shown in the cross-sectional view 3600 of fig. 36, the actions described with respect to fig. 22-26 are performed. For example, these actions form the inner absorber layer 114, the cap layer 118, the second contact region 124, and the interconnect structure 126, and further remove the hard mask layer 1502. Further, in removing the hard mask layer 1502 described with respect to fig. 26, the third sacrificial layer 1702 is removed.

Although fig. 33 to 36 are described with reference to the method, it will be understood that the structures shown in these figures are not limited to the method, but may be independent of the method. While fig. 33-36 are described as a series of acts, it will be appreciated that the order of the acts may be varied in other embodiments. While fig. 33-36 are illustrated and described as a particular set of acts, some acts illustrated and/or described may be omitted in other embodiments. Moreover, acts not shown and/or described may be included in other embodiments.

Referring to fig. 37-41, a series of cross-sectional views 3700-4100 of some alternative embodiments of the method of fig. 8-26 are provided, wherein at the top of the semiconductor substrate and at the second avalanche well, the peripheral absorption layer has square ends. For example, the sensor device may correspond to the sensor device of fig. 4C or some other suitable sensor device.

As shown in cross-sectional view 3700 of fig. 37, the actions described with respect to fig. 33 are performed. For example, these actions form first avalanche well 110, second avalanche well 112, vertical link well 120, first contact region 122, trench 1602, hard mask layer 1502, and third sacrificial layer 1702.

As also shown in cross-section 3700 of fig. 37, peripheral absorber layer 116 is epitaxially grown in trench 1602 according to the actions described with respect to fig. 29. Thus, the peripheral absorber layer 116 grows out of the trench 1602.

As shown in cross-sectional view 3800 of fig. 38, the acts described with respect to fig. 35 are performed to selectively etch peripheral absorption layer 116 and form an opening 2002 exposing second avalanche well 112. Because the end of the peripheral absorption layer 116 at the second avalanche well 112 is formed by selective etching, the end is square instead of tapered. The square end reduces dark current at the second avalanche well 112 better than the tapered end.

As shown in cross-sectional view 3900 of fig. 39, the actions described with respect to fig. 30 are performed to epitaxially grow inner absorber layer 114 to fill the remainder of trench 1602.

As shown in cross-section 4000 of fig. 40, the actions described with respect to fig. 31 are performed to planarize the top of the inner absorber layer 114 and flatten the top of the inner absorber layer 114. Further, unlike fig. 31, planarization removes the third sacrificial layer 1702. Because the planarization extends into the inner absorber layer 114, the planarization squares the ends of the peripheral absorber layer 116 at the top of the peripheral absorber layer 116. The square end reduces dark current at the top of the peripheral absorber layer 116 better than the tapered end.

As shown in the cross-sectional view 4100 of fig. 41, the actions described with respect to fig. 32 are performed. For example, these actions form the cap layer 118, the second contact region 124, and the interconnect structure 126, and further remove the hard mask layer 1502.

Although fig. 37 to 41 are described with reference to the method, it will be understood that the structures shown in these figures are not limited to the method, but may be independent of the method. While fig. 37-41 are described as a series of acts, it will be appreciated that the order of the acts may be varied in other embodiments. While fig. 37-41 are illustrated and described as a particular set of acts, some acts illustrated and/or described may be omitted in other embodiments. Moreover, acts not shown and/or described may be included in other embodiments.

In some embodiments, the present disclosure provides a semiconductor structure for a photodetector, the semiconductor structure comprising: a semiconductor substrate including an avalanche region where the p-type region and the n-type region form a PN junction; an inner absorber layer recessed into the semiconductor substrate, wherein the inner absorber layer has a bottom protrusion protruding toward the avalanche region; and a peripheral absorbent layer located on a sidewall of the inner absorbent layer and a bottom of the inner absorbent layer and also extending from the sidewall to the bottom protrusion; wherein the inner absorber layer and the peripheral absorber layer share a common semiconductor material and have a smaller bandgap than the semiconductor substrate, and the peripheral absorber layer has a doping concentration that is elevated relative to the doping concentration of the inner absorber layer. In some embodiments, the peripheral absorbent layer has sloped sidewalls facing and directly contacting the bottom protrusions. In some embodiments, the peripheral absorber layer has a vertical sidewall facing and directly contacting the bottom protrusion, and wherein the vertical sidewall extends perpendicular to the top surface of the semiconductor substrate. In some embodiments, the ends of the peripheral absorber layer at the top surface of the semiconductor substrate are square. In some embodiments, the end of the peripheral absorber layer at the top surface of the semiconductor substrate is tapered. In some embodiments, the doping concentration of the peripheral absorber layer is uniform throughout the thickness of the peripheral absorber layer. In some embodiments, the bottom protrusion protrudes to one of the p-type region and the n-type region, and wherein the peripheral absorber layer has the same doping type as the one of the p-type region and the n-type region.

In some embodiments, the present disclosure provides a sensor device comprising: a silicon substrate; a first well buried in the silicon substrate and having a first doping type; a second well located above and directly on the first well in the silicon substrate, wherein the second well has a second doping type opposite to the first doping type; a germanium structure located above the second well and recessed into the silicon substrate; undoped regions in the germanium structure; and a doped region in the germanium structure; wherein the doped region surrounds a bottom corner of the undoped region to separate the bottom corner from the silicon substrate, and the first and second wells and the germanium structure form a photodetector. In some embodiments, the germanium structure includes tin. In some embodiments, the doping concentration of the doped region decreases from the silicon substrate to the undoped region. In some embodiments, the germanium structure is in direct contact with the silicon substrate at an interface, wherein the doped region continuously lines the interface from the second well to a top corner of the silicon substrate. In some embodiments, the first well has a width greater than the germanium structure, wherein the second well has a width less than the germanium structure. In some embodiments, the sensor device further comprises: and a silicon layer covering the germanium structure. In some embodiments, the sensor device further comprises: a third well extending laterally around the germanium structure in a closed path and also extending perpendicularly from the periphery of the first well to the top of the silicon substrate, wherein the third well has the first doping type.

In some embodiments, the present disclosure provides a method of forming a photodetector, the method comprising: forming a first well buried in the semiconductor substrate, and the first well having a first doping type; performing a first etch on the semiconductor substrate to form a trench, the trench being located above and spaced apart from the first well; doping the semiconductor substrate through the trench to form a second well on the first well, wherein the second well has a second doping type opposite to the first doping type; epitaxially growing a peripheral absorber layer on the exposed surface of the semiconductor substrate in the trench, the peripheral absorber layer having a second doping type; and epitaxially growing an inner absorber layer to fill the remainder of the trench over the peripheral absorber layer; wherein the peripheral absorber layer and the inner absorber layer are semiconductive and have a smaller bandgap than the semiconductor substrate. In some embodiments, epitaxial growth of the peripheral absorber layer is performed while masking the second well. In some embodiments, the method further comprises: depositing a sacrificial layer to line the trench, wherein doping is performed through the sacrificial layer; and performing a second etch on the sacrificial layer to remove the sacrificial layer from the sidewalls of the semiconductor substrate in the trench, wherein after the second etch is completed, a remaining portion of the sacrificial layer covers the second well; wherein the epitaxial growth of the peripheral absorber layer is performed with the remaining portion of the sacrificial layer in place. In some embodiments, the epitaxial growth of the peripheral absorber layer is performed while the second well is exposed in the trench, wherein the method further comprises: a second etch is performed on the peripheral absorber layer to form an opening exposing the second well prior to epitaxial growth of the inner absorber layer. In some embodiments, the method further comprises: a capping layer is epitaxially grown on top of the peripheral absorber layer and the inner absorber layer, wherein the capping layer is semiconductive and has the same band gap as the semiconductor substrate. In some embodiments, the epitaxial growth of the peripheral absorber layer is for a time sufficient to grow the peripheral absorber layer outside the trench, wherein the method further comprises: planarization is performed on the peripheral absorber layer and the inner absorber layer.

The foregoing outlines features of a drop-off embodiment so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure for a photodetector, comprising:

a semiconductor substrate including an avalanche region where a p-type region and an n-type region form a PN junction;

an inner absorber layer recessed into the semiconductor substrate, wherein the inner absorber layer has a bottom protrusion protruding toward the avalanche region; and

a peripheral absorbent layer located on a sidewall of the inner absorbent layer and a bottom of the inner absorbent layer and also extending from the sidewall to the bottom protrusion;

wherein the inner absorber layer and the outer absorber layer share a common semiconductor material and have a smaller bandgap than the semiconductor substrate, an

The peripheral absorber layer has a doping concentration that is elevated relative to the doping concentration of the inner absorber layer.

2. The semiconductor structure of claim 1, wherein the peripheral absorber layer has sloped sidewalls facing the bottom protrusion and directly contacting the bottom protrusion.

3. The semiconductor structure of claim 1, wherein the peripheral absorber layer has a vertical sidewall facing and directly contacting the bottom protrusion, and wherein the vertical sidewall extends perpendicular to a top surface of the semiconductor substrate.

4. The semiconductor structure of claim 1, wherein an end of the peripheral absorber layer at a top surface of the semiconductor substrate is square.

5. The semiconductor structure of claim 1, wherein an end of the peripheral absorber layer at a top surface of the semiconductor substrate is tapered.

6. The semiconductor structure of claim 1, wherein the doping concentration of the peripheral absorber layer is uniform throughout a thickness of the peripheral absorber layer.

7. The semiconductor structure of claim 1, wherein the bottom protrusion protrudes to one of the p-type region and the n-type region, and wherein the peripheral absorber layer has a same doping type as the one of the p-type region and the n-type region.

8. A sensor device, comprising:

a silicon substrate;

a first well buried in the silicon substrate and having a first doping type;

a second well located above and directly on the first well in the silicon substrate, wherein the second well has a second doping type opposite to the first doping type;

a germanium structure located above the second well and recessed into the silicon substrate;

an undoped region located in the germanium structure; and

a doped region located in the germanium structure;

wherein the doped region surrounds a bottom corner of the undoped region to separate the bottom corner from the silicon substrate, and

the first well and the second well and the germanium structure form a photodetector.

9. The sensor device of claim 8, wherein the germanium structure comprises tin.

10. A method of forming a photodetector, the method comprising:

forming a first well buried in a semiconductor substrate, and the first well having a first doping type;

performing a first etch on the semiconductor substrate to form a trench, the trench being located above and spaced apart from the first well;

Doping the semiconductor substrate through the trench to form a second well on the first well, wherein the second well has a second doping type opposite to the first doping type;

epitaxially growing a peripheral absorber layer on an exposed surface of the semiconductor substrate in the trench, and the peripheral absorber layer having the second doping type; and

epitaxially growing an inner absorber layer to fill a remaining portion of the trench over the peripheral absorber layer;

wherein the peripheral absorber layer and the inner absorber layer are semiconductive and have a smaller bandgap than the semiconductor substrate.