CN117608684A

CN117608684A - Reconfigurable architecture generation method, reconfigurable architecture generation device, reconfigurable architecture generation equipment, reconfigurable architecture generation medium and reconfigurable architecture generation product

Info

Publication number: CN117608684A
Application number: CN202311531977.1A
Authority: CN
Inventors: 谷江源; 回浩嘉; 韩慧明; 林宥旭
Original assignee: Shanghai Tsinghua International Innovation Center; Tsinghua University
Current assignee: Shanghai Tsinghua International Innovation Center; Tsinghua University
Priority date: 2023-11-16
Filing date: 2023-11-16
Publication date: 2024-02-27

Abstract

The application relates to a reconfigurable architecture generation method, device, equipment, medium and product. The method comprises the following steps: and responding to a generation instruction of the target reconfigurable architecture, acquiring function description information of the target reconfigurable architecture, screening out target function plugins meeting the function description information from a function plugin library comprising a plurality of preconfigured reconfigurable function plugins, and finally generating the target reconfigurable architecture based on the target function plugins. By adopting the method, the reconfigurable architecture can be quickly and accurately generated.

Description

Reconfigurable architecture generation method, reconfigurable architecture generation device, reconfigurable architecture generation equipment, reconfigurable architecture generation medium and reconfigurable architecture generation product

Technical Field

The present disclosure relates to the field of reconfigurable architecture technologies, and in particular, to a reconfigurable architecture generation method, device, apparatus, medium, and product.

Background

With the rapid development of reconfigurable computing technology, the reconfigurable architecture is applied to more and more fields such as embedded systems, artificial intelligence, machine learning and the like due to the characteristics of flexibility and customizable performance.

In the related art, when the reconfigurable architecture is applied, the hardware resources of the reconfigurable architecture are generally required to be adjusted to meet the operation requirement. If the hardware resources in the reconfigurable architecture cannot meet the application requirements, a new reconfigurable architecture needs to be redeveloped.

Therefore, how to quickly and accurately generate a reconfigurable architecture is a technical problem to be solved.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a reconfigurable architecture generation method, apparatus, device, medium, and product that can quickly and accurately generate a reconfigurable architecture.

In a first aspect, the present application provides a reconfigurable architecture generation method, including:

responding to a generation instruction of the target reconfigurable architecture, and acquiring function description information of the target reconfigurable architecture;

screening out target function plug-ins meeting the function description information from a function plug-in library; the function plug-in library comprises a plurality of preconfigured reconfigurable function plug-ins;

based on the target function plug-in, a target reconfigurable architecture is generated.

In one embodiment, obtaining the function description information of the target reconfigurable architecture includes:

a functional requirements selection field for displaying a target reconfigurable architecture;

and determining the function description information of the target reconfigurable architecture according to the function requirements input by the user in the function requirement selection field.

In one embodiment, screening target function plugins from a function plugin library, where the target function plugins satisfy function description information includes:

Determining the plug-in type and the plug-in number of the target function plug-ins according to the function description information;

and searching the function plug-ins matched with the plug-in types and the plug-in numbers from the function plug-in library, and determining the function plug-ins as target function plug-ins.

In one embodiment, the construction process of the function plug-in library includes:

obtaining a plurality of reconfigurable architecture functions;

obtaining all plugins corresponding to each architecture function according to the architecture function of each reconfigurable architecture;

and summarizing all the plugins corresponding to the architecture functions to obtain a function plugin library.

In one embodiment, all plugins corresponding to each architecture function are summarized to obtain a function plugin library, including:

obtaining the plug-in type of each plug-in;

and classifying all the plugins corresponding to each architecture function according to different plugin types to obtain a function plugin library.

In one embodiment, the method further comprises:

acquiring data to be processed and processing logic;

sorting the target function plug-ins in the target reconfigurable architecture based on the processing logic;

and according to the target reconfigurable framework after the plug-in sequencing, calculating the data to be processed to obtain a data processing result.

In a second aspect, the present application further provides a reconfigurable architecture generation apparatus, including:

the instruction response module is used for responding to the generation instruction of the target reconfigurable architecture and acquiring the function description information of the target reconfigurable architecture;

the plug-in screening module is used for screening target function plug-ins meeting the function description information from the function plug-in library; the function plug-in library comprises a plurality of preconfigured reconfigurable function plug-ins;

and the architecture generating module is used for generating a target reconfigurable architecture based on the target function plug-in.

In a third aspect, the present application also provides a computer device comprising a memory storing a computer program and a processor implementing the steps of the method of any one of the embodiments of the first aspect described above when the computer program is executed.

In a fourth aspect, the present application also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of any of the embodiments of the first aspect described above.

In a fifth aspect, the present application also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the method of any of the embodiments of the first aspect described above.

The reconfigurable architecture generation method, the reconfigurable architecture generation device, the reconfigurable architecture generation equipment, the reconfigurable architecture generation medium and the reconfigurable architecture generation product are used for responding to the generation instruction of the target reconfigurable architecture, acquiring the function description information of the target reconfigurable architecture, screening out the target function plugins meeting the function description information from a function plugin library comprising a plurality of reconfigurable function plugins which are preconfigured, and finally generating the target reconfigurable architecture based on the target function plugins. In the method, the target reconfigurable architecture is generated according to the target function plug-in determined by the function description information of the target reconfigurable architecture, so that the target reconfigurable architecture can be matched with the function description information at one time, and the accuracy of the target reconfigurable architecture is improved. In addition, when the target function plug-in is acquired, compared with the mode that blind screening is needed to be carried out from the function plug-ins of various reconfigurable architectures in the related art, the method and the device for screening the function plug-in are faster and more accurate in the mode that the function description information is directly screened from the function plug-in library of the function plug-ins of the various reconfigurable architectures which are configured in advance.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for a person having ordinary skill in the art.

FIG. 1 is a diagram of an application environment for a computer device method in one embodiment;

FIG. 2 is a flow diagram of a method of reconfigurable architecture generation in one embodiment;

FIG. 3 is a flow chart of the information acquisition steps in one embodiment;

FIG. 4 is a flow diagram of a plug-in acquisition step in one embodiment;

FIG. 5 is a flow diagram of a plug-in library acquisition step in one embodiment;

FIG. 6 is a flowchart illustrating a plug-in library acquisition step according to another embodiment;

FIG. 7 is a flow chart of data processing steps in one embodiment;

FIG. 8 is a schematic diagram of an execution framework for reconfigurable fabric generation in one embodiment;

FIG. 9 is a schematic diagram of an application flow of reconfigurable architecture generation in one embodiment;

fig. 10 is a block diagram of a reconfigurable architecture generation apparatus in one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

The reconfigurable architecture generation method provided by the embodiment of the application can be applied to computer equipment shown in fig. 1, wherein the computer equipment can be a server, and an internal structure diagram of the computer equipment can be shown in fig. 1. The computer device includes a processor, a memory, an Input/Output interface (I/O) and a communication interface. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface is connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is for storing reconfigurable architecture generation data. The input/output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a reconfigurable architecture generation method.

It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.

With the updating iteration of the algorithm, the new algorithm with more complex application scene is continuously combined among different algorithms, and the two-dimensional challenges are presented for the current hardware architecture. The abundance of applications in the space dimension allows for ever-increasing computational scales, while in the time dimension, the hardware platform must be compatible with fast-updating algorithms, ultimately creating challenges for design flexibility, design complexity, development cycle, and chip overhead.

The traditional domain-specific architecture (Domain Specific Architectures) has limited flexibility in various application scenarios, which in turn results in a loss of performance, power consumption, area, etc. dimensions of the hardware architecture when processing these algorithms. To address these challenges, referred to as spatial dimensions, configurable spatial architectures have evolved, with Coarse-granularity reconfigurable architecture (CGRA) being the most representative. Coarse-grained reconfigurable architecture implements streaming of Data Flow applications by mapping a computational Flow Graph (Data Flow Graph) onto an array of processor units (Process Element Array, PEA), which can be embodied not only in the reconstruction of operation classes within Processing Elements (PEs), but also in the reconstruction of Data paths represented by the manner of interconnection between PEs. However, such architecture has a long development period and high development cost.

Furthermore, from a time dimension challenge, the development cycle is related to the hardware programming platform employed. Ideas and ideas of agile development have long been introduced into the flow of software development, but hardware development has been lacking in the proposal of related theoretical guidance and design paradigms. The mainstream hardware development platforms today can be divided into three types: hardware description language expanded on the basis of Verilog, hardware description language based on high-level synthesis (High Level Synthesis) and emerging hardware description language. While these languages can increase and improve hardware development efficiency so that it can follow the changes in application scenarios, the level of abstraction introduced by these languages, the hostile support to EDA tools, and the lack of corresponding theoretical guidelines make it undesirable to improve development efficiency. There is a need to propose design paradigms that can improve development efficiency using emerging hardware description languages.

Based on this, the embodiment of the application provides a reconfigurable architecture generating method, which generates a new reconfigurable architecture through parameterizable and spliced hierarchical hardware architecture design thought. The method takes a more flexible plug-in service module with a self-adaptive port as a basic module for designing a hardware architecture, fully exerts the flexibility and the high efficiency of the method in a bottom-up design flow, can introduce parameters, can realize different expression forms of the same architecture through the splicing of different modules, and further rapidly and accurately generates a target reconfigurable architecture.

It should be noted that the beneficial effects or the technical problems to be solved by the embodiments of the present application are not limited to this one, but may be other implicit or related problems, and particularly, reference may be made to the following description of embodiments.

The following describes the technical solution of the present application and how the technical solution of the present application solves the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings. In one exemplary embodiment, as shown in fig. 2, there is provided a reconfigurable architecture generation method, the method comprising:

s201, responding to a generation instruction of the target reconfigurable architecture, and acquiring function description information of the target reconfigurable architecture.

The generation instruction of the target reconfigurable architecture may be triggered by a user based on actual requirements, and the function description information of the target reconfigurable architecture may be generated by the user based on application requirements.

The target reconfigurable architecture in the embodiment of the application can be applied to multiple scenes according to actual requirements, such as voice processing, video processing, image processing and the like. Then, according to the application scenario, the target reconfigurable architecture in the embodiment of the present application may be a speech processing target reconfigurable architecture, a video processing target reconfigurable architecture, an image processing target reconfigurable architecture, or the like.

Further, before the target reconfigurable architecture works under different scenes, the user generally inputs the processing requirements of the data to be processed, such as the generation instruction of the target reconfigurable architecture carried by the functional description information of voice recognition, video clipping or image segmentation, etc., to the computer device. Then, the computer device modifies the reconfigurable hardware internal program according to the function description information to generate a target reconfigurable framework supporting the function description information.

The generating instruction of the target reconfigurable architecture carries function description information, and the computer equipment responds to the generating instruction of the target reconfigurable architecture and reads all the function description information.

In practical application, the function description information of the target reconfigurable structure comprises basic function description information and extended function description information.

The computer device may store basic function description information in advance, and obtain target reconfigurable function description information according to the extended function description information input by the user and in combination with the pre-stored basic function description information.

S202, screening target function plug-ins meeting the function description information from a function plug-in library; the library of function plug-ins includes a pre-configured plurality of reconfigurable function plug-ins.

Wherein the library of function plug-ins comprises a pre-configured plurality of reconfigurable function plug-ins. In the embodiment of the application, the function plug-in library is generated according to architecture development experience in advance before responding to the generation instruction of the target reconfigurable architecture. And after the target reconfigurable architecture is generated subsequently, the function plug-in library can be replenished again according to plug-ins in the target reconfigurable architecture so as to maintain timeliness of the function plug-in library and facilitate regeneration of a new target reconfigurable architecture again.

The computer equipment determines the plug-in identification according to the function description information, screens all plug-ins corresponding to the plug-in identification from the function plug-in library, and determines the plug-ins as target function plug-ins.

S203, generating a target reconfigurable framework based on the target function plug-in.

And inputting the target function plug-in into the initial reconfigurable architecture to instruct the initial reconfigurable architecture to receive the target function plug-in, and carrying out hardware update to obtain the target reconfigurable architecture.

In the embodiment of the application, in response to a generation instruction of a target reconfigurable architecture, function description information of the target reconfigurable architecture is acquired, then target function plugins meeting the function description information are screened out from a function plugin library comprising a plurality of preconfigured reconfigurable function plugins, and finally the target reconfigurable architecture is generated based on the target function plugins. In the method, the target reconfigurable architecture is generated according to the target function plug-in determined by the function description information of the target reconfigurable architecture, so that the target reconfigurable architecture can be matched with the function description information at one time, and the accuracy of the target reconfigurable architecture is improved. In addition, when the target function plug-in is acquired, compared with the mode that blind screening is needed to be carried out from the function plug-ins of various reconfigurable architectures in the related art, the method and the device for screening the function plug-in are faster and more accurate in the mode that the function description information is directly screened from the function plug-in library of the function plug-ins of the various reconfigurable architectures which are configured in advance.

As can be seen from the foregoing embodiments, the generation process of the target reconfigurable architecture is performed based on the function description information, and the foregoing embodiments do not limit the manner of acquiring the function description information. Based on this, one possible implementation of acquiring the function description information is explained below by way of one embodiment.

In an exemplary embodiment, as shown in fig. 3, obtaining the function description information of the target reconfigurable architecture includes:

s301, a function requirement selection column of the target reconfigurable architecture is displayed.

The function requirement selection field is used for collecting function description information, and can be presented in a visual editing interface, and the interface comprises a plurality of candidate function requirements and corresponding check boxes for indicating a user to check the corresponding candidate function requirements based on application requirements.

In the case of an excessive variety of candidate functional requirements, the functional requirement selection field may also be a blank editing interface for the user to directly input information of the functional requirements based on the application requirements.

S302, determining the function description information of the target reconfigurable architecture according to the function requirements input by the user in the function requirement selection field.

According to the function requirement input by the user on the function requirement selection field, determining the operation resources required by the target reconfigurable architecture, such as how many times of addition, how many times of multiplication, how many times of circulation, how many times of iteration and the like are required to be executed by the target reconfigurable architecture, so as to obtain the function description information of the target reconfigurable architecture.

In the embodiment of the application, the function description information of the target reconfigurable architecture is determined by displaying the function requirement selection column of the target reconfigurable architecture to the user, which is equivalent to fully considering the actual application requirement of the user before constructing the target reconfigurable architecture, and the function requirement of the user on the target reconfigurable architecture is clearly and accurately known in advance, so that the target reconfigurable architecture meeting the actual application requirement of the user can be generated conveniently.

The function plug-in library comprises various plug-ins, and in order to reduce the manufacturing cost of the target reconfigurable architecture as much as possible, the target function plug-ins actually required can be determined from the function plug-in library, so that the target reconfigurable architecture is constructed. Based on this, one way of how the target function plugin is determined from the function plugin library is described below by way of one embodiment.

In an exemplary embodiment, as shown in fig. 4, selecting a target function plug-in from a function plug-in library that satisfies the function description information includes:

s401, determining the plug-in type and the plug-in number of the target function plug-ins according to the function description information.

One plug-in type corresponds to a class of operation types, such as addition, subtraction, multiplication, division, open square, exponent, etc. The number of plugins represents the number of plugin types, i.e. the number of operations of the operation type corresponding to the plugin type.

Optionally, the function description information is a plug-in type input by a user and the number of plug-ins corresponding to each plug-in type, and in this case, the function description information is directly determined as the plug-in type and the plug-in number of the target function plug-ins.

Optionally, the function description information is an operation flow input by a user, in this case, by analyzing the content of the operation flow, an operation type related in the operation flow is determined as a plug-in type of the target function plug-in, and the number of times of occurrence of each operation type in the operation flow is determined as the number of plug-ins of the plug-in type corresponding to the target function plug-in.

S402, searching the function plug-ins matched with the plug-in types and the plug-in numbers from the function plug-in library, and determining the function plug-ins as target function plug-ins.

According to the plug-in types, determining the function plug-ins corresponding to each plug-in type from the function plug-in library, and according to the plug-in number of each plug-in type, determining the function plug-ins with the same plug-in number of each plug-in type, namely the target function plug-ins.

Because the content of the functional plugins corresponding to different plugin types is different, and the content of the plurality of functional plugins corresponding to the same plugin type is the same, the functional plugins corresponding to each plugin type can be determined from the functional plugin library according to the plugin type, and the functional plugins of each plugin type are copied according to the plugin number of each plugin type so as to obtain the target functional plugin.

In the embodiment of the application, the plug-in type and the plug-in number of the target function plug-ins are determined by analyzing the function description information, and the objective description of the target function plug-ins is accurately determined from two dimensions of the plug-in type and the plug-in number, so that the target function plug-ins can be quickly and accurately found from a function plug-in library.

The target function plugins are determined from a preset function plugin library, and in order to improve the generation speed of the target reconfigurable architecture, the more plugin types in the function plugin library, the better the plugin types are, the more plugin numbers of the plugin types are. Based on this, the construction process of the function plug-in library will be described below.

In an exemplary embodiment, as shown in fig. 5, the construction process of the function plug-in library includes:

s501, obtaining a plurality of reconfigurable architecture functions.

It should be noted that each reconfigurable architecture has the characteristics of flexibility and customizable structure, that is, each reconfigurable architecture has at least one architecture function.

Typically, the architecture functions of each reconfigurable architecture, divided by function type, may include basic functions and extended functions.

The computer device can identify all architecture functions corresponding to each reconfigurable architecture by parsing the various reconfigurable hardware resources.

S502, obtaining all plugins corresponding to each architecture function according to the architecture function of each reconfigurable architecture.

For any architecture function of each reconfigurable architecture, the implementation may be performed by an operation step corresponding to one plug-in, or may be performed by a combination of operation steps corresponding to a plurality of plug-ins of different types, or may be performed by a combination of operation steps corresponding to a plurality of plug-ins of the same type.

There are also a wide variety of card types and a plurality of cards under the same card type facing a wide variety of architecture functions. Based on this, in the embodiment of the present application, the plugins corresponding to each architecture function are read, so as to obtain all plugins corresponding to each architecture function.

And S503, summarizing all the plugins corresponding to the architecture functions to obtain a function plugin library.

And dividing all plugins corresponding to each architecture function according to a preset division rule to obtain a function plugin library.

Illustratively, according to the function types of the architecture functions, multiple groups of plug-ins under the same function type are combined and divided together to obtain a function plug-in library taking the function types as units.

In the embodiment of the application, according to all the plugins corresponding to the architecture functions of the multiple reconfigurable architectures, a function plugin library is obtained, and various plugins are obtained from the dimension of the reconfigurable architecture type and the dimension of the architecture function type, so that a comprehensive and rich function plugin library is obtained.

Next, an implementation manner of "summarizing all the plug-ins corresponding to each architecture function to obtain the function plug-in library" in the foregoing embodiment S503 will be described. In one exemplary embodiment, as shown in fig. 6, comprises:

s601, obtaining the plug-in type of each plug-in.

And reading the operation type of each plug-in, and determining the operation type of each plug-in as the plug-in type.

S602, classifying all the plugins corresponding to each architecture function according to different plugin types to obtain a function plugin library.

All the plug-ins of the same plug-in type are combined according to different plug-in types. And then, for any plug-in type, obtaining the number of the plug-ins under the plug-in type, and the like, so as to obtain the number of the plug-ins under all the plug-in types, and further generating a functional plug-in library with clear plug-in types and clear plug-in numbers.

In the embodiment of the application, under the condition of acquiring all the plugins of all the architecture functions, classifying all the plugins according to different plugin types, counting the number of plugins corresponding to each plugin type, and further obtaining the function plugin library with distinct types and quantities, which is not only beneficial to quickly searching target function plugins, but also convenient for subsequent reconstruction according to new target reconfigurable architecture, and expanding the function plugin library.

In an exemplary embodiment, as shown in fig. 7, the method further comprises:

s701, acquiring data to be processed and processing logic.

The data to be processed may be a variable to be processed or a data set to be processed. Processing logic represents the manner in which data to be processed is operated on, and typically includes a combination of multiple operation types.

According to the embodiment of the application, the data processing interface can be displayed after the target reconfigurable framework is generated, and the data to be processed and the processing logic are determined according to the data and the logic input by the user on the data processing interface. The data processing interface may also be presented at the same time as the function requirements selection field of the target reconfigurable architecture is presented, i.e., prior to generating the reconfigurable architecture, to instruct the user to input data to be processed and processing logic.

S702, sorting the target function plug-ins in the target reconfigurable architecture based on the processing logic.

Based on the processing logic of the data to be processed, determining the execution number of the target function plug-in corresponding to the processing logic, and sequencing the target function plug-in according to the execution number to obtain the target reconfigurable architecture with the data processing function.

It should be noted that, in the case that the target function plugin in the target reconfigurable architecture is determined based on the function description information input by the user, and the processing logic is generated based on the user input, the type and the number of the target function plugin in the target reconfigurable architecture should be completely corresponding to the processing logic theoretically, that is, the processing logic may involve all the target function plugins.

S703, calculating the data to be processed according to the target reconfigurable framework after the plug-in sequencing, and obtaining a data processing result.

Inputting the data to be processed into the target reconfigurable architecture, indicating the target reconfigurable architecture to calculate the data to be processed, and determining the calculation result of the target reconfigurable architecture as the data processing result of the data to be processed.

In addition, because the target reconfigurable architecture itself has the characteristics of parallel operation and high performance, when the calculation logic of the data to be processed is more complex and the calculation scale is larger, the advantage of obtaining the data processing result through the target reconfigurable architecture calculation in the embodiment of the application is more obvious.

In the embodiment of the application, based on processing logic, the target function plug-ins in the target reconfigurable architecture are ordered to obtain the target reconfigurable architecture with the data processing function, then the target reconfigurable architecture is used for calculating the data to be processed to obtain the data processing result, the advantage of parallel calculation in the reconfigurable architecture is fully utilized, and the operation speed of the data to be processed is improved.

In a specific embodiment, there is provided a reconfigurable architecture generation method, the method comprising:

(1) A variety of reconfigurable architecture functions are obtained.

(2) And acquiring all plugins corresponding to each architecture function according to the architecture function of each reconfigurable architecture.

(3) And obtaining the plug-in type of each plug-in.

(4) And classifying all the plugins corresponding to each architecture function according to different plugin types to obtain a function plugin library.

(5) In response to the generation instruction of the target reconfigurable architecture, a functional requirement selection bar of the target reconfigurable architecture is presented.

(6) And determining the function description information of the target reconfigurable architecture according to the function requirements input by the user in the function requirement selection field.

(7) Determining the plug-in type and the plug-in number of the target function plug-ins according to the function description information; the library of function plug-ins includes a pre-configured plurality of reconfigurable function plug-ins.

(8) And searching the function plug-ins matched with the plug-in types and the plug-in numbers from the function plug-in library, and determining the function plug-ins as target function plug-ins.

(9) Based on the target function plug-in, a target reconfigurable architecture is generated.

Under the condition of acquiring the target reconfigurable architecture, the data to be processed and the processing logic can be acquired, the target function plug-ins in the target reconfigurable architecture are ordered based on the processing logic, and finally the data to be processed is calculated according to the target reconfigurable architecture after the plug-ins are ordered, so that the data processing result is obtained.

In one exemplary embodiment, the hardware development flow corresponding to the architecture generation method is divided into four phases: definition Layer design (Definition Layer) based on functions, implementation Layer design (Implementation Layer) based on plug in Service (plug in-Service), application Layer design (Application Layer) capable of being spliced, generation Layer design (Generation Layer) for realizing various hardware architectures, and the method is named as a DIAG design method according to initial letters of different layers.

Referring to fig. 8, fig. 8 is a schematic diagram of an execution framework of the DIAG design method, and as shown in fig. 8, the whole execution framework is divided into four flows, namely, function definition, plug-in implementation, module application and hardware generation, from development of a software layer to generation of a hardware layer, and the whole execution framework is low-cost layer by layer and distinct in logic. Next, the design contents of the four hardware development flows will be described in order.

(1) And (3) function definition, namely designing a corresponding definition layer.

In achieving the target reconfigurable architecture, the first step, like any hardware development, is to define a specification. It is unique in that the common features of the underlying hardware system, i.e. the application-specific domain processing, are extracted. Support for complex algorithms is built on commonalities. Hardware resources and architecture are divided into three parts:

(1) the basic framework (i.e., basic function tree) is composed of basic function segments necessary for the normal operation of the system. Generally, the base framework adopts a tree structure, as the functional segments can be further decoupled into fine granularity.

(2) An extension is an optional fragment set for enriching computing resources.

(3) The parameters are extracted from the variable stiffener settings. These canonical parts represent fine-grained classification and renaming of functions, but do not necessarily reflect their circuit-level physical meaning.

(2) Plug-in implementation corresponds to implementation layer design of plug-in Service (plug-Service).

The implementation layer is where the definition layer's physical circuit description and interface refinement occurs, following the function-oriented approach described above. Plug-ins and services are the basic components that make up this layer.

By recording the function dependency relationship between the plugins, the hardware micro-architecture is not realized until the plugins and parameters thereof are established. In the process of plug-in implementation, the following three steps are required for building the plug-in:

(1) the function fragments are packed into plug-ins according to clear and intuitive principles and then assigned to the variable tree structure.

Wherein each root node in the tree structure holds a handle for one hardware data type, which is critical for the basic framework waiting for initialization.

(2) The data type is initialized based on the root node (for the base framework) and the service call (for the extension).

(3) Hardware logic matching associated with the above initialized data implementation. This step corresponds to a conventional modular hardware design. Except that all future extensions may be structured and embedded in the corresponding plug-ins, e.g. multiplication units, floating point number calculation units, etc., according to the three steps described above. The dependencies between these units and other plugins are achieved through an implicit Service judgment and detection mechanism.

(3) And the module is applied and corresponds to the design of the spliced application layer.

The application layer involves integrating and refining the plug-ins into a parameterized generator. In one aspect, when other plug-ins call getService [ ], the connections between the hardware signals within each plug-in and its associated initialization logic are loaded as needed. On the other hand, the type and number of plug-ins invoked represent hardware resources in a particular architecture.

For example, in a CPU, the infrastructure (i.e., the basic framework) consists of four pipeline stages. Other plug-ins (e.g., cache, scoreBoard and Reorder Buffer) act as extensions to each pipeline stage. By inserting these extensions and passing parameters, the basic framework can exhibit unique features and functionality to support complex control, accurate error checking, and even facilitate instruction set architecture (Instruction Set Architecture, ISA) modification. Although hardware generators theoretically have field-specific integrity, their utilization and performance of logic resources may not be as expected, which is contrary to the original intent. Thus, in most cases, the generator is designed to support a particular subset of applications within the domain to achieve substantial acceleration. This strategy is called functional cutting, which is also an advantage of the plug-in introduction.

(4) And generating hardware, and correspondingly realizing the generation layer design of various hardware architectures.

Hardware circuits described in Verilog/VHDL, such as SpinalHDL, are generated using methods defined in emerging HDLs. Standard simulation tools and formal verification techniques may be used as usual. The set of functional plugins of the effective hardware architecture and its hardware architecture parameters may be stored as presets to speed up advanced system integration. Furthermore, the preset configuration of the generated target reconfigurable architecture is empirically determined and may not provide the best solution in a given situation. Thus, the performance power area (Performance power area, PPA) analyzed from the algorithm by the simulation model can be further converted into parameters of the generator. The parameter calibration is achieved by a negative feedback loop between the generation layer and the definition layer.

In the embodiment of the application, the plug-in service is used as a basic module for forming the hardware architecture generator, the design flow is divided into four processes of definition layer design based on functions, implementation layer design based on plug-in service, splice application layer design and generation layer design for realizing various hardware architectures, and the hardware architecture designed based on the method has parameterized characteristics and is beneficial to version maintenance and rapid generation of circuits meeting requirements.

Taking Coarse-grained reconfigurable architecture (CGRA) as an example, please refer to fig. 9, fig. 9 is a schematic diagram of application of DIAG method in cross-domain CGRA hardware architecture design.

And S901, developing a tool chain.

According to the characteristics of fragmenting, diversifying and updating iteration rapidness of the field-specific application, the data flow characteristics are extracted from the field-specific application and serve as the framework characteristics of the CGRA.

S902, architecture description.

The CGRA hardware architecture is described by combining with the development flow of the emerging agile hardware, and a plug-in service mechanism in the DIAG design method is introduced to generate a parameterizable and spliced domain-specific hardware architecture, for example, the array size of the hardware architecture can be changed, the storage space size can be changed, the configuration format of PE can be changed, and the like.

S903, modular design.

Based on the architecture description, modular design is carried out, and a DIAG design method is further combined to generate a final hardware architecture module.

S904, programming.

The hardware generation layer is used for realizing preset key application plugins such as multiplication, division and the like so as to realize heterogeneous integration of the processing unit array, and various hardware architectures can be generated according to preset parameters so as to accelerate cross-domain application.

Still taking the CGRA architecture as an example, a description is given of a paradigm corresponding to the DIAG method: the function definition layer, the abstract representation of the hierarchy is represented by a tree structure. Branches of the definition layer are created according to the function requirements, and leaves are represented in the extended functions. This mechanism ensures that every possible branch is available, but ultimately only leaves containing the required data type are generated.

The plug-in implementation layer relates to a gradual hardware circuit refinement process, and the abstract description is converted into a plug-in of the hardware description from the definition layer. This process is completed in three stages, create config, create early and create late, each following the blocking execution method, the next stage will stop until all plug-in processing of the current stage is completed. Thus, hardware logic is only generated when the trace signal is defined somewhere in the plug-in and captured by pattern matching. These three phases also correspond to three phases of hardware development: signal assertion, signal connection, logic implementation between signals. Unlike hardware description languages, which must assert signals during the programming phase, all potential signals in the plug-in implementation layer can be defined at this layer. As in the function definition layer, the function segments that direct the hardware generation have a tree structure. Thus, the plug-in definition includes methods related to the tree structure, such as adding/deleting nodes and searching paths. By these methods, a specific tree is constructed in which the base nodes are assigned at the beginning of creation and the extension nodes are added through service calls. Finally, logic between signals is designed based on the data handles present in the node list at a later stage of creation.

At the module application layer, the CGRA generator is built up by plug-in bottom-up integration. First a GGRA processing unit is defined which is capable of performing integer operations and floating point operations. To meet the critical path constraint, the decoding stage is delayed by an additional 1 period. Furthermore, the GGRA processing unit also derives a heterogeneous processing unit that exclusively performs load/store operations, which represents a high degree of flexibility in plug-in technology. At the higher level of RCA, interconnect network constructors are applied in the processing element array, allowing the shared resources and controllers to be customized in the processing element array. Furthermore, at the top level of the CGRA generator, RCA is integrated with specific items written in the open source hardware languages (VexRiscv and AXI).

At the hardware generation layer, a multi-functional CGRA generator is implemented based on predefined configuration information, which is then converted to Verilog/VHDL using the support of spinalHDL. Various types of CGRA architectures may be preset, such as mesh64, thread256, and syston 128. And integrate them with test stimulus generator, not only can verify the function of different frameworks fast, but also can extract the computational characteristics of different frameworks fast, in order to search for the optimal solution under the specific domain further.

It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.

Based on the same inventive concept, the embodiment of the application also provides a reconfigurable architecture generation device for implementing the reconfigurable architecture generation method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in the embodiments of the reconfigurable architecture generation device or devices provided below may refer to the limitation of the reconfigurable architecture generation method hereinabove, and will not be repeated herein.

In an exemplary embodiment, as shown in fig. 10, there is provided a reconfigurable architecture generation apparatus including: an instruction response module 1001, a plug-in filtering module 1002, and an architecture generation module 1003, wherein:

the instruction response module 1001 is configured to obtain, in response to a generation instruction of the target reconfigurable architecture, functional description information of the target reconfigurable architecture;

the plug-in screening module 1002 is configured to screen out a target function plug-in that satisfies the function description information from the function plug-in library; the function plug-in library comprises a plurality of preconfigured reconfigurable function plug-ins;

the architecture generation module 1003 is configured to generate a target reconfigurable architecture based on the target function plugin.

In an exemplary embodiment, the instruction response module 1001 includes a selection bar presentation unit and an information determination unit, where:

the selection bar display unit is used for displaying a function requirement selection bar of the target reconfigurable architecture;

and the information determining unit is used for determining the function description information of the target reconfigurable architecture according to the function requirements input by the user in the function requirement selection column.

In an exemplary embodiment, the plug-in screening module 1002 includes a plug-in determination unit and a plug-in screening unit, where:

The plug-in determining unit is used for determining the plug-in type and the plug-in number of the target function plug-ins according to the function description information;

and the plug-in screening unit is used for searching the functional plug-ins matched with the plug-in types and the plug-in numbers from the functional plug-in library and determining the functional plug-ins as target functional plug-ins.

In an exemplary embodiment, the reconfigurable architecture generation apparatus further includes a function acquisition module, a plugin acquisition module, and a plugin summary module, where:

the function acquisition module is used for acquiring a plurality of reconfigurable architecture functions;

the plug-in acquisition module is used for acquiring all plug-ins corresponding to each architecture function according to the architecture function of each reconfigurable architecture;

and the plug-in summarizing module is used for summarizing all plug-ins corresponding to each architecture function to obtain a function plug-in library.

In an exemplary embodiment, the plug-in summarization module includes a type acquisition unit and a plug-in classification unit, where:

the type acquisition unit is used for acquiring the plug-in type of each plug-in;

and the plug-in classifying unit is used for classifying all plug-ins corresponding to each architecture function according to different plug-in types to obtain a functional plug-in library.

In an exemplary embodiment, the reconfigurable architecture generation apparatus further includes a logic acquisition module, a plug-in ordering module, and a result acquisition module, wherein:

The logic acquisition module is used for acquiring data to be processed and processing logic;

the plug-in sequencing module is used for sequencing the target function plug-ins in the target reconfigurable architecture based on the processing logic;

the result acquisition module is used for reconstructing the target according to the plug-in ordered target, and calculating the data to be processed to obtain a data processing result.

The respective modules in the above-described reconfigurable architecture generation apparatus may be implemented in whole or in part by software, hardware, or a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In one exemplary embodiment, a computer device is provided comprising a memory and a processor, the memory having stored therein a computer program, the processor when executing the computer program performing the steps of:

In an exemplary embodiment, the processor when executing the computer program further performs the steps of:

obtaining a plurality of reconfigurable architecture functions;

Obtaining the plug-in type of each plug-in;

acquiring data to be processed and processing logic;

In one exemplary embodiment, a computer readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, performs the steps of:

In an exemplary embodiment, the computer program when executed by the processor further performs the steps of:

obtaining a plurality of reconfigurable architecture functions;

obtaining the plug-in type of each plug-in;

acquiring data to be processed and processing logic;

In one exemplary embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, performs the steps of:

obtaining a plurality of reconfigurable architecture functions;

obtaining the plug-in type of each plug-in;

acquiring data to be processed and processing logic;

It should be noted that, the user information (including, but not limited to, user equipment information, user personal information, etc.) and the data (including, but not limited to, data for analysis, stored data, presented data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party, and the collection, use, and processing of the related data are required to meet the related regulations.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the various embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the various embodiments provided herein may include at least one of relational databases and non-relational databases. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic units, quantum computing-based data processing logic units, etc., without being limited thereto.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.

Claims

1. A method of reconfigurable architecture generation, the method comprising:

responding to a generation instruction of a target reconfigurable architecture, and acquiring function description information of the target reconfigurable architecture;

And generating the target reconfigurable framework based on the target function plug-in.

2. The method of claim 1, wherein the obtaining the functional description information of the target reconfigurable architecture comprises:

a functional requirement selection bar displaying the target reconfigurable architecture;

and determining the function description information of the target reconfigurable structure according to the function requirements input by the user in the function requirement selection field.

3. The method according to claim 1, wherein the screening out the target function plug-ins satisfying the function description information from the function plug-in library includes:

determining the plug-in type and the plug-in number of the target function plug-in according to the function description information;

and searching the function plug-ins matched with the plug-in types and the plug-in numbers from the function plug-in library, and determining the function plug-ins as the target function plug-ins.

4. A method according to any one of claims 1-3, wherein the process of building the library of functional plug-ins comprises:

acquiring the architecture functions of the plurality of reconfigurable architectures;

And summarizing all the plugins corresponding to the architecture functions to obtain the function plugin library.

5. The method of claim 4, wherein the aggregating all plugins corresponding to each architecture function to obtain the function plugin library includes:

obtaining the plug-in type of each plug-in;

and classifying all the plugins corresponding to the architecture functions according to different plugin types to obtain the function plugin library.

6. A method according to any one of claims 1-3, wherein the method further comprises:

acquiring data to be processed and processing logic;

and calculating the data to be processed according to the target reconfigurable framework after the plug-in sequencing to obtain a data processing result.

7. A reconfigurable architecture generation apparatus, the apparatus comprising:

the instruction response module is used for responding to a generation instruction of the target reconfigurable architecture and acquiring the function description information of the target reconfigurable architecture;

the plug-in screening module is used for screening out target function plug-ins meeting the function description information from the function plug-in library; the function plug-in library comprises a plurality of preconfigured reconfigurable function plug-ins;

And the architecture generating module is used for generating the target reconfigurable architecture based on the target function plug-in.

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 6 when the computer program is executed.

9. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 6.