CN117608660A - Instruction scheduling method, device, medium and electronic equipment - Google Patents

Instruction scheduling method, device, medium and electronic equipment Download PDF

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Publication number
CN117608660A
CN117608660A CN202311569736.6A CN202311569736A CN117608660A CN 117608660 A CN117608660 A CN 117608660A CN 202311569736 A CN202311569736 A CN 202311569736A CN 117608660 A CN117608660 A CN 117608660A
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target
instruction
machine instruction
expected
determining
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杨磊
杨楷
都春霞
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Shanghai Silang Technology Co ltd
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Shanghai Silang Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/37—Compiler construction; Parser generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The embodiment of the application discloses an instruction scheduling method, an instruction scheduling device, a medium and electronic equipment. The method comprises the following steps: determining target hardware resources on which a target machine instruction depends and the number of instruction cycles to be executed by the target machine instruction according to the type of the target instruction to which the target machine instruction to be scheduled belongs; determining expected occupation pressure generated by executing a target machine instruction on a target hardware resource in the current execution beat and a target resource type to which the target hardware resource belongs; and determining the expected execution beat of the target machine instruction according to the expected occupation pressure, the target resource type and the number of instruction cycles to be executed by the target machine instruction. According to the technical scheme, in the process of scheduling the target machine instruction, the expected occupied pressure of the execution target machine instruction on the target hardware resource is considered in advance, the effectiveness and reliability of instruction scheduling are guaranteed, and in the subsequent register allocation stage, the overflow of a register can be reduced, and the pressure of the register is effectively reduced.

Description

Instruction scheduling method, device, medium and electronic equipment
Technical Field
The application relates to the technical field of computers, in particular to the technical field of compiling optimization, and especially relates to an instruction scheduling method, an instruction scheduling device, a medium and electronic equipment.
Background
Instruction scheduling and register allocation are two important issues of compiler optimization, which have a great impact on the execution efficiency of programs. The register allocation and instruction scheduling are performed in two phases, either before or after the register allocation.
If the register allocation is performed before instruction scheduling, the same register may be allocated to different variables, resulting in pseudo-dependencies, thus reducing instruction level parallelism of the code. If instruction scheduling is performed prior to register allocation, increased instruction level parallelism may greatly increase register pressure, resulting in register overflow. The method has the advantages of ensuring the parallelism of instruction level, avoiding register overflow and having important significance for improving the execution efficiency of the program.
Disclosure of Invention
The application provides an instruction scheduling method, an instruction scheduling device, a medium and electronic equipment, which can achieve the purposes of improving the effectiveness and reliability of instruction scheduling, reducing register overflow and effectively reducing register pressure in a subsequent register allocation stage.
According to a first aspect of the present application, there is provided an instruction scheduling method, the method comprising:
determining target hardware resources on which a target machine instruction depends and the number of instruction cycles to be executed by the target machine instruction according to the type of the target instruction to which the target machine instruction to be scheduled belongs;
Determining expected occupation pressure generated by executing the target machine instruction on the target hardware resource in the current execution beat and a target resource type to which the target hardware resource belongs;
and determining the expected execution beat of the target machine instruction according to the expected occupation pressure, the target resource type and the number of instruction cycles to be executed by the target machine instruction.
According to a second aspect of the present application, there is provided an instruction scheduling apparatus, the apparatus comprising:
the instruction type determining module is used for determining target hardware resources on which the target machine instruction depends and the number of instruction cycles to be executed by the target machine instruction according to the target instruction type to which the target machine instruction to be scheduled belongs;
the occupied pressure determining module is used for determining expected occupied pressure generated by executing the target machine instruction on the target hardware resource in the current execution beat and the target resource type to which the target hardware resource belongs;
and the execution beat time determining module is used for determining the expected execution beat time of the target machine instruction according to the expected occupied pressure, the target resource type and the instruction cycle number required to be executed by the target machine instruction.
According to a third aspect of the present invention, embodiments of the present application provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements an instruction scheduling method as described in embodiments of the present application.
According to a fourth aspect of the present invention, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable by the processor, where the processor executes the computer program to implement an instruction scheduling method according to an embodiment of the present application.
According to the technical scheme, according to the target instruction type of the target machine instruction to be scheduled, determining target hardware resources on which the target machine instruction depends and the number of instruction cycles to be executed by the target machine instruction; determining expected occupation pressure generated by executing a target machine instruction on a target hardware resource in the current execution beat and a target resource type to which the target hardware resource belongs; and determining the expected execution beat of the target machine instruction according to the expected occupation pressure, the target resource type and the number of instruction cycles to be executed by the target machine instruction. According to the method and the device, in the scheduling process of the target instruction, the expected occupied pressure of the target hardware resource generated by the execution of the target machine instruction in the current execution beat is considered, the effectiveness and the reliability of instruction scheduling are improved, the overflow of a register can be reduced in the subsequent register allocation stage, and the pressure of the register is effectively reduced.
It should be understood that the description of this section is not intended to identify key or critical features of the embodiments of the application or to delineate the scope of the application. Other features of the present application will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1A is a flow chart of an instruction scheduling method provided according to a first embodiment;
FIG. 1B is a schematic illustration of a directed acyclic graph provided according to an embodiment one;
FIG. 2 is a flow chart of a method of instruction scheduling provided according to a second embodiment;
fig. 3 is a schematic structural diagram of an instruction scheduling apparatus according to a third embodiment of the present application;
fig. 4 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present application.
Detailed Description
In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," "target," and "candidate" in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1A is a flowchart of an instruction scheduling method according to an embodiment, which is applicable to the case of instruction scheduling for a VLIW processor with high cost for register overflow, and the method may be configured to be executed by an instruction scheduling apparatus, where the instruction scheduling apparatus is implemented in hardware and/or software, and may be integrated in an electronic device running the system.
As shown in fig. 1A, the method includes:
s110, determining target hardware resources on which the target machine instruction depends and the number of instruction cycles to be executed by the target machine instruction according to the type of the target instruction to which the target machine instruction to be scheduled belongs.
The target machine instruction to be scheduled refers to a machine instruction which needs to be scheduled. The target machine instruction is compiled by the program code. The target instruction type refers to an instruction type to which a target machine instruction belongs, and the different types of machine instructions depend on different hardware resources, so that the required execution cycle also has a difference. The target hardware resource refers to a hardware resource on which a target machine instruction depends. Optionally, the target hardware resources include: hardware storage resources and hardware computing resources. Exemplary hardware storage resources include: addition registers, multiplication registers, shift registers, and the like, the hardware calculation unit includes: adder, multiplier, memory, etc. The target instruction type comprises an operation instruction, a memory access instruction and the like. Wherein the operation instruction may be an addition instruction or a multiplication instruction. It will be appreciated that an add instruction typically requires one instruction cycle to be executed and a memory access instruction typically requires three instruction cycles to be executed.
S120, determining expected occupation pressure generated by executing the target machine instruction on the target hardware resource in the current execution beat and the target resource type of the target hardware resource.
Wherein, the current execution beat refers to the beat which has not been allocated to the machine instruction. For example, the first execution beat to the third execution beat are assigned to a last machine instruction, where the last machine instruction is a machine instruction that is adjacent to and executed prior to the target machine instruction. Illustratively, the last machine instruction is a memory access instruction. The last machine instruction has a dependency relationship with the target machine instruction, and the target machine instruction depends on the instruction execution result of the last machine instruction. In this case, the current execution beat is the fourth execution beat. In the current execution beat, the target hardware resources occupied by the last machine instruction may not have been released, that is, the target hardware resources may still be in occupancy. The target hardware resource already carries a certain pressure. In this case, if the target machine instruction is allocated to the current execution beat, it is necessary to determine the expected occupation pressure of the execution target machine instruction on the target hardware resource and the target resource type to which the target hardware resource belongs in the current execution beat. Where the expected occupancy pressure is related to the pressure that the target hardware resource in the current execution beat has been subjected to without executing the target machine instruction, and is also related to the target hardware resource that is required to execute the target machine instruction. Different resource types have different degrees of influence on program execution efficiency. The execution cycle of the operation instruction is smaller than that of the access instruction. The impact of hardware storage resources on program execution efficiency is particularly pronounced. Illustratively, register overflow may result in longer program execution times because the register overflows and the compiler overflows the results into the stack. The program needs to read and write these variables in memory, which counteracts the benefits gained by using multiple values to accumulate in parallel, resulting in the advantages of parallel accumulation being lost. Especially VLIW processors.
S130, determining the expected execution beat of the target machine instruction according to the expected occupation pressure, the target resource type and the number of instruction cycles to be executed by the target machine instruction.
And determining whether the target machine instruction can be allocated to the current execution beat or not according to the expected occupancy pressure and the target resource type, and determining the cycle span of the execution target machine instruction according to the number of instruction cycles to be executed by the target machine instruction, thereby determining the expected execution beat of the target machine instruction.
According to the technical scheme, according to the target instruction type of the target machine instruction to be scheduled, determining target hardware resources on which the target machine instruction depends and the number of instruction cycles to be executed by the target machine instruction; determining expected occupation pressure generated by executing a target machine instruction on a target hardware resource in the current execution beat and a target resource type to which the target hardware resource belongs; and determining the expected execution beat of the target machine instruction according to the expected occupation pressure, the target resource type and the number of instruction cycles to be executed by the target machine instruction. According to the method and the device, in the scheduling process of the target instruction, the expected occupied pressure of the target hardware resource generated by the execution of the target machine instruction in the current execution beat is considered, the effectiveness and the reliability of instruction scheduling are improved, the overflow of a register can be reduced in the subsequent register allocation stage, and the pressure of the register is effectively reduced.
In an alternative embodiment, determining an expected occupancy pressure on the target hardware resource resulting from executing the target machine instruction in a current execution beat includes: determining the available resource quantity of the target hardware resources remained in the current execution beat and the expected resource quantity of the target hardware resources required to be occupied by the execution of the target machine instruction; and determining the expected occupation pressure of executing the target machine instruction to the target hardware resource in the current execution time according to the available resource quantity and the expected resource quantity.
The number of available resources refers to the number of hardware resources available for subsequent machine instructions, except the number of hardware resources occupied by the last machine instruction. The number of desired resources that may be occupied by a target machine instruction to execute the target machine instruction may be determined based on the type of target instruction to which the target machine instruction belongs. Illustratively, the add instruction requires an adder and an add register.
And determining the expected occupation pressure of the execution target machine instruction on the target hardware resource in the current execution beat according to the available resource quantity and the expected resource quantity. Optionally, determining a relative size relationship between the number of available resources and the number of expected resources, and determining whether the number of available resources can meet the resource occupation requirement of the target machine quality according to the relative size relationship, thereby determining an expected occupation pressure of executing the target machine instruction on the target hardware resource in the current execution beat. According to the technical scheme, a feasible expected occupation pressure determining method is provided, and data support is provided for instruction scheduling.
In an alternative embodiment, before determining the target hardware resource on which the target machine instruction depends and the number of instruction cycles that the target machine instruction needs to execute, the method further comprises: acquiring target program codes to be compiled, and compiling the target program codes to obtain candidate machine instructions; determining instruction dependency relationships among the candidate machine instructions, and determining instruction execution sequences of the candidate machine instructions based on the instruction dependency relationships; and determining the target machine instruction to be scheduled from the candidate machine instructions based on the instruction execution sequence.
Where object code refers to a software application, the object code includes a series of instructions, and in particular, different programming languages are used to program a computer for performing a particular task. The candidate machine instructions are compiled from compiler object code and are a set of instructions, files, or steps that are a single operation of the processor that needs to be executed by the processor. It can be appreciated that there are two instructions of instruction dependency, the execution of the latter instruction depends on the instruction execution result of the former instruction. The instruction dependencies between the candidate machine instructions are used to determine an instruction execution order between the candidate machine instructions. Based on the instruction execution order, a target machine instruction to be scheduled is determined from the candidate machine instructions.
Optionally, constructing a directed acyclic graph of the candidate machine instructions based on instruction dependencies between the candidate machine instructions; the candidate machine instructions are nodes of a directed acyclic graph, edges in the directed acyclic graph being used to indicate instruction dependencies between the candidate machine instructions. The instruction execution order of the candidate machine instructions is determined according to the hierarchy in which the nodes in the directed acyclic graph are located. Alternatively, there are no edges connecting each other between nodes at the same level, that is, there are no instruction dependencies between candidate machine instructions at the same level, and they can be executed in parallel.
By way of example, the object code may be the following code fragments written in the C language:
int d，e；void func(inta，int b，int c){d＝a+b；e＝d+c；}
7 candidate machine instructions may be obtained by compiling them by a compiler. % 1=lda, respectively; %2 = ldb; %3 = ld c; % 4=% 1+%2; d=st% 4; % 5=% 4+%; e=st% 5. Where "Ld" and "St" denote memory access instructions, "+" denotes addition instructions, and "%" denotes virtual registers. It is noted that in the code compiling stage, only parallelism of code execution is considered, virtual registers are used in the process of generating the directed acyclic graph, and there are infinite virtual registers, in this example, 1-%5 is used by the compiler, and 5 virtual registers are used in total. Fig. 1B is a schematic diagram of a directed acyclic graph provided according to a first embodiment. Referring to FIG. 1B, the candidate machine instructions have an instruction execution order of A, B, C, D, E, F, and G, where A, B, and C are executable in parallel and F and G are executable in parallel. For example, the candidate machine instructions a, B, and C are allocated to the first execution beat, where the candidate machine instructions a, B, and C are all access instructions, and the number of instruction cycles to be executed is 3, so that the 1 st execution beat to the 3 rd execution beat are occupied by the candidate machine instructions a, B, and C, and the 4 th execution beat is not yet allocated to the candidate execution instruction, and the current execution beat is the 4 th execution beat. And determining the target execution instruction as D according to the instruction order.
According to the technical scheme, the feasible target machine instruction determining method is provided, the accuracy of instruction scheduling is guaranteed, and data support is provided for considering the parallelism of instruction execution in the instruction scheduling process.
Example two
Fig. 2 is a flowchart of an instruction scheduling method according to a second embodiment. The present embodiment is further optimized on the basis of the above embodiment.
As shown in fig. 2, the method includes:
s210, determining target hardware resources on which the target machine instruction depends and the number of instruction cycles to be executed by the target machine instruction according to the type of the target instruction to which the target machine instruction to be scheduled belongs.
S220, determining expected occupation pressure generated by executing the target machine instruction on the target hardware resource in the current execution beat and the target resource type of the target hardware resource.
S230, according to the type of the target resource to which the target hardware resource belongs, weighting the expected occupation pressure generated by executing the target machine instruction to the target hardware resource to obtain a weighted processing result.
The target hardware resources comprise hardware computing resources and hardware storage resources, the influence degree of different resource types on the program execution efficiency is different, and the influence of the hardware storage resources on the program execution efficiency is particularly obvious. Illustratively, register overflow may result in longer program execution times because the register overflows and the compiler overflows the results into the stack. The program needs to read and write these variables in memory, which counteracts the benefits gained by using multiple values to accumulate in parallel, resulting in the advantages of parallel accumulation being lost. Especially VLIW processors.
And weighting the expected occupation pressure generated by executing the target machine instruction to the target hardware resource according to the target resource type of the target hardware resource to obtain a weighted processing result. Specifically, according to the target resource type to which the target hardware resource belongs, a pressure weight coefficient of the expected occupation pressure is determined, and the expected occupation pressures of different resource types are given different coefficient weights to influence the weighted processing result.
Optionally, a larger pressure weight coefficient is given to a hardware storage resource with a larger influence on the program execution efficiency, that is, the resource occupation pressure of the instruction execution on the hardware storage resource such as a register is focused in the instruction scheduling process.
In an alternative embodiment, weighting the expected occupancy pressure generated by executing the target machine instruction on the target hardware resource according to the target resource type to which the target hardware resource belongs includes: if the target hardware resource belongs to a hardware storage resource, weighting the expected occupation pressure generated by executing the target machine instruction on the target hardware resource based on a first weight coefficient; if the target hardware resource belongs to a hardware computing resource, weighting the expected occupation pressure generated by executing the target machine instruction on the target hardware resource based on a second weight coefficient; wherein the first weight coefficient is greater than the second weight coefficient.
The target hardware resources comprise hardware computing resources and hardware storage resources, different resource types have different influence degrees on the program execution efficiency, and the influence of the hardware storage resources on the program execution efficiency is particularly obvious. Illustratively, register overflow may result in longer program execution times because the register overflows and the compiler overflows the results into the stack. The program needs to read and write these variables in memory, which counteracts the benefits gained by using multiple values to accumulate in parallel, resulting in the advantages of parallel accumulation being lost. Especially VLIW processors. Weighting the expected occupation pressure generated by the execution target machine instruction on the hardware storage resource by using the first weight coefficient to obtain a first weighted result; and weighting the expected occupation pressure generated by the execution target machine instruction on the hardware computing resource by using the second weight coefficient to obtain a second weighted result. Wherein the first weight coefficient is greater than the second weight coefficient. The sum of the first weighted result and the second weighted result is determined as determining an expected occupancy pressure of the target hardware resource by executing the target machine instruction in the current execution beat. The first weight coefficient and the second weight coefficient are determined according to actual service requirements, and are not limited herein.
According to the technical scheme, the feasible expected occupation pressure determining method is provided, a larger pressure weight coefficient is given to the expected occupation pressure generated by the hardware storage resource, and technical support is provided for reducing register overflow and reducing register pressure in the subsequent register allocation stage.
S240, updating the expected occupied pressure according to the weighted processing result to obtain a pressure updating result.
The weighting processing result considers the influence degree of the hardware resource type on the program execution efficiency, and is an important data reference for guaranteeing the effectiveness and reliability of instruction scheduling. And updating the expected occupied pressure according to the weighted processing result to obtain a pressure updating result.
S250, based on the pressure updating result and the number of instruction cycles to be executed by the target machine instruction, determining the expected execution beat of the target machine instruction.
And determining whether the target machine instruction can be allocated to the current execution beat or not according to the pressure updating result, and determining the cycle span of executing the target machine instruction according to the number of instruction cycles required to be executed by the target machine instruction, thereby determining the expected execution beat of the target machine instruction.
According to the technical scheme, according to the type of the target resource to which the target hardware resource belongs, the expected occupation pressure generated by executing the target machine instruction to the target hardware resource is weighted, and a weighted processing result is obtained; and updating the expected occupied pressure according to the weighted processing result to obtain a pressure updating result. And determining the expected execution beat of the target machine instruction based on the pressure update result and the number of instruction cycles to be executed by the target machine instruction. According to the technical scheme, the influence degree of the hardware resource type on the program execution efficiency is considered, and technical support is provided for reducing register overflow and reducing register pressure in the subsequent register allocation stage.
In an alternative embodiment, the determining the expected execution beat of the target machine instruction based on the pressure update result and the number of instruction cycles that the target machine instruction needs to execute includes: if the pressure updating result is smaller than the maximum bearing pressure of the target hardware resource, determining the current execution beat as the initial execution beat; and determining the expected execution beat of the target machine instruction according to the initial execution beat and the number of instruction cycles to be executed by the target machine instruction.
The maximum bearing pressure of the target hardware resource refers to the maximum pressure that the target hardware resource can bear. The relative magnitude relation between the maximum bearing pressure of the target hardware resource and the pressure updating result is determined, and the expected execution beat of the target machine instruction is determined.
If the pressure updating result is smaller than the maximum bearing pressure of the target hardware resource, the current execution time is determined to be the initial execution time, wherein the current execution time is indicated that the target machine instruction is executed at the current execution time and does not exceed the load of the target hardware resource. Then, the cycle span of executing the target machine instruction is determined according to the number of instruction cycles to be executed by the target machine instruction. And determining the expected execution beat of the target machine instruction according to the initial execution beat and the period span.
Continuing with the above example, the current execution beat is the 1 st execution beat, the target machine instruction is B, that is,% 2=ldb, the target machine instruction is a memory access instruction, and the number of cycles the target machine instruction needs to execute is 3, that is, the cycle span of the target machine instruction is 3 cycles. Assuming that the hardware resources of the processor are 3 concurrent accesses (3 ld instructions or st instructions can be executed in parallel at most in the same beat), 1 adder (1 addition instruction can be executed in parallel at most in the same beat), and 2 physical registers R1 and R2. The maximum bearing pressure of the hardware storage resource is 2, the maximum bearing pressure of the hardware computing resource is 1, the physical register R1 is occupied by the machine instruction A in the 1 st execution time, 1 physical register is needed for executing the machine instruction B in the 1 st execution time, and the target hardware resource is the hardware storage resource, that is, the current execution time does not exceed the load of the hardware storage resource when the target machine instruction is executed, the 1 st execution time is taken as the initial execution time of the machine instruction B, the number of periods needed to be executed by the machine instruction B is 1, and the expected execution time of the machine instruction B can be determined to be the 1 st execution time to the 3 rd execution time.
In an alternative embodiment, the determining the expected execution beat of the target machine instruction based on the pressure update result and the number of instruction cycles that the target machine instruction needs to execute includes: if the pressure updating result is larger than the maximum bearing pressure of the target hardware resources, determining the number of available resources of the target hardware resources remained in the follow-up execution beats; and determining an expected occupancy pressure generated by executing the target machine instruction on the target hardware resource in the subsequent execution beat based on the available resource quantity of the target hardware resource remaining in the subsequent execution beat and the expected resource quantity of the target hardware resource required to be occupied by executing the target machine instruction until the expected occupancy pressure is smaller than the maximum bearing pressure of the target hardware resource.
If the pressure update result is greater than the maximum bearing pressure of the target hardware resource, the current execution time will not be determined as the initial execution time if the current execution time exceeds the load of the target hardware resource. The initial execution beat of the target machine instruction is generated in a subsequent execution beat subsequent to the current execution beat.
Specifically, based on the number of available resources of the target hardware resource remaining in the subsequent execution beat and the number of expected resources of the target hardware resource that need to be occupied by the execution of the target machine instruction, an expected occupancy pressure generated by the execution of the target machine instruction on the target hardware resource in the subsequent execution beat is determined until the expected occupancy pressure is less than a maximum bearing pressure of the target hardware resource.
Continuing with the above example, assume that there are only 3 concurrent accesses (up to 3 ld instructions or st instructions can be executed in parallel in the same beat), 1 adder (up to 1 add instruction can be executed in parallel in the same beat), and 3 physical registers R1, R2, and R3 in the hardware resources of the processor. The maximum bearing pressure of the hardware storage resource is 3, and the maximum bearing pressure of the hardware computing resource is 1. The parallel execution machine instructions a, B and C need to occupy 3 physical registers, in the case that the machine instructions a and B have been allocated to the 1 st execution beat, the machine instruction C, i.e.,% 3=ldc, is taken as the target machine instruction, the 1 st execution beat is the current execution beat, 2 physical registers of the processor are already occupied by the machine instructions a and B, and the current execution beat executes the target machine instruction beyond the load of the target hardware resource, so that the expected occupation pressure generated by the target machine instruction on the target hardware resource by the execution target machine instruction in the subsequent execution beat is determined, the machine instructions a and B need to execute 3 instruction cycles, that is, the physical registers R1 and R2 occupy 3 execution beats by the machine instructions a and B, the 4 th execution beat is determined as the subsequent execution beat, the physical registers R1 and R2 occupied by the machine instruction a and R2 are released before the 4 th execution beat, and the load of the target hardware resource is not exceeded in the 4 th execution beat, so that the 4 th execution beat is determined as the initial execution beat, the 4 th execution beat is the target execution target machine instruction, and the expected execution beat is the target machine instruction, and the target execution beat is the target execution beat is the same, and the execution needs to be carried out for the 4 th execution beat, and the execution needs to take 3 times.
According to the technical scheme, the hardware resource pressure of each execution beat is dynamically evaluated in the instruction scheduling process, so that the hardware resource pressure of any unit of any beat is ensured not to exceed the maximum bearing pressure, the effectiveness and reliability of instruction scheduling are improved, the overflow of a register can be reduced in the subsequent register allocation stage, and the register pressure is effectively reduced.
In a specific embodiment, based on the above description, a conventional PreRA scheduling method is used to improve the instruction concurrency as a priority policy, and the instruction scheduling result is shown in Table 1:
TABLE 1
In the traditional PreRA scheduling method, the expected total execution period is 9 beats, and the instruction sequence for scheduling output is as follows: %3 = ld c; %1 = ld a; %2 = ldb; % 4=% 1+%2; d=st% 4; % 5=% 4+%3; e=st% 5.
In fact, since the processor has only 2 physical registers, after the instruction scheduling is finished, the register allocation stage finds that the physical registers of the instruction sequence are insufficient, and a pair of register overflow instructions can be generated to ensure correct data flow, and the code segments become after the register allocation: r1=ldc; stack=StR1 (overflow instruction 1: R1 is stored onto Stack, stack space Stack is in memory); r1=lda; r2=ldb; r1=r1+r2; d=str1; r2=ld Stack (overflow instruction 2: read stored value from Stack space Stack into register R2); r1=r1+r2; e=str1
As a result of the scheduling by the conventional PreRA scheduling method, since the register overflows after the scheduling, the final total execution cycle is 16 beats, and the final emission scheme of the machine instruction using the physical register is shown in table 2:
TABLE 2
By adopting the instruction scheduling method provided by the application, the instruction scheduling result is shown in the following table 3:
TABLE 3 Table 3
The expected total execution period of the instruction scheduling result is 11 beats, and the instruction sequence of scheduling output is as follows: %1 = ld a; %2 = ldb; % 4=% 1+%2; %3 = ld c; d=st% 4; % 5=% 4+%3; e=st% 5.
After the instruction scheduling is finished, register allocation is directly carried out according to the register use condition recorded in the scheduling process, and the code segments are changed into instruction sequences shown in the following table: r=lda; r2=ldb; r1=r1+r2; r2=ldc; d=str2; r1=r1+r2; e=str1; the final instruction execution is shown in table 4:
TABLE 4 Table 4
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Based on the instruction scheduling method provided by the application, the final instruction execution situation is consistent with the situation expected in the instruction scheduling process of the application, and the total time is 11 beats to complete the execution of all instructions.
Example III
Fig. 3 is a schematic structural diagram of an instruction scheduling apparatus provided in a third embodiment of the present application, where the embodiment may be applicable to a case of instruction scheduling for a VLIW processor with a relatively high cost for register overflow, where the apparatus may be implemented by software and/or hardware and may be integrated in an electronic device such as an intelligent terminal.
As shown in fig. 3, the apparatus may include:
the instruction type determining module 310 is configured to determine, according to a target instruction type to which a target machine instruction to be scheduled belongs, a target hardware resource on which the target machine instruction depends and a number of instruction cycles to be executed by the target machine instruction.
The occupation pressure determining module 320 is configured to determine an expected occupation pressure generated by executing the target machine instruction on the target hardware resource in the current execution beat, and a target resource type to which the target hardware resource belongs.
The execution beat determining module 330 is configured to determine an expected execution beat of the target machine instruction according to the expected occupancy pressure, the target resource type, and the number of instruction cycles that the target machine instruction needs to execute.
According to the technical scheme, according to the target instruction type of the target machine instruction to be scheduled, determining target hardware resources on which the target machine instruction depends and the number of instruction cycles to be executed by the target machine instruction; determining expected occupation pressure generated by executing a target machine instruction on a target hardware resource in the current execution beat and a target resource type to which the target hardware resource belongs; and determining the expected execution beat of the target machine instruction according to the expected occupation pressure, the target resource type and the number of instruction cycles to be executed by the target machine instruction. According to the method and the device, in the scheduling process of the target instruction, the expected occupied pressure of the target hardware resource generated by the execution of the target machine instruction in the current execution beat is considered, the effectiveness and the reliability of instruction scheduling are improved, the overflow of a register can be reduced in the subsequent register allocation stage, and the pressure of the register is effectively reduced.
Optionally, the occupancy pressure determination module 320 includes: the resource quantity determining submodule is used for determining the available resource quantity of the target hardware resources remained in the current execution beat and the expected resource quantity of the target hardware resources required to be occupied by the execution of the target machine instruction; and the occupation pressure determining submodule is used for determining the expected occupation pressure of the target hardware resource generated by executing the target machine instruction in the current execution beat according to the available resource quantity and the expected resource quantity.
Optionally, executing the beat determination module 330 includes: the weighting processing sub-module is used for carrying out weighting processing on expected occupation pressure generated by executing the target machine instruction on the target hardware resource according to the type of the target resource to which the target hardware resource belongs, so as to obtain a weighting processing result; the pressure updating sub-module is used for updating the expected occupied pressure according to the weighted processing result to obtain a pressure updating result; and the execution beat time determining sub-module is used for determining the expected execution beat time of the target machine instruction based on the pressure updating result and the instruction cycle number required to be executed by the target machine instruction.
Optionally, the weighting processing sub-module includes: the first weighting processing unit is used for weighting the expected occupation pressure generated by executing the target machine instruction on the target hardware resource based on a first weight coefficient if the target hardware resource belongs to a hardware storage resource; the second weighting processing unit is used for weighting the expected occupation pressure generated by executing the target machine instruction on the target hardware resource based on a second weight coefficient if the target hardware resource belongs to a hardware computing resource; wherein the first weight coefficient is greater than the second weight coefficient.
Optionally, the apparatus further includes: the code compiling module is used for acquiring target program codes to be compiled before determining target hardware resources on which the target machine instruction depends and the number of instruction cycles to be executed by the target machine instruction, and compiling the target program codes to obtain candidate machine instructions; a dependency determination module, configured to determine an instruction dependency between the candidate machine instructions, and determine an instruction execution order of the candidate machine instructions based on the instruction dependency; and the target instruction determining module is used for determining the target machine instruction to be scheduled from the candidate machine instructions based on the instruction execution sequence.
Optionally, the executing beat time determining submodule includes: the first execution time determining unit is used for determining the current execution time as the initial execution time if the pressure updating result is smaller than the maximum bearing pressure of the target hardware resource; and the second execution time determining unit is used for determining the expected execution time of the target machine instruction according to the initial execution time and the number of instruction cycles required to be executed by the target machine instruction.
Optionally, the executing beat time determining submodule includes: a third execution beat determining unit, configured to determine, if the pressure update result is greater than the maximum bearing pressure of the target hardware resource, an available resource number of the target hardware resource remaining in the subsequent execution beat; and the fourth execution beat determining unit is used for determining the expected occupation pressure of the target machine instruction on the target hardware resource in the subsequent execution beat based on the available resource quantity of the target hardware resource remained in the subsequent execution beat and the expected resource quantity of the target hardware resource needed to be occupied by the execution of the target machine instruction until the expected occupation pressure is smaller than the maximum bearing pressure of the target hardware resource.
The instruction scheduling device provided by the embodiment of the invention can execute the instruction scheduling method provided by any embodiment of the application, and has the corresponding performance module and beneficial effects of executing the instruction scheduling method.
In the technical scheme of the disclosure, the related user data are collected, stored, used, processed, transmitted, provided, disclosed and the like, all conform to the regulations of related laws and regulations and do not violate the popular regulations of the public order.
Example IV
Fig. 4 illustrates a schematic diagram of an electronic device 410 that may be used to implement an embodiment. The electronic device 410 comprises at least one processor 411, and a memory communicatively coupled to the at least one processor 411, such as a Read Only Memory (ROM) 412, a Random Access Memory (RAM) 413, etc., wherein the memory stores computer programs executable by the at least one processor, and the processor 411 may perform various suitable actions and processes in accordance with the computer programs stored in the Read Only Memory (ROM) 412 or the computer programs loaded from the storage unit 418 into the Random Access Memory (RAM) 413. In the RAM 413, various programs and data required for the operation of the electronic device 410 may also be stored. The processor 411, the ROM 412, and the RAM 413 are connected to each other through a bus 414. An input/output (I/O) interface 415 is also connected to bus 414.
Various components in the electronic device 410 are connected to the I/O interface 415, including: an input unit 416 such as a keyboard, a mouse, etc.; an output unit 417 such as various types of displays, speakers, and the like; a storage unit 418, such as a magnetic disk, optical disk, or the like; and a communication unit 419 such as a network card, modem, wireless communication transceiver, etc. The communication unit 419 allows the electronic device 410 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.
The processor 411 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 411 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 411 performs the various methods and processes described above, such as instruction scheduling methods.
In some embodiments, the instruction scheduling method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as storage unit 418. In some embodiments, some or all of the computer program may be loaded and/or installed onto the electronic device 410 via the ROM 412 and/or the communication unit 419. When the computer program is loaded into RAM 413 and executed by processor 411, one or more steps of the instruction scheduling method described above may be performed. Alternatively, in other embodiments, the processor 411 may be configured to perform instruction scheduling methods in any other suitable manner (e.g., by means of firmware).
Various implementations of the systems and techniques described here above can be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out the methods of the present application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this application, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data processing server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present application may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solutions of the present application are achieved, and the present application is not limited herein.
The above embodiments do not limit the scope of the application. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application are intended to be included within the scope of the present application.

Claims (10)

1. A method of instruction scheduling, the method comprising:
determining target hardware resources on which a target machine instruction depends and the number of instruction cycles to be executed by the target machine instruction according to the type of the target instruction to which the target machine instruction to be scheduled belongs;
determining expected occupation pressure generated by executing the target machine instruction on the target hardware resource in the current execution beat and a target resource type to which the target hardware resource belongs;
And determining the expected execution beat of the target machine instruction according to the expected occupation pressure, the target resource type and the number of instruction cycles to be executed by the target machine instruction.
2. The method of claim 1, wherein the determining an expected occupancy pressure on the target hardware resource resulting from executing the target machine instruction in a current execution beat comprises:
determining the available resource quantity of the target hardware resources remained in the current execution beat and the expected resource quantity of the target hardware resources required to be occupied by the execution of the target machine instruction;
and determining the expected occupation pressure of executing the target machine instruction to the target hardware resource in the current execution time according to the available resource quantity and the expected resource quantity.
3. The method of claim 1, wherein determining the expected execution beat of a target machine instruction based on the expected occupancy pressure, the target resource type, and the number of instruction cycles the target machine instruction needs to execute, comprises:
according to the type of the target resource to which the target hardware resource belongs, weighting the expected occupation pressure generated by executing the target machine instruction to the target hardware resource to obtain a weighted processing result;
Updating the expected occupied pressure according to the weighted processing result to obtain a pressure updating result;
and determining the expected execution beat of the target machine instruction based on the pressure updating result and the instruction cycle number to be executed by the target machine instruction.
4. A method according to claim 3, wherein weighting the expected occupancy pressure generated by executing the target machine instruction on the target hardware resource according to the target resource type to which the target hardware resource belongs comprises:
if the target hardware resource belongs to a hardware storage resource, weighting the expected occupation pressure generated by executing the target machine instruction on the target hardware resource based on a first weight coefficient;
if the target hardware resource belongs to a hardware computing resource, weighting the expected occupation pressure generated by executing the target machine instruction on the target hardware resource based on a second weight coefficient; wherein the first weight coefficient is greater than the second weight coefficient.
5. The method of claim 1, wherein prior to determining the target hardware resource on which the target machine instruction depends and the number of instruction cycles that the target machine instruction needs to execute, the method further comprises:
Acquiring target program codes to be compiled, and compiling the target program codes to obtain candidate machine instructions;
determining instruction dependency relationships among the candidate machine instructions, and determining instruction execution sequences of the candidate machine instructions based on the instruction dependency relationships;
and determining the target machine instruction to be scheduled from the candidate machine instructions based on the instruction execution sequence.
6. The method of claim 3, wherein determining an expected execution beat of a target machine instruction based on the pressure update result and a number of instruction cycles the target machine instruction needs to execute comprises:
if the pressure updating result is smaller than the maximum bearing pressure of the target hardware resource, determining the current execution beat as the initial execution beat based on the current execution beat;
and determining the expected execution beat of the target machine instruction according to the initial execution beat and the number of instruction cycles to be executed by the target machine instruction.
7. The method of claim 3, wherein determining an expected execution beat of a target machine instruction based on the pressure update result and a number of instruction cycles the target machine instruction needs to execute comprises:
If the pressure updating result is larger than the maximum bearing pressure of the target hardware resources, determining the number of available resources of the target hardware resources remained in the follow-up execution beats;
and determining an expected occupancy pressure generated by executing the target machine instruction on the target hardware resource in the subsequent execution beat based on the available resource quantity of the target hardware resource remaining in the subsequent execution beat and the expected resource quantity of the target hardware resource required to be occupied by executing the target machine instruction until the expected occupancy pressure is smaller than the maximum bearing pressure of the target hardware resource.
8. An instruction scheduling apparatus, the apparatus comprising:
the instruction type determining module is used for determining target hardware resources on which the target machine instruction depends and the number of instruction cycles to be executed by the target machine instruction according to the target instruction type to which the target machine instruction to be scheduled belongs;
the occupied pressure determining module is used for determining expected occupied pressure generated by executing the target machine instruction on the target hardware resource in the current execution beat and the target resource type to which the target hardware resource belongs;
And the execution beat time determining module is used for determining the expected execution beat time of the target machine instruction according to the expected occupied pressure, the target resource type and the instruction cycle number required to be executed by the target machine instruction.
9. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the instruction scheduling method of any one of claims 1-7.
10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable by the processor, wherein the processor implements the instruction scheduling method of any one of claims 1-7 when executing the computer program.
CN202311569736.6A 2023-11-22 2023-11-22 Instruction scheduling method, device, medium and electronic equipment Pending CN117608660A (en)

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