CN117608468A - Data moving method, device, equipment and computer readable storage medium - Google Patents

Data moving method, device, equipment and computer readable storage medium Download PDF

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Publication number
CN117608468A
CN117608468A CN202311368330.1A CN202311368330A CN117608468A CN 117608468 A CN117608468 A CN 117608468A CN 202311368330 A CN202311368330 A CN 202311368330A CN 117608468 A CN117608468 A CN 117608468A
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China
Prior art keywords
pointer
dma
request
command
dma request
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CN202311368330.1A
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Chinese (zh)
Inventor
段宗胜
孟繁毅
杨帆
陈帅
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Yusur Technology Co ltd
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Yusur Technology Co ltd
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Priority to CN202311368330.1A priority Critical patent/CN117608468A/en
Publication of CN117608468A publication Critical patent/CN117608468A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0647—Migration mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure relates to a data movement method, apparatus, device, and computer-readable storage medium. If the request pointer is different from the prefetch pointer, reading a DMA request command from a command buffer area of the processor according to the residual capacity of the temporary buffer memory in the DMA component, storing the DMA request command into the temporary buffer memory, updating the prefetch pointer according to the sum of the number of the read DMA request command and the numerical value of the prefetch pointer, taking the DMA request command out of the temporary buffer memory, executing data moving operation according to the DMA request command, and updating the completion pointer based on the DMA request command after the data moving operation is completed. The method and the device can support simultaneous issuing of a plurality of request commands, the processor stores the request commands in the command buffer area of the processor, the DMA component can acquire the request commands from the command buffer area of the processor, the interaction frequency of the processor and the DMA component is reduced, the load pressure of the processor is released, the performance of the DMA is improved, the multichannel DMA is supported, and the parallel processing capability of the DMA is improved.

Description

Data moving method, device, equipment and computer readable storage medium
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a data migration method, apparatus, device, and computer readable storage medium.
Background
Direct memory addressing (Direct Memory Access, DMA) components are an important component of computer systems that are typically used to assist processors in completing data movement, relieving the processor of load pressure. The data transfer mechanism directly from one storage unit to another storage unit can exist between different peripheral devices inside the same host, and can also realize data interaction between different hosts depending on a network or a bridge chip.
In the related art, when data is moved, after a processor issues a request command to a certain DMA component, the processor needs to continuously query the completion status of the DMA component, and after the request command is completed, the processor can issue a new request command to the DMA component. This single command loop approach cannot accommodate a large number of data movement scenarios. In order to alleviate the situation of stacking of data moving commands at the processor end, the number of DMA components can be increased, namely, the multi-channel DMA scheme can improve the data moving efficiency to a certain extent.
However, as the DMA channels increase, the processor needs to maintain more DMA component configuration information and poll more completion status, so that the interaction frequency between the processor and the DMA component is also higher, which causes the load on the processor to be greater and greater, resulting in a decrease in the data moving efficiency of the DMA component.
Disclosure of Invention
In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a data moving method, apparatus, device, and computer readable storage medium, so as to reduce the interaction frequency between a processor and a DMA component, reduce the load pressure of the processor, and improve the data moving efficiency of the DMA component.
In a first aspect, an embodiment of the present disclosure provides a data migration method, applied to a data migration assembly, the method including:
judging whether the request pointer is the same as the prefetch pointer;
if the request pointer is different from the prefetch pointer, reading a DMA request command from a command cache area of a processor according to the residual capacity of the temporary cache in the DMA component, storing the DMA request command into the temporary cache, and updating the prefetch pointer according to the sum of the number of the read DMA request commands and the numerical value of the prefetch pointer;
executing data moving operation according to the DMA request command;
and updating a completion pointer based on the DMA request command after the data transfer operation is completed.
In some embodiments, before the performing the data movement operation according to the DMA request command, the method further includes:
Judging whether the moving state of the data moving assembly is an idle state or not;
the executing the data moving operation according to the DMA request command includes:
and if the moving state is an idle state, executing data moving operation according to the DMA request command.
In some embodiments, after the performing the data movement operation according to the DMA request command, the method further includes:
acquiring a data transfer result, and judging whether the DMA request command is abnormal or not based on the data transfer result;
if the DMA request command is judged to be abnormal in execution, storing the DMA request command into an error command cache, and updating an error number register;
and updating a completion pointer based on the DMA request command after the error number register is updated.
In a second aspect, an embodiment of the present disclosure provides a data migration method, applied to a processor, including:
reading a request pointer and a completion pointer;
judging whether the request pointer is identical with the completion pointer;
if the request pointer is different from the completion pointer, determining the number of unfinished commands and the number of DMA request commands allowed to be newly issued based on the difference value between the request pointer and the completion pointer;
If the number of the newly issued DMA request commands is allowed to be larger than zero, filling the newly issued DMA request commands in the cache addresses corresponding to the request pointers, and updating the request pointers according to the number of the newly issued DMA request commands after the commands are filled.
In some embodiments, the method further comprises:
reading an error number register;
judging whether the error quantity in the error quantity register is zero or not;
if the error number is not zero, reading the abnormal DMA request command from the error command cache, processing the abnormal DMA request command, and continuing to execute the steps of reading the error number register and the later.
In some embodiments, after the determining whether the number of errors in the number of errors register is zero, the method further comprises:
if the error number is zero, reading a request pointer and a completion pointer;
judging whether the request pointer is identical with the completion pointer;
if the request pointer is different from the completion pointer, continuing to execute the steps of reading the error number register and the later until the request pointer is judged to be the same as the completion pointer.
In a third aspect, embodiments of the present disclosure provide a data mover for use with a data mover assembly, the apparatus comprising:
the first judging module is used for judging whether the request pointer is the same as the prefetch pointer or not;
a reading module, configured to read a DMA request command from a command buffer of a processor according to a remaining capacity of a temporary cache in the DMA component if the request pointer is different from the prefetch pointer, store the DMA request command into the temporary cache, and update the prefetch pointer according to a sum of a number of the read DMA request commands and a numerical value of the prefetch pointer;
the execution module is used for executing data moving operation according to the DMA request command;
and the first updating module is used for updating the completion pointer based on the DMA request command after the data moving operation is completed.
In a fourth aspect, an embodiment of the present disclosure provides a data moving apparatus, applied to a processor, the apparatus including:
the first reading module is used for reading the request pointer and the completion pointer;
the first judging module is used for judging whether the request pointer is the same as the completion pointer;
the determining module is used for determining the number of unfinished commands and the number of DMA request commands allowed to be newly issued based on the difference value between the request pointer and the completion pointer if the request pointer is different from the completion pointer;
And the second judging module is used for filling the newly issued DMA request command at the cache address corresponding to the request pointer if the number of the newly issued DMA request command is allowed to be larger than zero, and updating the request pointer according to the number of the newly issued DMA request command after the command is filled.
In a fifth aspect, embodiments of the present disclosure provide an electronic device, including:
a memory;
a processor; and
a computer program;
wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method according to the first aspect.
In a sixth aspect, embodiments of the present disclosure provide a computer readable storage medium having stored thereon a computer program for execution by a processor to implement the method of the first aspect.
In a seventh aspect, the presently disclosed embodiments also provide a computer program product comprising a computer program or instructions which, when executed by a processor, implement the method as described in the first aspect.
The data moving method, device, equipment and computer readable storage medium provided by the embodiment of the disclosure are characterized in that whether a request pointer is identical to a prefetch pointer is judged, if the request pointer is not identical to the prefetch pointer, a DMA request command is read from a command buffer area of a processor according to the residual capacity of a temporary buffer memory in a DMA component, the DMA request command is stored in the temporary buffer memory, the prefetch pointer is updated according to the sum of the number of the read DMA request commands and the numerical value of the prefetch pointer, the DMA request command is taken out from the temporary buffer memory, and a data moving operation is executed according to the DMA request command, and after the data moving operation is completed, the pointer is updated based on the DMA request command. Compared with the prior art, the method and the device can support simultaneous issuing of a plurality of request commands through a cyclic pointer mechanism of a request pointer, a prefetch pointer and a completion pointer, the processor stores the request commands in a command cache area of the processor, a subsequent DMA component can acquire the request commands from the command cache area of the processor, the interaction frequency of the processor and the DMA component is reduced, the completion pointer is updated based on the DMA request commands, the processor does not need to inquire the completion state of each request command, only needs to periodically inquire the update condition of the completion pointer, the load pressure of the processor is released, the performance of the DMA is further improved, the multi-channel DMA is supported, and the parallel processing capability of the DMA is improved. Each channel in the multi-channel DMA adopts the same circulating pointer to carry out DMA state interaction, so that the speed of issuing commands by a processor can be greatly improved, and the number of times of completing state polling is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a flow chart of a data movement method according to an embodiment of the present disclosure;
FIG. 2 is a diagram of a DMA cycle pointer interaction mechanism provided by embodiments of the present disclosure;
FIG. 3 is a flowchart of a data movement method according to another embodiment of the present disclosure;
FIG. 4 is a flowchart of a data movement method according to another embodiment of the present disclosure;
FIG. 5 is a flowchart of a data movement method according to another embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a data transferring device according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a data moving device according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.
Direct memory addressing (Direct Memory Access, DMA) components are an important component of computer systems that are typically used to assist processors in completing data movement, relieving the processor of load pressure. The data transfer mechanism directly from one storage unit to another storage unit can exist between different peripheral devices inside the same host, and can also realize data interaction between different hosts depending on a network or a bridge chip.
In the related art, when data is moved, after a processor issues a request command to a certain DMA component, the processor needs to continuously query the completion status of the DMA component, and after the request command is completed, the processor can issue a new request command to the DMA component. This single command loop approach cannot accommodate a large number of data movement scenarios. In order to alleviate the situation of stacking of data moving commands at the processor end, the number of DMA components can be increased, namely, the multi-channel DMA scheme can improve the data moving efficiency to a certain extent.
However, as the DMA channels increase, the processor needs to maintain more DMA component configuration information and poll more completion status, so that the interaction frequency between the processor and the DMA component is also higher, which causes the load on the processor to be greater and greater, resulting in a decrease in the data moving efficiency of the DMA component. In view of this problem, embodiments of the present disclosure provide a data migration method, which is described below in connection with specific embodiments.
Fig. 1 is a flowchart of a data moving method according to an embodiment of the disclosure. The execution subject of the method is a data mover. The data transfer component may be a DMA component or other data transfer component. The method can be applied to a scene of moving data, and can also be applied to a scene of moving data based on a DMA request command. It can be appreciated that the data migration method provided by the embodiment of the present disclosure may also be applied in other scenarios.
The framework of a DMA component generally comprises three parts: the device comprises a configuration unit, a source data unit and a destination data unit. The configuration unit is responsible for receiving a data moving request command issued by the processor and recording a completion state for the processor to inquire; the source data unit reads data from the source equipment according to the command analyzed by the configuration unit; and the destination data unit sends the data read by the source data unit to the terminal equipment.
The following describes the data migration method shown in fig. 1, which is applied to the data migration assembly, and includes the following specific steps:
s101, judging whether the request pointer is identical with the prefetch pointer.
The data transfer unit may be a DMA unit or other data transfer units, and is not limited herein. In this embodiment, the data moving component is exemplified by a DMA component, as shown in fig. 2, where the request pointer, the prefetch pointer, and the completion pointer together form a DMA cycle pointer, the request pointer is used to indicate a position where a new request command is to be issued, the prefetch pointer is used to indicate a position where a command is to be prefetched, the completion pointer is used to indicate a position where a command is to be completed, and according to the pointers, an address where the DMA command is stored in a command buffer of the processor can be converted. The DMA component determines whether the request pointer is the same as the prefetch pointer. Specifically, the DMA unit reads the request pointer and the prefetch pointer, and then determines whether the request pointer and the prefetch pointer are identical.
S102, if the request pointer is different from the prefetch pointer, reading a DMA request command from a command cache area of a processor according to the residual capacity of the temporary cache in the DMA component, storing the DMA request command into the temporary cache, and updating the prefetch pointer according to the sum of the number of the read DMA request commands and the numerical value of the prefetch pointer.
If the DMA component judges that the request pointer is different from the prefetch pointer, indicating that a request command to be processed exists, the DMA component can read the DMA request command from a command cache area of a processor according to the internal cache condition of the DMA component, store the DMA request command into a temporary cache, and meanwhile, add the current numerical value of the prefetch pointer with the read DMA request command number according to the read DMA request command number to obtain a new prefetch pointer. As shown in fig. 2, the DMA component may read command 1 from a command buffer of the processor, i.e., a processor DMA request command area, store command 1 into an internal cache, and update a prefetch pointer to a prefetch pointer register. In some embodiments, if the DMA component determines that the request pointer is the same as the prefetch pointer, indicating that there is no request command to process, then no processing is required. As shown in fig. 2, the processor stores the request command to be processed in the command buffer of the processor, for example, stores the command 1, the command 2, the command … … and the command n in the command buffer of the processor, that is, the DMA request command of the processor, and the DMA component reads the DMA request command from the command buffer of the processor, stores the DMA request command in the internal buffer and updates the DMA request command to the prefetch pointer.
S103, taking out the DMA request command from the temporary cache, and executing data moving operation according to the DMA request command.
After the DMA request command is stored in the temporary cache, the DMA component takes the DMA request command out of the temporary cache and executes data moving operation according to the DMA request command.
S104, updating a completion pointer based on the DMA request command after the data transfer operation is completed.
Further, when the data transfer operation is completed, the DMA component updates a completion pointer based on the DMA request command. Specifically, the DMA component updates the completion pointer by 1 to the completion pointer register after each data movement is completed, indicating that a DMA request command has been completed, and the processor does not need to constantly query the completion status of the DMA request command, thereby relieving the load pressure of the processor.
According to the embodiment of the disclosure, whether a request pointer is identical to a prefetch pointer or not is judged, if the request pointer is not identical to the prefetch pointer, a DMA request command is read from a command cache area of a processor according to the residual capacity of a temporary cache in a DMA component, the DMA request command is stored in the temporary cache, the prefetch pointer is updated according to the sum of the number of the read DMA request commands and the numerical value of the prefetch pointer, the DMA request command is taken out from the temporary cache, and a data moving operation is executed according to the DMA request command, and after the data moving operation is completed, the pointer is updated based on the DMA request command. Compared with the prior art, the method and the device can support simultaneous issuing of a plurality of request commands through a cyclic pointer mechanism of a request pointer, a prefetch pointer and a completion pointer, the processor stores the request commands in a command cache area of the processor, a subsequent DMA component can acquire the request commands from the command cache area of the processor, the interaction frequency of the processor and the DMA component is reduced, the completion pointer is updated based on the DMA request commands, the processor does not need to inquire the completion state of each request command, only needs to periodically inquire the update condition of the completion pointer, the load pressure of the processor is released, the performance of the DMA is further improved, the multi-channel DMA is supported, and the parallel processing capability of the DMA is improved. Each channel in the multi-channel DMA adopts the same circulating pointer to carry out DMA state interaction, so that the speed of issuing commands by a processor can be greatly improved, and the number of times of completing state polling is reduced.
Fig. 3 is a flowchart of a data moving method according to another embodiment of the present disclosure, where the method is applied to a data moving component, and as shown in fig. 3, the method includes the following steps:
s301, judging whether the request pointer is identical with the prefetch pointer.
Specifically, the implementation process and principle of S301 and S101 are identical, and will not be described herein.
S302, if the request pointer is different from the prefetch pointer, reading a DMA request command from a command buffer area of a processor according to the residual capacity of the temporary buffer memory in the DMA component, storing the DMA request command into the temporary buffer memory, and updating the prefetch pointer according to the sum of the number of the read DMA request commands and the numerical value of the prefetch pointer.
Specifically, the implementation process and principle of S302 and S102 are consistent, and will not be described herein.
S303, judging whether the moving state of the data moving component is an idle state or not.
In this embodiment, the data transfer component is exemplified as a DMA component, and the DMA component determines whether the current transfer state is an idle state.
S304, if the moving state is an idle state, executing data moving operation according to the DMA request command.
And if the moving state is judged to be the idle state, executing data moving operation according to the DMA request command. In some embodiments, if the move status is determined to be a non-idle status, it is indicated that the data move operation of the last DMA request command has not been completed and needs to wait.
S305, acquiring a data transfer result, and judging whether the DMA request command is abnormal or not based on the data transfer result.
In this embodiment, the DMA module obtains a data movement result, and further determines whether the DMA request command is abnormal according to the data movement result. In some embodiments, if the data transfer result is abnormal, determining that the DMA request command is abnormal; and if the data moving result is normal, judging that the DMA request command is normally executed.
S306, if the DMA request command is judged to be abnormal in execution, the DMA request command is stored into an error command cache, and an error number register is updated.
In this embodiment, if the DMA component determines that the DMA request command is abnormal, the DMA request command is stored in an error command buffer, and the error number register is updated. Specifically, if the data move operation detects an exception, and cannot be completed, the DMA component stores the abnormal DMA request command in the error command cache and updates the error number by 1 to the error number register. Optionally, the DMA component may feed back an abnormal condition of the DMA request command to the processor, and process the abnormal DMA request command through an exception handling interface provided by the processor, thereby improving system stability.
S307, updating a completion pointer based on the DMA request command after updating the error number register.
Further, the DMA component updates the completion pointer when the error number register is updated.
And S308, if the DMA request command is judged to be normally executed, updating a completion pointer based on the DMA request command after the data transfer operation is completed.
If the DMA request command is judged to be normally executed, after the data moving operation is completed, the DMA component updates a completion pointer based on the DMA request command. Specifically, the DMA component updates the completion pointer based on the DMA request command, indicating that the DMA request command has been completed, and the processor does not need to continually query the completion status of the DMA request command, thereby relieving the load pressure on the processor.
According to the embodiment of the disclosure, by judging whether the request pointer is identical to the prefetch pointer, if the request pointer is not identical to the prefetch pointer, reading a DMA request command from a command cache area of a processor according to the residual capacity of the internal cache, storing the DMA request command into the internal cache, and updating the prefetch pointer. And then judging whether the moving state of the data moving component is an idle state, and if the moving state is the idle state, executing data moving operation according to the DMA request command. Further, a data transfer result is obtained, whether the DMA request command is abnormal or not is judged based on the data transfer result, if the DMA request command is abnormal, the DMA request command is stored into an error command cache, and an error number register is updated. And updating a completion pointer based on the DMA request command after the error number register is updated. Compared with the prior art, the embodiment of the disclosure can support the simultaneous issuing of a plurality of request commands through a cyclic pointer mechanism of the request pointer, the prefetch pointer and the completion pointer, reduce the interaction frequency between the processor and the DMA component, update the completion pointer based on the DMA request commands, and the processor does not need to inquire the completion state of each request command, only needs to periodically inquire the completion pointer and the update condition of the error number register, so that the load pressure of the processor is released, the performance of the DMA is further improved, the multichannel DMA is supported, and the parallel processing capability of the DMA is improved.
Fig. 4 is a flowchart of a data moving method according to an embodiment of the present disclosure. The execution subject of the method is a processor. The method can be applied to a scene of moving data, and can also be applied to a scene of moving data based on a DMA request command. It can be appreciated that the data migration method provided by the embodiment of the present disclosure may also be applied in other scenarios.
The following describes a data migration method shown in fig. 4, which is applied to a processor, and includes the following specific steps:
s401, reading a request pointer and a completion pointer.
As shown in fig. 2, the request pointer, the prefetch pointer, and the completion pointer together form a DMA loop pointer, where the request pointer is used to indicate a position where a new request command is to be issued, the prefetch pointer is used to indicate a position where a command is to be prefetched, the completion pointer is used to indicate a position where a command is to be completed, and according to the pointers, an address where the DMA command is stored in a command buffer of the processor can be converted.
The relationship between the request pointer and the completion pointer is used to provide the basis for the processor to determine whether the DMA is complete.
When the two are equal, the instruction issued by the processor is indicated, and the DMA component is completely executed.
When the two are not equal, the request pointer-the completion pointer=the difference value, when the difference value is positive, the difference value is the number of unfinished commands, and the (cyclic pointer depth-the difference value-1) is the number of DMA request commands allowed to be newly issued; when the difference is negative, (the loop pointer depth + the difference) is the number of outstanding commands, (the absolute value of the difference-1) is the number of DMA request commands allowed to be issued newly.
S402, judging whether the request pointer is identical with the completion pointer.
After reading the values of the request pointer and the completion pointer registers, the processor determines whether the request pointer and the completion pointer are the same.
S403, if the request pointer is different from the completion pointer, determining the number of outstanding commands and the number of DMA request commands allowed to be newly issued based on the difference value between the request pointer and the completion pointer.
If the request pointer is judged to be different from the completion pointer, indicating that the DMA request command is not completely completed, and determining the number of incomplete commands and the number of DMA request commands allowed to be newly issued based on the difference value between the request pointer and the completion pointer.
Optionally, the newly issued DMA request command number= (loop pointer total depth-outstanding command number-1) is allowed.
In some embodiments, if the request pointer is determined to be the same as the completion pointer, indicating that the pending request command has been fully executed, there is no pending request command.
S404, if the number of the newly issued DMA request commands is allowed to be larger than zero, filling the newly issued DMA request commands in the cache addresses corresponding to the request pointers, and updating the request pointers according to the number of the newly issued DMA request commands after the commands are filled.
If the number of the newly issued DMA request commands is allowed to be larger than zero, the processor fills the newly issued DMA request commands in the cache addresses corresponding to the request pointers, and after the commands are filled, the request pointers are updated according to the sum of the number of the newly issued DMA request commands and the numerical value of the request pointers.
According to the embodiment of the disclosure, whether the request pointer is identical to the completion pointer is judged by reading the request pointer and the completion pointer, if the request pointer is not identical to the completion pointer, the number of outstanding commands and the number of DMA request commands allowed to be newly issued are determined based on the difference value between the request pointer and the completion pointer, if the number of DMA request commands allowed to be newly issued is greater than zero, the newly issued DMA request commands are filled in the cache addresses corresponding to the request pointer, and after the commands are filled, the request pointer is updated according to the number of the newly issued DMA request commands. Compared with the prior art, the method and the device can support simultaneous issuing of a plurality of request commands, store the request commands in the command buffer area of the processor, acquire the request commands from the command buffer area of the processor by the subsequent DMA component, reduce the interaction frequency of the processor and the DMA component, release the load pressure of the processor, further improve the performance of the DMA, support multi-channel DMA and improve the parallel processing capability of the DMA through a cyclic pointer mechanism of the request pointer, the prefetch pointer and the completion pointer. Each channel in the multi-channel DMA adopts the same circulating pointer to carry out DMA state interaction, so that the speed of issuing commands by a processor can be greatly improved, and the number of times of completing state polling is reduced.
Fig. 5 is a flowchart of a data moving method according to another embodiment of the present disclosure, where the method is applied to a processor, and as shown in fig. 5, the method includes the following steps:
s501, a read request pointer and a completion pointer.
Specifically, the implementation process and principle of S501 and S401 are identical, and will not be described herein.
S502, judging whether the request pointer is the same as the completion pointer, if so, executing S511, otherwise, executing S503.
Specifically, the implementation process and principle of S502 and S402 are consistent, and will not be described herein.
S503, if the request pointer is different from the completion pointer, determining the number of outstanding commands and the number of DMA request commands allowed to be newly issued based on the difference value between the request pointer and the completion pointer.
Specifically, the implementation procedure and principle of S503 and S403 are consistent, and will not be described herein.
S504, if the number of the newly issued DMA request commands is allowed to be larger than zero, filling the newly issued DMA request commands in the cache addresses corresponding to the request pointers, and updating the request pointers according to the number of the newly issued DMA request commands after the commands are filled.
Specifically, the implementation process and principle of S504 and S404 are consistent, and will not be described herein.
S505, reading an error quantity register.
In this embodiment, the processor reads the error number register, in which the error number of the DMA request command, that is, the number of abnormal DMA request commands is recorded.
S506, judging whether the error number in the error number register is zero, if so, executing S508, otherwise executing S507.
In this embodiment, the processor determines whether the number of errors in the error number register is zero.
S507, if the error number is not zero, reading the abnormal DMA request command from the error command cache, processing the abnormal DMA request command, and continuing to execute the steps of reading the error number register and the later.
In this embodiment, if it is determined that the number of errors is not zero, the abnormal DMA request command is read from the error command buffer, and the abnormal DMA request command is processed, and steps S505 and following S505 are continuously performed. And reading an abnormal DMA request command from the error command cache by the processor every 1 time, processing the abnormal DMA request command, subtracting 1 from the error number recorded by the error number register, and the like until the error number is 0. Optionally, the processing of the abnormal DMA request command may be performed by adopting processing measures such as command retransmission or abnormal alarm, so as to help to improve stability of the system.
In some embodiments, when the processor processes the abnormal DMA request command, the abnormal DMA request command may be restored to the command buffer of the processor, and the DMA component may re-read the abnormal DMA request command from the command buffer of the processor, thereby performing a data movement operation on the abnormal DMA request command. In some embodiments, the abnormal DMA request command may also be processed based on an abnormal processing interface, so as to improve system stability.
S508, if the error number is zero, the request pointer and the completion pointer are read.
If the number of errors is determined to be zero, the processor reads the request pointer and the completion pointer.
S509, judging whether the request pointer is the same as the completion pointer, if so, executing S511, otherwise, executing S505.
After reading the request pointer and the completion pointer, the processor determines whether the request pointer and the completion pointer are the same. If the request pointer is different from the completion pointer, continuing to execute the steps of reading the error number register and the later until the request pointer is judged to be the same as the completion pointer. If it is determined that the request pointer is not identical to the completion pointer, continuing to execute step S505 and steps after S505; if it is determined that the request pointer is identical to the completion pointer, S510 is performed.
S510, ending.
If the request pointer is the same as the completion pointer, the current flow is ended, the request pointer and the completion pointer are continuously read, and the new execution flow is started in the subsequent steps.
According to the embodiment of the disclosure, whether the request pointer is identical to the completion pointer is judged by reading the request pointer and the completion pointer, if the request pointer is not identical to the completion pointer, the number of outstanding commands and the number of DMA request commands allowed to be newly issued are determined based on the difference value between the request pointer and the completion pointer, if the number of DMA request commands allowed to be newly issued is greater than zero, the newly issued DMA request commands are filled in the cache addresses corresponding to the request pointer, and after the commands are filled, the request pointer is updated according to the number of the newly issued DMA request commands. Further, reading an error number register, judging whether the error number in the error number register is zero, if the error number is not zero, reading an abnormal DMA request command from an error command cache, processing the abnormal DMA request command, and continuing to execute the steps of reading the error number register and the later; if the error number is zero, reading a request pointer and a completion pointer, judging whether the request pointer is identical to the completion pointer, if the request pointer is not identical to the completion pointer, continuing to execute the steps of reading the error number register and the later until the request pointer is judged to be identical to the completion pointer. Compared with the prior art, the embodiment of the disclosure can support the simultaneous issuing of a plurality of request commands through a cyclic pointer mechanism of a request pointer, a prefetch pointer and a completion pointer, reduce the interaction frequency of a processor and a DMA component, release the load pressure of the processor, further improve the performance of the DMA, support multi-channel DMA and improve the parallel processing capability of the DMA. And, the present disclosure determines whether the number of errors in the error number register is zero. If the number of errors is not zero, reading the abnormal DMA request command from the error command cache, and processing the abnormal DMA request command, so that the abnormality can be processed, and the stability of the system is improved by adopting processing measures such as command retransmission or abnormality alarm.
Fig. 6 is a schematic structural diagram of a data transferring device according to an embodiment of the disclosure. The data mover may be a data mover assembly as described in the above embodiments, or the data mover may be a component or assembly of the data mover assembly. The data moving device provided in the embodiment of the present disclosure may execute the processing flow provided in the embodiment of the data moving method, as shown in fig. 6, where the data moving device 60 includes: a first judging module 61, a reading module 62, an executing module 63, a first updating module 64; the first determining module 61 is configured to determine whether the request pointer is the same as the prefetch pointer; the reading module 62 is configured to read a DMA request command from a command buffer of the processor according to a remaining capacity of the temporary cache in the DMA module if the request pointer is different from the prefetch pointer, store the DMA request command into the temporary cache, and update the prefetch pointer according to a sum of a number of the read DMA request command and a value of the prefetch pointer; the execution module 63 is configured to take out a DMA request command from the temporary cache, and execute a data movement operation according to the DMA request command; the first updating module 64 is configured to update a completion pointer based on the DMA request command after the data transfer operation is completed.
Optionally, before the executing module 63 executes the data movement operation according to the DMA request command, the data movement device 60 further includes: a second judgment module 65; the second judging module 65 is configured to judge whether the moving state of the data moving component is an idle state;
the execution module 63 is specifically configured to, when executing the data moving operation according to the DMA request command: and if the moving state is an idle state, executing data moving operation according to the DMA request command.
Optionally, after the executing module 63 executes the data movement operation according to the DMA request command, the data movement device 60 further includes: a third judging module 66, a storing module 67, and a second updating module 68; the third judging module 66 is configured to obtain a data movement result, and judge whether the DMA request command is abnormal based on the data movement result; the storing module 67 is configured to store the DMA request command into an error command cache and update an error number register if it is determined that the DMA request command is abnormal to execute; the second update module 68 is configured to update the completion pointer based on the DMA request command after the error number register is updated.
The data moving device of the embodiment shown in fig. 6 may be used to implement the technical solution of the above method embodiment, and its implementation principle and technical effects are similar, and will not be described herein again.
Fig. 7 is a schematic structural diagram of a data moving device according to an embodiment of the disclosure. The data mover may be a processor as described in the above embodiments, or the data mover may be a component or assembly in the processor. The data moving device provided in the embodiment of the present disclosure may execute the processing flow provided in the embodiment of the data moving method, as shown in fig. 7, where the data moving device 70 includes: a first reading module 71, a first judging module 72, a determining module 73, a second judging module 74; the first reading module 71 is configured to read the request pointer and the completion pointer; the first judging module 72 is configured to judge whether the request pointer is the same as the completion pointer; the determining module 73 is configured to determine, if the request pointer is different from the completion pointer, a number of outstanding commands and a number of DMA request commands allowed to be newly issued based on a difference between the request pointer and the completion pointer; the second determining module 74 is configured to fill the newly issued DMA request command at the cache address corresponding to the request pointer if the number of DMA request commands allowed to be newly issued is greater than zero, and update the request pointer according to the number of DMA request commands newly issued after the command is filled.
Optionally, the data moving device 70 further includes: a second reading module 75, a third judging module 76, and a first processing module 77; the second reading module 75 is used for reading the error number register; the third determining module 76 is configured to determine whether the number of errors in the error number register is zero; the first processing module 77 is configured to read the abnormal DMA request command from the error command buffer and process the abnormal DMA request command if the error number is not zero, and continue to execute the steps of reading the error number register and the following steps.
Optionally, after the third determining module 76 determines whether the number of errors in the number of errors register is zero, the data moving device 70 further includes: a third reading module 78, a second processing module 79; the third reading module 78 is configured to read the request pointer and the completion pointer if the number of errors is zero, and determine whether the request pointer and the completion pointer are the same; the second processing module 79 is configured to, if the request pointer is different from the completion pointer, continue to execute the steps of reading the error number register and thereafter until it is determined that the request pointer is the same as the completion pointer.
The data moving device of the embodiment shown in fig. 7 may be used to implement the technical solution of the above method embodiment, and its implementation principle and technical effects are similar, and will not be described herein again.
Fig. 8 is a schematic structural diagram of an electronic device in an embodiment of the disclosure. Referring now in particular to fig. 8, a schematic diagram of an electronic device 600 suitable for use in implementing embodiments of the present disclosure is shown. The electronic device shown in fig. 8 is merely an example and should not be construed to limit the functionality and scope of use of the disclosed embodiments.
As shown in fig. 8, the electronic device 600 may include a processing means (e.g., a central processing unit, a graphics processor, etc.) 601 that may perform various suitable actions and processes to implement the data migration method of the embodiments as described in the present disclosure according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage means 608 into a Random Access Memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the electronic apparatus 600 are also stored. The processing device 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
In general, the following devices may be connected to the I/O interface 605: input devices 606 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, and the like; an output device 607 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 608 including, for example, magnetic tape, hard disk, etc.; and a communication device 609. The communication means 609 may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data. While fig. 8 shows an electronic device 600 having various means, it is to be understood that not all of the illustrated means are required to be implemented or provided. More or fewer devices may be implemented or provided instead.
In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a non-transitory computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts, thereby implementing the data migration method as described above. In such an embodiment, the computer program may be downloaded and installed from a network via communication means 609, or from storage means 608, or from ROM 602. The above-described functions defined in the methods of the embodiments of the present disclosure are performed when the computer program is executed by the processing device 601.
It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.
In addition, the embodiment of the disclosure also provides a vehicle, including: a memory; a processor; a computer program; wherein the computer program is stored in the memory and configured to be executed by the processor to implement the data movement method as described above.
In some implementations, the clients, servers may communicate using any currently known or future developed network protocol, such as HTTP (HyperText Transfer Protocol ), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), the internet (e.g., the internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed networks.
The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.
The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to:
Judging whether the request pointer is the same as the prefetch pointer;
if the request pointer is different from the prefetch pointer, reading a DMA request command from a command cache area of a processor according to the residual capacity of the temporary cache in the DMA component, storing the DMA request command into the temporary cache, and updating the prefetch pointer according to the sum of the number of the read DMA request commands and the numerical value of the prefetch pointer;
taking out a DMA request command from the temporary cache, and executing data moving operation according to the DMA request command;
and updating a completion pointer based on the DMA request command after the data transfer operation is completed.
Alternatively, the electronic device may perform other steps described in the above embodiments when the above one or more programs are executed by the electronic device.
Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including, but not limited to, an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.
The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a Complex Programmable Logic Device (CPLD), and the like.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The foregoing description is only of the preferred embodiments of the present disclosure and description of the principles of the technology being employed. It will be appreciated by persons skilled in the art that the scope of the disclosure referred to in this disclosure is not limited to the specific combinations of features described above, but also covers other embodiments which may be formed by any combination of features described above or equivalents thereof without departing from the spirit of the disclosure. Such as those described above, are mutually substituted with the technical features having similar functions disclosed in the present disclosure (but not limited thereto).
Moreover, although operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

Claims (10)

1. A method of data movement applied to a data movement assembly, the method comprising:
judging whether the request pointer is the same as the prefetch pointer;
if the request pointer is different from the prefetch pointer, reading a DMA request command from a command cache area of a processor according to the residual capacity of the temporary cache in the DMA component, storing the DMA request command into the temporary cache, and updating the prefetch pointer according to the sum of the number of the read DMA request commands and the numerical value of the prefetch pointer;
taking out a DMA request command from the temporary cache, and executing data moving operation according to the DMA request command;
and updating a completion pointer based on the DMA request command after the data transfer operation is completed.
2. The method of claim 1, wherein prior to performing the data move operation in accordance with the DMA request command, the method further comprises:
Judging whether the moving state of the data moving assembly is an idle state or not;
the executing the data moving operation according to the DMA request command includes:
and if the moving state is an idle state, executing data moving operation according to the DMA request command.
3. The method of claim 1, wherein after performing the data movement operation in accordance with the DMA request command, the method further comprises:
acquiring a data transfer result, and judging whether the DMA request command is abnormal or not based on the data transfer result;
if the DMA request command is judged to be abnormal in execution, storing the DMA request command into an error command cache, and updating an error number register;
and updating a completion pointer based on the DMA request command after the error number register is updated.
4. A method of data movement, for use with a processor, the method comprising:
reading a request pointer and a completion pointer;
judging whether the request pointer is identical with the completion pointer;
if the request pointer is different from the completion pointer, determining the number of unfinished commands and the number of DMA request commands allowed to be newly issued based on the difference value between the request pointer and the completion pointer;
If the number of the newly issued DMA request commands is allowed to be larger than zero, filling the newly issued DMA request commands in the cache addresses corresponding to the request pointers, and updating the request pointers according to the number of the newly issued DMA request commands after the commands are filled.
5. The method according to claim 4, wherein the method further comprises:
reading an error number register;
judging whether the error quantity in the error quantity register is zero or not;
if the error number is not zero, reading the abnormal DMA request command from the error command cache, processing the abnormal DMA request command, and continuing to execute the steps of reading the error number register and the later.
6. The method of claim 5, wherein after said determining if the number of errors in said number of errors register is zero, said method further comprises:
if the error number is zero, reading a request pointer and a completion pointer;
judging whether the request pointer is identical with the completion pointer;
if the request pointer is different from the completion pointer, continuing to execute the steps of reading the error number register and the later until the request pointer is judged to be the same as the completion pointer.
7. A data mover for use with a data mover assembly, the apparatus comprising:
the first judging module is used for judging whether the request pointer is the same as the prefetch pointer or not;
a reading module, configured to read a DMA request command from a command buffer of a processor according to a remaining capacity of a temporary cache in the DMA component if the request pointer is different from the prefetch pointer, store the DMA request command into the temporary cache, and update the prefetch pointer according to a sum of a number of the read DMA request commands and a numerical value of the prefetch pointer;
the execution module is used for taking out a DMA request command from the temporary cache and executing data moving operation according to the DMA request command;
and the first updating module is used for updating the completion pointer based on the DMA request command after the data moving operation is completed.
8. A data mover for use with a processor, the apparatus comprising:
the first reading module is used for reading the request pointer and the completion pointer;
the first judging module is used for judging whether the request pointer is the same as the completion pointer;
the determining module is used for determining the number of unfinished commands and the number of DMA request commands allowed to be newly issued based on the difference value between the request pointer and the completion pointer if the request pointer is different from the completion pointer;
And the second judging module is used for filling the newly issued DMA request command at the cache address corresponding to the request pointer if the number of the newly issued DMA request command is allowed to be larger than zero, and updating the request pointer according to the number of the newly issued DMA request command after the command is filled.
9. An electronic device, comprising:
a memory;
a processor; and
a computer program;
wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method of any one of claims 1-6.
10. A computer readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the method according to any of claims 1-6.
CN202311368330.1A 2023-10-20 2023-10-20 Data moving method, device, equipment and computer readable storage medium Pending CN117608468A (en)

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Application Number Priority Date Filing Date Title
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Country Link
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