CN117608348A - Voltage supply circuit and method of converting multiple voltage levels - Google Patents

Abstract

An embodiment of the present disclosure provides a voltage supply circuit and a method of converting a plurality of voltage levels. The voltage supply circuit comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor and a voltage modulation circuit. The first NMOS transistor takes a first control signal and a grounding voltage as a grid electrode and a source electrode. The second NMOS transistor takes a second control signal complementary to the first control signal and a grounding voltage as a grid electrode and a source electrode. The first and second PMOS transistors have a first power supply voltage as a source. The voltage modulation circuit is coupled between the first to second PMOS transistors and the first to second NMOS transistors to provide a first intermediate signal based on the first control signal and the second control signal. In some embodiments, the first intermediate signal has a first logic state corresponding to a first supply voltage or a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage.

Description

Voltage supply circuit and method of converting multiple voltage levels

Technical field

An embodiment of the present disclosure relates to a voltage supply circuit and a method of converting multiple voltage levels, and in particular, to a voltage supply circuit having a core device and a method of converting multiple voltage levels.

Background technique

The semiconductor industry has experienced rapid development due to the increasing integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density comes from multiple reductions in the minimum feature size, allowing more components to be integrated into a specific area.

Contents of the invention

An embodiment of the present disclosure provides a voltage supply circuit, including a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a voltage modulation circuit and a power switch control circuit. The first NMOS transistor has the first control signal as a gate electrode and the ground voltage as a source electrode. The second NMOS transistor has a second control signal complementary to the first control signal as a gate electrode and a ground voltage as a source electrode. The first PMOS transistor has the first power supply voltage as its source. The second PMOS transistor has the first power supply voltage as its source. The voltage modulation circuit is coupled between the first to second PMOS transistors and the first to second NMOS transistors for providing a first intermediate signal based on the first control signal and the second control signal, wherein the first The intermediate signal assumes a first logic state corresponding to a first supply voltage, or a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage. The power switch control circuit is used to output a third intermediate signal, and the third intermediate signal presents a first logical state corresponding to the second power supply voltage, or a second logical state corresponding to the ground voltage.

An embodiment of the present disclosure provides a voltage supply circuit including a first partial voltage generator, a first level converter, a plurality of first inverters and a plurality of second inverters. The first partial voltage generator is used to generate a first voltage, and the first voltage is a first small part of the power supply voltage. The first level converter is powered by the power supply voltage and used to generate a first intermediate signal based on the first voltage. A plurality of first inverters are coupled between the power supply voltage and the first voltage to couple the power supply voltage to the output node based on the first intermediate signal. A plurality of second inverters are coupled between the first voltage and ground voltage or between the second voltage and ground voltage to couple the output node to the ground voltage, where the second voltage is a second fraction of the supply voltage.

An embodiment of the present disclosure provides a method for converting multiple voltage levels, including the following steps: receiving a first partial voltage as a first small portion of a power supply voltage; providing a first intermediate signal based on the first partial voltage, the first intermediate signal The signal presents a first logic state corresponding to the power supply voltage or a second logic state corresponding to the first partial voltage; and based on the first intermediate signal, an output voltage is output, and the output voltage is the power supply voltage or the ground voltage.

Description of drawings

Aspects of the present case will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, each feature is not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is an example circuit diagram of a voltage supply circuit according to some embodiments of the present disclosure;

FIG. 2 is a waveform diagram of various signals presented by the voltage supply circuit of FIG. 1 according to some embodiments of the present disclosure;

3 is an example circuit diagram of another voltage supply circuit according to some embodiments of the present disclosure;

FIG. 4 is an example circuit diagram of yet another voltage supply circuit according to some embodiments of the present disclosure;

FIG. 5 is an example circuit diagram of yet another voltage supply circuit according to some embodiments of the present disclosure;

FIG. 6 is an example circuit diagram of a voltage level converter that may be implemented by any of the voltage supply circuits of FIGS. 1 and 3-5 in accordance with some embodiments of the present disclosure;

FIG. 7 is an example circuit diagram of a partial voltage generator that may be implemented by the voltage supply circuit of FIG. 1 according to some embodiments of the present disclosure;

FIG. 8 is an example circuit diagram of a partial voltage generator that may be implemented by any of the voltage supply circuits of FIGS. 3-5 in accordance with some embodiments of the present disclosure; and

9 is a flowchart illustrating an example method for operating a voltage supply circuit of an embodiment of the present disclosure, in accordance with some embodiments of the present disclosure.

【Symbol Description】

100,300,400,500: Voltage supply circuit

700,800,810,850: Voltage generator

900:Method

902,904,906,908,910: Operation

C1,C2,L1,L2: voltage level converter

G1: The first part of the voltage generator

G2: The second part of the voltage generator

HVDD: first part voltage

I1～I4: first inverter

I5～I9: second inverter

I10～I20: inverter

LVDD: second part voltage

M1, M2, M5, M6, M9, M10: NMOS transistors

M19, M23～M25, M30: NMOS transistor

M3, M4, M7, M8: PMOS transistors

M11～M18, M20～M22: PMOS transistor

MG: partial voltage generator

MVDD: partial voltage

N1~N11: nodes

P1, P2: Power switch control circuit

PCGATE:signal

PD, PS: control signal

PV,qgb,Vx: intermediate signal

psvq_i: second intermediate signal

pstb1,qg2b_i: output

qg2b_ii: intermediate signal

R1～R5, R1’, R2’: resistors

S1: Voltage modulation circuit

V1:Part One

V2:Part Two

V3:Part Three

VD1: voltage detector

VDD: logic voltage

VDDQ: output voltage

VQPS: power supply voltage

Vref_H, Vref_L: reference voltage

VSS: ground voltage

YSELB, YSELB’: control signal

Detailed ways

The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present application. Of course, these are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include that additional features may be formed between the first feature and the second feature. An embodiment in which the first feature and the second feature are not in direct contact between the two features. Additionally, reference symbols and/or letters may be repeated in each instance. This repetition is for simplicity and clarity and does not inherently indicate a relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, spatially relative terms (such as "below," "below," "lower," "above," "upper," and the like) may be used herein to describe an element or element illustrated in the figures. The relationship of a feature to another element (or elements) or feature (or features). Spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted similarly.

As the pace toward next-generation nodes continues to accelerate, these advanced nodes can offer benefits such as higher speeds, higher density, lower power, and more. However, advanced nodes do not always provide input-output (I/O) devices or other devices with large channel lengths. For example, in some advanced nodes, nearly all transistors formed on the die are implemented as core devices (configured in, for example, a gate-all-around (GAA) transistor structure). It is true that this core device can have higher speeds, operate at lower voltages, and be formed at higher density than I/O devices, but this core device is generally more susceptible to excessive stress and damage.

For example, the I/O needs of a system often involve signal transfer between the integrated circuit die and component connections with large capacitances, such as those associated with printed circuit board traces, cables, etc. The resulting signal sends greater drive power and voltage. I/O devices interface the faster, smaller signals from the main die to these other higher capacitance components, and typically carry the signals at higher voltages. As non-limiting examples, memory circuits (eg, eFuse memory circuits or one-time programmable (OTP) memory circuits) often rely on I/O circuits to provide high voltages to operate (eg, , programming, erasing, etc.) memory circuit.

A level shifter is one of a variety of such I/O circuits that can provide high voltages. Typically, level translators convert signal levels from one power domain to another. Implementing the level converter only with core devices in the prior art may cause device reliability issues. For example, during operation of such an existing level shifter, the gate-to-drain, gate-to-source, and/or drain-to-source voltage drops in each core device may be higher. (e.g., higher than the maximum stress voltage of the core device). This phenomenon may damage the level converter, which may negatively affect the operation of the coupling circuit. Therefore, existing level converters are not entirely satisfactory in many aspects.

This disclosure example provides various embodiments that utilize only the core device's voltage supply circuit. As disclosed in one embodiment of the present disclosure, the voltage supply circuit includes: a voltage supply circuit for generating a first intermediate signal based on a partial voltage that is a fraction of the power supply voltage, and generating a second intermediate signal based on one or more control signals. Intermediate signal. In various embodiments, the first intermediate signal may have opposite logic states (i.e., logic "1" and logic "0") corresponding to the supply voltage and the partial voltage, respectively, and the second intermediate signal may have its respective corresponding The opposite logic state of part voltage and ground voltage. Furthermore, the disclosed voltage supply circuit may include a plurality of series-coupled first inverters and a plurality of series-coupled second inverters using the first intermediate signal and the second intermediate signal as inputs respectively. Based on the first intermediate signal and the second intermediate signal, the voltage supply circuit may provide a voltage output equal to the power supply voltage or the ground voltage. In various embodiments, each core device included in the disclosed voltage supply circuit has a voltage drop less than or equal to a partial voltage between any two terminals thereof. Therefore, in the disclosed voltage supply circuit, the stress problem commonly faced by existing level converters can be completely avoided.

FIG. 1 is an example circuit diagram of a voltage supply circuit 100 according to various embodiments. The voltage supply circuit 100 includes a voltage level converter C1, a power switch control circuit P1, a partial voltage generator MG, a plurality of first inverters I1˜I4 and a plurality of second inverters I5˜I9. Typically, the partial voltage generator MG can provide the voltage level converter C1 with a partial voltage of the supply voltage. The voltage level converter C1 may generate a first intermediate signal based on the partial voltage, the first intermediate signal having opposite logic states respectively corresponding to the supply voltage and the partial voltage. The power switch control circuit P1 may generate a second intermediate signal having opposite logic states respectively corresponding to the partial voltage and the ground voltage. The first inverters I1 - I4 and the second inverters I5 - I9 may then respectively input the first intermediate signal and the second intermediate signal to jointly determine the voltage level at the output node of the voltage supply circuit 100 .

The voltage level converter C1 includes a voltage modulation circuit (ie, a voltage multi-structure) S1 coupled between the PMOS transistors M3 and M4 and the NMOS transistors M1 and M2. The voltage multi-structure S1 is configured to operate based on the control signals YSELB and YSELB'. Provides intermediate signal qgb. In various embodiments, the control signals YSELB and YSELB', which are input signals of the voltage supply circuit 100, may each transition within the first voltage domain (eg, transition from 0V (VSS) to 0.75V (VDD)). With the voltage level converter C1, the intermediate signal qgb can assume a first logic state corresponding to the supply voltage VQPS, or a second logic state corresponding to the partial voltage MVDD which is a fraction of the supply voltage VQPS. For example, the supply voltage VQPS (received by the voltage supply circuit 100) may be about 1.8V, and the partial voltage MVDD is about half of the supply voltage VQPS, that is, about 0.9V. In other words, the control signal YSELB/YSELB' in the first voltage domain (0 to 0.75V) can be used as the intermediate signal qgb to be converted in the second voltage domain (0.9 to 1.8V).

The voltage level converter C1 includes an NMOS transistor M1. The NMOS transistor M1 has the control signal YSELB as a gate and the ground voltage as a source. The voltage level converter C1 includes an NMOS transistor M2. The NMOS transistor M2 has a control signal YSELB' complementary to the control signal YSELB as a gate and a ground voltage as a source. The voltage level converter C1 includes a PMOS transistor M3 having the power supply voltage VQPS as a source. The voltage supply circuit 100 includes a PMOS transistor M4 with the power supply voltage VQPS as a source.

Specifically, the voltage multi-structure S1 of the voltage level converter C1 includes an NMOS transistor M5 with a partial voltage MVDD as its gate and connected to the NMOS transistor M1. The voltage multi-structure S1 includes an NMOS transistor M6, which has a partial voltage MVDD as its gate and is connected to the NMOS transistor M2. The voltage multi-structure S1 includes a PMOS transistor M7 with the drain voltage of the NMOS transistor M6 as a gate and a partial voltage MVDD as a drain. The voltage multi-structure S1 includes a PMOS transistor M8, which has the drain voltage of the NMOS transistor M6 as its gate and a partial voltage MVDD as its drain. Voltage multi-structure S1 includes an NMOS transistor M9 having as its gate the source voltage of a PMOS transistor M7 which is also coupled to intermediate signal gqb. Voltage multi-structure S1 includes NMOS transistor M10 with its gate having the source voltage of PMOS transistor M8 also coupled to intermediate signal qgb.

In some embodiments, voltage multi-structure S1 includes PMOS transistor M11 connected to PMOS transistor M3, and PMOS transistor M12 connected to PMOS transistor M4. The PMOS transistors M11 and M12 usually have the signal PCGATE as the gate, and the signal PCGATE can be a fixed voltage (for example, 0.9V when the partial voltage MVDD is supplied at 0.9V). The multi-voltage structure S1 includes a PMOS transistor M13 with a partial voltage MVDD as a gate, and a PMOS transistor M14 with a partial voltage MVDD as a gate. The voltage multi-structure S1 includes a PMOS transistor M15 with the partial voltage MVDD as a source, and a PMOS transistor M16 with the partial voltage MVDD as a source.

Furthermore, the voltage supply circuit 100 includes inverters I1, I2, I3 and I4 coupled in series to each other, each of which is coupled between the supply voltage VQPS and the partial voltage MVDD. The voltage supply circuit 100 includes a PMOS transistor M17. The PMOS transistor M17 has the power supply voltage VQPS as a source and the output voltage VDDQ as a drain. The voltage supply circuit 100 includes a PMOS transistor M18. The PMOS transistor M18 has the partial voltage MVDD as its gate, is connected to the PMOS transistor M17, and has the ground voltage VDDQ as its drain. The voltage supply circuit 100 includes an NMOS transistor M19. The NMOS transistor M19 has a ground voltage as a source and an output voltage VDDQ as a drain. The voltage supply circuit 100 further includes inverters I5, I6, I7, I8 and I9 coupled in series to each other, each of which is coupled between the supply voltage VQPS and the partial voltage MVDD. The voltage supply circuit 100 includes a power switch control circuit P1 for outputting an intermediate signal PV based on the control signals PS and PD that are complementary to each other. In various embodiments, the power switch control circuit P1 may also include a level converter powered by the partial voltage MVDD. This level converter converts the control signal PS/PD as an intermediate signal PV (for example, in the first voltage domain , from 0V (VSS) to 0.75V (VDD)), the intermediate signal PV presents a first logic state corresponding to the partial voltage MVDD, or a second logic state corresponding to the ground voltage. In other words, the control signal PS/PD in the first voltage domain (0 to 0.75V) can be converted in the third voltage domain (0 to 0.9V) as the intermediate signal PV.

In various embodiments, the two intermediate signals qgb and PV can be input to the serially coupled inverters I1˜I4 and I5˜I9 respectively, so that the power supply voltage VQPS or the ground voltage VSS is output as the output voltage VDDQ. In other words, the voltage supply circuit 100 can convert the signal from the first voltage domain to the second voltage domain. For example, the voltage supply circuit 100 may convert the control signal YSELB/YSELB' in the first voltage domain (0 to 0.75V) into the intermediate signal qgb in the second voltage domain (0.9 to 1.8V). In addition, using the intermediate signal PV (outputted by the power switch control circuit P1) in the third voltage domain (0 to 0.9V), the voltage supply circuit 100 can provide the output voltage VDDQ in the fourth voltage domain (0 to 1.8V). Operation examples of the voltage supply circuit 100 will be described below.

To illustrate the operation of the disclosed voltage level converter C1, some nodes are referenced below. For example, in Figure 1, voltage multi-structure S1 includes node N1 connected to the drain of NMOS transistor M5, the gate of PMOS transistor M7, and the source of NMOS transistor M9. The voltage multi-structure includes node N2 connected to the drain of NMOS transistor M6, the gate of PMOS transistor M8, and the source of NMOS transistor M10. Voltage multi-structure S1 includes node N3 connected to the gate of PMOS transistor M4, the drain of PMOS transistor M13, and the gate of NMOS transistor M9. Voltage multi-structure S1 includes node N4 connected to the gate of PMOS transistor M3, the drain of PMOS transistor M14, and the gate of NMOS transistor M10. Voltage multi-structure S1 includes node N5 connected to the gate of PMOS transistor M3, the drain of PMOS transistor M15, and the gate of NMOS transistor M9. Voltage multi-structure S1 includes node N6 connected to the gate of PMOS transistor M3, the drain of PMOS transistor M16, and the gate of NMOS transistor M10. Voltage multi-structure S1 includes node N7 connected to the drain of PMOS transistor M11, the source of PMOS transistor M13, and the drain of NMOS transistor M9. Voltage multi-structure S1 includes node N8 connected to the drain of PMOS transistor M12, the source of PMOS transistor M14, and the drain of NMOS transistor M10. Voltage multi-structure S1 includes node N9 connected to the drain of PMOS transistor M11, the gate of PMOS transistor M15, and the drain of NMOS transistor M9. Voltage multi-structure S1 includes node N10 connected to the drain of PMOS transistor M12, the gate of PMOS transistor M16, and the drain of NMOS transistor M10. The PMOS transistor M18 and the NMOS transistor M19 have a node N11 with a common drain, and the node N11 outputs the voltage VDDQ from the voltage supply circuit 100 .

In response to control signals YSELB and YSELB' provided at low (eg, 0V) and high (eg, 0.75V) respectively, the low YSELB gate voltage turns off NMOS transistor M1, and the high YSELB' gate voltage turns on NMOS transistor M2 . NMOS transistor M2 pulls its drain voltage down to 0V. The NMOS transistor M6 with the partial voltage MVDD as its gate can be turned on, so that the voltage at the node N2 is pulled down to 0V. 0V at the node N2 which is the gate of the PMOS transistor M8 can turn on the PMOS transistor M8. In this way, the source and drain of the PMOS transistor M8 can exhibit approximately the same voltage (MVDD, for example, 0.9V). This condition makes the intermediate signal qgb equal to the logic low partial voltage MVDD.

At the same time, the control signals PS and PD can be provided to the power switch control circuit P1 as high (for example, 0.75V) and low (for example, 0V) respectively, so that the power switch control circuit P1 can output a partial voltage MVDD (for example, 0.9V). ) and is a logic high intermediate signal PV. By inputting the intermediate signals qgb (at logic low) and PV (at logic high) to the series-coupled inverters I1 ~ I4 and I5 ~ I9 respectively, the PMOS transistor M17 can be turned on (wherein the PMOS transistor M18 is always turned on on) and the NMOS transistor M19 can be turned off, so that the power supply voltage VQPS can be coupled to the output node N11, that is, the output voltage VDDQ is presented at VQPS (1.8V). For example, the intermediate signal qgb of logic low is inverted by the inverter I1 and output as a logic high, which is further inverted by the inverter I2 and output as a logic low, which is further inverted by the inverter I3 and output as a logic high. . In this way, the output qg2b_i of the inverter I3 is logic high, and is further inverted by the inverter I4 and output to logic low to turn on the PMOS transistor M17. Similarly, the intermediate signal PV with a logic high is inverted by the inverter I9 and output as a logic low, which is further inverted by the inverter I8 and output as a logic high, and so on. In this way, the output pstb1 of the inverter I6 is logic high, and is further inverted by the inverter I5 and output to logic low to turn off the NMOS transistor M19.

Table I below summarizes the corresponding logic states/voltage levels at some nodes of the voltage supply circuit 100.

Table I

In response to the control signal YSELB being high (e.g. 0.75V) and the control signal YSELB' being low (e.g. 0V), the high YSELB gate voltage turns on the NMOS transistor M1 and the low YSELB' gate voltage turns off the NMOS transistor M2. NMOS transistor M1 pulls its drain voltage down to 0V. The NMOS transistor M5 with the partial voltage MVDD as its gate can be turned on, so that the voltage at the node N1 is pulled down to 0V. 0V at the node N1 which is the gate of the PMOS transistor M7 can turn on the PMOS transistor M7. In this way, the source and drain of the PMOS transistor M7 can exhibit approximately the same voltage (MVDD, for example, 0.9V). This condition causes PMOS transistor M4 to conduct and helps transfer the supply voltage VQPS (at the source of PMOS transistor M4) to the source of PMOS transistor M12 which has a fixed voltage (PCGATE) as its gate. Therefore, the drain of the PMOS transistor M12 is approximately equal to 1.8V, causing the PMOS transistor M14 with MVDD (for example, 0.9V) as the gate to be turned on, so that its drain is present at 1.8V. In this way, the intermediate signal qgb (connected to the drain of PMOS transistor M14) is equal to a logic high of 1.8V (ie, the supply voltage VQPS).

At the same time, the control signals PD and PS can be provided to the power switch control circuit P1 as high (eg, 0.75V) and low (eg, 0V) respectively, so that the power switch control circuit P1 can output a voltage equal to the ground voltage (eg, 0V). Logic low intermediate signal PV. By inputting the intermediate signals qgb (at logic high) and PV (at logic low) to the series-coupled inverters I1˜I4 and I5˜I9 respectively, the PMOS transistor M17 can be turned off, and the NMOS transistor M19 can be turned off. is turned on so that the ground voltage can be coupled to the output node N11, that is, the output voltage VDDQ is presented at the ground voltage (0V). For example, the intermediate signal qgb with a logic high is inverted by the inverter I1 and output as a logic low. It is further inverted by the inverter I2 and output as a logic high. It is further inverted by the inverter I3 and output as a logic low. . In this way, the output qg2b_i of the inverter I3 is logic low, and is further inverted by the inverter I4 and output to logic high to turn off the PMOS transistor M17. Similarly, the intermediate signal PV with a logic low is inverted by the inverter I9 and output as a logic high, which is further inverted by the inverter I8 and output as a logic low, and so on. In this way, the output pstb1 of the inverter I6 is logic low, and is further inverted by the inverter I5 and output to logic high to turn on the NMOS transistor M19.

Table II below summarizes the corresponding logic states/voltage levels at some nodes of the voltage supply circuit 100.

Table II

Figure 2 depicts the corresponding waveforms over time of the signals (eg, voltage levels) at the nodes summarized in Tables I and II. For example, FIG. 2 shows the control signal PS, the control signal YSELB, the intermediate signal qgb, the intermediate signal qg2b_i, the intermediate signal pstb1, the partial voltage MVDD and the output signal VDDQ. Except for the generated partial voltage MVDD (provided at a relatively fixed level), each signal is in a low logic state (corresponding to the lower limit of the corresponding voltage domain) and a high logic state (corresponding to the upper limit of the corresponding voltage domain). ) pulse signal transition between. Specifically, the control signals PS and YSELB can each transition between a logic low (eg, about 0V) and a logic high (eg, about 0.75V); the intermediate signals qgb and qg2b_i can each transition between a logic low (eg, about 0.9V). ) and a logic high (e.g., about 1.8V); the intermediate signal pstb1 can transition between a logic low (e.g., about 0V) and a logic high (e.g., about 0.9V); and the output signal VDDQ can be at a logic low (e.g., approximately 0V) to a logic high (e.g., approximately 1.8V). As a non-limiting example, when the control signal PS is high and the control signal YSELB is low, the output signal VDDQ may be equal to about 1.8V (VQPS); and when the control signal PS is low and the control signal YSELB is high, the output signal VDDQ Can be equal to about 0V (ground).

FIG. 3 is an example circuit diagram of another voltage supply circuit 300 in accordance with some embodiments. Voltage supply circuit 300 is similar to voltage supply circuit 100 (shown in FIG. 1 ), except that voltage supply circuit 300 may provide an output voltage based on more than one partial voltage. As such, the voltage supply circuit 300 can convert the input voltage to a relatively wider voltage domain (compared to the voltage supply circuit 100 ), or each transistor of the voltage supply circuit 300 can operate under lower voltage stress (compared to the voltage supply circuit 100 ). compared to circuit 100). Therefore, the following description of the voltage supply circuit 300 will focus on the points of difference.

For example, the voltage supply circuit 300 includes a first partial voltage generator G1 and a second partial voltage generator G2, two voltage level converters L1 and L2, a power switch control circuit P2, and a first group of serially coupled inverters. I10, I11, I12 and I13, a second set of serially coupled inverters I14, I15, I16 and I17 and a third set of serially coupled inverters I18, I19 and I20. The voltage generators G1 and G2 can provide the first part of the voltage HVDD and the second part of the voltage LVDD respectively. In some embodiments, the supply voltage VQPS (received by the voltage supply circuit 300) may be about 1.8V, and the partial voltage HVDD is about two-thirds of the supply voltage VQPS, that is, about 1.2V, and the partial voltage LVDD is the power supply The voltage is about one-third of VQPS, which is about 0.6V. Partial voltages HVDD and LVDD can power voltage level converters L1 and L2 respectively.

Based on the operating principle similar to the level converter C1 (of the voltage supply circuit 100 of FIG. 1 ), the voltage level converters L1 and L2 can respectively generate the first intermediate signal qgb and the second intermediate signal psvq_i. For example, the first intermediate signal qgb may appear as a first logic state corresponding to the power supply voltage VQPS, or a second logic state corresponding to the partial voltage HVDD; and the second intermediate signal psvq_i may appear as a first logic state corresponding to the partial voltage HVDD. logic state, or a second logic state corresponding to partial voltage LVDD. Similar to the power switch control circuit P1 (of the voltage supply circuit 100 of FIG. 1 ), the power switch control circuit P2 may generate a third intermediate signal PV having opposite logic corresponding to the partial voltage LVDD and the ground voltage respectively. state. In other words, the first intermediate signal qgb can transition from the partial voltage HVDD (eg, 1.2V) to the power supply voltage VQPS (eg, 1.8V) in the first voltage domain; the second intermediate signal psvq_i can transition from the partial voltage LVDD in the second voltage domain. (eg, 0.6V) to a partial voltage HVDD (eg, 1.2V); and the third intermediate signal PV may transition from ground (eg, 0V) to a partial voltage LVDD (eg, 0.6V) in the third voltage domain.

The first inverters I10-I13, the second inverters I14-I17 and the third inverters I18-I20 respectively input the first intermediate signal qgb, the second intermediate signal psvq_i and the third intermediate signal PV to jointly determine The voltage level VDDQ at the output node N11. For example, to output the signal VDDQ of 1.8V (VQPS), the voltage level converter L1 provides the intermediate signal qgb at a logic low (e.g., 1.2V), and the voltage level converter L2 provides an intermediate signal qgb at a logic low (e.g., 0.6V ), and the power switch control circuit P2 provides an intermediate signal PV at a logic high (eg, 0.6V). In this way, the intermediate signals qg2b_i and qg2b_ii can be output as logic low by the first inverters I10˜I13 and the second inverters I14˜I17 respectively. This condition will turn on the PMOS transistor M20 (wherein the PMOS transistor M21 is turned on), turning on the PMOS transistor M22 is turned on and NMOS transistor M23 is turned off (with NMOS transistor M24 turned off). The intermediate signal pstb1 can be output as logic low by the third inverter I18~20, and this condition will turn off the NMOS transistor M25. Therefore, the supply voltage VQPS (eg, 1.8V) can be passed to the node N11 through the turned-on transistors M20, M21, and M22 as the output signal VDDQ, while keeping the node N11 decoupled from ground through the turned-off transistors M23, M24, and M25. .

On the other hand, in order to output the signal VDDQ of 0V (ground), the voltage level converter L1 provides the intermediate signal qgb at a logic high (eg, 1.8V), and the voltage level converter L2 provides an intermediate signal qgb at a logic high (eg, 1.2V). V), and the power switch control circuit P2 provides an intermediate signal PV at a logic low (eg, 0V). In this way, the intermediate signals qg2b_i and qg2b_ii can be outputted as logic high by the first inverters I10~I13 and the second inverters I14~I17 respectively. This condition will turn off the PMOS transistor M20, turn off the PMOS transistor M22 and turn on the NMOS. Transistor M23. The intermediate signal pstb1 can be output as a logic high by the third inverter I18~20, and this condition will turn on the NMOS transistor M25. Therefore, the output signal VDDQ can be coupled to the ground voltage through the turned-on transistors M23, M24, and M25, while keeping the node N11 decoupled from the supply voltage VQPS through the turned-off transistors M20, M21, and M22.

FIG. 4 is an example circuit diagram of yet another voltage supply circuit 400 according to some embodiments. Voltage supply circuit 400 is similar to voltage supply circuit 300 (shown in FIG. 3 ) except that even with two voltage generators, voltage supply circuit 400 may also have a level shifter. In this way, the voltage supply circuit 400 can also convert the input voltage to a relatively wider voltage domain (compared to the voltage supply circuit 100 ), or each transistor of the voltage supply circuit 400 can operate under lower voltage stress (compared to the voltage supply circuit 100 ). voltage supply circuit 100). Therefore, the following description of the voltage supply circuit 400 will focus on the points of difference.

For example, the voltage supply circuit 400 includes a first partial voltage generator G1 and a second partial voltage generator G2, a voltage level converter L1, a power switch control circuit P2, and a first set of serially coupled inverters I10 and I11 , I12 and I13 and a second set of serially coupled inverters I18, I19 and I20. The voltage generators G1 and G2 can provide the first part of the voltage HVDD and the second part of the voltage LVDD respectively. In some embodiments, the supply voltage VQPS (received by the voltage supply circuit 300) may be about 1.8V, and the partial voltage HVDD is about two-thirds of the supply voltage VQPS, that is, about 1.2V, and the partial voltage LVDD is the power supply The voltage is about one-third of VQPS, which is about 0.6V. Partial voltages HVDD and LVDD can power voltage level converters L1 and L2 respectively.

Based on an operating principle similar to the level converter C1 (of the voltage supply circuit 100 of FIG. 1 ), the voltage level converter L1 may generate the first intermediate signal qgb based on the partial voltage HVDD. For example, the first intermediate signal qgb may assume a first logic state corresponding to the supply voltage VQPS, or a second logic state corresponding to the partial voltage HVDD. Similar to the power switch control circuit P1 (of the voltage supply circuit 100 of FIG. 1 ), the power switch control circuit P2 may generate a second intermediate signal PV having opposite logic corresponding to the partial voltage LVDD and the ground voltage respectively. state. In other words, the first intermediate signal qgb can transition from the partial voltage HVDD (eg, 1.2V) to the power supply voltage VQPS (eg, 1.8V) in the first voltage domain; and the second intermediate signal PV can be self-grounded (eg, 1.2V) in the second voltage domain. For example, 0V) to a partial voltage LVDD (for example, 0.6V).

The first inverters I10 to I13 and the second inverters I18 to I20 respectively input the first intermediate signal qgb and the second intermediate signal PV to jointly determine the voltage level VDDQ at the output node N11. For example, to output the signal VDDQ of 1.8V (VQPS), the voltage level converter L1 provides the intermediate signal qgb at a logic low (for example, 1.2V), while the power switch control circuit P2 provides a logic high (for example, 0.6V) The intermediate signal PV. In this way, the intermediate signal qg2b_i can be output as logic low by the first inverters I10˜I13. This condition will turn on the PMOS transistor M20 (wherein the PMOS transistor M21 is turned on). The intermediate signal pstb1 can be output as logic low by the third inverter I18~20, and this condition will turn off the NMOS transistor M25. Therefore, the supply voltage VQPS (eg, 1.8V) can be passed to the node N11 as the output signal VDDQ through the turned-on transistors M20 and M21, while keeping the node N11 decoupled from ground through the turned-off transistor M25.

On the other hand, in order to output the signal VDDQ of 0V (ground), the voltage level converter L1 provides the intermediate signal qgb at a logic high (for example, 1.8V), and the power switch control circuit P2 provides a logic low (for example, 0V) The intermediate signal PV. In this way, the intermediate signal qg2b_i can be output as logic high by the first inverters I10˜I13, and this condition will turn on the PMOS transistor M20. The intermediate signal pstb1 can be output as a logic high by the third inverter I18~20, and this condition will turn on the NMOS transistor M25. Therefore, the output signal VDDQ can be coupled to the ground voltage through the turned-on transistors M22 and M25, while keeping the node N11 decoupled from the supply voltage VQPS through the turned-off transistor M20.

FIG. 5 is an example circuit diagram of yet another voltage supply circuit 500 according to some embodiments. The voltage supply circuit 500 is similar to the voltage supply circuit 300 (shown in FIG. 3 ) except that the voltage supply circuit 500 may further include a voltage detector. In this way, the voltage supply circuit 500 can also convert the input voltage to a relatively wider voltage domain (compared to the voltage supply circuit 100 ), or each transistor of the voltage supply circuit 500 can operate under lower voltage stress (compared to the voltage supply circuit 100 ). voltage supply circuit 100). Therefore, the following description of the voltage supply circuit 500 will focus on the points of difference.

In various embodiments, the voltage supply circuit 500 includes a voltage detector VD1 to detect whether the lower logic voltage VDD used to drive the control signal (eg, control signal YSELB, YSELB', PS, PD, etc.) has been ready, or is stable compared to the supply voltage VQPS. For example, if the logic voltage VDD is not ready when the power supply voltage VQPS is provided, the voltage detector VD1 can force the output signal VDDQ to ground. In some embodiments, the voltage detector VD1 (which essentially consists of multiple inverters with relatively weak PMOS transistors) may be based on comparing the voltage level of the logic voltage VDD with the voltage level of the power supply voltage VQPS. Compare to output another intermediate signal Vx. In response to determining that the logic voltage VDD is not ready, the voltage detector VD1 outputs the intermediate signal Vx at a logic high. In this way, regardless of whether the intermediate signal PV is output as logic high or low, the inverter I18 can receive a logic low, which is pulled to the ground voltage by the NMOS transistor M30 turned on by the logic high intermediate signal Vx. Therefore, the intermediate signal pstb1 can be output with a logic high, thereby turning on the NMOS transistor M25 to pull the output signal VDDQ to ground.

6 is an example circuit diagram of another voltage level converter C2 according to various embodiments. Voltage level converter C2 is similar to voltage level converter C1 (shown in Figure 1), with some connections between NMOS transistors M9 and M10 being changed. Therefore, the following explanation will focus on the points of difference. As shown in FIG. 6 , the gate of the NMOS transistor M10 is connected to the gate of the PMOS transistor M8 rather than to the source of the PMOS transistor M8 (as shown in FIG. 1 ). Similarly, the gate of NMOS transistor M9 is connected to the gate of PMOS transistor M7 rather than to the source of PMOS transistor M7 (as shown in FIG. 1 ).

FIG. 7 is an example circuit diagram of a voltage generator 700 for one of various implementations of voltage generator MG (shown in FIG. 1 ). The voltage generator 700 may generate a partial voltage (eg, MVDD) based on the supply voltage (eg, VQPS) and the ground voltage (eg, VSS).

As shown in FIG. 7 , the voltage generator 700 includes a first part V1 , a second part V2 and a third part V3 . The first part V1 can be used as a power divider, the second part V2 can be used as a push/pull driver, and the third part V3 can be used to stabilize the output (ie partial voltage MVDD). In some embodiments, the first part V1 includes two sets of resistors R1 and R2 used to jointly generate a bias voltage, a plurality of NMOS transistors and a plurality of PMOS transistors; the second part V2 includes a plurality of resistors used to jointly pull or push the output. NMOS transistors and multiple PMOS transistors; and the third part V3 includes multiple MOS capacitors to jointly stabilize the output. In some other embodiments, each resistor may be implemented as a MOS diode while remaining within the scope of this disclosure. Generally speaking, the partial voltage MVDD is equal to the ratio of the first set of resistors R1 to the second set of resistors R2 multiplied by the supply voltage VQPS:

MVDD=N×VQPS

where the coefficient N is defined as:

R2/(R1+R2)

For example, when R1/R2 equals 1, N equals 1/2. Thus, MVDD is equal to 1/2×VQPS. In another example, when R1/R2 equals 1/2, N equals 2/3. Thus, MVDD is equal to 2/3×VQPS. When R1/R2 equals 2, N equals 1/3. Thus, MVDD is equal to 1/3×VQPS.

FIG. 8 is an example circuit diagram of a voltage generator 800 for one of various embodiments of a combination of voltage generators G1 and G2 (shown in FIGS. 3 , 4 , and 5 ). The voltage generator 800 may generate multiple partial voltages (eg, HVDD and LVDD) based on the supply voltage (eg, VQPS) and the ground voltage (eg, VSS). Voltage generator 800 is similar to voltage generator 700 . Therefore, the following description of voltage generator 800 will focus on the points of difference.

As shown in FIG. 8, voltage generator 800 includes a combination of voltage generators 810 and 850, each of which is similar to voltage generator 700 (e.g., includes three part). For example, the voltage generator 810 may provide the first partial voltage HVDD based on the ratio of the first group of resistors R1 and the second group of resistors R2 multiplied by the power supply voltage VQPS; and the voltage generator 850 may provide the first partial voltage HVDD based on the ratio of the first group of resistors R1' and the second group of resistors R2 The ratio of the second set of resistors R2' is multiplied by the supply voltage VQPS to provide the second portion of the voltage LVDD. As a non-limiting example, the ratio of R1 to R1+R2 (22 to 60) can be about 0.36, and the ratio of R2 to R1+R2 (38 to 60) can be about 0.63, which results in the output HVDD and LVDD respectively being About 0.6V and 1.2V (when VQPS is 1.8V). In addition, the voltage generator 800 includes a voltage divider, which is also coupled between the power supply voltage VQPS and the ground voltage to provide reference voltages Vref_H and Vref_L to the voltage generators 810 and 850 respectively. In some embodiments, the voltage divider may include three sets of resistors R3, R4, and R5. Continuing from the above example, the ratio of these three sets of resistors R3, R4 and R5 can be 11:8:11.

9 is a flowchart illustrating an example method 900 for operating a voltage supply circuit of an embodiment of the present disclosure, in accordance with various embodiments. It should be noted that method 900 is an example only and is not intended to limit this disclosure. Accordingly, it should be understood that any additional operations may be provided during, before, and after method 900 of FIG. 9, and some other operations may be described only briefly in this disclosure. Method 900 may be used to operate voltage supply circuit 100, 300, 400, or 500. Accordingly, the operations of method 900 will be described below in conjunction with the elements illustrated in Figures 1-8.

Briefly, method 900 begins with the operation 902 of generating a first portion of a voltage as a first fraction of a supply voltage, followed by the optional operation 904 of generating a second portion of a voltage as a second fraction of a supply voltage. Next, operation 906 is performed to generate a first intermediate signal based on at least the first partial voltage, then operation 908 is performed to generate a second intermediate signal based on at least one or more control signals, and then operation 908 is performed to provide an output voltage based on the first intermediate signal and the second intermediate signal. Operation 910. In various embodiments, the output voltage appears as a supply voltage or a ground voltage.

Corresponding to operation 902 of FIG. 9, a first portion of voltage that is a first fraction of the power supply voltage may be generated by the voltage generator. In the example of FIG. 1 , the voltage generator MG of the voltage supply circuit 100 (shown in FIG. 1 ) can generate a partial voltage MVDD, and the partial voltage MVDD is a small part of the power supply voltage VQPS. In various embodiments, the partial voltage MVDD may allow each transistor of the disclosed voltage level converter C1 (shown in FIG. 1) or C2 (FIG. 6) to operate under relatively low voltage stress (eg, below 1V). )operate. In this way, whether each transistor is implemented as an NMOS or PMOS, it can be implemented as a core device with a relatively thin gate dielectric layer while being unaffected by high voltage stress.

Corresponding to optional operation 904 of FIG. 9, another portion of the voltage, which is the second fraction of the supply voltage, may be generated by another voltage generator. In the examples of FIGS. 3 to 5 , the first part of the voltage and the second part of the voltage may be generated by the voltage generators G1 and G2 respectively. These multiple partial voltages allow each transistor of a disclosed voltage level converter (L1 in Figure 4) or multiple voltage level converters (L1 and L2 in Figure 3 or Figure 5) to operate at a relatively low Operate under voltage stress (e.g. below 1V). The following description of method 900 will primarily use the example of a single partial voltage (eg, Figure 1).

Corresponding to operation 906 of FIG. 9, the first intermediate signal may be generated by the voltage level converter. Continuing with the example of Figure 1, the voltage level converter C1 can generate the intermediate signal qgb based on the first partial voltage MVDD (together with a pair of control signals YSELB and YELB'). In various embodiments, with the help of level converter C1, the control signals YESLB and TESLB' (in the first voltage domain, for example, from 0V to 0.75V) can be converted or otherwise output to be in different voltage domains. The intermediate signal qgb in the second voltage domain (for example, from the partial voltage MVDD (0.9V) to the supply voltage VQPS (1.8V)), while keeping each transistor of the level converter C1 under relatively low voltage stress (for example , not greater than 0.9V).

Corresponding to operation 908 of FIG. 9, the second intermediate signal may be generated by the power switch control circuit. Continuing with the example of FIG. 1 , the power switch control circuit P1 may generate the intermediate signal PV based on the first partial voltage MVDD (together with a pair of control signals PS and PD). In various embodiments, the power switch control circuit P1 may also include a voltage level converter powered by the partial voltage MVDD. This voltage level converter may convert the control signal PS/PD (from the first voltage domain, for example, from 0V to 0.75V) is converted or otherwise output to an intermediate signal PV in a different third voltage domain (eg, from ground (0V) to partial voltage MVDD (0.9V)).

Corresponding to operation 910 of FIG. 9 , an output voltage may be provided based on the first intermediate signal and the second intermediate signal. Continuing with the example of FIG. 1 , the first intermediate signal qgb and the second intermediate signal PV may be respectively input to the first group of serially coupled inverters (for example, I1 to I4) and the second group of serially coupled inverters. device (for example, I5 to I9). With the first intermediate signal and the second intermediate signal configured to be in the appropriate logic state, the output voltage can be provided in a fourth voltage domain, for example, from ground (0V) to the supply voltage VQPS (1.8V) while maintaining Each transistor of inverters I1 to I9 is subject to relatively low voltage stress (eg, no greater than 0.9V).

Referring again to the voltage supply circuit 100 of Figure 1, multiple voltage multi-structures S1 can be "stacked" between PMOS transistors M3 and M4 and NMOS transistors M1 and M2 to handle higher supply voltages VQPS (so that the output has a wider voltage level voltage VDDQ) while keeping each transistor subject to relatively low voltage stress (e.g., no greater than 0.9V). In other words, the level of the power supply voltage VQPS may be proportional to the number of stacked voltage multi-structures S1. For example, when the power supply voltage VQPS is equal to approximately 1.8V, the voltage supply circuit 100 may include a voltage multi-structure S1 (as shown in FIG. 1 ). In another example, when the supply voltage VQPS is equal to approximately 3.6V, the supply circuit 100 may include two voltage multi-structures S1 stacked between PMOS transistors M3 and M4 and NMOS transistors M1 and M2.

An embodiment of this disclosure provides a voltage supply circuit. The voltage supply circuit includes a first NMOS transistor with the first control signal as a gate and a ground voltage as a source. The voltage supply circuit includes a second NMOS transistor with a second control signal complementary to the first control signal as a gate and a ground voltage as a source. The voltage supply circuit includes a first PMOS transistor with the first power supply voltage as a source. The voltage supply circuit includes a second PMOS transistor, and the second PMOS transistor has the first power supply voltage as a source. The voltage supply circuit includes a voltage modulation circuit. The voltage modulation circuit is coupled between the first to second PMOS transistors and the first to second NMOS transistors for controlling the voltage based on the first control signal and the second control signal. Provide the first intermediate signal. In some embodiments, the first intermediate signal has a first logic state corresponding to a first supply voltage or a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage. The voltage supply circuit includes a power switch control circuit configured to output a third intermediate signal. The third intermediate signal presents a first logic state corresponding to the second power supply voltage or a second logic state corresponding to the ground voltage.

In some embodiments, the voltage supply circuit further includes an even number of first inverters, serially coupled to each other, and each first inverter is coupled between the first power supply voltage and the second power supply voltage, wherein the first inverter The phase converter is used to output a second intermediate signal based on the first intermediate signal.

In some embodiments, the voltage supply circuit further includes an odd number of second inverters serially coupled to each other, and each second inverter is coupled between the second supply voltage and the ground voltage, wherein the second inverter The device is configured to output a fourth intermediate signal based on the third intermediate signal.

In some embodiments, the voltage supply circuit further includes a third PMOS transistor having the second intermediate signal as a gate, the first power supply voltage as a source, and the output voltage as a drain.

In some embodiments, the voltage supply circuit further includes a third NMOS transistor having the fourth intermediate signal as a gate, the ground voltage as a source, and the output voltage as a drain.

In some embodiments, in response to the third PMOS transistor being turned on and the third NMOS transistor being turned off, the output voltage is configured to be in the first logic state, and in response to the third PMOS transistor being turned off and the third NMOS transistor being turned on, the output voltage is The voltage is used to be in the second logic state.

In some embodiments, the output voltage assumes a first logic state corresponding to the first supply voltage or a second logic state corresponding to the ground voltage.

In some embodiments, the voltage modulation circuit includes a fourth NMOS transistor, a fifth NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The fourth NMOS transistor has the second power supply voltage as its gate and is connected to the first NMOS transistor. The fifth NMOS transistor has the second power supply voltage as its gate and is connected to the second NMOS transistor. The fourth PMOS transistor has the drain voltage of the fourth NMOS transistor as its gate and the second power supply voltage as its drain. The fifth PMOS transistor has the drain voltage of the fifth NMOS transistor as its gate and the second power supply voltage as its drain. The sixth NMOS transistor has as its gate the source voltage of the fourth PMOS transistor which is also coupled to the first intermediate signal. The seventh NMOS transistor has as its gate the source voltage of the fifth PMOS transistor which is also coupled to the first intermediate signal.

In some embodiments, each of the first to seventh NMOS transistors and the first to fifth PMOS transistors has a voltage drop of less than 1 volt between any two of its plurality of terminals. .

In some embodiments, each of the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor have the same gate oxide thickness.

In another embodiment of the present disclosure, a voltage supply circuit is provided. The voltage supply circuit includes a first partial voltage generator, the first partial voltage generator is used to generate a first voltage, and the first voltage is a first small part of the power supply voltage. The voltage supply circuit includes a first level converter. The first level converter is powered by the power supply voltage and is used to generate a first intermediate signal based on the first voltage. The voltage supply circuit includes a plurality of first inverters. These first inverters The phase converter is coupled between the supply voltage and the first voltage for coupling the supply voltage to the output node based on the first intermediate signal. The voltage supply circuit includes a plurality of second inverters coupled between the first voltage and the ground voltage or between the second voltage and the ground voltage to couple the output node to the ground voltage, wherein the second The voltage is the second smallest fraction of the supply voltage.

In some embodiments, the voltage supply circuit further includes a second partial voltage generator for generating a second voltage, wherein the second voltage is a second fraction of the supply voltage.

In some embodiments, the voltage supply circuit further includes a second level converter for receiving the second voltage from the second partial voltage generator and outputting the second intermediate signal.

In some embodiments, the voltage supply circuit further includes a plurality of third inverters coupled between the first voltage and the second voltage, wherein the plurality of third inverters are connected between the second level converter and the output node. between to couple the supply voltage to the output node based on the second intermediate signal.

In some embodiments, the voltage supply circuit further includes a power switch control circuit for outputting a third intermediate signal to the plurality of second inverters, and the third intermediate signal presents a first logic state corresponding to the first voltage, so that The ground voltage is decoupled from the output node, or assumes a second logic state corresponding to the ground voltage, causing the ground voltage to be coupled to the output node.

In some embodiments, the voltage supply circuit further includes a voltage detector coupled to the plurality of second inverters, wherein the voltage detector is used to determine whether to force the output node to be coupled to ground voltage.

In some embodiments, each transistor of the first level shifter has a voltage drop of less than 1 volt between any two of its plurality of terminals.

Yet another embodiment of the present disclosure provides a method of converting multiple voltage levels. The method includes receiving the first portion of the voltage as a first fraction of the supply voltage. The method includes providing a first intermediate signal based on the first partial voltage, the first intermediate signal assuming a first logic state corresponding to the supply voltage or a second logic state corresponding to the first partial voltage. The method includes outputting an output voltage based on the first intermediate signal, and the output voltage is a power supply voltage or a ground voltage.

In some embodiments, the method further includes the steps of: receiving a second partial voltage as a second fraction of the supply voltage; and providing a second intermediate signal based on the second partial voltage, the second intermediate signal appearing as a second fraction of the supply voltage. a logic state or a second logic state corresponding to the second part of the voltage; and based on the second intermediate signal, output an output voltage, the output voltage being a power supply voltage or a ground voltage.

In some embodiments, the method further includes the steps of: providing a third intermediate signal, the third intermediate signal exhibiting a first logic state corresponding to the first partial voltage or a second logic state corresponding to the ground voltage; and based on the third intermediate signal Signal, output voltage, the output voltage is the supply voltage or ground voltage.

As used herein, the terms "about" and "approximately" generally refer to plus or minus 10% of the stated value. For example, approximately 0.5 would include 0.45 and 0.55, approximately 10 would include 9 to 11, and approximately 1000 would include 900 to 1100.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those familiar with the art should also realize that such equivalent structures do not deviate from the spirit and scope of the disclosure, and those familiar with the art can make various changes and substitutions without departing from the spirit and scope of the disclosure. and changes.

Claims (10)

1. A voltage supply circuit, characterized in that it includes: a first NMOS transistor with a first control signal as the gate and a ground voltage as the source; a second NMOS transistor with a second control signal complementary to the first control signal as a gate and the ground voltage as a source; a first PMOS transistor with a first power supply voltage as a source; a second PMOS transistor with the first power supply voltage as a source; A voltage modulation circuit coupled between the first PMOS transistor to the second PMOS transistor and the first NMOS transistor to the second NMOS transistor for providing a voltage modulation circuit based on the first control signal and the second control signal. a first intermediate signal, wherein the first intermediate signal exhibits a first logic state corresponding to the first supply voltage, or a first logic state corresponding to a second supply voltage that is a fraction of the first supply voltage 2 logical states; and A power switch control circuit is used to output a third intermediate signal, the third intermediate signal exhibits a first logic state corresponding to the second power supply voltage, or a second logic state corresponding to the ground voltage. 2. The voltage supply circuit of claim 1, further comprising: An even number of first inverters are serially coupled to each other, and each first inverter is coupled between the first power supply voltage and the second power supply voltage; The even number of first inverters is used to output a second intermediate signal based on the first intermediate signal. 3. The voltage supply circuit of claim 2, further comprising: An odd number of second inverters are serially coupled to each other, and each second inverter is coupled between the second power supply voltage and the ground voltage; The odd-numbered second inverters are used to output a fourth intermediate signal based on the third intermediate signal. 4. The voltage supply circuit of claim 3, further comprising: A third PMOS transistor has the second intermediate signal as a gate, the first power supply voltage as a source, and an output voltage as a drain. 5. The voltage supply circuit of claim 4, further comprising: A third NMOS transistor has the fourth intermediate signal as a gate, the ground voltage as a source, and the output voltage as a drain. 6. The voltage supply circuit of claim 5, wherein the output voltage is in a first logic state in response to the third PMOS transistor being turned on and the third NMOS transistor being turned off. The third PMOS transistor is turned off and the third NMOS transistor is turned on, and the output voltage is used to be in a second logic state. 7. The voltage supply circuit of claim 1, wherein the voltage modulation circuit includes: a fourth NMOS transistor, with the second power supply voltage as a gate and connected to the first NMOS transistor; a fifth NMOS transistor, with the second power supply voltage as a gate and connected to the second NMOS transistor; a fourth PMOS transistor, with a drain voltage of the fourth NMOS transistor as the gate, and with the second power supply voltage as the drain; a fifth PMOS transistor, with a drain voltage of the fifth NMOS transistor as a gate, and with the second power supply voltage as a drain; a sixth NMOS transistor with a source voltage of the fourth PMOS transistor also coupled to the first intermediate signal as a gate; and A seventh NMOS transistor has a source voltage of the fifth PMOS transistor also coupled to the first intermediate signal as a gate. 8. The voltage supply circuit of claim 7, wherein each of the first to seventh NMOS transistors and the first to fifth PMOS transistors has a plurality of There is a voltage drop of less than 1 volt between any two of the terminals. 9. A voltage supply circuit, characterized in that it includes: a first partial voltage generator for generating a first voltage, the first voltage being a first fraction of a power supply voltage; a first level converter, powered by the power supply voltage, for generating a first intermediate signal based on the first voltage; A plurality of first inverters coupled between the power supply voltage and the first voltage for coupling the power supply voltage to an output node based on the first intermediate signal; and A plurality of second inverters are coupled between the first voltage and a ground voltage or between a second voltage and the ground voltage to couple the output node to the ground voltage, wherein the second voltage is a second fraction of the supply voltage. 10. A method for converting multiple voltage levels, characterized by comprising the following steps: receiving a first portion of voltage as a first fraction of a supply voltage; Provide a first intermediate signal based on the first partial voltage, the first intermediate signal exhibiting a first logic state corresponding to the supply voltage or a second logic state corresponding to the first partial voltage; and Based on the first intermediate signal, an output voltage is output, and the output voltage is the power supply voltage or a ground voltage.