CN117608348A - Voltage supply circuit and method for converting multiple voltage levels - Google Patents

Abstract

An embodiment of the present disclosure provides a voltage supply circuit and a method of converting a plurality of voltage levels. The voltage supply circuit comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor and a voltage modulation circuit. The first NMOS transistor takes a first control signal and a grounding voltage as a grid electrode and a source electrode. The second NMOS transistor takes a second control signal complementary to the first control signal and a grounding voltage as a grid electrode and a source electrode. The first and second PMOS transistors have a first power supply voltage as a source. The voltage modulation circuit is coupled between the first to second PMOS transistors and the first to second NMOS transistors to provide a first intermediate signal based on the first control signal and the second control signal. In some embodiments, the first intermediate signal has a first logic state corresponding to a first supply voltage or a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage.

Description

Voltage supply circuit and method for converting multiple voltage levels

Technical Field

An embodiment of the present disclosure relates to a voltage supply circuit and a method for converting a plurality of voltage levels, and more particularly, to a voltage supply circuit with a core device and a method for converting a plurality of voltage levels.

Background

As the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) continues to increase, the semiconductor industry has experienced rapid growth. In most cases, the increase in integration density results from multiple reductions in minimum feature size, so that more elements can be integrated into a particular area.

Disclosure of Invention

An embodiment of the present disclosure provides a voltage supply circuit including a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a voltage modulation circuit, and a power switch control circuit. The first NMOS transistor takes a first control signal as a grid electrode and takes a grounding voltage as a source electrode. The second NMOS transistor takes a second control signal which is complementary to the first control signal as a grid electrode and takes a grounding voltage as a source electrode. The first PMOS transistor takes a first power supply voltage as a source electrode. The second PMOS transistor takes the first power supply voltage as a source electrode. The voltage modulation circuit is coupled between the first PMOS transistor and the second PMOS transistor and the first NMOS transistor and the second NMOS transistor for providing a first intermediate signal based on the first control signal and the second control signal, wherein the first intermediate signal is in a first logic state corresponding to the first power supply voltage or in a second logic state corresponding to the second power supply voltage which is a fraction of the first power supply voltage. The power switch control circuit is used for outputting a third intermediate signal which is in a first logic state corresponding to the second power voltage or in a second logic state corresponding to the grounding voltage.

An embodiment of the present disclosure provides a voltage supply circuit including a first partial voltage generator, a first level shifter, a plurality of first inverters and a plurality of second inverters. The first partial voltage generator is used for generating a first voltage which is a first small part of the power supply voltage. The first level shifter is powered by the power supply voltage for generating a first intermediate signal based on the first voltage. The plurality of first inverters are coupled between the power supply voltage and the first voltage for coupling the power supply voltage to the output node based on the first intermediate signal. The plurality of second inverters are coupled between the first voltage and the ground voltage or between the second voltage and the ground voltage for coupling the output node to the ground voltage, wherein the second voltage is a second fraction of the power supply voltage.

An embodiment of the present disclosure provides a method of converting a plurality of voltage levels, comprising the steps of: receiving a first partial voltage that is a first fraction of a supply voltage; providing a first intermediate signal based on the first partial voltage, the first intermediate signal assuming a first logic state corresponding to the supply voltage or a second logic state corresponding to the first partial voltage; and outputting an output voltage based on the first intermediate signal, wherein the output voltage is a power supply voltage or a ground voltage.

Drawings

The aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the features are not drawn to scale in accordance with standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is an example circuit diagram of a voltage supply circuit according to some embodiments of the present disclosure;

FIG. 2 is a waveform diagram of various signals presented by the voltage supply circuit of FIG. 1 according to some embodiments of the present disclosure;

FIG. 3 is an example circuit diagram of another voltage supply circuit according to some embodiments of the present disclosure;

FIG. 4 is an example circuit diagram of yet another voltage supply circuit depicted in accordance with some embodiments of the present disclosure;

FIG. 5 is an example circuit diagram of yet another voltage supply circuit according to some embodiments of the present disclosure;

FIG. 6 is an example circuit diagram of a voltage level converter that may be implemented by any of the voltage supply circuits of FIGS. 1, 3-5, depicted in accordance with some embodiments of the present disclosure;

FIG. 7 is an example circuit diagram of a portion of a voltage generator that may be implemented by the voltage supply circuit of FIG. 1, depicted in accordance with some embodiments of the present disclosure;

FIG. 8 is an example circuit diagram of a partial voltage generator that may be implemented by any of the voltage supply circuits of FIGS. 3-5, depicted in accordance with some embodiments of the present disclosure; and

FIG. 9 is a flowchart illustrating an example method for operating a voltage supply circuit of an embodiment of the present disclosure, according to some embodiments of the present disclosure.

[ symbolic description ]

100,300,400,500 Voltage supply Circuit

700,800,810,850 Voltage Generator

900 method

902,904,906,908,910 operations

C1, C2, L1, L2 voltage level converter

G1 first partial voltage generator

G2 second partial voltage generator

HVDD first partial voltage

I1 to I4 first inverter

I5 to I9 second inverter

I10 to I20 inverter

LVDD second partial voltage

M1, M2, M5, M6, M9, M10: NMOS transistors

M19, M23-M25, M30 NMOS transistor

M3, M4, M7, M8: PMOS transistors

M11-M18, M20-M22 PMOS transistor

MG partial voltage generator

MVDD: partial Voltage

N1-N11 nodes

P1, P2 power switch control circuit

PCGATE signal

PD, PS control Signal

PV, qgb, vx intermediate signal

psvq_i second intermediate signal

pstb1, qg2b_i output

qg2b_ii intermediate signal

R1-R5, R1', R2': resistor

S1 voltage regulating circuit

V1 first part

V2 second part

V3 third part

VD1 voltage detector

VDD: logic voltage

VDDQ, output voltage

VQPS supply voltage

Vref_H, vref_L reference voltage

VSS: ground voltage

YSELB, YSELB': control signal

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, for ease of description, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein to describe one element or feature's relationship to another element (or elements) or feature (or features) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As the pace of the next generation node development continues to increase, these advanced nodes may provide various advantages, such as higher speed, higher density, lower power, etc. However, advanced nodes do not always provide input-output (I/O) devices or other devices with large channel lengths. For example, in some advanced nodes, almost all transistors formed on the die are implemented as core devices (configured in, for example, a gate-all-around (GAA) transistor structure). The core device may indeed have a higher speed, operate at a lower voltage, and be formed at a higher density than the I/O device, but the core device is generally more susceptible to overstress and damage.

For example, the I/O requirements of the system typically involve signaling between the integrated circuit die and component connections having large capacitances, such as component connections associated with printed circuit board traces, cables, etc., requiring greater drive power and voltage than signaling that occurs within the integrated circuit die. The I/O device interfaces the faster, smaller signals of the main die to these other higher capacitance elements and typically transmits signals at higher voltages. As a non-limiting example, memory circuits (e.g., eFuse memory circuits or one-time programmable (OTP) memory circuits) typically rely on I/O circuitry to provide high voltages to operate (e.g., program, erase, etc.) the memory circuits.

A level shifter is one of various such I/O circuits capable of providing a high voltage. In general, a level shifter may shift a signal level from one power domain to another. The level shifter is implemented only by the core device in the prior art, and a problem of device reliability may occur. For example, during operation of such conventional level shifters, the voltage drop from gate to drain, gate to source, and/or drain to source in each core device may be high (e.g., above the maximum stress voltage of the core device). This phenomenon may damage the level shifter, thereby negatively affecting the operation of the coupling circuit. Thus, existing level shifters are not entirely satisfactory in many aspects.

The present disclosure provides various embodiments of a voltage supply circuit that utilizes only core devices. As disclosed in an embodiment of the present disclosure, the voltage supply circuit includes: the voltage supply circuit is used for generating a first intermediate signal based on a partial voltage which is a small part of the power supply voltage and generating a second intermediate signal based on one or more control signals. In various embodiments, the first intermediate signal may have opposite logic states (i.e., logic "1" and logic "0") corresponding to the power supply voltage and the partial voltage, respectively, and the second intermediate signal may have opposite logic states corresponding to the partial voltage and the ground voltage, respectively. In addition, the disclosed voltage supply circuit may include a plurality of serially coupled first inverters and a plurality of serially coupled second inverters using the first intermediate signal and the second intermediate signal as inputs, respectively. The voltage supply circuit may provide a voltage output equal to the power supply voltage or the ground voltage based on the first intermediate signal and the second intermediate signal. In various embodiments, each core device included in the disclosed voltage supply circuit has a voltage drop between any two terminals thereof that is less than or equal to a partial voltage. Therefore, in the disclosed voltage supply circuit, the stress problem generally faced by the existing level shifter can be completely avoided.

Fig. 1 is an example circuit diagram of a voltage supply circuit 100, depicted in accordance with various embodiments. The voltage supply circuit 100 includes a voltage level shifter C1, a power switch control circuit P1, a partial voltage generator MG, a plurality of first inverters I1 to I4, and a plurality of second inverters I5 to I9. In general, the partial voltage generator MG may supply the partial voltage of the power supply voltage to the voltage level shifter C1. The voltage level shifter C1 may generate a first intermediate signal based on the partial voltage, the first intermediate signal having opposite logic states corresponding to the power supply voltage and the partial voltage, respectively. The power switch control circuit P1 may generate a second intermediate signal having opposite logic states corresponding to the partial voltage and the ground voltage, respectively. The first inverters I1-I4 and the second inverters I5-I9 may then input a first intermediate signal and a second intermediate signal, respectively, to collectively determine the voltage level at the output node of the voltage supply circuit 100.

The voltage level shifter C1 includes a voltage modulation circuit (i.e., a voltage multi-structure) S1 coupled between the PMOS transistors M3 and M4 and the NMOS transistors M1 and M2, the voltage multi-structure S1 providing an intermediate signal qgb based on the control signals YSELB and YSELB'. In various embodiments, the control signals YSELB and YSELB', which are input signals of the voltage supply circuit 100, may each be transitioned (e.g., from 0V (VSS) to 0.75V (VDD)) in the first voltage domain. With the voltage level shifter C1, the intermediate signal qgb can assume a first logic state corresponding to the supply voltage VQPS or a second logic state corresponding to the partial voltage MVDD that is a fraction of the supply voltage VQPS. For example, the power supply voltage VQPS (received by the voltage supply circuit 100) may be about 1.8V, while the partial voltage MVDD is about half the power supply voltage VQPS, i.e., about 0.9V. In other words, the control signal YSELB/YSELB' in the first voltage domain (0 to 0.75V) may be converted in the second voltage domain (0.9 to 1.8V) as the intermediate signal qgb.

The voltage level shifter C1 includes an NMOS transistor M1, wherein the NMOS transistor M1 has a control signal YSELB as a gate and a ground voltage as a source. The voltage level shifter C1 includes an NMOS transistor M2, wherein the NMOS transistor M2 has a gate electrode of a control signal YSELB' complementary to the control signal YSELB, and a source electrode of a ground voltage. The voltage level shifter C1 includes a PMOS transistor M3 having a power supply voltage VQPS as a source. The voltage supply circuit 100 includes a PMOS transistor M4 having a power supply voltage VQPS as a source.

In particular, the voltage multi-structure S1 of the voltage level shifter C1 includes an NMOS transistor M5 with a partial voltage MVDD as a gate and connected to the NMOS transistor M1. The voltage multi-structure S1 includes an NMOS transistor M6, and the NMOS transistor M6 takes a partial voltage MVDD as a gate and is connected to the NMOS transistor M2. The voltage multi-structure S1 includes a PMOS transistor M7, where the PMOS transistor M7 uses the drain voltage of the NMOS transistor M6 as the gate and uses the partial voltage MVDD as the drain. The voltage multi-structure S1 includes a PMOS transistor M8, where the PMOS transistor M8 uses the drain voltage of the NMOS transistor M6 as the gate and uses the partial voltage MVDD as the drain. The voltage multi-structure S1 includes an NMOS transistor M9, the NMOS transistor M9 having a source voltage of a PMOS transistor M7 also coupled to the intermediate signal gqb as a gate. The voltage multi-structure S1 includes an NMOS transistor M10, the NMOS transistor M10 having a source voltage of a PMOS transistor M8 also coupled to the intermediate signal qgb as a gate.

In some embodiments, the voltage multi-structure S1 includes a PMOS transistor M11 connected to a PMOS transistor M3, and a PMOS transistor M12 connected to a PMOS transistor M4. The PMOS transistors M11 and M12 are typically gated by a signal PCGATE, which may be a fixed voltage (e.g., 0.9V when the partial voltage MVDD is supplied at 0.9V). The voltage multi-structure S1 includes a PMOS transistor M13 with a partial voltage MVDD as a gate, and a PMOS transistor M14 with a partial voltage MVDD as a gate. The voltage multi-structure S1 includes a PMOS transistor M15 with a partial voltage MVDD as a source, and a PMOS transistor M16 with a partial voltage MVDD as a source.

Furthermore, the voltage supply circuit 100 includes inverters I1, I2, I3, and I4 coupled in series with each other, each of which is coupled between the power supply voltage VQPS and the partial voltage MVDD. The voltage supply circuit 100 includes a PMOS transistor M17, where the PMOS transistor M17 uses the power voltage VQPS as a source and the output voltage VDDQ as a drain. The voltage supply circuit 100 includes a PMOS transistor M18, wherein the PMOS transistor M18 has a partial voltage MVDD as a gate, is connected to the PMOS transistor M17, and has a ground voltage VDDQ as a drain. The voltage supply circuit 100 includes an NMOS transistor M19, where the NMOS transistor M19 has a ground voltage as a source and an output voltage VDDQ as a drain. The voltage supply circuit 100 further includes inverters I5, I6, I7, I8, and I9 coupled in series with each other, each coupled between a supply voltage VQPS and a partial voltage MVDD. The voltage supply circuit 100 includes a power switch control circuit P1, and the power switch control circuit P1 is configured to output an intermediate signal PV based on control signals PS and PD complementary to each other. In various embodiments, the power switch control circuit P1 may also include a level shifter powered by the partial voltage MVDD, which converts the control signal PS/PD as an intermediate signal PV (e.g., from 0V (VSS) to 0.75V (VDD) in the first voltage domain), which assumes a first logic state corresponding to the partial voltage MVDD or a second logic state corresponding to the ground voltage. In other words, the control signal PS/PD in the first voltage domain (0 to 0.75V) may be converted in the third voltage domain (0 to 0.9V) as the intermediate signal PV.

In various embodiments, the two intermediate signals qgb and PV can be input to the serially coupled inverters I1-I4 and I5-I9, respectively, such that the power voltage VQPS or the ground voltage VSS is output as the output voltage VDDQ. In other words, the voltage supply circuit 100 may convert a signal from a first voltage domain to a second voltage domain. For example, the voltage supply circuit 100 may convert the control signal YSELB/YSELB' in a first voltage domain (0 to 0.75V) to an intermediate signal qgb in a second voltage domain (0.9 to 1.8V). Further, with the intermediate signal PV (output by the power switch control circuit P1) in the third voltage domain (0 to 0.9V), the voltage supply circuit 100 can provide the output voltage VDDQ in the fourth voltage domain (0 to 1.8V). An example of the operation of the voltage supply circuit 100 will be described below.

To illustrate the operation of the disclosed voltage level shifter C1, some nodes are referred to as follows. For example, in fig. 1, the voltage multi-structure S1 includes a node N1 connected to the drain of the NMOS transistor M5, the gate of the PMOS transistor M7, and the source of the NMOS transistor M9. The voltage multi-structure includes a node N2 connected to the drain of NMOS transistor M6, the gate of PMOS transistor M8, and the source of NMOS transistor M10. The voltage multi-structure S1 includes a node N3 connected to the gate of the PMOS transistor M4, the drain of the PMOS transistor M13, and the gate of the NMOS transistor M9. The voltage multi-structure S1 includes a node N4 connected to the gate of the PMOS transistor M3, the drain of the PMOS transistor M14, and the gate of the NMOS transistor M10. The voltage multi-structure S1 includes a node N5 connected to the gate of the PMOS transistor M3, the drain of the PMOS transistor M15, and the gate of the NMOS transistor M9. The voltage multi-structure S1 includes a node N6 connected to the gate of the PMOS transistor M3, the drain of the PMOS transistor M16, and the gate of the NMOS transistor M10. The voltage multi-structure S1 includes a node N7 connected to the drain of the PMOS transistor M11, the source of the PMOS transistor M13, and the drain of the NMOS transistor M9. The voltage multi-structure S1 includes a node N8 connected to the drain of the PMOS transistor M12, the source of the PMOS transistor M14, and the drain of the NMOS transistor M10. The voltage multi-structure S1 includes a node N9 connected to the drain of the PMOS transistor M11, the gate of the PMOS transistor M15, and the drain of the NMOS transistor M9. The voltage multi-structure S1 includes a node N10 connected to the drain of the PMOS transistor M12, the gate of the PMOS transistor M16, and the drain of the NMOS transistor M10. The PMOS transistor M18 and the NMOS transistor M19 have a node N11 with a common drain, and the node N11 outputs the voltage VDDQ from the voltage supply circuit 100.

In response to control signals YSELB and YSELB' provided at low (e.g. 0V) and high (e.g. 0.75V), respectively, the low YSELB gate voltage turns off NMOS transistor M1 and the high YSELB gate voltage turns on NMOS transistor M2. The NMOS transistor M2 pulls down its drain voltage to 0V. The NMOS transistor M6 with the partial voltage MVDD as the gate may be turned on, so that the voltage at the node N2 is pulled down to 0V. The PMOS transistor M8 may be turned on by 0V at the node N2 which is the gate of the PMOS transistor M8. Thus, the source and drain of the PMOS transistor M8 may approximately exhibit the same voltage (MVDD, e.g., 0.9V). This condition causes the intermediate signal qgb to be equal to the logic low partial voltage MVDD.

Meanwhile, the control signals PS and PD may be provided to the power switch control circuit P1 as high (e.g., 0.75V) and low (e.g., 0V), respectively, such that the power switch control circuit P1 may output an intermediate signal PV equal to the partial voltage MVDD (e.g., 0.9V) and logic high. By inputting the intermediate signals qgb (at logic low) and PV (at logic high) to the serially coupled inverters I1-I4 and I5-I9, respectively, the PMOS transistor M17 can be turned on (with the PMOS transistor M18 always on) and the NMOS transistor M19 can be turned off, such that the supply voltage VQPS can be coupled to the output node N11, i.e., the output voltage VDDQ is presented at VQPS (1.8V). For example, the intermediate signal qgb of logic low is inverted by inverter I1 and output as logic high, further inverted by inverter I2 and output as logic low, and further inverted by inverter I3 and output as logic high. Thus, the output qg2b_i of inverter I3 is logic high and is further inverted by inverter I4 and output as logic low to turn on PMOS transistor M17. Similarly, the intermediate signal PV of logic high is inverted by inverter I9 and output as logic low, which is further inverted by inverter I8 and output as logic high, and so on. Thus, the output pstb1 of the inverter I6 is logic high, and is further inverted by the inverter I5 and output as logic low to turn off the NMOS transistor M19.

Table I below summarizes the corresponding logic states/voltage levels at some nodes of the voltage supply circuit 100.

TABLE I

In response to the control signal YSELB being high (e.g., 0.75V) and the control signal YSELB 'being low (e.g., 0V), the high YSELB gate voltage turns on the NMOS transistor M1 and the low YSELB' gate voltage turns off the NMOS transistor M2. The NMOS transistor M1 pulls down its drain voltage to 0V. The NMOS transistor M5 with the partial voltage MVDD as the gate may be turned on, so that the voltage at the node N1 is pulled down to 0V. The PMOS transistor M7 may be turned on by 0V at the node N1 as the gate of the PMOS transistor M7. Thus, the source and drain of the PMOS transistor M7 may approximately exhibit the same voltage (MVDD, e.g., 0.9V). This condition turns on PMOS transistor M4 and helps pass supply voltage VQPS (at the source of PMOS transistor M4) to the source of PMOS transistor M12, which is gated by a fixed voltage (PCGATE). Thus, the drain of the PMOS transistor M12 is approximately equal to 1.8V, so that the PMOS transistor M14 having the MVDD (e.g., 0.9V) as the gate is turned on, thereby making the drain thereof appear at 1.8V. As such, the intermediate signal qgb (connected to the drain of PMOS transistor M14) is equal to 1.8V of logic high (i.e., supply voltage VQPS).

Meanwhile, the control signals PD and PS may be provided to the power switch control circuit P1 as high (e.g., 0.75V) and low (e.g., 0V), respectively, so that the power switch control circuit P1 may output a logic low intermediate signal PV equal to the ground voltage (e.g., 0V). By inputting the intermediate signals qgb (at logic high) and PV (at logic low) to the serially coupled inverters I1-I4 and I5-I9, respectively, the PMOS transistor M17 may be turned off and the NMOS transistor M19 may be turned on such that the ground voltage may be coupled to the output node N11, i.e., the output voltage VDDQ is presented at ground voltage (0V). For example, the intermediate signal qgb of logic high is inverted by inverter I1 and output as logic low, further inverted by inverter I2 and output as logic high, and further inverted by inverter I3 and output as logic low. Thus, the output qg2b_i of inverter I3 is logic low and is further inverted by inverter I4 and output as logic high to turn off PMOS transistor M17. Similarly, the intermediate signal PV of logic low is inverted by the inverter I9 and output as logic high, which is further inverted by the inverter I8 and output as logic low, and so on. Thus, the output pstb1 of the inverter I6 is logic low, and is further inverted by the inverter I5 and output as logic high to turn on the NMOS transistor M19.

Table II below summarizes the corresponding logic states/voltage levels at some nodes of the voltage supply circuit 100.

Table II

Fig. 2 depicts the corresponding waveforms of the signals (e.g., voltage levels) at the nodes summarized in tables I and II over time. For example, fig. 2 shows a control signal PS, a control signal YSELB, an intermediate signal qgb, an intermediate signal qg2b_i, an intermediate signal pstb1, a partial voltage MVDD, and an output signal VDDQ. Each signal is a pulse signal that transitions between a low logic state (corresponding to the lower limit of the respective voltage domain) and a high logic state (corresponding to the upper limit of the respective voltage domain), except for the generated partial voltage MVDD (provided at a relatively fixed level). Specifically, the control signals PS and YSELB may each transition between a logic low (e.g., about 0V) and a logic high (e.g., about 0.75V); intermediate signals qgb and qg2b_i may each transition between a logic low (e.g., about 0.9V) and a logic high (e.g., about 1.8V); the intermediate signal pstb1 may transition between a logic low (e.g., about 0V) and a logic high (e.g., about 0.9V); and the output signal VDDQ may transition between logic low (e.g., about 0V) and logic high (e.g., about 1.8V). As a non-limiting example, when the control signal PS is high and the control signal YSELB is low, the output signal VDDQ may be equal to about 1.8V (VQPS); and when the control signal PS is low and the control signal YSELB is high, the output signal VDDQ may be equal to about 0V (ground).

Fig. 3 is an example circuit diagram of another voltage supply circuit 300 depicted in accordance with some embodiments. The voltage supply circuit 300 is similar to the voltage supply circuit 100 (shown in fig. 1) except that the voltage supply circuit 300 may provide an output voltage based on more than one partial voltage. As such, the voltage supply circuit 300 may convert the input voltage to a relatively wider voltage domain (as compared to the voltage supply circuit 100), or each transistor of the voltage supply circuit 300 may operate at a lower voltage stress (as compared to the voltage supply circuit 100). Therefore, the following description about the voltage supply circuit 300 will focus on the difference point.

For example, the voltage supply circuit 300 includes a first partial voltage generator G1 and a second partial voltage generator G2, two voltage level shifters L1 and L2, a power switch control circuit P2, a first set of serially coupled inverters I10, I11, I12 and I13, a second set of serially coupled inverters I14, I15, I16 and I17, and a third set of serially coupled inverters I18, I19 and I20. The voltage generators G1 and G2 can respectively provide the first partial voltage HVDD and the second partial voltage LVDD. In some embodiments, the power supply voltage VQPS (received by the voltage supply circuit 300) may be about 1.8V, while the partial voltage HVDD is about two-thirds of the power supply voltage VQPS, i.e., about 1.2V, and the partial voltage LVDD is about one-third of the power supply voltage VQPS, i.e., about 0.6V. The partial voltages HVDD and LVDD may supply the voltage level shifters L1 and L2, respectively.

Based on the principle of operation of the level shifter C1 (of the voltage supply circuit 100 of fig. 1), the voltage level shifters L1 and L2 may generate the first intermediate signal qgb and the second intermediate signal psvq_i, respectively. For example, the first intermediate signal qgb can assume a first logic state corresponding to the power supply voltage VQPS or a second logic state corresponding to the partial voltage HVDD; and the second intermediate signal psvq_i may be presented as a first logic state corresponding to the partial voltage HVDD or as a second logic state corresponding to the partial voltage LVDD. Similar to the power switch control circuit P1 (of the voltage supply circuit 100 of fig. 1), the power switch control circuit P2 may generate a third intermediate signal PV having opposite logic states corresponding to the partial voltage LVDD and the ground voltage, respectively. In other words, the first intermediate signal qgb can transition from the partial voltage HVDD (e.g., 1.2V) to the supply voltage VQPS (e.g., 1.8V) within the first voltage domain; the second intermediate signal psvq_i may transition from the partial voltage LVDD (e.g., 0.6V) to the partial voltage HVDD (e.g., 1.2V) within the second voltage domain; and the third intermediate signal PV may transition from ground (e.g., 0V) to the partial voltage LVDD (e.g., 0.6V) within the third voltage domain.

The first, second and third inverters I10 to I13, I14 to I17 and I18 to I20 each respectively input a first intermediate signal qgb, a second intermediate signal psvq_i and a third intermediate signal PV to jointly determine the voltage level VDDQ at the output node N11. For example, to output a signal VDDQ of 1.8V (VQPS), the voltage level shifter L1 provides an intermediate signal qgb at logic low (e.g., 1.2V), and the voltage level shifter L2 provides an intermediate signal psvq_i at logic low (e.g., 0.6V), while the power switch control circuit P2 provides an intermediate signal PV at logic high (e.g., 0.6V). Thus, the intermediate signals qg2b_i and qg2b_ii can be output as logic low by the first inverters I10-I13 and the second inverters I14-I17, respectively, which turns on the PMOS transistor M20 (where the PMOS transistor M21 is on), turns on the PMOS transistor M22 and turns off the NMOS transistor M23 (where the NMOS transistor M24 is off). The intermediate signal pstb1 may be output as logic low by the third inverters I18 to 20, which turns off the NMOS transistor M25. Thus, the supply voltage VQPS (e.g., 1.8V) may be transferred to the node N11 through the turned-on transistors M20, M21, and M22 as the output signal VDDQ, while keeping the node N11 decoupled from ground through the turned-off transistors M23, M24, and M25.

On the other hand, to output the signal VDDQ at 0V (ground), the voltage level shifter L1 provides the intermediate signal qgb at logic high (e.g., 1.8V), and the voltage level shifter L2 provides the intermediate signal psvq_i at logic high (e.g., 1.2V), while the power switch control circuit P2 provides the intermediate signal PV at logic low (e.g., 0V). Thus, the intermediate signals qg2b_i and qg2b_ii can be output as logic high by the first inverters I10-I13 and the second inverters I14-I17, respectively, which turns off the PMOS transistor M20, turns off the PMOS transistor M22 and turns on the NMOS transistor M23. The intermediate signal pstb1 may be output as logic high by the third inverters I18 to 20, which turns on the NMOS transistor M25. Thus, the output signal VDDQ may be coupled to ground voltage through the turned-on transistors M23, M24, and M25, while maintaining the node N11 decoupled from the supply voltage VQPS through the turned-off transistors M20, M21, and M22.

Fig. 4 is an example circuit diagram of yet another voltage supply circuit 400 depicted in accordance with some embodiments. The voltage supply circuit 400 is similar to the voltage supply circuit 300 (shown in fig. 3) except that even with two voltage generators, the voltage supply circuit 400 may have one level shifter. As such, the voltage supply circuit 400 may also convert the input voltage to a relatively wider voltage domain (as compared to the voltage supply circuit 100), or may operate at a lower voltage stress in each transistor of the voltage supply circuit 400 (as compared to the voltage supply circuit 100). Therefore, the following description of the voltage supply circuit 400 will focus on the difference point.

For example, the voltage supply circuit 400 includes a first partial voltage generator G1 and a second partial voltage generator G2, a voltage level shifter L1, a power switch control circuit P2, a first set of serially coupled inverters I10, I11, I12, and I13, and a second set of serially coupled inverters I18, I19, and I20. The voltage generators G1 and G2 can respectively provide the first partial voltage HVDD and the second partial voltage LVDD. In some embodiments, the power supply voltage VQPS (received by the voltage supply circuit 300) may be about 1.8V, while the partial voltage HVDD is about two-thirds of the power supply voltage VQPS, i.e., about 1.2V, and the partial voltage LVDD is about one-third of the power supply voltage VQPS, i.e., about 0.6V. The partial voltages HVDD and LVDD may supply the voltage level shifters L1 and L2, respectively.

Based on the principle of operation of the level shifter C1 (of the voltage supply circuit 100 of fig. 1) similar, the voltage level shifter L1 may generate the first intermediate signal qgb based on the partial voltage HVDD. For example, the first intermediate signal qgb may take on a first logic state corresponding to the power supply voltage VQPS or a second logic state corresponding to the partial voltage HVDD. Similar to the power switch control circuit P1 (of the voltage supply circuit 100 of fig. 1), the power switch control circuit P2 may generate the second intermediate signal PV having opposite logic states corresponding to the partial voltage LVDD and the ground voltage, respectively. In other words, the first intermediate signal qgb can transition from the partial voltage HVDD (e.g., 1.2V) to the supply voltage VQPS (e.g., 1.8V) within the first voltage domain; and the second intermediate signal PV may transition from ground (e.g., 0V) to a partial voltage LVDD (e.g., 0.6V) within the second voltage domain.

The first inverters I10-I13 and the second inverters I18-I20 each respectively input a first intermediate signal qgb and a second intermediate signal PV to collectively determine the voltage level VDDQ at the output node N11. For example, to output a signal VDDQ of 1.8V (VQPS), the voltage level shifter L1 provides an intermediate signal qgb at logic low (e.g., 1.2V), while the power switch control circuit P2 provides an intermediate signal PV at logic high (e.g., 0.6V). Thus, the intermediate signal qg2b_i is output as logic low by the first inverters I10-I13, which turns on the PMOS transistor M20 (wherein the PMOS transistor M21 is turned on). The intermediate signal pstb1 may be output as logic low by the third inverters I18 to 20, which turns off the NMOS transistor M25. Thus, the supply voltage VQPS (e.g., 1.8V) may be transferred to the node N11 through the turned-on transistors M20 and M21 as the output signal VDDQ, while keeping the node N11 decoupled from ground through the turned-off transistor M25.

On the other hand, in order to output the signal VDDQ at 0V (ground), the voltage level shifter L1 supplies the intermediate signal qgb at logic high (e.g., 1.8V), and the power switch control circuit P2 supplies the intermediate signal PV at logic low (e.g., 0V). Thus, the intermediate signal qg2b_i can be output as logic high by the first inverters I10-I13, which turns on the PMOS transistor M20. The intermediate signal pstb1 may be output as logic high by the third inverters I18 to 20, which turns on the NMOS transistor M25. Thus, the output signal VDDQ may be coupled to ground voltage through the turned-on transistors M22 and M25, while the node N11 is kept decoupled from the supply voltage VQPS through the turned-off transistor M20.

Fig. 5 is an example circuit diagram of yet another voltage supply circuit 500 depicted in accordance with some embodiments. Voltage supply circuit 500 is similar to voltage supply circuit 300 (shown in fig. 3), except that voltage supply circuit 500 may further include a voltage detector. As such, the voltage supply circuit 500 may also convert the input voltage to a relatively wider voltage domain (as compared to the voltage supply circuit 100), or may operate at a lower voltage stress in each transistor of the voltage supply circuit 500 (as compared to the voltage supply circuit 100). Therefore, the following description about the voltage supply circuit 500 will focus on the difference point.

In various embodiments, the voltage supply circuit 500 includes a voltage detector VD1 to detect whether a lower logic voltage VDD for driving control signals (e.g., control signals YSELB, YSELB', PS, PD, etc.) is ready or stable compared to the power supply voltage VQPS. For example, if the logic voltage VDD is not ready when the power voltage VQPS is already provided, the voltage detector VD1 can force the output signal VDDQ to ground. In some embodiments, the voltage detector VD1 (which essentially consists of a plurality of inverters with relatively weak PMOS transistors) may output another intermediate signal Vx based on comparing the voltage level of the logic voltage VDD with the voltage level of the power supply voltage VQPS. In response to determining that the logic voltage VDD is not ready, the voltage detector VD1 outputs an intermediate signal Vx at logic high. Thus, the inverter I18 receives a logic low, which is pulled to ground by the NMOS transistor M30 turned on by the intermediate signal Vx of logic high, regardless of whether the intermediate signal PV is output as logic high or low. Thus, the intermediate signal pstb1 may be output with logic high, thereby turning on the NMOS transistor M25 to pull the output signal VDDQ to ground.

Fig. 6 is an example circuit diagram of another voltage level shifter C2, depicted in accordance with various embodiments. The voltage level shifter C2 is similar to the voltage level shifter C1 (shown in fig. 1), in that some connections between the NMOS transistors M9 and M10 are changed. Therefore, the following description will focus on the difference point. As shown in fig. 6, the gate of the NMOS transistor M10 is connected to the gate of the PMOS transistor M8, instead of being connected to the source of the PMOS transistor M8 (as shown in fig. 1). Similarly, the gate of NMOS transistor M9 is connected to the gate of PMOS transistor M7, rather than to the source of PMOS transistor M7 (as shown in FIG. 1).

Fig. 7 is an example circuit diagram of a voltage generator 700 of one of the various embodiments of the voltage generator MG (shown in fig. 1). The voltage generator 700 may generate a partial voltage (e.g., MVDD) based on a power supply voltage (e.g., VQPS) and a ground voltage (e.g., VSS).

As shown in fig. 7, the voltage generator 700 includes a first portion V1, a second portion V2, and a third portion V3. The first part V1 may act as a power divider, the second part V2 may act as a push/pull driver, and the third part V3 may be used to stabilize the output (i.e., the partial voltage MVDD). In some embodiments, the first portion V1 includes two sets of resistors R1 and R2, a plurality of NMOS transistors, and a plurality of PMOS transistors to collectively generate a bias voltage; the second portion V2 includes a plurality of NMOS transistors and a plurality of PMOS transistors to pull or push the output together; and the third section V3 includes a plurality of MOS capacitors to collectively stabilize the output. In some other embodiments, each resistor may be implemented as a MOS diode while remaining within the scope of the present disclosure. In general, the partial voltage MVDD is equal to the ratio of the first set of resistors R1 to the second set of resistors R2 multiplied by the supply voltage VQPS:

MVDD＝N×VQPS

Wherein the coefficient N is defined as:

R2/(R1+R2)

for example, when R1/R2 is equal to 1, N is equal to 1/2. Thus, MVDD is equal to 1/2 XVQPS. In another example, when R1/R2 is equal to 1/2, N is equal to 2/3. Thus, MVDD is equal to 2/3 XVQPS. When R1/R2 is equal to 2, N is equal to 1/3. Thus, MVDD is equal to 1/3 XVQPS.

Fig. 8 is an example circuit diagram of a voltage generator 800 of one of the various embodiments of the combination of voltage generators G1 and G2 (as shown in fig. 3, 4 and 5). The voltage generator 800 may generate a plurality of partial voltages (e.g., HVDD and LVDD) based on a power supply voltage (e.g., VQPS) and a ground voltage (e.g., VSS). The voltage generator 800 is similar to the voltage generator 700. Therefore, the following description about the voltage generator 800 will focus on the difference point.

As shown in fig. 8, voltage generator 800 includes a combination of voltage generators 810 and 850, each of voltage generators 810 and 850 being similar to voltage generator 700 (e.g., including three portions operably coupled to each other). For example, the voltage generator 810 may provide the first partial voltage HVDD based on a ratio of the first group resistor R1 to the second group resistor R2 multiplied by the power supply voltage VQPS; and the voltage generator 850 may provide the second partial voltage LVDD based on a ratio of the first set of resistors R1 'to the second set of resistors R2' multiplied by the power supply voltage VQPS. As a non-limiting example, the ratio of R1 to r1+r2 (22 to 60) may be about 0.36 and the ratio of R2 to r1+r2 (38 to 60) may be about 0.63, this condition results in outputs HVDD and LVDD of about 0.6V and 1.2V, respectively (when VQPS is 1.8V). In addition, the voltage generator 800 includes a voltage divider also coupled between the power voltage VQPS and the ground voltage to provide reference voltages vref_h and vref_l to the voltage generators 810 and 850, respectively. In some embodiments, the voltage divider may include three sets of resistors R3, R4, and R5. Continuing with the example above, the ratio of the three sets of resistors R3, R4, and R5 may be 11:8:11.

FIG. 9 is a flowchart depicting an example method 900 for operating a voltage supply circuit of an embodiment of the present disclosure, according to various embodiments. It should be noted that the method 900 is merely an example and is not intended to limit the present disclosure. Thus, it should be understood that any additional operations may be provided during, before, and after the method 900 of fig. 9, and that some other operations may be described only briefly in this disclosure. The method 900 may be used to operate a voltage supply circuit 100, 300, 400, or 500. Accordingly, the operation of method 900 will be described below in connection with the elements illustrated in fig. 1-8.

Briefly, the method 900 begins with an operation 902 of generating a first portion of a supply voltage, followed by an optional operation 904 of generating a second portion of the supply voltage, followed by an operation 906 of generating a first intermediate signal based on at least the first portion of the supply voltage, followed by an operation 908 of generating a second intermediate signal based on at least one or more control signals, followed by an operation 910 of providing an output voltage based on the first intermediate signal and the second intermediate signal. In various embodiments, the output voltage is presented as a supply voltage or a ground voltage.

Corresponding to operation 902 of fig. 9, a first portion of the voltage, which is a first fraction of the supply voltage, may be generated by the voltage generator. In the example of fig. 1, the voltage generator MG of the voltage supply circuit 100 (shown in fig. 1) may generate a partial voltage MVDD, which is a fraction of the power supply voltage VQPS. In various embodiments, the partial voltage MVDD may be such that each transistor of the disclosed voltage level converter C1 (shown in fig. 1) or C2 (fig. 6) may operate at relatively low voltage stress (e.g., below 1V). Thus, each transistor, whether implemented as an NMOS or PMOS, may be implemented as a core device having a relatively thin gate dielectric layer while being immune to high voltage stress.

Corresponding to optional operation 904 of fig. 9, another portion of the voltage that is the second small portion of the supply voltage may be generated by another voltage generator. In the examples of fig. 3 to 5, the first partial voltage and the second partial voltage may be generated by the voltage generators G1 and G2, respectively. The plurality of partial voltages allows each transistor of one disclosed voltage level shifter (e.g., L1 of fig. 4) or a plurality of voltage level shifters (e.g., L1 and L2 of fig. 3 or 5) to operate at relatively low voltage stress (e.g., below 1V). The following description of method 900 will primarily use an example of a single partial voltage (e.g., fig. 1).

Corresponding to operation 906 of fig. 9, the first intermediate signal may be generated by a voltage level converter. Continuing with the example of fig. 1, the voltage level shifter C1 may generate the intermediate signal qgb based on the first partial voltage MVDD (along with a pair of control signals YSELB and YELB'). In various embodiments, with the aid of the level shifter C1, the control signals YESLB and TESLB' (in a first voltage domain, e.g., from 0V to 0.75V) may be converted or otherwise output as an intermediate signal qgb in a different second voltage domain, e.g., from the partial voltage MVDD (0.9V) to the supply voltage VQPS (1.8V), while maintaining each transistor of the level shifter C1 accepting relatively low voltage stress (e.g., no greater than 0.9V).

Corresponding to operation 908 of fig. 9, the second intermediate signal may be generated by a power switch control circuit. Continuing with the example of fig. 1, the power switch control circuit P1 may generate the intermediate signal PV based on the first partial voltage MVDD (along with a pair of control signals PS and PD). In various embodiments, the power switch control circuit P1 may also include a voltage level shifter powered by the partial voltage MVDD, which may shift or otherwise output the control signal PS/PD (from a first voltage domain, e.g., from 0V to 0.75V) as an intermediate signal PV in a different third voltage domain, e.g., from ground (0V) to the partial voltage MVDD (0.9V).

Corresponding to operation 910 of fig. 9, an output voltage may be provided based on the first intermediate signal and the second intermediate signal. Continuing with the example of fig. 1, the first intermediate signal qgb and the second intermediate signal PV may be input to a first set of serially coupled inverters (e.g., I1-I4) and a second set of serially coupled inverters (e.g., I5-I9), respectively. With the first and second intermediate signals configured to be in the appropriate logic states, the output voltage may be provided in a fourth voltage domain, e.g., from ground (0V) to supply voltage VQPS (1.8V), while maintaining each transistor of inverters I1-I9 subject to relatively low voltage stress (e.g., no greater than 0.9V).

Referring again to the voltage supply circuit 100 of fig. 1, a plurality of voltage multi-structures S1 may be "stacked" between PMOS transistors M3 and M4 and NMOS transistors M1 and M2 to handle the higher supply voltage VQPS (so as to output a voltage VDDQ having a wider voltage level) while maintaining each transistor accepting a relatively low voltage stress (e.g., no greater than 0.9V). In other words, the level of the power supply voltage VQPS may be proportional to the number of stacked voltage multi-structures S1. For example, when the power supply voltage VQPS is equal to about 1.8V, the voltage supply circuit 100 may include a voltage multi-structure S1 (shown in fig. 1). In another example, when the supply voltage VQPS is equal to about 3.6V, the supply circuit 100 may include two voltage multi-structures S1 stacked between the PMOS transistors M3 and M4 and the NMOS transistors M1 and M2.

An embodiment of the present disclosure provides a voltage supply circuit. The voltage supply circuit comprises a first NMOS transistor, wherein the first NMOS transistor takes a first control signal as a grid electrode and takes a grounding voltage as a source electrode. The voltage supply circuit comprises a second NMOS transistor with a second control signal complementary to the first control signal as a gate and a ground voltage as a source. The voltage supply circuit comprises a first PMOS transistor, and the first PMOS transistor takes a first power supply voltage as a source electrode. The voltage supply circuit comprises a second PMOS transistor, and the second PMOS transistor takes the first power supply voltage as a source electrode. The voltage supply circuit comprises a voltage modulation circuit, and the voltage modulation circuit is coupled between the first PMOS transistor and the second PMOS transistor and between the first NMOS transistor and the second NMOS transistor and is used for providing a first intermediate signal based on a first control signal and a second control signal. In some embodiments, the first intermediate signal has a first logic state corresponding to a first supply voltage or a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage. The voltage supply circuit comprises a power switch control circuit for outputting a third intermediate signal which assumes a first logic state corresponding to the second power supply voltage or a second logic state corresponding to the ground voltage.

In some embodiments, the voltage supply circuit further comprises an even number of first inverters coupled in series with each other, each first inverter coupled between the first power supply voltage and the second power supply voltage, wherein the first inverter is configured to output the second intermediate signal based on the first intermediate signal.

In some embodiments, the voltage supply circuit further comprises an odd number of second inverters serially coupled to each other, each second inverter coupled between the second power supply voltage and the ground voltage, wherein the second inverter is configured to output a fourth intermediate signal based on the third intermediate signal.

In some embodiments, the voltage supply circuit further includes a third PMOS transistor having a gate for the second intermediate signal, a source for the first supply voltage, and a drain for the output voltage.

In some embodiments, the voltage supply circuit further includes a third NMOS transistor having a gate of the fourth intermediate signal, a source of the ground voltage, and a drain of the output voltage.

In some embodiments, the output voltage is to be in a first logic state in response to the third PMOS transistor being on and the third NMOS transistor being off, and the output voltage is to be in a second logic state in response to the third PMOS transistor being off and the third NMOS transistor being on.

In some embodiments, the output voltage exhibits a first logic state corresponding to a first supply voltage or a second logic state corresponding to a ground voltage.

In some embodiments, the voltage regulating circuit includes a fourth NMOS transistor, a fifth NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The fourth NMOS transistor takes the second power supply voltage as a grid electrode and is connected to the first NMOS transistor. The fifth NMOS transistor takes the second power supply voltage as a grid electrode and is connected to the second NMOS transistor. The fourth PMOS transistor has a drain voltage of the fourth NMOS transistor as a gate and a second power supply voltage as a drain. The fifth PMOS transistor has a drain voltage of the fifth NMOS transistor as a gate and a second power supply voltage as a drain. The sixth NMOS transistor has a source voltage of a fourth PMOS transistor that is also coupled to the first intermediate signal as a gate. The seventh NMOS transistor has a source voltage of a fifth PMOS transistor that is also coupled to the first intermediate signal as a gate.

In some embodiments, each of the first through seventh NMOS transistors and the first through fifth PMOS transistors has a voltage drop of less than 1 volt between any two of its plurality of terminals.

In some embodiments, each of the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor has the same gate oxide thickness.

In another embodiment of the present disclosure, a voltage supply circuit is provided. The voltage supply circuit includes a first partial voltage generator for generating a first voltage, which is a first fraction of the power supply voltage. The voltage supply circuit comprises a first level shifter, wherein the first level shifter is powered by a power supply voltage and is used for generating a first intermediate signal based on the first voltage; the voltage supply circuit includes a plurality of first inverters coupled between a supply voltage and a first voltage for coupling the supply voltage to the output node based on a first intermediate signal. The voltage supply circuit includes a plurality of second inverters coupled between the first voltage and the ground voltage or between the second voltage and the ground voltage for coupling the output node to the ground voltage, wherein the second voltage is a second fraction of the power supply voltage.

In some embodiments, the voltage supply circuit further comprises a second partial voltage generator to generate a second voltage, wherein the second voltage is a second fraction of the supply voltage.

In some embodiments, the voltage supply circuit further includes a second level shifter to receive the second voltage from the second partial voltage generator and output a second intermediate signal.

In some embodiments, the voltage supply circuit further comprises a plurality of third inverters coupled between the first voltage and the second voltage, wherein the plurality of third inverters are connected between the second level shifter and the output node for coupling the supply voltage to the output node based on the second intermediate signal.

In some embodiments, the voltage supply circuit further comprises a power switch control circuit to output a third intermediate signal to the plurality of second inverters, the third intermediate signal being presented in a first logic state corresponding to the first voltage, decoupling the ground voltage from the output node, or in a second logic state corresponding to the ground voltage, coupling the ground voltage to the output node.

In some embodiments, the voltage supply circuit further comprises a voltage detector coupled to the plurality of second inverters, wherein the voltage detector is configured to determine whether to forcibly couple the output node to the ground voltage based on comparing the power supply voltage with the logic power supply voltage.

In some embodiments, each transistor of the first level shifter has a voltage drop of less than 1 volt between any two of its plurality of terminals.

Yet another embodiment of the present disclosure provides a method of converting a plurality of voltage levels. The method includes receiving a first portion voltage that is a first fraction of a supply voltage. The method includes providing a first intermediate signal based on a first partial voltage, the first intermediate signal exhibiting a first logic state corresponding to a supply voltage or a second logic state corresponding to the first partial voltage. The method includes outputting an output voltage based on the first intermediate signal, the output voltage being a power supply voltage or a ground voltage.

In some embodiments, the method further comprises the steps of: receiving a second partial voltage as a second small portion of the power supply voltage; providing a second intermediate signal based on the second partial voltage, the second intermediate signal assuming a first logic state corresponding to the supply voltage or a second logic state corresponding to the second partial voltage; and outputting an output voltage based on the second intermediate signal, the output voltage being a power supply voltage or a ground voltage.

In some embodiments, the method further comprises the steps of: providing a third intermediate signal that assumes a first logic state corresponding to the first partial voltage or a second logic state corresponding to the ground voltage; and outputting an output voltage based on the third intermediate signal, the output voltage being a power supply voltage or a ground voltage.

As used herein, the terms "about" and "approximately" generally refer to plus or minus 10% of the value. For example, about 0.5 would comprise 0.45 and 0.55, about 10 would comprise 9 to 11, and about 1000 would comprise 900 to 1100.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A voltage supply circuit, comprising:

a first NMOS transistor with a first control signal as gate and a ground voltage as source;

a second NMOS transistor with a second control signal complementary to the first control signal as a gate and the ground voltage as a source;

a first PMOS transistor having a first power supply voltage as a source;

A second PMOS transistor using the first power supply voltage as a source electrode;

a voltage modulation circuit coupled between the first PMOS transistor to the second PMOS transistor and the first NMOS transistor to the second NMOS transistor for providing a first intermediate signal based on the first control signal and the second control signal, wherein the first intermediate signal assumes a first logic state corresponding to the first power supply voltage or a second logic state corresponding to a second power supply voltage that is a fraction of the first power supply voltage; and

A power switch control circuit is used for outputting a third intermediate signal which is in a first logic state corresponding to the second power voltage or in a second logic state corresponding to the grounding voltage.

2. The voltage supply circuit of claim 1, further comprising:

an even number of first inverters serially coupled to each other, each first inverter coupled between the first power supply voltage and the second power supply voltage;

the even number of the first inverters are used for outputting a second intermediate signal based on the first intermediate signal.

3. The voltage supply circuit of claim 2, further comprising:

An odd number of second inverters serially coupled to each other, each second inverter being coupled between the second power supply voltage and the ground voltage;

the odd number of second inverters are used for outputting a fourth intermediate signal based on the third intermediate signal.

4. The voltage supply circuit of claim 3, further comprising:

and a third PMOS transistor having the second intermediate signal as a gate, the first power supply voltage as a source, and an output voltage as a drain.

5. The voltage supply circuit of claim 4, further comprising:

and a third NMOS transistor having the fourth intermediate signal as a gate, the ground voltage as a source, and the output voltage as a drain.

6. The voltage supply circuit of claim 5 wherein the output voltage is configured to be in a first logic state in response to the third PMOS transistor being on and the third NMOS transistor being off, and the output voltage is configured to be in a second logic state in response to the third PMOS transistor being off and the third NMOS transistor being on.

7. The voltage supply circuit of claim 1 wherein the voltage modulation circuit comprises:

A fourth NMOS transistor having the second power supply voltage as a gate and connected to the first NMOS transistor;

a fifth NMOS transistor having the second power supply voltage as a gate and connected to the second NMOS transistor;

a fourth PMOS transistor having a drain voltage of the fourth NMOS transistor as the gate and the second power supply voltage as the drain;

a fifth PMOS transistor having a drain voltage of the fifth NMOS transistor as the gate and the second power supply voltage as the drain;

a sixth NMOS transistor having a source voltage of the fourth PMOS transistor that is also coupled to the first intermediate signal as a gate; and

A seventh NMOS transistor having a source voltage of the fifth PMOS transistor also coupled to the first intermediate signal as a gate.

8. The voltage supply circuit of claim 7 wherein each of the first through seventh NMOS transistors and the first through fifth PMOS transistors has a voltage drop between any two of its terminals of less than 1 volt.

9. A voltage supply circuit, comprising:

a first partial voltage generator for generating a first voltage, the first voltage being a first fraction of a power supply voltage;

A first level shifter powered by the power supply voltage for generating a first intermediate signal based on the first voltage;

a plurality of first inverters coupled between the power supply voltage and the first voltage for coupling the power supply voltage to an output node based on the first intermediate signal; and

And a plurality of second inverters coupled between the first voltage and a ground voltage or between a second voltage and the ground voltage for coupling the output node to the ground voltage, wherein the second voltage is a second fraction of the power supply voltage.

10. A method of converting a plurality of voltage levels, comprising the steps of:

receiving a first partial voltage as a first fraction of a supply voltage;

providing a first intermediate signal based on the first partial voltage, the first intermediate signal exhibiting a first logic state corresponding to the power supply voltage or a second logic state corresponding to the first partial voltage; and

Based on the first intermediate signal, an output voltage is output, wherein the output voltage is the power supply voltage or a ground voltage.