CN117607666A - Pseudo-random test parameter generation method, aging test method and scan chain circuit - Google Patents
Pseudo-random test parameter generation method, aging test method and scan chain circuit Download PDFInfo
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Abstract
The invention discloses a pseudo-random test parameter generation method, an aging test method and a scan chain circuit, wherein the pseudo-random test parameter generation method comprises the following steps: initializing a scan chain circuit to generate at least one output value; acquiring a previous output value of the scan chain circuit, and executing a bit operation method comprising binary bit level conversion operation on the previous output value to obtain a current output value of the scan chain circuit; and repeatedly executing the bit level conversion operation until reaching a preset time threshold, and taking the current output value as a pseudo-random test parameter. The invention automatically generates the pseudo random number input parameters of the scan chain circuit by repeatedly using the output value and the bit level conversion operation of the previous scan chain circuit, and replaces the real random number, thereby not only simulating various input conditions possibly occurring in practical application, but also increasing the test coverage rate; and the degree of automation of the test can be improved, the manual intervention is reduced, and the test efficiency is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit design technologies, and in particular, to a pseudo-random test parameter generating method, an aging test method, and a scan chain circuit.
Background
As digital circuits age, a reliable test method is needed to evaluate and verify the correctness and stability of the digital circuits. Scan chain circuits are a commonly used test method, which is widely applied to the technology of testing a device under test (such as a chip), and verify the functional correctness and stability of the device under test by inputting a specific signal into an input port of the device under test and observing the result of an output port. In other words, if the test is to be completed by the scan chain circuit, a series of complete input information must be input from the scan chain circuit input terminal to ensure complete test coverage of the device under test.
At present, the burn-in test of a device under test requires strict control of the electrical excitation conditions due to the influence of the test mode and the test purpose so as to simulate the worst case possibly encountered by the device under test under the actual working conditions, and if the burn-in test is performed on a test machine, it may not be ensured that the applied electrical excitation conditions are completely consistent with the conditions encountered by the device in actual use, which may affect the accuracy and reliability of the test result. In order to avoid these problems, the burn-in test of the device under test cannot be performed on the test machine, and is not performed on the test machine, which means that the scan chain circuit lacks a self-complete random signal input sequence, and thus cannot guarantee complete test coverage.
Disclosure of Invention
The invention aims to provide a pseudo-random test parameter generation method, which aims to solve the technical problems that the prior art cannot generate self-complete pseudo-random test parameters applied to a scan chain circuit, so that the test efficiency and the test coverage rate are low.
One of the objectives of the present invention is to provide a scan chain circuit.
One of the purposes of the present invention is to provide a burn-in system.
In order to achieve one of the above objects, the present invention provides a pseudo-random test parameter generating method, which is applied to a scan chain circuit, the method comprising: initializing a scan chain circuit to generate at least one output value; acquiring a previous output value of the scan chain circuit, and executing a bit operation method comprising binary bit level conversion operation on the previous output value to obtain a current output value of the scan chain circuit; and repeatedly executing the bit level conversion operation until reaching a preset time threshold, and taking the current output value as a pseudo-random test parameter.
As a further improvement of an embodiment of the present invention, the scan chain circuit is disposed in the device under test; the pseudo-random test parameter is used as a test input parameter of the scan chain circuit when the tested device executes the burn-in test.
As a further improvement of an embodiment of the present invention, the bit operation method includes a shift operation strategy and a logic operation strategy; wherein the shift operation strategy comprises at least one of a left shift operation and a right shift operation; the logic operation strategy comprises at least one of a logical AND operation and a logical OR operation.
As a further improvement of an embodiment of the present invention, the "initializing the scan chain circuit to generate at least one output value" specifically includes: and configuring the scan chain circuit to be in a cascade state, and generating at least one initialization output value according to the current true random number.
As a further improvement of one embodiment of the present invention, the "generating at least one initialization output value according to the current true random number" specifically includes: processing the current true random number and the reset output value according to a logic operation strategy, and generating a first output value as the initialization output value; the "performing a bit operation method including a binary bit level conversion operation on the previous output value" to obtain the current output value of the scan chain circuit specifically includes: and taking the first output value as the previous output value and executing binary bit level conversion operation to obtain a second output value as the current output value.
As a further improvement of an embodiment of the present invention, the scan chain circuit includes a seed register; before the generating at least one initialization output value according to the current true random number, the method further comprises: and receiving and updating the current true random number stored in the seed register according to a preset time interval.
As a further improvement of an embodiment of the present invention, the "performing a bit operation method including a binary bit level conversion operation on the previous output value" to obtain the current output value of the scan chain circuit specifically includes: determining a current shift operation based on the shift operation strategy, and executing the current shift operation on the previous output value to obtain a current shift intermediate value; and determining a current logical operation based on the logical operation strategy, and executing the current logical operation on the current shift intermediate value and the previous output value to obtain the current output value of the scan chain circuit.
As a further improvement of an embodiment of the present invention, the scan chain circuit performs a first shift operation and a first logic operation at a first time, and generates a first output value; at a second time after the first time, the "determining, based on the shift operation policy, a current shift operation, and executing the current shift operation on the previous output value, to obtain a current shift intermediate value" specifically includes: based on the shift operation strategy, fixing a second shift operation after the first shift operation, and executing the second shift operation on the first output value to obtain a second shift intermediate value; the step of determining a current logical operation based on the logical operation policy, and performing the current logical operation on the current shift intermediate value and the previous output value to obtain the current output value of the scan chain circuit specifically includes: and based on the logic operation strategy, fixing a second logic operation after the first logic operation, and executing the second logic operation on the second shift intermediate value and the first output value to obtain a second output value as the current output value at the second moment.
As a further improvement of an embodiment of the present invention, the "repeatedly performing the bit level conversion operation until reaching the preset time threshold, and taking the current output value as the pseudo random test parameter" specifically includes: determining a current scanning time corresponding to the current output value; judging whether the current scanning time is smaller than a preset scanning time threshold value or not; if yes, the scanning chain circuit is controlled to continuously and repeatedly execute the bit level conversion operation, and the current output value is used as the previous output value of the next iteration; if not, fixing the current output value as the pseudo-random test parameter.
In order to achieve one of the above objects, the present invention also provides a scan chain circuit comprising: a first register, configured to obtain a previous output value of a scan chain circuit, and execute a first operation policy including binary bit level conversion operation on the previous output value; the second register is coupled to the first register and is used for executing a second operation strategy comprising binary bit level conversion operation according to the output of the first register to obtain a current output value; the method comprises the steps of using a current output value as a pseudo-random test parameter when an iteration ending signal is received; and, the circuit is used for initializing a scan chain circuit and generating at least one output value; and the timer is coupled to the second register and used for timing and outputting the iteration ending signal to the second register when the iteration duration reaches a preset time threshold.
As a further improvement of an embodiment of the present invention, the first register is configured to store and implement a shift operation policy, and the second register is configured to store and implement a logic operation policy; the shift operation strategy comprises at least one of a left shift operation and a right shift operation; the logic operation strategy comprises at least one of a logical AND operation and a logical OR operation.
As a further improvement of an embodiment of the present invention, the scan chain circuit further includes: a seed register for receiving and updating the stored current true random number according to a preset time interval when coupled to the true random number generator; the current true random number is used to initialize a scan chain circuit.
In order to achieve one of the above objects, the present invention further provides a burn-in test system, comprising: the scan chain circuit is arranged in the tested device, when the tested device receives the aging test instruction, the pseudo-random test parameter generated by the pseudo-random test parameter generation method is used as a test input parameter of the scan chain circuit, and the simulation accelerated aging operation is performed on the tested device under the guidance of the pseudo-random test parameter.
Compared with the prior art, the embodiment of the invention has at least one of the following beneficial effects:
the invention adopts a pseudo-random test parameter generation method, and automatically generates the pseudo-random test parameters of the scan chain circuit by repeatedly using the output value and the bit level conversion operation of the previous scan chain circuit, thereby replacing the real random number, not only simulating various possible input conditions in practical application, but also increasing the comprehensiveness and coverage rate of the test; moreover, the automation degree of the generation process of the pseudo-random test parameters is high, a more comprehensive test input value is generated through iterative operation, and more circuit states are covered through automatic test, so that the test can be completed in a shorter time, and the test efficiency is improved.
Drawings
FIG. 1 is a schematic diagram illustrating steps of a method for generating pseudo-random test parameters according to an embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating steps of a pseudo random test parameter generating method according to a first embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating steps of a method for generating pseudo-random test parameters according to a second embodiment of the present invention.
Fig. 4 is a schematic diagram showing a refinement step of step S2 of the pseudo-random test parameter generating method according to an embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating a refinement step of step S3 of the pseudo random test parameter generating method according to an embodiment of the present invention.
FIG. 6 is a schematic diagram of a scan chain circuit according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of a preferred embodiment of a pseudo-random test parameter generating method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the invention and structural, methodological, or functional modifications of these embodiments that may be made by one of ordinary skill in the art are included within the scope of the invention.
It should be noted that the term "comprises," "comprising," or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The method for generating the test parameters of the scan chain circuit is an important method for using pseudo random numbers to replace true random numbers to detect the performance and the reliability of the circuit, and can perform comprehensive and effective aging test by generating effective pseudo random test parameters serving as test input parameters of the scan chain circuit, so that the generation of the pseudo random test parameters has important practical significance.
Based on this, the invention provides a pseudo-random test parameter generation method, as shown in fig. 1, which specifically includes the following steps:
step S1, initializing a scanning chain circuit and generating at least one output value;
step S2, obtaining a previous output value of the scan chain circuit, and executing a bit operation method comprising binary bit level conversion operation on the previous output value to obtain a current output value of the scan chain circuit;
and S3, repeatedly executing the bit level conversion operation until reaching a preset time threshold, and taking the current output value as a pseudo-random test parameter.
Thus, by repeatedly using the output value of the previous scan chain circuit and the bit level conversion operation, the pseudo-random number test parameters are automatically generated, and the pseudo-random number test parameters can replace real random numbers to simulate various input conditions possibly occurring in practical application, so that the test coverage rate is increased.
Wherein the scan chain circuit is a structure for testing and fault diagnosis that can be used to serially access and operate several registers or flip-flops in an integrated circuit. In particular, loading a test pattern or scan pattern into a scan chain circuit may transfer data and control signals between registers or flip-flops in an integrated scan chain circuit for testing or fault diagnosis.
It should be noted that the pseudo-random test parameter generating method may be applied to a scan chain circuit, and the scan chain circuit may be disposed in a device under test. In particular, the pseudo-random test parameters may be used as test input parameters for the scan chain circuit when the device under test performs burn-in testing. In other words, the scan chain circuit may perform the corresponding operations by receiving and parsing control signals as part of internal testing and diagnostics of the device under test.
Further, the bit operation method may include a shift operation strategy and a logic operation strategy for step S2. Wherein the shift operation policy may include at least one of a left shift operation and a right shift operation; the logical operation policy may include at least one of a logical AND operation and a logical OR operation.
It should be noted that the shift operation strategy is not limited to a certain shift operation, and may include a combination of a plurality of shift operation operations, and different shift operation strategies (i.e., different shift operation operations or a combination thereof) may be used when different iteration numbers are performed. In other words, the iterative operation process and the shift operation strategy may establish a corresponding mapping relationship. Similarly, the logic operation strategy and the shift operation strategy have similar characteristics, and reference may be made to the description of the shift operation strategy, which is not described herein.
Initializing the scan chain circuit in step S1 may include setting an initial state and an initial output value of the scan chain circuit to ensure normal operation of the subsequent scan chain circuit.
Specifically, in one aspect, the pseudo-random test parameters may be used for burn-in testing of a device under test (e.g., a chip), where the scan chain circuit is subjected to an initialization operation for the burn-in test prior to the burn-in testing using the scan chain circuit, e.g., setting the initialization state of the scan chain circuit to a cascade state, to provide a preparation for a subsequent generation of test input parameters for the burn-in test.
Based on this, in one embodiment, the following steps may be specifically included for step S1:
step S1', the scan chain circuit is configured to be in a cascade state, and at least one initialization output value is generated according to the current true random number.
Therefore, through setting the cascade state, the quick and stable connection and communication of a plurality of circuits inside the tested device can be realized, and the overall operation efficiency and performance of the tested device are improved.
The cascade state may refer to a process of connecting a plurality of devices or components in a certain order, receiving or processing an input signal and outputting a signal, and may be understood as a staged process in which each component or device receives an output signal of a previous component or device and serves as an input signal of a current component or device. Therefore, data transmission among a plurality of devices can be realized, not only can the functional test of single devices or components be realized, but also the test of the whole system can be realized, and the test coverage rate is improved.
When the scan chain circuit is in the cascade state, the scan chain circuit is set to the scan chain mode, and the scan chain mode can be used for conveniently determining whether the scan chain circuit is in the normal working state by detecting the state of each circuit in cascade connection. In this way, direct access to all flip-flops in the device under test by the CPU can be avoided, thereby quickly determining the operational state of all circuits.
In particular, the scan chain circuit may receive and parse a control signal sent from the JTAG (Joint Test Action Group) port, which may contain a plurality of commands or data, where the commands and data may be used to set register values for the scan chain circuit. When the scan chain circuit receives the control signal, the scan chain circuit may update a value of a register in the scan chain circuit according to the command and the data, and set the scan chain circuit to a cascade state. The JTAG port is a standard interface for detecting, debugging and programming chips, and can be embedded into a digital integrated circuit to realize remote control and debugging of the chips.
On the other hand, when the scan chain circuit is in the cascade state, the initialization scan chain circuit may further include an initialization output value, where the initialization output value may be the last output value of the current iteration of the scan chain circuit.
Based on this, as shown in fig. 2, in the first embodiment, the pseudo random test parameter generating method may specifically include the steps of:
step P1, receiving and updating the current true random number stored in the seed register according to a preset time interval;
based on this, step S1' may specifically include:
s1', configuring the scan chain circuit to be in a cascade state, processing the current true random number and the reset output value according to a logic operation strategy, and generating a first output value as the initialization output value;
in the step S2, the "performing a bit operation method including a binary bit level conversion operation on the previous output value" to obtain the current output value of the scan chain circuit may specifically include:
s2', taking the first output value as the previous output value and executing binary bit level conversion operation to obtain a second output value as the current output value;
and S3, repeatedly executing the bit level conversion operation until reaching a preset time threshold, and taking the current output value as a pseudo-random test parameter.
Therefore, the reset output value and the current true random number of the scan chain circuit are obtained to generate the initialization output value, so that the behavior and the state of the circuit can be accurately reflected, the true random and the accuracy of the test are enhanced, the quality and the reliability of the generation parameters of the scan chain circuit are improved, and the test coverage rate is improved.
The reset output value in step S1″ may refer to a specific state or value output by the output terminal after the scan chain circuit is reset. The specific reset output value may vary from circuit design to circuit design and from reset logic to reset logic.
Further, in order to ensure the randomness of the output result of the scan chain circuit, the scan chain circuit may further include a seed register, where the data stored in the seed register is a true random number and may be used as a random data source of the scan chain circuit.
As shown in fig. 3, in the second embodiment, the pseudo random test parameter generating method may specifically include the following steps:
step S1, initializing a scanning chain circuit and generating at least one output value;
step S21, based on the shift operation strategy, determining a current shift operation, and executing the current shift operation on the previous output value to obtain a current shift intermediate value;
step S22, based on the logic operation strategy, determining the current logic operation, and executing the current logic operation on the current shift intermediate value and the previous output value to obtain the current output value of the scan chain circuit;
and S3, repeatedly executing the bit level conversion operation until reaching a preset time threshold, and taking the current output value as a pseudo-random test parameter.
Therefore, the behavior and the state of the scan chain circuit can be simulated more accurately based on the shift operation strategy and the logic operation strategy, so that the integrity and the randomness of the output value are ensured, and the quality of the output value is improved.
Wherein, based on the shift operation strategy and the logic operation strategy, the shift operation strategy and the logic operation strategy are not limited to a single shift operation and logic operation, and different operation strategies can be selected according to different iteration times. In other words, the scan chain circuit may perform different shift operation policies and logic operation policies at different times.
Further, as shown in fig. 4, in one embodiment, it may be assumed that the scan chain circuit performs a first shift operation and a first logic operation at a first time to generate a first output value; at a second time point after the first time point, step S21 may specifically include:
step S21', based on the shift operation strategy, fixing a second shift operation after the first shift operation, and executing the second shift operation on the first output value to obtain a second shift intermediate value;
similarly, step S22 may specifically include:
step S22', based on the logic operation policy, fixing a second logic operation after the first logic operation, and executing the second logic operation on the second shift intermediate value and the first output value to obtain a second output value as the current output value at the second moment.
In this way, the specific shift operation and logic operation are determined based on the shift operation strategy and the logic operation strategy, so that the scan chain circuit can execute different operations according to different strategies and time points, and the flexibility is high, and the expansion and maintenance are easy.
The first time point does not necessarily refer to an initial time point of performing the binary bit level shift operation by the scan chain circuit, and may refer to any time point of performing the level shift operation by the scan chain circuit, at which time the scan chain circuit may sequentially perform the first shift operation and the first logic operation.
In addition, the first shifting operation and the second shifting operation can be the same or different, and can be set according to actual requirements. When the shift operation strategy includes a single shift operation, the first shift operation and the second shift operation are the same, and the processing mode of the previous output value at the first moment is the same as the processing mode of the first output value at the second moment, but the execution time has a sequence.
When the shift operation policy includes a plurality of shift operation operations, the first shift operation and the second shift operation may be different, and a processing manner of a previous output value at a first time is different from a processing manner of the previous output value at a second time, and there is a sequence in execution time. Similarly, the first logic operation and the second logic operation have the same characteristics, and are not described herein.
In addition, step S1 'and step S1″ are derivative steps of step S1, and step S2', step S21 to step S22, and step S21 'to step S22' are derivative steps of step S2.
To facilitate understanding of the above procedure, for example, assume that a first shift operation (e.g., shift left by one bit) and a first logic operation (e.g., a logical or operation) are performed at a first time, a binary number 01100101 having a first output value of 8 bits is generated, and at a second time after the first time, if the shift operation strategy sets a shift left by one bit (i.e., a second shift operation), a second shift intermediate value is 00110010; if the logic operation policy sets a logical and operation (i.e., a second logic operation), a second shift intermediate value of 0100101 & 00110010=00100000 is obtained.
In order to balance the efficiency of generating parameters of the scan chain circuit and the coverage rate of the scan chain circuit, reasonable time limit can be set, so that the parameter generation efficiency can be improved and unnecessary resource consumption can be reduced while certain test coverage rate is ensured.
Based on this, as shown in fig. 5, in one embodiment, for step S3, the present invention provides a refinement step, which may specifically include:
step S31, determining the current scanning time corresponding to the current output value;
step S32, judging whether the current scanning time is smaller than a preset scanning time threshold value;
if yes, step S33A is skipped, the scanning chain circuit is controlled to continuously and repeatedly execute the bit level conversion operation, and the current output value is used as the previous output value of the next iteration;
if not, step S33B is skipped, and the current output value is fixed as the pseudo-random test parameter.
Therefore, through accurate time control, flexible iterative scanning and reliable output result determination, the pseudo-randomness and the comprehensiveness of the test parameters of the scan chain circuit are improved, and the coverage range of the scan chain circuit test is enlarged.
The current output value can be understood as the current output value at the current moment. Of course, the iterative process is not limited to the determination of the scan time, but can also be determined by the pseudo-randomness of the random test parameters generated by the scan chain circuit. Specifically, in the iteration process, if the pseudo-randomness of the randomness test parameter generated by the scan chain circuit reaches the preset standard, the test is considered to be sufficient, iteration is not required to be continued, and the current output value (i.e. the output value generated in the last iteration) is fixed as the randomness test parameter, so that the iteration process can be controlled more accurately, and the comprehensiveness and efficiency of the scan chain circuit test are ensured.
The invention also provides a scan chain circuit which can correspondingly execute the pseudo-random test parameter generation method to generate corresponding test input parameters. The test input parameters are input into a scan chain circuit of a tested device, and burn-in test is executed to finish self-completeness test of the scan chain circuit (the scan chain circuit generates the test input parameters, and the scan chain circuit finishes the burn-in test).
Based on this, as shown in fig. 6, the scan chain circuit may include:
a first register, configured to obtain a previous output value of a scan chain circuit, and execute a first operation policy including binary bit level conversion operation on the previous output value;
the second register is coupled to the first register and is used for executing a second operation strategy comprising binary bit level conversion operation according to the output of the first register to obtain a current output value; the method comprises the steps of using a current output value as a pseudo-random test parameter when an iteration ending signal is received; and, the circuit is used for initializing a scan chain circuit and generating at least one output value;
and the timer is coupled to the second register and used for timing and outputting the iteration ending signal to the second register when the iteration duration reaches a preset time threshold.
Therefore, the randomness of the data can be improved by controlling the first register and the second register to execute the operation strategy and the iteration control comprising the binary bit level conversion operation, and the comprehensive coverage rate of the subsequent aging test is ensured.
Wherein the first register may be used to store and implement a shift operation policy and the second register may be used to store and implement a logic operation policy; the shift operation policy may include at least one of a left shift operation and a right shift operation; the logical operation policy may include at least one of a logical AND operation and a logical OR operation.
In particular, a shift operation register may be employed to store the second operation policy (i.e., a logical operation policy); the first operation policy (i.e., shift operation policy) is stored by a logical operation register, and may be used to record a type of shift operation (e.g., shift left, shift right, etc.), a number of bits shifted (e.g., a number of bits shifted, etc.), and a start time of the shift operation. The start time of the shift operation is preferably all initialization values in the registers are set.
Of course, the present invention is not limited to the use of registers, and other storage spaces are also possible, and the registers are not limited to the storage bit operation method, but may also store bit operation steps or bit operation flows. These steps may be some column operations from initializing configuration parameter settings to final output results, without specific limitation.
Furthermore, the scan chain circuit further includes: a seed register for receiving and updating the stored current true random number according to a preset time interval when coupled to the true random number generator; the current true random number is used to initialize a scan chain circuit.
Therefore, the true random number is received and updated according to the preset time interval, so that the true random number is used for initializing a scanning chain circuit, and the randomness and the reliability of the test are improved.
Wherein the seed register is designed to be able to be coupled to a true random number generator. This means that the seed register can take the true random numbers directly from the true random number generator and use these to initialize the scan chain circuit. This initialization approach may increase the randomness and unpredictability of the scan chain circuit, thereby increasing the coverage and reliability of the test.
In addition, the true random number generator is used for generating random number seeds, and the random number seeds output by the true random number generator are generated based on physical random phenomena or processes, and the phenomena or processes have true randomness.
Preferably, after each iteration, the true random number is controlled to generate a new true random number and update it into the seed register, so that it is ensured that the current true random number is updated after each iteration. The updating mechanism can cover more circuit states, increase test diversity and coverage, and improve test coverage.
The various embodiments, examples or specific examples provided herein may be combined with one another to ultimately form a plurality of preferred embodiments.
For example, fig. 7 shows a schematic diagram of the principle structure of the scan chain circuit in a preferred embodiment. The process of the preferred embodiment will be summarized below in connection with fig. 7.
Initializing the scan chain circuit specifically includes storing and implementing a shift operation policy by employing a shift operation register (i.e., a first register), storing and implementing a logic operation policy by employing a logic algorithm register (i.e., a second register), updating and storing a current true random number by employing a seed register.
And configuring the scan chain circuit to be in a cascade state, wherein all circuits enter a scan chain mode except a seed register where a current true random number is located, a shift operation register where a shift operation strategy and a logic operation strategy are located and a logic algorithm register.
Controlling a true random number generator to periodically generate a true random number, and periodically updating the true random number into the seed register; calculating to obtain the previous output value of the scanning chain circuit according to the current true random number updated in the seed register and the logic operation strategy set in the shift operation register; determining a current shift operation based on a shift operation strategy set in the shift operation register, and executing the current shift operation on the previous output value to obtain a current shift intermediate value, wherein the current shift intermediate value can be stored in another shift register; and determining a current logical operation based on a logical operation strategy set in the logical operation register, and executing the current logical operation on the current shift intermediate value and the previous output value to obtain the current output value of the scan chain circuit.
And using a timer coupled to the logic operation register to time and outputting the iteration ending signal to the second register when the iteration duration reaches a preset time threshold value, and taking the current output value as a pseudo-random test parameter.
The invention also provides an aging test system, which comprises: the device comprises a scan chain circuit, wherein the scan chain circuit is arranged in a tested device, when the tested device receives an aging test instruction, a pseudo-random test parameter generated by executing the pseudo-random test parameter generation method is used as a test input parameter of the scan chain circuit, and the simulated accelerated aging operation is executed on tested equipment under the guidance of the pseudo-random test parameter.
In the system, the scan chain circuit is not only an input end of a test (receiving pseudo-random test parameters) but also an output end of the test (performing simulation accelerated aging on a tested device), so that the closed loop test of the scan chain circuit can be realized, and the accuracy and the reliability of the test can be improved.
The simulation accelerates the initialization operation of aging, and can simulate aging and aging conditions caused by long-time use of a tested device (such as a chip), so that the reliability and durability of the chip can be detected and analyzed more accurately. In the present invention, the initial values of the seed register, the shift operation register, and the logic operation register may be set using a JTAG port.
In summary, the present invention obtains the current output value of the scan chain circuit by acquiring the previous output value and the bit operation method of the scan chain circuit in the device under test and performing a binary bit level conversion operation on the previous output value according to the bit operation method; and iterating until the scanning time of the scanning chain circuit reaches a preset time threshold value, and generating a pseudo-random test parameter. The method has strong controllability, and by repeatedly executing the shift operation of the previous output value, the current shift intermediate value after shift, and the logic operation of the previous output value and the current shift intermediate value, the degree of automation of the test is improved, the manual intervention is reduced, and the test efficiency is improved; and the pseudo-random number input parameters of the scan chain circuit are automatically generated, and the pseudo-random number input parameters can replace real random numbers, so that various input conditions possibly occurring in practical application can be simulated, and the coverage rate of the test is increased.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.
Claims (14)
1. A method for generating a pseudo-random test parameter, wherein the method for generating the pseudo-random test parameter is applied to a scan chain circuit, and the method comprises the following steps:
initializing a scan chain circuit to generate at least one output value;
acquiring a previous output value of the scan chain circuit, and executing a bit operation method comprising binary bit level conversion operation on the previous output value to obtain a current output value of the scan chain circuit;
and repeatedly executing the bit level conversion operation until reaching a preset time threshold, and taking the current output value as a pseudo-random test parameter.
2. The method of claim 1, wherein the scan chain circuit is disposed within a device under test;
the pseudo-random test parameter is used as a test input parameter of the scan chain circuit when the tested device executes the burn-in test.
3. The pseudo-random test parameter generating method according to claim 1, wherein the bit operation method comprises a shift operation strategy and a logic operation strategy; wherein the shift operation strategy comprises at least one of a left shift operation and a right shift operation; the logic operation strategy comprises at least one of a logical AND operation and a logical OR operation.
4. The method of claim 1, wherein the initializing the scan chain circuit to generate at least one output value comprises:
and configuring the scan chain circuit to be in a cascade state, and generating at least one initialization output value according to the current true random number.
5. The method of claim 4, wherein generating at least one initialization output value based on the current true random number comprises:
processing the current true random number and the reset output value according to a logic operation strategy, and generating a first output value as the initialization output value;
the "performing a bit operation method including a binary bit level conversion operation on the previous output value" to obtain the current output value of the scan chain circuit specifically includes:
and taking the first output value as the previous output value and executing binary bit level conversion operation to obtain a second output value as the current output value.
6. The method of generating pseudo-random test parameters according to claim 4, wherein the scan chain circuit comprises a seed register; before the generating at least one initialization output value according to the current true random number, the method further comprises:
and receiving and updating the current true random number stored in the seed register according to a preset time interval.
7. The method for generating pseudo-random test parameters according to claim 3, wherein said performing a bit operation method including a binary bit level conversion operation on said previous output value to obtain a current output value of said scan chain circuit comprises:
determining a current shift operation based on the shift operation strategy, and executing the current shift operation on the previous output value to obtain a current shift intermediate value;
and determining a current logical operation based on the logical operation strategy, and executing the current logical operation on the current shift intermediate value and the previous output value to obtain the current output value of the scan chain circuit.
8. The method of claim 7, wherein the scan chain circuit performs a first shift operation and a first logic operation at a first time to generate a first output value; at a second time after the first time, the "determining, based on the shift operation policy, a current shift operation, and executing the current shift operation on the previous output value, to obtain a current shift intermediate value" specifically includes:
based on the shift operation strategy, fixing a second shift operation after the first shift operation, and executing the second shift operation on the first output value to obtain a second shift intermediate value;
the step of determining a current logical operation based on the logical operation policy, and performing the current logical operation on the current shift intermediate value and the previous output value to obtain the current output value of the scan chain circuit specifically includes:
and based on the logic operation strategy, fixing a second logic operation after the first logic operation, and executing the second logic operation on the second shift intermediate value and the first output value to obtain a second output value as the current output value at the second moment.
9. The method for generating a pseudo-random test parameter according to claim 1, wherein the step of repeatedly performing the bit level conversion operation until reaching a predetermined time threshold, and using the current output value as the pseudo-random test parameter specifically comprises:
determining a current scanning time corresponding to the current output value;
judging whether the current scanning time is smaller than a preset scanning time threshold value or not;
if yes, the scanning chain circuit is controlled to continuously and repeatedly execute the bit level conversion operation, and the current output value is used as the previous output value of the next iteration;
if not, fixing the current output value as the pseudo-random test parameter.
10. A scan chain circuit, comprising:
a first register, configured to obtain a previous output value of a scan chain circuit, and execute a first operation policy including binary bit level conversion operation on the previous output value;
the second register is coupled to the first register and is used for executing a second operation strategy comprising binary bit level conversion operation according to the output of the first register to obtain a current output value; the method comprises the steps of using a current output value as a pseudo-random test parameter when an iteration ending signal is received; and, the circuit is used for initializing a scan chain circuit and generating at least one output value;
and the timer is coupled to the second register and used for timing and outputting the iteration ending signal to the second register when the iteration duration reaches a preset time threshold.
11. The scan chain circuit of claim 10, wherein the first register is to store and implement a shift operation policy and the second register is to store and implement a logic operation policy; the shift operation strategy comprises at least one of a left shift operation and a right shift operation; the logic operation strategy comprises at least one of a logical AND operation and a logical OR operation.
12. The scan chain circuit according to claim 10, wherein the scan chain circuit further comprises:
a seed register for receiving and updating the stored current true random number according to a preset time interval when coupled to the true random number generator; the current true random number is used to initialize a scan chain circuit.
13. A burn-in test system, comprising:
the device comprises a scan chain circuit, wherein the scan chain circuit is arranged in a device under test, when the device under test receives an aging test instruction, the pseudo-random test parameters generated by the pseudo-random test parameter generation method according to any one of claims 1-9 are used as test input parameters of the scan chain circuit, and the simulation accelerated aging operation is performed on the device under test under the guidance of the pseudo-random test parameters.
14. The burn-in system of claim 13 further comprising a true random number generator for coupling to the scan chain circuit only during an initialization phase to provide a true random number for initializing the scan chain circuit.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5574733A (en) * | 1995-07-25 | 1996-11-12 | Intel Corporation | Scan-based built-in self test (BIST) with automatic reseeding of pattern generator |
| CN1858999A (en) * | 2005-08-17 | 2006-11-08 | 华为技术有限公司 | Pseudo-random sequence generating device |
| CN101515479A (en) * | 2009-03-30 | 2009-08-26 | 北京中星微电子有限公司 | Method for increasing test coverage of scan chain and device thereof |
| CN102749574A (en) * | 2012-07-18 | 2012-10-24 | 中国科学院微电子研究所 | Scan test method and scan test circuit |
| CN103592593A (en) * | 2012-08-13 | 2014-02-19 | 亚德诺半导体股份有限公司 | Semiconductor circuit and methodology for in-system scan testing |
| CN111694546A (en) * | 2020-06-12 | 2020-09-22 | 成都海光集成电路设计有限公司 | Method and device for generating pseudo-random binary sequence code |
| CN114076883A (en) * | 2021-11-10 | 2022-02-22 | 北京中电华大电子设计有限责任公司 | Aging circuit, chip aging test method and chip |
| CN116699372A (en) * | 2023-08-08 | 2023-09-05 | 北京燧原智能科技有限公司 | Chip burn-in test circuit |
-
2023
- 2023-12-28 CN CN202311824185.3A patent/CN117607666B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5574733A (en) * | 1995-07-25 | 1996-11-12 | Intel Corporation | Scan-based built-in self test (BIST) with automatic reseeding of pattern generator |
| CN1858999A (en) * | 2005-08-17 | 2006-11-08 | 华为技术有限公司 | Pseudo-random sequence generating device |
| CN101515479A (en) * | 2009-03-30 | 2009-08-26 | 北京中星微电子有限公司 | Method for increasing test coverage of scan chain and device thereof |
| CN102749574A (en) * | 2012-07-18 | 2012-10-24 | 中国科学院微电子研究所 | Scan test method and scan test circuit |
| CN103592593A (en) * | 2012-08-13 | 2014-02-19 | 亚德诺半导体股份有限公司 | Semiconductor circuit and methodology for in-system scan testing |
| CN111694546A (en) * | 2020-06-12 | 2020-09-22 | 成都海光集成电路设计有限公司 | Method and device for generating pseudo-random binary sequence code |
| CN114076883A (en) * | 2021-11-10 | 2022-02-22 | 北京中电华大电子设计有限责任公司 | Aging circuit, chip aging test method and chip |
| CN116699372A (en) * | 2023-08-08 | 2023-09-05 | 北京燧原智能科技有限公司 | Chip burn-in test circuit |
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