CN117596865A

CN117596865A - Memory device and method of forming the same

Info

Publication number: CN117596865A
Application number: CN202310927425.6A
Authority: CN
Inventors: 王言虹; 刘威; 刘雅琴; 黄诗琪; 陈亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-08-10
Filing date: 2023-07-26
Publication date: 2024-02-23

Abstract

A memory device is disclosed that includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a memory cell having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed on one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with a second side of the first peripheral circuit remote from the memory array structure.

Description

Memory device and method of forming the same

Cross Reference to Related Applications

The present application claims priority from U.S. provisional application No.63/396,753 filed 8/10 at 2022, the entire contents of which are incorporated herein by reference.

Background

The present disclosure relates to a memory device and a method of manufacturing the same.

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, planar processing and fabrication techniques become challenging and costly. As a result, the storage density of the planar memory cell approaches the upper limit.

A three-dimensional (3D) memory architecture may address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuitry for facilitating operation of the memory array.

Disclosure of Invention

In one aspect, a memory device is disclosed. The memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a memory portion having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed on one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with a second side of the first peripheral circuit remote from the memory array structure.

In some implementations, the first peripheral circuit includes a sense amplifier circuit and a word line driver circuit. In some implementations, the second peripheral circuit includes an analog circuit.

In some embodiments, the memory array structure includes a first surface having a pad extraction structure and a second surface opposite the first surface in a first direction in contact with the first peripheral circuit.

In some embodiments, the memory portion is disposed between the first surface and the vertical transistor in the first direction. In some embodiments, the vertical transistor is disposed between the first surface and the memory portion in the first direction.

In some embodiments, the memory device further includes a first connection structure extending between the first peripheral circuit and the second peripheral circuit in the first direction.

In some embodiments, the memory device further includes a second connection structure extending in the first direction in the memory array structure between the first surface and the second surface. In some embodiments, the second connection structure is in contact with the pad extraction structure.

In some embodiments, the first peripheral circuitry is disposed in a first peripheral substrate, the second peripheral circuitry is disposed in a second peripheral substrate, and the thickness of the first peripheral substrate is less than the thickness of the second peripheral substrate.

In some embodiments, a vertical transistor includes a semiconductor body extending in a first direction and a gate structure coupled to at least one side of the semiconductor body in a second direction perpendicular to the first direction.

In another aspect, a storage system is disclosed. The storage system includes: a storage device configured to store data; and a memory controller coupled to the memory device and configured to control the memory array structure through the first peripheral circuit. The memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a memory portion having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed on one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with a second side of the first peripheral circuit remote from the memory array structure.

In yet another aspect, a storage device is disclosed. The memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor and a memory portion coupled to the vertical transistor. The first peripheral circuit is disposed on one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with a second side of the first peripheral circuit remote from the memory array structure.

In some implementations, the first peripheral circuit includes a first connection structure extending through the first peripheral substrate in a first direction.

In yet another aspect, a storage system is disclosed. The storage system includes: a storage device configured to store data; and a memory controller coupled to the memory device and configured to control the memory array structure through the first peripheral circuit. The memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor and a memory portion coupled to the vertical transistor. The first peripheral circuit is disposed on one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with a second side of the first peripheral circuit remote from the memory array structure.

In yet another aspect, a method for forming a memory device is disclosed. The memory array structure is formed on a first substrate. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a memory portion having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. Peripheral circuitry is formed on one side of the memory array structure. The peripheral circuit includes a first peripheral circuit and a second peripheral circuit.

In some embodiments, the first peripheral circuit and the second peripheral circuit are formed as peripheral circuits by stacking together, and the memory array structure is bonded to the peripheral circuits.

In yet another aspect, a method for forming a memory device is disclosed. The memory array structure is formed on a first substrate. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a memory portion having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is formed in the second substrate. The third substrate is formed on the first peripheral circuit. The second peripheral circuit is formed on the third substrate. The memory array structure is bonded to the second peripheral circuit.

In some embodiments, the vertical transistor is formed on the fourth substrate such that the second terminal of the vertical transistor is in contact with the fourth substrate. The memory portion is formed on the vertical transistor such that a first end of the memory portion is coupled to a first terminal of the vertical transistor. The first substrate is formed on the storage portion. The fourth substrate is removed.

In some embodiments, the vertical transistor is formed on the first substrate such that the second terminal of the vertical transistor is in contact with the first substrate. The memory portion is formed on the vertical transistor such that a first end of the memory portion is coupled to a first terminal of the vertical transistor.

In some embodiments, a dielectric layer is formed on the third substrate. An implantation operation is performed on the third substrate. The third substrate is bonded on the first peripheral circuit. The dielectric layer is in contact with the first peripheral circuitry.

In some embodiments, a hydrogen ion implantation operation is performed on the third substrate from a side having the dielectric layer.

In some embodiments, a portion of the third substrate is removed. The second peripheral circuit is formed on the remaining portion of the third substrate.

In some embodiments, the first connection structure is formed in a second peripheral circuit extending through the third substrate.

In some embodiments, the memory array structure is bonded to the second peripheral circuit. The first substrate is removed. The pad extraction structure is formed on the memory array structure.

In yet another aspect, a method for forming a memory device is disclosed. The memory array structure is formed on a first substrate. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a memory portion having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is formed on the second substrate. The second peripheral circuit is formed on the third substrate. The first peripheral circuit is bonded to the second peripheral circuit. The memory array structure is bonded to the first peripheral circuit.

In some embodiments, the second substrate is thinned. A dielectric layer is formed on the thinned second substrate. The thinned second substrate is bonded to the second peripheral circuit such that the dielectric layer is in contact with the second peripheral circuit.

In some embodiments, the fifth substrate is formed on the first peripheral circuit. The fifth substrate is used as a supporting substrate to thin the second substrate. The thinned second substrate is bonded to the second peripheral circuit such that the thinned second substrate is in contact with the second peripheral circuit. The fifth substrate is removed.

In some embodiments, the first connection structure is formed in a first peripheral circuit extending through the second substrate.

In some embodiments, the memory array structure is bonded to the first peripheral circuit. The first substrate is removed. A pad extraction structure is formed over the memory array structure.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1A illustrates a schematic diagram of a cross-section of a memory device, according to some aspects of the present disclosure.

Fig. 1B illustrates a schematic diagram of a cross-section of another memory device, according to some aspects of the present disclosure.

Fig. 2 illustrates a schematic diagram of a memory device including peripheral circuitry and an array of memory cells each having vertical transistors, in accordance with some aspects of the present disclosure.

Fig. 3 illustrates a schematic circuit diagram of a memory device including peripheral circuitry and an array of Dynamic Random Access Memory (DRAM) cells, in accordance with some aspects of the present disclosure.

Fig. 4 illustrates a schematic circuit diagram of a memory device including peripheral circuitry and an array of Phase Change Memory (PCM) cells, in accordance with some aspects of the present disclosure.

Fig. 5 illustrates a schematic diagram of a cross-section of a storage device, according to some aspects of the present disclosure.

Fig. 6 illustrates a schematic diagram of a cross-section of a memory device, according to some aspects of the present disclosure.

Fig. 7-18 illustrate a fabrication process for forming a memory device including vertical transistors, in accordance with some aspects of the present disclosure.

Fig. 19 illustrates a flow chart of a method for forming a memory device, in accordance with some aspects of the present disclosure.

Fig. 20 illustrates a block diagram of a system having a storage device, in accordance with some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

Although specific constructions and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements may be used without departing from the scope of this disclosure. Moreover, the present disclosure may also be used in a variety of other applications. The functional and structural features as described in the present disclosure may be combined, adjusted, and modified from each other in a manner not specifically depicted in the drawings so that such combinations, adjustments, and modifications are within the scope of the present disclosure.

Generally, terms may be understood, at least in part, from the use of context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a" or "an" may be equally understood as conveying a singular usage or a plural usage, depending at least in part on the context. In addition, also depending at least in part on the context, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described.

It should be readily understood that the meanings of "on", "over" and "over" in this disclosure should be interpreted in the broadest sense so that "on" means not only directly on "something but also includes the meaning of having an intermediate feature or layer therebetween, and" over "or" over "means not only the meaning of" over "or" over "something, but also the meaning of" over "or" over "something and no intermediate feature or layer therebetween (i.e., directly on something).

Further, spatially relative terms, such as "below," "lower," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along tapered surfaces. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers in which interconnect lines and/or vertical interconnect access (via) contacts are formed, and one or more dielectric layers.

Transistors are used as switches or selection devices in memory cells of some memory devices, such as DRAM, PCM, and ferroelectric DRAM (FRAM). However, the planar transistors commonly used in existing memory cells have a horizontal structure with word lines buried in the substrate and bit lines over the substrate. Since the source and drain of the planar transistor are laterally disposed at different locations, the area occupied by the transistor is increased. The design of planar transistors also complicates the placement of interconnect structures (such as word lines and bit lines) coupled to memory cells, e.g., limits the pitch of word lines and/or bit lines, thereby increasing manufacturing complexity and reducing production yields. Further, since the bit line and the memory portion (e.g., capacitor or PCM element) are disposed on the same side of the planar transistor (above the transistor and substrate), the bit line process margin is limited by the memory portion, and the coupling capacitance between the bit line and the memory portion (e.g., capacitor) increases. As saturated drain currents continue to increase, planar transistors may also suffer from high leakage currents, which is undesirable for the performance of the memory device.

On the other hand, the memory cell array and the peripheral circuits for controlling the memory cell array are generally arranged side by side in the same plane. As the number of memory cells increases, the size of components (e.g., transistors, word lines, and/or bit lines) in the memory cell array needs to be reduced in order to maintain the same chip size, so as not to significantly reduce the memory cell array efficiency.

To address one or more of the foregoing problems, the present disclosure introduces a solution in which vertical transistors replace planar transistors as switches and select devices in memory cell arrays of memory devices (e.g., DRAM, PCM, and FRAM). Vertically arranged transistors (e.g., drain and source overlap in plan view) may reduce the area of the transistor and simplify the layout of interconnect structures, such as metal routing of word lines and bit lines, as compared to planar transistors, which may reduce manufacturing complexity and improve yield. For example, the pitch of the word lines and/or bit lines may be reduced for ease of fabrication. The vertical structure of the transistor also allows the bit line and the memory portion (e.g., capacitor) to be arranged on opposite sides of the transistor in a vertical direction (e.g., one above and one below the transistor) so that the process margin of the bit line can be increased and the coupling capacitance between the bit line and the memory portion can be reduced.

Consistent with the scope of the present disclosure, memory cell arrays having vertical transistors and peripheral circuits of the memory cell arrays may be formed on different wafers and bonded together in a face-to-face fashion, in accordance with some aspects of the present disclosure. Thus, the thermal budget used to fabricate the memory cell array does not affect the fabrication of the peripheral circuitry. The stacked memory cell array and peripheral circuits may also reduce chip size compared to a side-by-side arrangement, thereby improving array efficiency. In some embodiments, more than one memory cell array is stacked on top of each other using bonding techniques to further increase array efficiency. In some embodiments, the word lines and bit lines are disposed close to the bonding interface because the vertically arranged transistors may be coupled to the peripheral circuitry through a large number (e.g., millions) of parallel bonding contacts across the bonding interface that make direct, short-distance (e.g., micron-scale) electrical connections between the memory cell array and the peripheral circuitry to improve the throughput and input/output (I/O) speed of the memory device.

In some embodiments, the vertical transistors disclosed herein include multi-gate transistors (e.g., gate-all-around (GAA) transistors, tri-gate transistors, or double-gate transistors) that may have a larger gate control area, thereby achieving better channel control with a smaller sub-threshold swing. The leakage current of the multi-gate transistor can also be significantly reduced as the channel is fully depleted. Thus, using a multi-gate transistor instead of a planar transistor may achieve better speed (saturated drain current)/leakage current performance.

In some implementations, the vertical transistors disclosed herein include single gate transistors (also referred to as single side gate transistors) that are arranged mirror symmetrically with respect to transistors adjacent in the bit line direction due to the division of the multiple gate transistors (e.g., double gate transistors) using trench isolation extending in the word line direction. Thus, the memory cell density in the bit line direction may be significantly increased (e.g., doubled) as compared to using a process such as self-aligned double patterning (SADP) without unduly complicating the manufacturing process. Furthermore, mirror symmetric single gate transistors have a larger process window for word line, bit line, and transistor pitch reduction than planar transistors or multi-gate vertical transistors (e.g., with double sided or fully surrounding gates).

Fig. 1A illustrates a schematic diagram of a cross-section of a memory device 100, according to some aspects of the present disclosure. The memory device 100 represents an example of a bonded chip. The components of the memory device 100 (e.g., the memory cell array and the peripheral circuits) may be formed separately on different substrates and then bonded to form a bonded chip. The memory device 100 may include a first semiconductor structure 102, the first semiconductor structure 102 including peripheral circuitry of a memory cell array. The memory device 100 may further include a second semiconductor structure 104 including an array of memory cells. Peripheral circuitry (e.g., control and sense circuitry) may include any suitable digital, analog, and/or mixed signal circuitry for facilitating operation of the memory cell array. For example, the peripheral circuitry may include one or more of page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), input/output (e.g., I/O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the functional circuitry described above (e.g., subcircuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). According to some embodiments, the peripheral circuitry in the first semiconductor structure 102 uses Complementary Metal Oxide Semiconductor (CMOS) technology, which may be implemented, for example, by logic processes (e.g., technology nodes of 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

As shown in fig. 1A, the memory device 100 may further include a second semiconductor structure 104, the second semiconductor structure 104 including an array of memory cells (memory cell array) that may use transistors as switching and selection devices. In some embodiments, the array of memory cells comprises an array of DRAM cells. For convenience of description, the memory cell array in the present disclosure may be described by taking a DRAM cell array as an example. It should be understood that the memory cell array is not limited to a DRAM cell array and may include any other suitable type of memory cell array that may use transistors as switching and selection devices, such as PCM cell arrays, static Random Access Memory (SRAM) cell arrays, FRAM cell arrays, resistive memory cell arrays, magnetic memory cell arrays, spin Transfer Torque (STT) memory cell arrays, to name a few, or any combination thereof.

The second semiconductor structure 104 may be a DRAM device in which the memory cells are provided in the form of an array of DRAM cells. In some embodiments, each DRAM cell includes a capacitor for storing one bit of data as a positive or negative charge and one or more transistors (also referred to as pass transistors) that control (e.g., switch and select) access thereto. In some implementations, each DRAM cell is a transistor, a capacitor (1T 1C) cell. Since the transistor always leaks a small amount of charge, the capacitor slowly discharges, resulting in depletion of the information stored therein. Thus, according to some embodiments, the DRAM cells must be refreshed, for example, by peripheral circuitry in the first semiconductor structure 102, to retain the data.

As shown in fig. 1A, the memory device 100 further includes a bonding interface 106 vertically (in a vertical direction, e.g., the Z-direction in fig. 1A) between the first semiconductor structure 102 and the second semiconductor structure 104. As described in detail below, the first semiconductor structure 102 and the second semiconductor structure 104 may be fabricated separately (and in some embodiments in parallel) such that the thermal budget for fabricating one of the first and second semiconductor structures 102 and 104 does not limit the process of fabricating the other of the first and second semiconductor structures 102 and 104. Further, a large number of interconnects (e.g., bond contacts) may be formed through the bond interface 106 to form a direct, short-range (e.g., micron-sized) electrical connection between the first semiconductor structure 102 and the second semiconductor structure 104, as opposed to a long-range (e.g., millimeter or centimeter-sized) chip-to-chip data bus on a circuit board (e.g., a Printed Circuit Board (PCB)), thereby eliminating chip interface delays and achieving high-speed I/O throughput while reducing power consumption. Data transfer between the array of memory cells in the second semiconductor structure 104 and peripheral circuitry in the first semiconductor structure 102 may be performed through interconnections (e.g., bond contacts) across the bond interface 106. By vertically integrating the first and second semiconductor structures 102 and 104, the chip size may be reduced and the memory cell density may be increased.

It should be appreciated that the relative positions of the stacked first semiconductor structure 102 and second semiconductor structure 104 are not limited. Fig. 1B illustrates a schematic diagram of a cross-section of another storage device 101, according to some embodiments. In the memory device 100 of fig. 1A, the second semiconductor structure 104 including the memory cell array is located above the first semiconductor structure 102 including the peripheral circuit, unlike the memory device 100 of fig. 1A, in the memory device 101 of fig. 1B, the first semiconductor structure 102 including the peripheral circuit is located above the second semiconductor structure 104 including the memory cell array. However, according to some embodiments, in the memory device 101, the bonding interface 106 is formed vertically between the first semiconductor structure 102 and the second semiconductor structure 104, and the first semiconductor structure 102 and the second semiconductor structure 104 are vertically bonded by bonding (e.g., hybrid bonding). Hybrid bonding, also known as "metal/dielectric hybrid bonding", is a direct bonding technique (e.g., bonding between surfaces without the use of an intermediate layer such as solder or adhesive) and metal-to-metal (e.g., copper-to-copper) bonding and dielectric-to-dielectric (e.g., silicon oxide-to-silicon oxide) bonding can be achieved simultaneously. Data transfer between the array of memory cells in the second semiconductor structure 104 and peripheral circuitry in the first semiconductor structure 102 may be performed through interconnections (e.g., bond contacts) across the bond interface 106.

Note that X, Y and Z-axis are included in fig. 1A and 1B to further illustrate the spatial relationship of components in storage devices 100 and 101. The substrate of the memory device includes two lateral surfaces extending laterally in the X-Y plane: a top surface on the front side of the wafer on which the semiconductor devices may be formed, and a bottom surface on the back side opposite the front side of the wafer. The Z axis is perpendicular to the X and Y axes. As used herein, when a substrate of a memory device is located in the lowest plane of the memory device in the Z-direction (a perpendicular direction to the X-Y plane, such as the thickness direction of the substrate), whether one component (e.g., a layer or device) of the memory device is located "on", "above" or "below" another component (e.g., a layer or device) in the Z-direction is determined relative to the substrate of the memory device. The same concepts used to describe spatial relationships apply throughout this disclosure.

Fig. 2 illustrates a schematic diagram of a memory device 200 including peripheral circuitry and an array of memory cells each having vertical transistors, in accordance with some aspects of the present disclosure. The memory device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. The memory devices 100 and 101 may be examples of the memory device 200 in which the memory cell array 201 and the peripheral circuit 202 may be included in the second and first semiconductor structures 104 and 102, respectively. Memory cell array 201 may be any suitable memory cell array in which each memory cell 208 includes a vertical transistor 210 and a memory portion 212 coupled to vertical transistor 210. In some embodiments, memory cell array 201 is a DRAM cell array and memory portion 212 is a capacitor for storing charge as binary information stored by the corresponding DRAM cell. In some embodiments, memory cell array 201 is a PCM cell array and memory portion 212 is a PCM element (e.g., comprising a chalcogenide alloy) for storing binary information of a corresponding PCM cell based on different resistivities of the PCM element in amorphous and crystalline phases. In some embodiments, memory cell array 201 is an FRAM cell array and memory portion 212 is a ferroelectric capacitor for storing binary information of a corresponding FRAM cell based on switching between two polarization states of a ferroelectric material under an external electric field.

As shown in fig. 2, the memory cells 208 may be arranged in a two-dimensional (2D) array having rows and columns. Memory device 200 may include a word line 204 coupling peripheral circuitry 202 and memory cell array 201 for controlling the switching of vertical transistors 210 in memory cells 208 located in a row, and memory device 200 may also include a bit line 206 coupling peripheral circuitry 202 and memory cell array 201 for transmitting data to and/or receiving data from memory cells 208 located in a column. That is, each word line 204 is coupled to a respective row of memory cells 208, and each bit line is coupled to a respective column of memory cells 208.

Consistent with the scope of the present disclosure, a vertical transistor 210, such as a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET), may be substituted for a planar transistor as a pass transistor for the memory cell 208 to reduce the area occupied by the pass transistor, coupling capacitance, and interconnect wiring complexity, as described in detail below. As shown in fig. 2, in some embodiments, unlike planar transistors where the active region is formed in the substrate, vertical transistor 210 includes a semiconductor body 214 that extends vertically (in the Z-direction) above the substrate (not shown). That is, the semiconductor body 214 may extend above the top surface of the substrate to allow a channel to be formed not only at the top surface of the semiconductor body 214 but also at one or more side surfaces thereof. As shown in fig. 2, for example, the semiconductor body 214 may have a rectangular parallelepiped shape to expose four sides thereof. It should be appreciated that the semiconductor body 214 may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor body 214 in plan view (e.g., in the X-Y plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an oval shape), or any other suitable shape. It should be understood that, consistent with the scope of the present disclosure, for a semiconductor body that is circular or oval in cross-section in plan view, the semiconductor body may still be considered to have multiple sides such that the gate structure is in contact with more than one side of the semiconductor body. As described below with respect to the fabrication process, the semiconductor body 214 may be formed from a substrate (e.g., by etching or epitaxy) and thus have the same semiconductor material (e.g., silicon crystalline silicon) as the substrate (e.g., silicon substrate).

As shown in fig. 2, the vertical transistor 210 may further include a gate structure 216 in contact with one or more sides of the semiconductor body 214, for example in one or more planes of the side surface(s) of the active region. In other words, the active region of the vertical transistor 210 (e.g., the semiconductor body 214) may be at least partially surrounded by the gate structure 216. The gate structure 216 may include a gate dielectric 218 on one or more sides of the semiconductor body 214, e.g., in contact with four side surfaces of the semiconductor body 214, as shown in fig. 2. The gate structure 216 may also include a gate electrode 220 over and in contact with the gate dielectric 218. Gate dielectric 218 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 218 may include silicon oxide, which is a form of gate oxide. The gate electrode 220 may comprise any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 220 may comprise doped polysilicon, which is a form of gate polysilicon. In some embodiments, the gate electrode 220 includes a plurality of conductive layers, such as a W layer over a TiN layer. It should be appreciated that in some examples, the gate electrode 220 and the word line 204 may be a continuous conductive structure. In other words, the gate electrode 220 may be considered part of the word line 204 forming the gate structure 216, or the word line 204 may be considered an extension of the gate electrode 220 to be coupled to the peripheral circuitry 202.

As shown in fig. 2, the vertical transistor 210 may further include a pair of source and drain electrodes (S/D, doped regions, also referred to as source and drain electrodes) formed at both ends of the semiconductor body 214, respectively, in a vertical direction (z-direction). The source and drain may be doped with any suitable P-type dopant, such As boron (B) or gallium (Ga), or any suitable N-type dopant, such As phosphorus (P) or arsenic (As). The source and drain may be separated in the vertical direction (z-direction) by a gate structure 216. In other words, the gate structure 216 is vertically formed between the source and drain. As a result, one or more channels (not shown) of the vertical transistor 210 may be formed in the semiconductor body 214 vertically between the source and drain when a gate voltage applied to the gate electrode 220 of the gate structure 216 exceeds a threshold voltage of the vertical transistor. That is, according to some embodiments, each channel of the vertical transistor 210 is also formed in a vertical direction along which the semiconductor body 214 extends.

In some embodiments, as shown in fig. 2, vertical transistor 210 is a multi-gate transistor. That is, the gate structure 216 may contact more than one side (e.g., four sides in fig. 2) of the semiconductor body 214 to form more than one gate, such that more than one channel may be formed between the source and drain in operation. That is, unlike planar transistors that include only a single planar gate (and create a single planar channel), the vertical transistor 210 shown in fig. 2 may include multiple vertical gates on multiple sides of the semiconductor body 214 due to the 3D structure of the semiconductor body 214 and the gate structure 216 surrounding multiple sides of the semiconductor body 214. As a result, the vertical transistor 210 shown in fig. 2 may have a larger gate control area compared to a planar transistor, thereby achieving better channel control with a smaller sub-threshold swing. Since the channel is fully depleted, the leakage current (I _off ) Can also be significantly reduced. As described in detail below, the multi-gate vertical transistors may include double-gate vertical transistors (e.g., double-side gate vertical transistors), tri-gate vertical transistors (e.g., tri-side gate vertical transistors), and GAA vertical transistors.

It should be appreciated that although vertical transistor 210 is shown in fig. 2 as a multi-gate transistor, the vertical transistors disclosed herein may also include single gate transistors as described in detail below. That is, the gate structure 216 may be in contact with a single side of the semiconductor body 214, for example, for the purpose of increasing transistor and memory cell density. It should also be appreciated that although gate dielectric 218 is shown as separate (a separate structure) from the other gate dielectrics of adjacent vertical transistors (not shown), gate dielectric 218 may be part of a continuous dielectric layer having multiple gate dielectrics of vertical transistors.

In planar transistors and some lateral multi-gate transistors (e.g., finfets), the active region (e.g., semiconductor body (e.g., fin)) extends laterally (in the X-Y plane) and the source and drain are disposed at different locations in the same lateral plane (X-Y plane). In contrast, in the vertical transistor 210, the semiconductor body 214 extends vertically (in the Z-direction) and the source and drain are disposed in different lateral planes, according to some embodiments. In some embodiments, the source and drain are formed at both ends of the semiconductor body 214 in a vertical direction (Z direction), respectively, so as to overlap in a plan view. As a result, the area occupied by the vertical transistor 210 (in the X-Y plane) can be reduced compared to planar transistors and lateral multi-gate transistors. Also, since the interconnections can be routed in different planes, the metal routing coupled to the vertical transistor 210 can also be simplified. For example, the bit line 206 and the memory portion 212 may be formed on opposite sides of the vertical transistor 210. In one example, the bit line 206 may be coupled to a source or drain at an upper end of the semiconductor body 214, while the storage 212 may be coupled to another source or drain at a lower end of the semiconductor body 214.

As shown in fig. 2, the memory portion 212 may be coupled to a source or drain of the vertical transistor 210. The memory portion 212 may include any device capable of storing binary data (e.g., 0 and 1), including, but not limited to, capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells. In some implementations, the vertical transistors 210 control selection and/or status switches of respective memory portions 212 coupled to the vertical transistors 210.

Fig. 3 illustrates a schematic diagram of a memory device 200 including peripheral circuitry and an array of memory cells each having vertical transistors, in accordance with some aspects of the present disclosure. In some implementations, as shown in fig. 3, each memory cell 208 is a DRAM cell 302 that includes a transistor 304 (e.g., implemented using vertical transistor 210 in fig. 2) and a capacitor 306 (e.g., an example of memory portion 212 in fig. 2). A gate of transistor 304 (e.g., corresponding to gate electrode 220) may be coupled to word line 204, one of a source and a drain of transistor 304 may be coupled to bit line 206, the other of the source and the drain of transistor 304 may be coupled to one electrode of capacitor 306, and the other electrode of capacitor 306 may be coupled to ground.

Fig. 4 illustrates a schematic diagram of a memory device 200 including peripheral circuitry and an array of memory cells each having vertical transistors, in accordance with some aspects of the present disclosure. In some implementations, as shown in fig. 4, each memory cell 208 is a PCM cell 402 that includes a transistor 404 (e.g., implemented using vertical transistor 210 in fig. 2) and a PCM element 406 (e.g., an example of memory portion 212 in fig. 2). A gate of transistor 404 (e.g., corresponding to gate electrode 220) may be coupled to word line 204, one of a source and a drain of transistor 404 may be coupled to ground, the other of the source and the drain of transistor 404 may be coupled to one electrode of PCM element 406, and the other electrode of PCM element 406 may be coupled to bit line 206.

Fig. 5 illustrates a schematic diagram of a cross-section of a storage device 500, according to some aspects of the present disclosure. As shown in fig. 5, the memory device 500 includes a memory cell 502, a first peripheral circuit 532, and a second peripheral circuit 552.

The memory cell 502 includes a vertical transistor 504 extending in the Z-direction. In some implementations, the vertical transistor 504 includes a semiconductor body 506 extending in the Z-direction, a first terminal 508 (e.g., a source terminal), and a second terminal 510 (e.g., a drain terminal). As shown in fig. 5, the first and second terminals 508 and 510 are formed at both ends of the semiconductor body 506 in a Z direction, which is a stacking direction of the memory cell 502, the first and second peripheral circuits 532 and 552. The vertical transistor 504 also includes a gate structure 512 coupled to at least one side of the semiconductor body 506. In some embodiments, the gate structure 512 may be formed on one side of the semiconductor body 506, e.g., a single-sided gate structure. In some embodiments, gate structures 512 may be formed on both sides of the semiconductor body 506, such as a dual gate structure. In some embodiments, a gate structure 512 may be formed around the semiconductor body 506, e.g., a Gate All Around (GAA) structure. In some embodiments, the gate structure 512 may be a multi-layer structure including a gate dielectric layer, a barrier layer, and a metal gate layer.

In some implementations, the memory cell 502 also includes a memory portion 516 having a first end coupled to the first terminal 508 of the vertical transistor 504. In some implementations, the storage 516 may be one or more capacitors. The bit line 514 is coupled to the second terminal 510 of the vertical transistor 504. As shown in fig. 5, a bonding interface 530 is formed between the memory cell 502 and the first peripheral circuit 532, and a bonding interface 550 is formed between the first peripheral circuit 532 and the second peripheral circuit 552. In some implementations, the bonding interface 530 may be a boundary between the memory cell 502 and the first peripheral circuit 532, and the bonding interface 550 may be a boundary between the first peripheral circuit 532 and the second peripheral circuit 552. In some implementations, the bonding interface 530 and the bonding interface 550 may be interfaces between the memory cell 502 and the first peripheral circuit 532, and during bonding operations between the first peripheral circuit 532 and the second peripheral circuit 552. In some embodiments, the bit line 514 is disposed between the vertical transistor 504 and the bonding interface 550.

In some implementations, the first peripheral circuitry 532 (e.g., control and sense circuitry 536) and the second peripheral circuitry 552 (e.g., analog circuitry 556) may comprise any suitable digital, analog, and/or mixed signal circuitry for facilitating the operation of the memory cell 502. In some implementations, the first peripheral circuit 532 may include one or more of a sense amplifier, a driver (e.g., a word line driver), any portion of the functional circuits described above (e.g., a subcircuit), or any active or passive component of the circuit (e.g., a transistor, diode, resistor, or capacitor). In some implementations, the second peripheral circuit 552 may include one or more of analog circuits 556, page buffers, decoders (e.g., row and column decoders), input/output (I/O) circuits, charge pumps, voltage sources or generators, current or voltage references, any portion of the functional circuits described above (e.g., subcircuits), or any active or passive component of the circuit (e.g., transistors, diodes, resistors, or capacitors).

In some implementations, the first peripheral circuit 532 may include one or more sense amplifier circuits and one or more word line driver circuits. In some implementations, the second peripheral circuit 552 may include one or more analog circuits 556. According to some embodiments, the first peripheral circuit 532 is formed on or in the substrate 534 using Complementary Metal Oxide Semiconductor (CMOS) technology, which may be implemented with logic processes (e.g., technology nodes of 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). According to some embodiments, the second peripheral circuit 552 is formed on or in the substrate 554 using CMOS technology, which may be implemented with logic processes (e.g., technology nodes of 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

As shown in fig. 5, the memory cell 502 may have two opposing surfaces, and the first peripheral circuit 532 is bonded to one of the surfaces through the bonding interface 530. The other surface forms a pad structure 522.

In some embodiments, vertical transistor 504 is disposed between bit line 514 and memory portion 516 along the Z-direction. In some embodiments, the contact structure 520 is formed in the memory device 500 extending through the memory cell 502. In some embodiments, the contact structure 520 is in contact with the first peripheral circuit 532 and the pad structure 522. In some implementations, a contact structure 518 is formed in the memory device 500 that extends in the Z-direction to connect the bit line 514 to the first peripheral circuit 532. In some embodiments, a contact structure 519 is formed in the memory device 500 that extends in the Z-direction to connect the gate structure 512 to the first peripheral circuit 532.

In some implementations, the memory device 500 further includes a redistribution layer 524 disposed between the vertical transistor 504 and the bonding interface 530. In some implementations, the bit lines 514 are coupled to the first peripheral circuitry 532 through the contact structures 518 and the redistribution layer 524. Structure 518 may extend in the Z-direction in memory cell 502 as shown in fig. 5. In some implementations, the memory device 500 further includes a redistribution layer 538 formed in the first peripheral circuit 532, and devices in the first peripheral circuit 532 may be coupled to the bonding interface 530 through the redistribution layer 538.

In some embodiments, the memory device 500 further includes a redistribution layer 525, and the second end of the memory portion 516 is in contact with the first peripheral circuit 532 through the redistribution layer 525 and the contact structure 521. In some embodiments, the contact structure 521 extends longer than the storage 516 in the Z-direction. The second peripheral circuit 552 is in contact with the first peripheral circuit 532, e.g., with the substrate 534, through the bonding interface 550. In other words, the first peripheral circuit 532 is disposed between the memory cell 502 and the second peripheral circuit 552.

Fig. 5 also illustrates a schematic diagram of a plan view of a memory cell 502, a first peripheral circuit 532, and a second peripheral circuit 552, in accordance with some aspects of the present disclosure. In some embodiments, the plan views of the memory cell 502, the first peripheral circuit 532, and the second peripheral circuit 552 overlap, and the memory cell 502, the first peripheral circuit 532, and the second peripheral circuit 552 are bonded to one another, as shown in fig. 5. As shown in fig. 5, the bit lines extend in the X direction, and the word lines extend in the Y direction perpendicular to the X direction. In some embodiments, even bit lines and odd bit lines may be connected to corresponding peripheral circuits from opposite sides of memory cell 502 in plan view. In some embodiments, even and odd word lines may be connected to corresponding peripheral circuits from opposite sides of the memory cell 502 in plan view. For example, even bit lines and odd bit lines may be picked up on both sides of the memory cell 502 in the X-direction, and even bit lines and odd word lines may be picked up on both sides of the memory cell 502 in the Y-direction.

As shown in fig. 5, the first peripheral circuit 532 and the second peripheral circuit 552 may include any suitable digital, analog, and/or mixed signal circuits for facilitating operation of the memory cell 502. In some implementations, the word line driver circuit and the sense amplifier circuit can be disposed in the first peripheral circuit 532, and the analog circuit can be disposed in the second peripheral circuit 552. It should be appreciated that the arrangement of the word line driver circuit, sense amplifier circuit, and analog circuit shown in fig. 5 is one example, and that the location may vary depending on the application.

As shown in fig. 5, a contact structure 580 is formed and extends in the Z-direction between the first peripheral circuit 532 and the second peripheral circuit 552. In some embodiments, the contact structures 580 are used to connect signals between the first peripheral circuit 532 and the second peripheral circuit 552, and also to transfer signals between the second peripheral circuit 552 and the memory cell 502. Because contact structure 580 is a Through Silicon Via (TSV) structure that penetrates substrate 534, in some embodiments, substrate 534 may be thinned to form contact structure 580. In other words, the thickness of the substrate 534 may be less than the thickness of the substrate 554.

Fig. 6 illustrates a schematic diagram of a cross-section of a storage device 600, according to some aspects of the present disclosure. As shown in fig. 6, the memory device 600 includes a memory cell 602, a first peripheral circuit 532, and a second peripheral circuit 552. In some embodiments, the first and second peripheral circuits 532, 552 in fig. 6 may be similar to the first and second peripheral circuits 532, 552 in fig. 5.

As shown in fig. 6, the memory cell 602 includes a vertical transistor 504 extending in the Z-direction. In some embodiments, the vertical transistor 504 in fig. 6 may be similar to the vertical transistor 504 in fig. 5, but disposed at a different location in the memory cell 602. In some implementations, the memory cell 602 also includes a memory portion 516 having a first end coupled to the first terminal 508 of the vertical transistor 504. In some embodiments, the memory portion 516 in fig. 6 may be similar to the memory portion 516 in fig. 5, except that it is disposed at a different location in the memory unit 602. In some embodiments, the memory portion 516 is disposed between the vertical transistor 504 and the bonding interface 530. In other words, the memory cell 602 may be a flip structure of the memory cell 502 along the Z-direction.

By forming the vertical transistor 504 instead of the horizontal cell transistor structure, the bit line 514 may be formed in the array wafer. The array wafer may have only the vertical transistors 504, bit lines 514, and metal redistribution layers, and all peripheral circuits including sense amplifiers, word Line (WL) drivers, decoders, power supplies, etc. are formed in the CMOS wafer. The array wafer and CMOS wafer are then bonded (e.g., hybrid bonded) together by high density Cu-to-Cu bonding vias. In some embodiments, two CMOS wafers may be applied: one of the CMOS wafers may include a sense amplifier, a Word Line (WL) driver, and the other CMOS wafer may include analog circuitry.

By forming the bit lines 514 on a first side of the cell array and the memory portions 516 on a second side of the cell array, complex bit line processes can be avoided and coupling capacitance between the bit lines can also be significantly reduced. Further, by bonding the array wafer and the CMOS wafer using a hybrid bonding process, all control circuits including bit line control circuits, word line control circuits, sense amplifiers, word line drivers/decoders, etc. can be placed above or below the cell array, so that array efficiency can be significantly improved and cell size can also be reduced.

Fig. 7-18 illustrate a fabrication process for forming a memory device 500 including a vertical transistor 504, in accordance with some aspects of the present disclosure. Fig. 19 illustrates a flow chart of a method 1900 for forming a memory device 500 in accordance with some aspects of the present disclosure. For purposes of better describing the present disclosure, the storage device 500 of FIGS. 7-18 and the method 1900 of FIG. 19 will be discussed together. It should be understood that the operations illustrated in method 1900 are not exhaustive and that other operations may be performed before, after, or between any of the illustrated operations. Further, some operations may be performed simultaneously or in a different order than shown in fig. 7-18 and 19.

As shown in fig. 7-10 and operation 1902 in fig. 19, a memory array structure, such as memory cell 502, is formed. The memory array structure may include a vertical transistor 504 having a first terminal 508 and a second terminal 510, a memory portion 516 having a first end coupled to the first terminal 508 of the vertical transistor 504, and a bit line 514 coupled to the second terminal 510 of the vertical transistor 504.

As shown in fig. 7, a substrate 570 is provided, and a vertical transistor 504 is formed over the substrate 570. In some implementations, the vertical transistor 504 includes a semiconductor body 506 extending in the Z-direction. The first terminal 508 and the second terminal 510 may be located on both sides of the semiconductor body 506. In some embodiments, the first terminal 508 and the second terminal 510 may be source and drain terminals of the vertical transistor 504 after the activation operation is performed later.

In some embodiments, after forming the semiconductor body 506, a gate structure 512 may be formed on at least one side of the semiconductor body 506. In some embodiments, the gate structure 512 may be a multi-layer structure including a gate dielectric layer, a barrier layer, and a metal gate layer. In some embodiments, a planarization operation may be performed to expose the semiconductor body 506.

In some embodiments, to form the gate structure 512, a gate dielectric is formed over the exposed portions of the semiconductor body 506, a conductive layer is deposited over the gate dielectric, and the conductive layer is patterned to form a gate electrode over the gate dielectric. As a result, the gate structures 512 may become word lines that all extend in the word line direction (Y direction).

As shown in fig. 7, a storage portion 516 is formed on the first terminal 508. In some embodiments, the first terminal 508 of the semiconductor body 506 may be doped to form a source/drain terminal, e.g., a source terminal of the vertical transistor 504, before forming the memory portion 516 on the first terminal 508. In some embodiments, an implantation process and/or a thermal diffusion process is performed to dope the P-type dopants or the N-type dopants to the exposed upper end of the semiconductor body 506 to form source/drain terminals. In some embodiments, a silicide layer is formed on the first terminal 508 by performing a silicidation process on the exposed end of the semiconductor body 506. Then, the storage portion 516 is formed on the first terminal 508, and one ends of the plurality of storage portions 516 are connected as shown in fig. 7.

As shown in fig. 7, a redistribution layer 525 is formed on the storage portion 516. In some embodiments, the memory portion 516 is located between the vertical transistor 504 and the redistribution layer 525 along the Z-direction.

As shown in fig. 8, a substrate 572 is bonded to the memory cell 502. Substrate 572 may serve as a carrier wafer in subsequent operations to form the bit lines. Then, as shown in fig. 9, the substrate 570 is removed to expose the second terminal 510 of the vertical transistor 504. In some embodiments, an implantation process and/or a thermal diffusion process is performed to dope the P-type dopant or the N-type dopant to the exposed second terminal 510 to form a source/drain terminal. In some embodiments, a silicide layer is formed on the second terminal 510 by performing a silicidation process on the exposed end layer of the semiconductor body 506.

As shown in fig. 10, a bit line 514 is formed on the second terminal 510 of the vertical transistor 504. In some embodiments, the bit line and word line extraction methods may be similar to the word line/bit line extraction shown in fig. 5. For example, the bit lines extend in the X direction, and the word lines extend in the Y direction perpendicular to the X direction. In some embodiments, even bit lines and odd bit lines may be connected to corresponding peripheral circuits from opposite sides of memory cell 502 in plan view. In some embodiments, even and odd word lines may be connected to corresponding peripheral circuits from opposite sides of the memory cell 502 in plan view. For example, even bit lines and odd bit lines may be picked up on both sides of the memory cell 502 in the X-direction, and even bit lines and odd word lines may be picked up on both sides of the memory cell 502 in the Y-direction.

As shown in fig. 11-18 and operation 1904 in fig. 19, peripheral circuitry is formed on one side of the memory array structure (e.g., memory cell 502). In some implementations, the peripheral circuitry includes a first peripheral circuit 532 and a second peripheral circuit 552.

Fig. 11-13 illustrate a manufacturing process for forming the first peripheral circuit 532 and the second peripheral circuit 552, and fig. 14-15 illustrate another manufacturing process for forming the first peripheral circuit 532 and the second peripheral circuit 552. It should be understood that the operations illustrated in fig. 11-13 and/or 14-15 are not exhaustive and that other operations may be performed before, after, or between any of the illustrated operations.

As shown in fig. 11, the second peripheral circuit 552 is formed on a substrate 554 or in the substrate 554. In some implementations, the second peripheral circuit 552 (e.g., analog circuit 556) may comprise any suitable digital, analog, and/or mixed signal circuits for facilitating the operation of the memory cell 502. The second peripheral circuit 552 may then be bonded to the substrate 534.

In some embodiments, the substrate 534 may be formed by using a smart cut process. The smart cut process involves two techniques, wafer bonding and ion implantation associated with temperature processing, which can cause the implanted wafer to split in depth. The process begins by processing substrate 534, which is then reused to create a silicon-on-insulator (SOI) wafer. The substrate 534 is processed by growing an oxide layer on one side. The oxide layer then forms a Bulk Oxide (BOX) layer of the substrate 534. Then, ion implantation of hydrogen ions is performed into the underlying silicon by the oxide, which forms a damaged layer at the end of the ion range. After bonding the substrate 534 to the second peripheral circuit 552, the substrate 534 is then cut across the damaged plane, and the thin silicon layer is transferred to the second peripheral circuit 552 to form an SOI structure. In some embodiments, a Chemical Mechanical Polishing (CMP) operation may be performed to complete the SOI surface.

As shown in fig. 12, the first peripheral circuit 532 is formed over a substrate 534 or in the substrate 534. The first peripheral circuit 532 includes control and sensing circuits 536. In some embodiments, the first peripheral circuitry 532 may include any suitable digital, analog, and/or mixed signal circuitry for facilitating operation of the memory cell 502. In some implementations, the first peripheral circuit 532 may include one or more of a sense amplifier, a driver (e.g., a word line driver), any portion of the functional circuits described above (e.g., a sub-circuit), or any active or passive component of the circuit (e.g., a transistor, diode, resistor, or capacitor).

Fig. 12 further shows a plan view of the first peripheral circuit 532 and the second peripheral circuit 552. As shown in fig. 12, the arrangement of the sense amplifier and the word line driver in the first peripheral circuit 532 may be different according to different designs, and the layout is not limited herein.

As shown in fig. 13, a redistribution layer 538 and a contact structure 580 are formed in the first peripheral circuit 532. The contact structure 580 is used to connect signals between the first peripheral circuit 532 and the second peripheral circuit 552 and also to transmit signals between the second peripheral circuit 552 and the memory unit 502. Because the contact structure 580 is a TSV structure penetrating the substrate 534, in some embodiments, the substrate 534 may be thinned to form the contact structure 580. In other words, the thickness of the substrate 534 may be less than the thickness of the substrate 554.

Fig. 14-15 illustrate another manner for forming the first peripheral circuit 532 and the second peripheral circuit 552. As shown in fig. 14, the first peripheral circuit 532 and the second peripheral circuit 552 may be formed separately. In some implementations, the first peripheral circuit 532 is formed on the substrate 534 or in the substrate 534. The first peripheral circuit 532 includes control and sensing circuits 536. In some embodiments, the first peripheral circuitry 532 may include any suitable digital, analog, and/or mixed signal circuitry for facilitating operation of the memory cell 502. In some implementations, the first peripheral circuit 532 may include one or more of a sense amplifier, a driver (e.g., a word line driver), any portion of the functional circuits described above (e.g., a sub-circuit), or any active or passive component of the circuit (e.g., a transistor, diode, resistor, or capacitor). Then, the substrate 535 is bonded to the first peripheral circuit 532. When the thinning operation of the substrate 534 is performed, the substrate 535 may be used as a carrier wafer. In some embodiments, the thinning operation of the substrate 534 may include dry etching, wet etching, CMP, or other suitable process.

The second peripheral circuit 552 is formed on the substrate 554 or in the substrate 554. In some implementations, the second peripheral circuit 552 (e.g., analog circuit 556) may comprise any suitable digital, analog, and/or mixed signal circuits for facilitating the operation of the memory cell 502. Then, the first peripheral circuit 532 and the second peripheral circuit 552 are bonded through the bonding interface 550.

As shown in fig. 15, the substrate 535 is removed and a redistribution layer 538 and a contact structure 580 are formed in the first peripheral circuit 532. The contact structure 580 is used to connect signals between the first peripheral circuit 532 and the second peripheral circuit 552 and also to transmit signals between the second peripheral circuit 552 and the memory unit 502. Because the contact structure 580 is a TSV structure penetrating the substrate 534, in some embodiments, the substrate 534 may be thinned to form the contact structure 580. In other words, the thickness of the substrate 534 may be less than the thickness of the substrate 554.

As shown in fig. 16, peripheral circuits including the first peripheral circuit 532 and the second peripheral circuit 552 from fig. 13 or fig. 15 may be bonded to the memory cell 502 from fig. 10 through the bonding interface 530. As shown in fig. 17, the substrate 572 is then removed.

As shown in fig. 18, a pad structure 522 is then formed on one side of the memory cell 502. In some embodiments, the memory cell 502 includes two sides in the Z-direction, one of which forms the pad structure 522 and the other of which is bonded to peripheral circuitry including the first peripheral circuitry 532 and the second peripheral circuitry 552.

By forming the vertical transistor 504 instead of the horizontal cell transistor structure, the bit line 514 may be formed in the array wafer. The array wafer may have only the vertical transistors 504, bit lines 514, and metal redistribution layers, and all peripheral circuits including sense amplifiers, word Line (WL) drivers, decoders, power supplies, etc. are formed in the CMOS wafer. The array wafer and the CMOS wafer are then bonded (e.g., hybrid bonded) together using high density Cu-to-Cu bonding vias. In some embodiments, two CMOS wafers may be applied: one of the CMOS wafers may include a sense amplifier, a Word Line (WL) driver, and the other CMOS wafer may include analog circuitry.

By forming the bit lines 514 on a first side of the cell array and the memory portions 516 on a second side of the cell array, a complicated bit line process can be avoided and the coupling capacitance between the bit lines can be significantly reduced. In addition, by bonding an array wafer and a CMOS wafer using a hybrid bonding process, all control circuits including a bit line control circuit, a word line control circuit, a sense amplifier, a word line driver/decoder, and the like can be placed above or below a cell array, and thus array efficiency can be significantly improved, and cell size can also be reduced.

Fig. 20 illustrates a block diagram of a system 2000 having a storage device, in accordance with some aspects of the present disclosure. The system 2000 may be a mobile phone, a desktop computer, a notebook computer, a tablet computer, a vehicle computer, a gaming machine, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 20, system 2000 may include a host 2008 and a storage system 2002 having one or more storage devices 2004 and a memory controller 2006. Host 2008 may be a processor of an electronic device, such as a Central Processing Unit (CPU) or a system on a chip (SoC), such as an Application Processor (AP). Host 2008 can be configured to send data to storage 2004 or receive data from storage 2004.

Storage 2004 may be any storage disclosed herein, such as storage 500 or 600. In some embodiments, memory device 2004 includes an array of memory cells, each memory cell including a vertical transistor, as described in detail above.

According to some implementations, a memory controller 2006 is coupled to storage 2004 and host 2008 and is configured to control storage 2004. The memory controller 2006 may manage data stored in the storage 2004 and communicate with the host 2008. The memory controller 2006 may be configured to control operations of the memory device 2004, such as read, write, and refresh operations. The memory controller 2006 may also be configured to manage various functions related to data stored or to be stored in the storage 2004, including, but not limited to, refresh and timing control, command/request conversion, buffer and scheduling, and power management. In some implementations, the memory controller 2006 is further configured to determine a maximum memory capacity that can be used by the computer system, a number of memory banks, a memory type and speed, a memory particle data depth and data width, and other important parameters. The memory controller 2006 may also perform any other suitable function. The memory controller 2006 may communicate with external devices (e.g., host 2008) according to a particular communication protocol. For example, the memory controller 2006 may communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a firewire protocol, and the like.

The foregoing description of the specific embodiments may be readily modified and/or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A storage device, comprising:

a memory array structure, the memory array structure comprising:

a vertical transistor having a first terminal and a second terminal;

a storage portion having a first end coupled to the first terminal of the vertical transistor; and

a bit line coupled to the second terminal of the vertical transistor;

a first peripheral circuit disposed at one side of the memory array structure and including a first side in contact with the memory array structure and a second side opposite to the first side in a first direction; and

a second peripheral circuit is disposed in contact with the second side of the first peripheral circuit remote from the memory array structure.

2. The memory device of claim 1, wherein the first peripheral circuit comprises a sense amplifier circuit and a word line driver circuit.

3. The memory device of claim 2, wherein the second peripheral circuit comprises an analog circuit.

4. The memory device of claim 1, wherein the memory array structure includes a first surface having a pad extraction structure and a second surface opposite the first surface in the first direction, the second surface being in contact with the first peripheral circuit.

5. The memory device according to claim 4, wherein the memory portion is provided between the first surface and the vertical transistor in the first direction.

6. The memory device according to claim 4, wherein the vertical transistor is provided between the first surface and the memory portion in the first direction.

7. The memory device of claim 6, further comprising a first contact structure extending in the first direction between the first peripheral circuit and the second peripheral circuit.

8. The memory device of claim 6, further comprising a second contact structure extending in the memory array structure between the first surface and the second surface in the first direction.

9. The memory device of claim 8, wherein the second contact structure is in contact with the pad extraction structure.

10. The memory device of claim 9, wherein the pad extraction structure is in contact with the first peripheral circuit through the second contact structure.

11. The memory device of claim 1, wherein the first peripheral circuit is disposed in a first peripheral substrate, the second peripheral circuit is disposed in a second peripheral substrate, and a thickness of the first peripheral substrate is less than a thickness of the second peripheral substrate.

12. The memory device of claim 1, wherein the vertical transistor comprises a semiconductor body extending in the first direction and a gate structure coupled to at least one side of the semiconductor body in a second direction perpendicular to the first direction.

13. A storage system, comprising:

a storage device configured to store data, and comprising:

a memory array structure, the memory array structure comprising:

a vertical transistor having a first terminal and a second terminal;

A bit line coupled to the second terminal of the vertical transistor;

a second peripheral circuit disposed in contact with the second side of the first peripheral circuit remote from the memory array structure; and

a memory controller coupled to the memory device and configured to control the memory array structure through the first peripheral circuit and the second peripheral circuit.

14. A storage device, comprising:

a memory array structure, the memory array structure comprising:

a vertical transistor; and

a memory portion coupled to the vertical transistor;

15. The memory device of claim 14, wherein the memory array structure includes a first surface having a pad extraction structure and a second surface opposite the first surface in the first direction, the second surface being in contact with the first peripheral circuit.

16. The memory device according to claim 15, wherein the memory portion is provided between the first surface and the vertical transistor in the first direction.

17. The memory device according to claim 15, wherein the vertical transistor is provided between the first surface and the memory portion in the first direction.

18. The memory device of claim 14, wherein the first peripheral circuit is disposed in a first peripheral substrate, the second peripheral circuit is disposed in a second peripheral substrate, and a thickness of the first peripheral substrate is less than a thickness of the second peripheral substrate.

19. The memory device of claim 18, wherein the first peripheral circuit includes a first connection structure extending through the first peripheral substrate in the first direction.

20. The memory device of claim 14, wherein the first peripheral circuit comprises a sense amplifier circuit and a word line driver circuit.

21. The memory device of claim 20, wherein the second peripheral circuit comprises an analog circuit.

22. A storage system, comprising:

a storage device configured to store data, and comprising:

a memory array structure, the memory array structure comprising:

a vertical transistor; and

a memory portion coupled to the vertical transistor;

23. A method for forming a memory device, comprising:

forming a memory array structure on a first substrate, wherein the memory array structure includes a vertical transistor having a first terminal and a second terminal, a memory portion having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor; and

A peripheral circuit is formed at one side of the memory array structure, wherein the peripheral circuit includes a first peripheral circuit and a second peripheral circuit.

24. The method of claim 23, wherein forming the peripheral circuit at one side of the memory array structure comprises:

forming the first peripheral circuit and the second peripheral circuit stacked together as the peripheral circuits; and

and bonding the memory array structure with the peripheral circuit.

25. A method for forming a memory device, comprising:

forming a memory array structure on a first substrate, wherein the memory array structure includes a vertical transistor having a first terminal and a second terminal, a memory portion having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor;

forming a first peripheral circuit in a second substrate;

forming a third substrate on the first peripheral circuit;

forming a second peripheral circuit on the third substrate; and

and bonding the memory array structure with the second peripheral circuit.

26. The method of claim 25, wherein forming the memory array structure on the first substrate comprises:

Forming the vertical transistor on a fourth substrate such that the second terminal of the vertical transistor is in contact with the fourth substrate;

forming the memory portion on the vertical transistor such that the first end of the memory portion is coupled to the first terminal of the vertical transistor;

forming the first substrate on the storage portion; and

and removing the fourth substrate.

27. The method of claim 25, wherein forming the memory array structure on the first substrate comprises:

forming the vertical transistor on the first substrate such that the second terminal of the vertical transistor is in contact with the first substrate; and

the memory portion is formed on the vertical transistor such that the first end of the memory portion is coupled to the first terminal of the vertical transistor.

28. The method of claim 25, wherein forming the third substrate on the first peripheral circuit comprises:

forming a dielectric layer on the third substrate;

performing an implantation operation on the third substrate; and

and bonding the third substrate on the first peripheral circuit, wherein the dielectric layer is in contact with the first peripheral circuit.

29. The method of claim 28, wherein performing an implant operation on the third substrate comprises:

a hydrogen ion implantation operation is performed on the third substrate from a side having the dielectric layer.

30. The method of claim 28, wherein forming the second peripheral circuit on the third substrate comprises:

removing a portion of the third substrate; and

the second peripheral circuit is formed on the remaining portion of the third substrate.

31. The method of claim 30, further comprising:

a first contact structure is formed in the second peripheral circuit extending through the third substrate.

32. The method of claim 25, wherein bonding the memory array structure with the second peripheral circuit comprises:

bonding the memory array structure on the second peripheral circuit;

removing the first substrate; and

and forming a pad extraction structure on the storage array structure.

33. A method for forming a memory device, comprising:

Forming a first peripheral circuit on a second substrate;

forming a second peripheral circuit on the third substrate;

bonding the first peripheral circuit with the second peripheral circuit; and

and bonding the memory array structure with the first peripheral circuit.

34. The method of claim 33, wherein forming the memory array structure on the first substrate comprises:

forming the first substrate on the storage portion; and

and removing the fourth substrate.

35. The method of claim 33, wherein forming the memory array structure on the first substrate comprises:

36. The method of claim 33, wherein bonding the first peripheral circuit with the second peripheral circuit comprises:

thinning the second substrate;

forming a dielectric layer on the thinned second substrate; and

bonding the thinned second substrate to the second peripheral circuit such that the dielectric layer is in contact with the second peripheral circuit.

37. The method of claim 33, wherein bonding the first peripheral circuit with the second peripheral circuit comprises:

forming a fifth substrate on the first peripheral circuit;

thinning the second substrate using the fifth substrate as a supporting substrate;

bonding a thinned second substrate to the second peripheral circuit such that the thinned second substrate is in contact with the second peripheral circuit; and

and removing the fifth substrate.

38. The method of claim 37, further comprising:

a first contact structure is formed in the first peripheral circuit extending through the second substrate.

39. The method of claim 33, wherein bonding the memory array structure to the first peripheral circuit comprises:

bonding the memory array structure to the first peripheral circuit;

Removing the first substrate; and

and forming a pad extraction structure on the storage array structure.