CN117594646A - Power semiconductor element and processing device thereof - Google Patents

Power semiconductor element and processing device thereof Download PDF

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Publication number
CN117594646A
CN117594646A CN202311526090.3A CN202311526090A CN117594646A CN 117594646 A CN117594646 A CN 117594646A CN 202311526090 A CN202311526090 A CN 202311526090A CN 117594646 A CN117594646 A CN 117594646A
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China
Prior art keywords
layer
trench portion
emission
semiconductor layer
trench
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CN202311526090.3A
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Chinese (zh)
Inventor
郑镇荣
高志亚
柳和廷
李宗宪
金东植
石松礼
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Zhejiang Wangrong Semiconductor Co ltd
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Zhejiang Wangrong Semiconductor Co ltd
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Priority to CN202311526090.3A priority Critical patent/CN117594646A/en
Publication of CN117594646A publication Critical patent/CN117594646A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]

Abstract

Embodiments of the present specification provide a power semiconductor element and a processing apparatus thereof, wherein the power semiconductor element includes: a first semiconductor layer, a second semiconductor layer, and a charge accumulation layer, each of which forms a field stop layer, is formed on the first semiconductor layer, is formed between the first semiconductor layer and the second semiconductor layer, and has a higher doping concentration than the first semiconductor layer and the first and second gates; the first groove part and the second groove part penetrate through the second semiconductor layer, extend to the first semiconductor layer and are mutually separated by a certain distance; an emitter formed over the second semiconductor layer; an emission layer formed between and in contact with the first and second trench portions; the structure of limiting the maximum current capacity of the short circuit can strengthen the soundness of the power semiconductor element, prevent the power semiconductor element from being destroyed before the operation of the protection circuit when the short circuit occurs, and enable the short circuit current to flow.

Description

Power semiconductor element and processing device thereof
Technical Field
Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a power semiconductor device and a processing apparatus thereof.
Background
An insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) has a high input impedance of a power field effect transistor and a high current flow capability of the bipolar transistor, and is mainly used as a power switching element. Such an insulated gate bipolar transistor can be largely classified into a planar gate and a trench gate, and recently, development of a trench gate capable of simultaneously increasing current density and reducing size (size) has been actively pursued.
In general, an insulated gate bipolar transistor includes: a 1 st conductive emission layer and a 2 nd conductive base layer, a 1 st conductive drift layer (base layer), a 2 nd conductive collector layer and base layer, and a gate electrode formed by blocking the drift layer with an insulating film. 2a channel is formed on the base layer by the allowable voltage of the gate electrode, and a small amount of carriers (holes) are injected from the collector layer into the drift layer, so that the conductivity is changed in the drift layer and the resistance is reduced, thereby reducing all voltages during conduction. Meanwhile, the insulated gate bipolar transistor has the problems: in a Short circuit (Short circuit), when the external load is lost to '0', when a Short circuit occurs, an external voltage is immediately supplied to the collector layer and the emitter layer. In the case of such a short circuit, a large amount of current is instantaneously supplied to the insulated gate bipolar transistor, and there is a problem in that a high power must be applied within several μs seconds to activate the protection circuit. Thus, a better solution is needed.
Disclosure of Invention
In view of this, the present embodiments provide a power semiconductor element and a processing apparatus thereof. One or more embodiments of the present specification relate to a power semiconductor device processing apparatus, a computing device, a computer-readable storage medium, and a computer program to solve the technical drawbacks existing in the prior art.
According to a first aspect of embodiments of the present specification, there is provided a power semiconductor element comprising: the first semiconductor layer 110, the second semiconductor layer 120 forming the field stop layer 111 are formed on the first semiconductor layer 110, the charge accumulation layer 130 is formed between the first semiconductor layer 110 and the second semiconductor layer 120, and the charge accumulation layer 130 has a higher doping concentration than the first semiconductor layer 110 and the first and second gate electrodes 142 and 142a;
the first trench 140 and the second trench 140a penetrate through the second semiconductor layer 120, extend to the first semiconductor layer 110, and are spaced apart from each other by a certain distance;
the emitter 150 is formed over the second semiconductor layer 120;
the first and second emission layers 160 and 160a are formed between the first and second groove parts 140 and 140a and contact the first and second groove parts 140 and 140 a;
the first barrier layer 170 and the second barrier layer 170a are disposed in parallel under the first trench portion 140 and the second trench portion 140a, spaced apart from each other by a certain distance, and perpendicularly intersect the first trench portion 140 and the second trench portion 140a, and block electrons from flowing from the first emission layer 160 and the second emission layer 160a to the collector 180;
the collector 180 is connected to a collector layer 181 formed under the first semiconductor layer 110.
In one possible implementation, the first and second emission layers 160 and 160a are formed directly above the spaces separated by the first and second barrier layers 170 and 170a, respectively;
the maximum current amount is characterized by being adjusted according to the size of the first and second emission layers 160 and 160a in the length direction and the separation distance between the first and second barrier layers 170 and 170 a.
In one possible implementation, the first and second trench portions 140 and 140a form insulating films 141, 141a at inner walls; and the first gate electrode 142 and the second gate electrode 142a are buried by the insulating films 141, 141a to be insulated from the second semiconductor layer 120 and the emission layer.
In one possible implementation, the emitter 150 forms an emitter contact 152 between the first trench portion 140 and the second trench portion 140a extending to the second semiconductor layer 120.
In one possible implementation, the first and second barrier layers are formed on the bottom surface of the charge accumulation layer 130, the bottom surfaces of the first and second trench portions 140 and 140a, and part of the lower surfaces of the first and second trench portions 140 and 140 a.
In one possible implementation, the method includes: the first barrier layer and the second barrier layer are spaced apart from the bottom surface of the charge storage layer 130 by a certain distance, and cover the bottom surfaces of the first trench portion 140 and the second trench portion 140a and part of the side surfaces of the first trench portion 140 and the second trench portion 140 a.
In one possible implementation, the method includes:
the first barrier layer and the second barrier layer are spaced apart from the bottom surface of the charge storage layer by a predetermined distance, and are formed below the bottom surfaces of the first trench 140 and the second trench 140a by a predetermined distance.
According to a second aspect of embodiments of the present specification, there is provided a power semiconductor element comprising: the first semiconductor layer 110, the second semiconductor layer 120, and the charge accumulation layer 130 forming the field stop layer 111 are formed on the first semiconductor layer 110, and the charge accumulation layer 130 is formed between the first semiconductor layer 110 and the second semiconductor layer 120, the charge accumulation layer 130 having a higher doping concentration than the first semiconductor layer 110;
the first trench 140 and the second trench 140a penetrate through the second semiconductor layer 120, extend to the first semiconductor layer 110, and are spaced apart from each other by a certain distance;
the emitter 150 is formed over the second semiconductor layer 120;
a third emission layer 160', a fourth emission layer 160' a, a fifth emission layer 161 'and a sixth emission layer 161' a are formed between the first and second groove parts 140 and 140a and in contact with the first and second groove parts 140 and 140 a;
the first barrier layer 170 and the second barrier layer 170a are disposed in parallel under the first trench 140 and the second trench 140a, spaced apart from each other by a certain distance, and perpendicularly intersect the parallel first trench 140 and second trench to block electrons from flowing from the third emission layer 160', the fourth emission layer 160' a, the fifth emission layer 161 'and the sixth emission layer 161' a to the collector 180;
the third, fourth, fifth and sixth emission layers 160',160' a, 161 'and 161' a are formed directly above the first and second barrier layers 170 and 170a, respectively.
In one possible implementation, the feature of maximum current amount is adjusted according to the distances between the third 160', fourth 160' a, fifth 161 'and sixth 161' a emissive layers to the first 170 and second 170a barrier layers and the separation distance between the first 170 and second 170a barrier layers.
In one possible implementation, the first and second trench portions 140 and 140a form insulating films 141, 141a at inner walls; and the first gate electrode 142 and the second gate electrode 142a are buried by the insulating films 141, 141a to be insulated from the second semiconductor layer 120 and the emission layer.
In one possible implementation, the emitter 150 forms an emitter contact 152 between the first trench portion 140 and the second trench portion 140a extending to the second semiconductor layer 120.
In one possible implementation, the first and second barrier layers are formed on the bottom surface of the charge accumulation layer 130, the bottom surfaces of the first and second trench portions 140 and 140a, and part of the lower surfaces of the first and second trench portions 140 and 140 a.
In one possible implementation, the method includes: the first barrier layer and the second barrier layer are spaced apart from the bottom surface of the charge storage layer 130 by a certain distance, and cover the bottom surfaces of the first trench portion 140 and the second trench portion 140a and part of the side surfaces of the first trench portion 140 and the second trench portion 140 a.
In one possible implementation, the method includes:
the first barrier layer and the second barrier layer are spaced apart from the bottom surface of the charge storage layer by a predetermined distance, and are formed below the bottom surfaces of the first trench 140 and the second trench 140a by a predetermined distance.
According to a third aspect of the embodiments of the present specification, there is provided a power semiconductor element processing apparatus for processing the aforementioned power semiconductor element.
Embodiments of the present specification provide a power semiconductor element and a processing apparatus thereof, wherein the power semiconductor element includes: a first semiconductor layer, a second semiconductor layer, and a charge accumulation layer, each of which forms a field stop layer, is formed on the first semiconductor layer, is formed between the first semiconductor layer and the second semiconductor layer, and has a higher doping concentration than the first semiconductor layer and the first and second gates; the first groove part and the second groove part penetrate through the second semiconductor layer, extend to the first semiconductor layer and are mutually separated by a certain distance; an emitter formed over the second semiconductor layer; an emission layer formed between and in contact with the first and second trench portions; the structure of limiting the maximum current capacity of the short circuit can strengthen the soundness of the power semiconductor element, prevent the power semiconductor element from being destroyed before the operation of the protection circuit when the short circuit occurs, and enable the short circuit current to flow.
Drawings
Fig. 1 is a first schematic view of a power semiconductor element provided in one embodiment of the present disclosure;
fig. 2 is a second schematic view of a power semiconductor device according to an embodiment of the present disclosure;
fig. 3 is a third schematic view of a power semiconductor device according to an embodiment of the present disclosure;
fig. 4 is a fourth schematic diagram of a power semiconductor element according to an embodiment of the present disclosure;
fig. 5 is a fifth schematic view of a power semiconductor element according to an embodiment of the present disclosure;
fig. 6 is a sixth schematic view of a power semiconductor element according to an embodiment of the present disclosure;
fig. 7 is a seventh schematic view of a power semiconductor element according to an embodiment of the present disclosure;
fig. 8 is an eighth schematic view of a power semiconductor element according to an embodiment of the present disclosure;
fig. 9 is a ninth schematic view of a power semiconductor element provided in an embodiment of the present disclosure;
fig. 10 is a tenth schematic view of a power semiconductor element provided in one embodiment of the present disclosure;
fig. 11 is an eleventh schematic view of a power semiconductor element provided in an embodiment of the present specification;
fig. 12 is a twelfth schematic view of a power semiconductor element according to an embodiment of the present disclosure.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present description. This description may be embodied in many other forms than described herein and similarly generalized by those skilled in the art to whom this disclosure pertains without departing from the spirit of the disclosure and, therefore, this disclosure is not limited by the specific implementations disclosed below.
The terminology used in the one or more embodiments of the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of the specification. As used in this specification, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used in one or more embodiments of the present specification refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that, although the terms first, second, etc. may be used in one or more embodiments of this specification to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first may also be referred to as a second, and similarly, a second may also be referred to as a first, without departing from the scope of one or more embodiments of the present description. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
According to a first aspect of the embodiments of the present specification, there is provided a power semiconductor element including a first semiconductor layer 110 forming a field stop layer 111, a second semiconductor layer 120 formed on the first semiconductor layer 110, a charge accumulation layer 130 formed between the first semiconductor layer 110 and the second semiconductor layer 120, and having a higher doping concentration than the first semiconductor layer 110 and the first and second gates 142 and 142a; the first trench 140 and the second trench 140a penetrate through the second semiconductor layer 120, extend to the first semiconductor layer 110, and are spaced apart from each other by a certain distance; an emitter 150 is formed over the second semiconductor layer 120; the first and second emission layers 160 and 160a are formed between the first and second groove parts 140 and 140a and contact the first and second groove parts 140 and 140 a; the first barrier layer 170 and the second barrier layer 170a are disposed in parallel below the first trench 140 and the second trench 140a, spaced apart from each other by a certain distance, and perpendicularly intersect the first trench 140 and the second trench 140a, and block the electrons from flowing from the first emission layer 160 and the second emission layer 160a to the collector 180; the collector 180 is connected to a collector layer 181 formed under the first semiconductor layer 110.
As shown in fig. 1 to 5, the power semiconductor device 100 in the embodiment of the present invention may be formed of a silicon substrate, and a gate wiring and an emitter 150 may be formed on the surface thereof.
Specifically, the power semiconductor element 100 may be formed by coating a first semiconductor layer 110 with a low concentration of an n-type dopant of a first conductivity type; for example, the coating concentration of the n-type dopant may be 10 13 ～10 16 /cm 3 Left and right. The first semiconductor layer 110 may be referred to as an n-type drift layer in view of the coating concentration of the n-type dopant. Further, a first semiconductorThe body layer 110 may sequentially form a field to layer 111 and a collector layer 181 under the n-type base layer, and a collector 180 may be further formed under the collector layer 181. The field stop layer 111 may be a layer coated with n-type dopant having a concentration higher than that of the first semiconductor layer 110, and a dopant concentration of 10 14 ～10 18 /cm 3 Left and right. That is, the first semiconductor layer 110 serves as a drift layer, is an n-type semiconductor layer having a low concentration, and in the off state, most of the voltage between collector and emitter is introduced to the first semiconductor layer 110, and the field stop layer 111 suppresses expansion of the depletion layer when a reverse voltage is applied.
In this way, the field stop layer 111 can obtain a higher breakdown voltage only through a drift region of a shorter distance, and thus the forward running characteristic can be improved. Further, the semiconductor element 100 may form a second semiconductor layer 120 under the first semiconductor layer 110. The second semiconductor layer 120 may be a region coated with a p-type dopant having a concentration of 10 15 ～10 19 /cm 3 Left and right; when the coating concentration of the P-type dopant is considered, it may be P0 or p+. Further, in order to store charges between the first semiconductor layer 110 and the second semiconductor layer 120, a charge Storage layer (Carrier Storage) 130 coated with n-type dopants may be formed, the concentration of which is higher than that of the first semiconductor layer 110 dopants. That is, the charge storage layer 130 is provided between the first semiconductor layer 110 and the second semiconductor layer 120, and in the element on state, holes can pass through the second semiconductor layer 120 to block the flow to the emitter, and further the carrier concentration of the first semiconductor layer 110 in the region immediately below the charge storage layer 130 is increased, thereby achieving the purpose of lowering the overall voltage. The first and second trench portions 140 and 140a may extend through the second semiconductor layer 120 and the charge accumulation layer 130 to the first semiconductor layer 110.
Further, the first groove part 140 and the second groove part 140a may be spaced apart from each other by a certain distance to form a parallel stripe (stripe) shape. The first and second groove parts 140 and 140a may form insulating films 141, 141a on the inner walls, respectively. The first and second trench portions 140 and 140a may form first and second gate electrodes 142 and 142a buried by the insulating films 141 and 141a to be insulated from the second semiconductor layer 120 and the first and second emission layers 160 and 160 a.
Further, the gate wiring and the emitter 150 may be formed over the second semiconductor layer 120 and the first and second trench portions 140 and 140a together with the insulating film 151. The emitter 150 may form an emitter contact 152 extending to the second semiconductor layer 120 between the first trench portion 140 and the second trench portion 140 a.
Further, the insulating film 151 may be formed in other regions than the emission contact 152 region, electrically separating the first and second gates 142 and 142a of the first and second trench portions 140 and 140a from the emitter 150. The first and second emission layers 160 and 160a may be formed on both sides of the emission contact 152, i.e., on the second semiconductor layer 120, in contact with the first and second trench portions 140 and 140a between the first and second trench portions 140 and 140a divided by the emission contact 152. The first and second emission layers 160 and 160a may be formed between the first and second groove parts 140 and 140a parallel to each other in a square shape of a certain size. The first and second emission layers 160 and 160a may be n-type emission layers coated with n-type dopants. The first and second emission layers 160 and 160a may be formed in a space between the first and second barrier layers 170 and 170a spaced apart from each other and in parallel, that is, may be formed directly above the space between the first and second barrier layers 170 and 170 a. The length of the first and second emission layers 160 and 160a may be equivalent to, but not limited to, a separation distance W1 from the first and second barrier layers 170 and 170 a; the separation distance W1 between the first barrier layer 170 and the second barrier layer 170a may be smaller or larger as needed. The first barrier layer 170 and the second barrier layer 170a may be formed of a p+ type carrier coated with a high concentration of P type dopant as a component for blocking the flow of electrons from the first emission layer 160 and the second emission layer 160a to the collector electrode 180. The first and second barrier layers 170 and 170a may be disposed under the charge accumulating layer 130 and the first and second trench portions 140 and 140 a. At this time, the first and second barrier layers 170 and 170a may wrap around the charge accumulating layer 130 and under the first and second trench portions 140 and 140 a. That is, the first barrier layer 170 and the second barrier layer 170a may cover the bottom surface of the charge storage layer 130, the bottom surfaces of the first trench 140 and the second trench 140a, and portions of the lower side surfaces of the first trench 140 and the second trench 140a may be side surfaces.
Further, as shown in fig. 6, the third barrier layer 170' and the second barrier layer may be spaced apart from the bottom surface of the charge accumulation layer 130 by a certain distance and cover the bottom surfaces of the first trench portion 140 and the second trench portion 140a, and part of the lower side surfaces of the first trench portion 140 and the second trench portion 140 a. Further, as shown in fig. 7, the fourth barrier layer 170″ and the second barrier layer may be formed under a certain distance from the bottom surfaces of the first trench portion 140 and the second trench portion 140 a.
Referring to fig. 1 to 5, the first barrier layer 170 and the second barrier layer 170a may perpendicularly intersect the first trench portion 140 and the second trench portion 140a and may be spaced apart from each other by a distance W1 in a parallel stripe shape. Further, the first barrier layer 170 and the second barrier layer 170a may flow electrons from the first emission layer 160 and the second emission layer 160a to the collector layer 181 through a region equivalent to a size of a mutual distance W1. Meanwhile, the collector layer 181 may be a p+ layer coated with p-type dopant having a concentration of 10 17 ～10 21 /cm 3 Left and right. Next, an operation of the power semiconductor device 100 in an embodiment of the present invention will be described. When a voltage is applied to the first and second gate electrodes 142 and 142a, the first and second emission layers 160 and 160a emit electrons to the first semiconductor layer 110 through the channel; after that, when the conductivity is changed after hole injection in the p+ collector layer 181, an Insulated Gate Bipolar Transistor (IGBT) is operated. At this time, the electron flow injected from the first and second emission layers 160 and 160a flowing to the collector layer 181 is intercepted by the first and second barrier layers 170 and 170a formed under the first and second trench portions 140 and 140a, and is blocked.
Further, since the flow of electrons is blocked by the first barrier layer 170 and the second barrier layer 170a, electrons flow through a channel formed by a space between the first barrier layer 170 and the second barrier layer 170a, and thus, a current amount that can flow can be restricted. Therefore, by limiting the sizes of the first and second emission layers 160 and 160a and the distance W1 between the first and second barrier layers 170 and 170a that prevent the flow of electrons, the maximum current capacity at the time of occurrence of a short circuit can be limited, and the tolerance, that is, the receiving amount at the time of a short circuit can be increased. Further, by adjusting the size of the first and second emission layers 160 and 160a in the length direction and the spacing distance W1 between the first and second barrier layers 170 and 170a, the required maximum current capacity can be adjusted. Fig. 8 to 12 are diagrams illustrating a power semiconductor element in another embodiment of the present invention. First, the same constituent elements will not be described in detail, and the same reference numerals are used for the same constituent elements.
Referring to fig. 8 to 12, in a second embodiment of the present invention, a power semiconductor element 100' includes: a first semiconductor layer 110 forming a field stop layer 111 thereunder; a second semiconductor layer 120 formed on the first semiconductor layer 110; and a charge accumulation layer 130 formed between the first and second semiconductor layers 110, 120 and having a higher doping concentration than the first semiconductor layer 110. Further, the power semiconductor device 100' of the second embodiment includes a gate 142 that penetrates the second semiconductor layer 120 and extends to the first semiconductor layer 110; the first groove 140, i.e., the second groove 140a, may be provided to be spaced apart from each other by a predetermined distance and have a shape of a strip parallel to each other. Further, the power semiconductor element 100' in the second embodiment may form an emitter 150 formed over the second semiconductor layer 120; the third, fourth, fifth and sixth emission layers 160',160' a, 161 'and 161' a are formed on the second semiconductor layer 120 and contact the first and second trench portions 140 and 140a between the first and second trench portions 140 and 140 a. Further, the power semiconductor element 100' in the second embodiment may form the first barrier layer 170 and the second barrier layer 170a, which are formed below the first trench portion 140 and the second trench portion 140 a. The first and second barrier layers 170 and 170a may cover bottom surfaces of the charge storage layer 130, bottom surfaces of the first and second trench portions 140 and 140a, and may cover a portion of lower side surfaces of the first and second trench portions 140 and 140 a.
Further, the third barrier layer 170', referring to fig. 6 and the second barrier layer, may be spaced apart from the bottom surface of the charge accumulation layer 130 by a certain distance, and may cover the bottom surfaces of the first and second trench portions 140 and 140a and a portion of the lower side surfaces of the first and second trench portions 140 and 140 a.
Further, the fourth barrier layer 170″ may be formed under a certain distance from the bottom surfaces of the first and second trench portions 140 and 140a with reference to fig. 7 and the second barrier layer. The first and second barrier layers 170 and 170a may perpendicularly intersect the first and second trench portions 140 and 140a that are parallel to each other. The first barrier layer 170 and the second barrier layer 170a may be spaced apart from each other by a distance W1 and have a parallel stripe shape. The first and second barrier layers 170 and 170a block electrons injected from the third, fourth, fifth and sixth emission layers 160',160' a, 161 'and 161' a from flowing during the flow of electrons toward the collector electrode 180. Electrons injected from the third emission layer 160', the fourth emission layer 160' a, the fifth emission layer 161 'and the sixth emission layer 161' a of the first barrier layer 170 and the second barrier layer 170a may flow toward the collector layer 181 through a region equivalent to the size of the mutual interval distance W1.
Further, the power semiconductor element 100' in the second embodiment may form a collector 180 that is in contact with a collector layer 181 formed under the first semiconductor layer 110. The power semiconductor element 100' in the second embodiment of the present invention has a configuration of the third emission layer 160', the fourth emission layer 160' a, the fifth emission layer 161' and the sixth emission layer 161' a which are different from those of the above embodiments. The third emission layer 160', the fourth emission layer 160' a, the fifth emission layer 161 'and the sixth emission layer 161' a in the second embodiment may be n-type emission layers coated with n-type dopants, and may be formed in regions between the first and second trench parts 140 and 140a divided by the emission contacts 152.
Further, the third emission layer 160', the fourth emission layer 160' a, the fifth emission layer 161 'and the sixth emission layer 161' a in the second embodiment may be formed at the second semiconductor layer 120 to be spaced apart from each other and contact the first and second trench parts 140 and 140a between the first and second trench parts 140 and 140 a. That is, a pair of emission layers 160',160' a may be formed at partial regions of the first and second groove parts 140 and 140a in a direction parallel to each other, and another pair of emission layers 161',161' a may be formed.
Further, third, fourth, fifth and sixth emission layers 160',160' a, 161 'and 161' a spaced apart from each other may be formed directly above the first and second barrier layers 170 and 170a, respectively. That is, the third emission layer 160', the fourth emission layer 160' a, the fifth emission layer 161 'and the sixth emission layer 161' a in the second embodiment of the present invention may be formed at upper side regions of the first barrier layer 170 and the second barrier layer 170a, respectively, which vertically intersect under the first trench portion 140 and the second trench portion 140a, thereby blocking the flow of electrons. The third, fourth, fifth and sixth emission layers 160', 161' and 161' a in the second embodiment have a certain difference from the first and second emission layers 160 and 160a in the first embodiment formed in a region directly above the space between the first and second barrier layers 170 and 170a, and thus electrons injected from the third, fourth, fifth and sixth emission layers 160',160' a, 161' and 161' a at both side ends are blocked from moving channels by the first and second barrier layers 170 and 170a formed below, thereby blocking flow.
Further, when electrons move through a channel formed by the distance W1 between the first barrier layer 170 and the second barrier layer 170a, the channel resistance increases, thereby blocking the flow of electrons. Therefore, when a short circuit occurs, the maximum current capacity can be limited by the distance of the channel from the third emission layer 160', the fourth emission layer 160' a, the fifth emission layer 161 'and the sixth emission layer 161' a to the first barrier layer 170 and the second barrier layer 170a, and the separation distance W1 between the first barrier layer 170 and the second barrier layer 170a, and thus the tolerance (or the bearing amount) at the time of the short circuit can be increased. Therefore, when a short circuit occurs, the robustness of the power semiconductor element can be enhanced by the structure of limiting the maximum current capacity of the short circuit, and the power semiconductor element is ensured not to be damaged before the protection circuit operates, and the short circuit current flows. Further, it is possible to realize an increase in the time required to activate the protection circuit at the time of short-circuiting by improving the soundness of the power semiconductor element.
The embodiments of the present specification also provide a power semiconductor element processing apparatus for processing the aforementioned power semiconductor element.
It should be noted that, for simplicity of description, the foregoing method embodiments are all expressed as a series of combinations of actions, but it should be understood by those skilled in the art that the embodiments are not limited by the order of actions described, as some steps may be performed in other order or simultaneously according to the embodiments of the present disclosure. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily all required for the embodiments described in the specification.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The preferred embodiments of the present specification disclosed above are merely used to help clarify the present specification. Alternative embodiments are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the teaching of the embodiments. The embodiments were chosen and described in order to best explain the principles of the embodiments and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. This specification is to be limited only by the claims and the full scope and equivalents thereof.

Claims (15)

1. A power semiconductor element, characterized by comprising: a first semiconductor layer (110) forming a field stop layer (111), a second semiconductor layer (120) formed on the first semiconductor layer (110), and a charge accumulation layer (130) formed between the first semiconductor layer (110) and the second semiconductor layer (120), the charge accumulation layer (130) having a higher doping concentration than the first semiconductor layer (110);
the first groove (140) and the second groove (140 a) penetrate through the second semiconductor layer (120) and extend to the first semiconductor layer (110) and are spaced a certain distance from each other;
an emitter (150) formed over the second semiconductor layer (120);
a first emission layer (160) and a second emission layer (160 a) are formed between the first trench portion (140) and the second trench portion (140 a) and are in contact with the first trench portion (140) and the second trench portion (140 a);
a first barrier layer (170) and a second barrier layer (170 a) are arranged in parallel below the first trench portion (140) and the second trench portion (140 a), are spaced apart from each other by a certain distance, and vertically intersect the first trench portion (140) and the second trench portion (140 a) to block electrons from flowing from the first emission layer (160) and the second emission layer (160 a) to the collector electrode (180);
the collector (180) is connected to a collector layer (181) formed under the first semiconductor layer (110).
2. The power semiconductor element according to claim 1, wherein the first emission layer (160) and the second emission layer (160 a) are formed directly above a space partitioned by the first barrier layer (170) and the second barrier layer (170 a), respectively;
the maximum current amount is characterized by adjusting the maximum current amount according to the dimension of the first and second emission layers (160, 160 a) in the length direction and the separation distance between the first and second barrier layers (170, 170 a).
3. The power semiconductor element according to claim 1 or 2, wherein the first trench portion (140) and the second trench portion (140 a) form insulating films (141, 141 a) on inner walls; and forming a first gate electrode (142) and a second gate electrode (142 a) buried by the insulating films (141, 141 a) to be insulated from the second semiconductor layer (120) and the emission layer.
4. The power semiconductor element according to claim 1 or 2, characterized in that the emitter (150) forms an emitter contact (152) between the first trench portion (140) and the second trench portion (140 a) extending to the second semiconductor layer (120).
5. The power semiconductor element according to claim 1 or 2, wherein the first and second barrier layers are formed on a bottom surface of the charge accumulation layer (130), a bottom surface of the first and second trench portions (140, 140 a), and a partial lower surface of the first and second trench portions (140, 140 a).
6. The power semiconductor element according to claim 1 or 2, characterized by comprising: the first barrier layer and the second barrier layer are spaced apart from the bottom surface of the charge storage layer (130) by a predetermined distance, and cover the bottom surfaces of the first trench portion (140) and the second trench portion (140 a) and part of the side surfaces of the first trench portion (140) and the second trench portion (140 a).
7. The power semiconductor element according to claim 1 or 2, characterized by comprising:
the first barrier layer and the second barrier layer are spaced apart from the bottom surface of the charge storage layer by a predetermined distance, and are formed below the bottom surfaces of the first trench portion (140) and the second trench portion (140 a) by a predetermined distance.
8. A power semiconductor element, characterized by comprising: a first semiconductor layer (110) forming a field stop layer (111), a second semiconductor layer (120) formed on the first semiconductor layer (110), and a charge accumulation layer (130) formed between the first semiconductor layer (110) and the second semiconductor layer (120), the charge accumulation layer (130) having a higher doping concentration than the first semiconductor layer (110);
the first groove (140) and the second groove (140 a) penetrate through the second semiconductor layer (120) and extend to the first semiconductor layer (110) and are spaced a certain distance from each other;
an emitter (150) formed over the second semiconductor layer (120);
a third emission layer (160 '), a fourth emission layer (160' a), a fifth emission layer (161 ') and a sixth emission layer (161' a) are formed between the first trench portion (140) and the second trench portion (140 a) and in contact with the first trench portion (140) and the second trench portion (140 a);
a first barrier layer (170) and a second barrier layer (170 a) are arranged in parallel below the first trench part (140) and the second trench part (140 a), are spaced apart from each other by a certain distance, and perpendicularly intersect the parallel first trench part (140) and second trench part to block electrons from flowing from the third emission layer (160 '), the fourth emission layer (160' a), the fifth emission layer (161 ') and the sixth emission layer (161' a) to the collector electrode (180);
the third emission layer (160 '), the fourth emission layer (160' a), the fifth emission layer (161 ') and the sixth emission layer (161' a) are respectively formed directly above the first barrier layer (170) and the second barrier layer (170 a).
9. The power semiconductor element according to claim 8, characterized in that the feature of the maximum current amount is adjusted according to the distance between the third emission layer (160 '), the fourth emission layer (160' a), the fifth emission layer (161 ') and the sixth emission layer (161' a) to the first barrier layer (170) and the second barrier layer (170 a) and the separation distance between the first barrier layer (170) and the second barrier layer (170 a).
10. The power semiconductor element according to claim 8 or 9, wherein the first trench portion (140) and the second trench portion (140 a) form insulating films (141, 141 a) on inner walls; and forming a first gate electrode (142) and a second gate electrode (142 a) buried by the insulating films (141, 141 a) to be insulated from the second semiconductor layer (120) and the emission layer.
11. The power semiconductor element according to claim 8 or 9, characterized in that the emitter (150) forms an emitter contact (152) between the first trench portion (140) and the second trench portion (140 a) extending to the second semiconductor layer (120).
12. The power semiconductor element according to claim 8 or 9, wherein the first and second barrier layers are formed on a bottom surface of the charge accumulation layer (130), a bottom surface of the first and second trench portions (140, 140 a), and a partial lower surface of the first and second trench portions (140, 140 a).
13. The power semiconductor element according to claim 8 or 9, characterized by comprising: the first barrier layer and the second barrier layer are spaced apart from the bottom surface of the charge storage layer (130) by a predetermined distance, and cover the bottom surfaces of the first trench portion (140) and the second trench portion (140 a) and part of the side surfaces of the first trench portion (140) and the second trench portion (140 a).
14. The power semiconductor element according to claim 8 or 9, characterized by comprising:
the first barrier layer and the second barrier layer are spaced apart from the bottom surface of the charge storage layer by a predetermined distance, and are formed below the bottom surfaces of the first trench portion (140) and the second trench portion (140 a) by a predetermined distance.
15. A power semiconductor element processing apparatus for processing the power semiconductor element according to claims 1 to 14.
CN202311526090.3A 2023-11-16 2023-11-16 Power semiconductor element and processing device thereof Pending CN117594646A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012129375A (en) * 2010-12-16 2012-07-05 On Semiconductor Trading Ltd Insulated gate bipolar transistor and method of manufacturing the same
US20180358437A1 (en) * 2017-06-09 2018-12-13 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
CN109891595A (en) * 2017-05-31 2019-06-14 富士电机株式会社 Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012129375A (en) * 2010-12-16 2012-07-05 On Semiconductor Trading Ltd Insulated gate bipolar transistor and method of manufacturing the same
CN109891595A (en) * 2017-05-31 2019-06-14 富士电机株式会社 Semiconductor device
US20180358437A1 (en) * 2017-06-09 2018-12-13 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

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