CN117594578A

CN117594578A - Semiconductor package including interface die stack, method and electronic device

Info

Publication number: CN117594578A
Application number: CN202311754117.4A
Authority: CN
Inventors: 杜树安; 逯永广; 杨柳; 郭瑞; 孟凡晓
Original assignee: Chengdu Haiguang Integrated Circuit Design Co Ltd
Current assignee: Chengdu Haiguang Integrated Circuit Design Co Ltd
Priority date: 2023-12-19
Filing date: 2023-12-19
Publication date: 2024-02-23

Abstract

The embodiment of the invention discloses a semiconductor package containing an interface tube core stack, a method and electronic equipment, relating to the technical field of semiconductor package, comprising the following steps: packaging a substrate; a first chip located on the package substrate and at least comprising a first interface die; and a second chip, located above the one chip, comprising at least one second interface die; at least one of the second interface die is interconnected with one of the first interface die in a direction perpendicular to the package substrate. The invention can solve the limit of the chip area to the number of more interfaces to a certain extent.

Description

Semiconductor package including interface die stack, method and electronic device

Technical Field

The invention relates to the technical field of semiconductor packaging. And more particularly to a semiconductor package including an interface Die (IO Die) stack, a method, and an electronic device.

Background

At present, as the performance of high-end chips such as CPU/GPU is continuously improved, the chip and packaging area are continuously increased; meanwhile, the requirements on high-speed interfaces are higher and higher, the number of interfaces is greatly increased, but the requirement of tiling more interfaces on a chip is limited due to the problem of limited chip area.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a semiconductor package including an interface die stack, a method and an electronic device, which can solve the limitation of the chip area on the number of more interfaces.

In order to achieve the aim of the invention, the following technical scheme is adopted:

the embodiment of the application provides a semiconductor package, which comprises:

packaging a substrate;

a first chip located on the package substrate and at least comprising a first interface die; the method comprises the steps of,

a second chip, located above the one chip, comprising at least one second interface die;

at least one of the second interface die is interconnected with one of the first interface die in a direction perpendicular to the package substrate. .

According to one specific implementation of an embodiment of the present application,

the first chip further comprises:

a first connection channel connected to the first interface die and passing through the first surface of the first chip in a direction perpendicular to the package substrate; wherein the second interface die is connected to the first connection via at the first surface of the first chip.

The first chip further includes: a first substrate, the first interface die being located on the first substrate;

wherein the first surface of the first chip is a surface of the first substrate remote from the first interface die.

According to a specific implementation manner of the embodiment of the present application, the second chip further includes:

a second substrate, the second interface die being located between the second substrate and the first substrate;

wherein the second interface die and the first interface die are correspondingly arranged in a direction perpendicular to the package substrate.

According to a specific implementation manner of the embodiment of the application, the area, exposed to the first surface of the first substrate, of the first connection channel forms a connection interface, and the first interface die and the second interface die are respectively connected at the corresponding connection interfaces.

According to a specific implementation manner of the embodiment of the application, the first interface die and the second interface die are connected through hybrid bonding at the corresponding connection interfaces.

According to a specific implementation manner of the embodiment of the application, a second connection channel is arranged on the second substrate, one end of the second connection channel is connected with the second interface die, penetrates through the second substrate along a direction perpendicular to the packaging substrate, and is exposed on the first surface of the second substrate;

Wherein the first surface of the second substrate is a surface of the second substrate remote from the second interface die.

According to a specific implementation manner of the embodiment of the application, the first surface of the second substrate is provided with a substrate for interconnection, the surface, away from the second substrate, of the substrate is interconnected with a connector for connecting with a peripheral device, and the second connection channel is interconnected with the substrate and is used for leading out an electric signal of the second chip to the connector through the substrate.

According to a specific implementation manner of the embodiment of the present application, a metal layer for interconnection is further disposed below the device layer where the first interface die is located; and a conductive bump is arranged at the bottom of the metal layer and is electrically connected to the packaging substrate.

According to a specific implementation manner of the embodiment of the present application, the first chip further includes at least one first semiconductor die, and the first semiconductor die is located at a side of the first interface die, and the first semiconductor die and the first interface die are interconnected through the metal layer and the conductive bump and are electrically connected to the package substrate;

the second chip further comprises at least one second semiconductor die, the second semiconductor die is located at the side of the second interface die, and the second semiconductor die and the first semiconductor die are correspondingly arranged in the direction perpendicular to the packaging substrate and are interconnected through the first connecting channel.

In a second aspect, an embodiment of the present invention provides a semiconductor packaging method, including:

forming a first chip, wherein the first chip at least comprises a first interface die;

forming a second chip, wherein the second chip comprises at least one second interface die;

the first and second chips are bonded such that at least one of the second interface dies is interconnected with one of the first interface dies in a direction perpendicular to the first and second chips.

According to a specific implementation manner of the embodiment of the present application, the forming a first chip includes: forming a first connection channel passing through a first surface of the first chip in a direction perpendicular to the first chip;

bonding the first and second chips such that at least one of the second interface dies interconnects with one of the first interface dies in a direction perpendicular to the first and second chips includes: the first chip and the second chip are bonded such that at least one of the second interface dies is connected with the first connection via at the first surface of the first chip.

According to a specific implementation of an embodiment of the present application, bonding the first chip and the second chip such that at least one of the second interface dies and one of the first interface dies are interconnected in a direction perpendicular to the first chip and the second chip includes: bonding, stacking and interconnecting the second surface of the second chip towards the first surface of the first chip;

Or, bonding, stacking and interconnecting the first surface of the second chip towards the first surface of the first chip;

the second surface is a surface of the device layer of the second chip, which is close to the first chip.

According to a specific implementation of an embodiment of the present application, the forming is performed on the first substrate before or after the first interface die along a first connection channel passing through the first surface of the first chip in a direction perpendicular to the first chip.

the forming of the first connection via through the first surface of the first chip in a direction perpendicular to the first chip is prepared on a first substrate prior to a first interface die, comprising: a first connection channel formed on a first surface passing through the first substrate in a direction perpendicular to the first substrate;

preparing a first interface die on at least a second surface of the first substrate, the first interface die being located at a device layer, the second surface being opposite the first surface;

forming a metal layer for interconnection below the device layer and interconnecting with the lower end of the first connecting channel;

And thinning the first surface of the first substrate to expose the upper ends of the first connecting channels to the first surface of the first substrate for interconnection with the second interface die.

the forming a first connection channel through a first surface of the first chip in a direction perpendicular to the first chip followed by a first interface die is prepared on a first substrate, comprising: preparing the first interface die on at least a second surface of the first substrate, the first interface die being located at a device layer, the second surface being opposite the first surface;

forming a metal layer for interconnection below the device layer, and thinning the first surface of the first substrate;

a first connection channel formed on a first surface of the first substrate, and having upper and lower ends thereof exposed, respectively; wherein the upper end of the first connecting channel is exposed for interconnection with a second interface die;

and interconnecting the metal layer with the lower end of the first connecting channel.

According to a specific implementation manner of the embodiment of the present application, the forming the second chip includes:

Forming a second interface die on at least a second surface of a second substrate; the method comprises the steps of,

a second connection channel is formed through the first surface of the second substrate in a direction perpendicular to the second chip, corresponding to the second interface die.

According to a specific implementation of an embodiment of the present application, the bonding the first chip and the second chip such that at least one of the second interface dies and one of the first interface dies are interconnected in a direction perpendicular to the first chip and the second chip includes: and bonding and connecting the connection interface of the second chip and the first chip by adopting mixed bonding of copper and silicon to form a vertical stack, and enabling the first interface tube core and the second interface tube core to vertically correspond.

According to a specific implementation of an embodiment of the present application, after bonding the first chip and the second chip such that at least one of the second interface dies is interconnected with one of the first interface dies in a direction perpendicular to the first chip and the second chip, the method further includes:

and integrally reversely mounting the first chip and the second chip which are vertically interconnected on the packaging substrate.

According to a specific implementation manner of the embodiment of the present application, the forming the first chip further includes: forming a first semiconductor die, wherein the first semiconductor die is located laterally of the first interface die;

the forming the second chip further includes: forming a second semiconductor die, wherein the second semiconductor die is located laterally of the second interface die;

the bonding of the first and second chips also interconnects at least one first semiconductor die and one second semiconductor die in a direction perpendicular to the first and second chips.

In a third aspect, an embodiment of the present invention further provides an electronic device, including a printed circuit board and the semiconductor package according to any one of the first aspect, where the semiconductor package is interconnected to the printed circuit board through the package substrate.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a semiconductor package according to an embodiment of the present application

Fig. 2 is a schematic structural diagram of a semiconductor package according to another embodiment of the present application;

fig. 3 is a schematic structural diagram of a semiconductor package according to another embodiment of the present disclosure;

fig. 4a is a flow chart illustrating a semiconductor packaging method according to an embodiment of the present disclosure;

fig. 4b is a schematic flow chart of a semiconductor packaging method according to another embodiment of the present application;

fig. 5 is a flow chart of a semiconductor packaging method according to another embodiment of the present application;

fig. 6 to 16 are schematic structural views of stages in the formation of stacked semiconductor packages according to an embodiment of the present application;

FIG. 17 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

fig. 18 is a schematic structural diagram of an application example of an electronic device according to another embodiment of the present application.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.

At present, as the performance of high-end chips such as CPU/GPU is continuously improved, the chip and packaging area are continuously increased; meanwhile, the requirements on high-speed interfaces are higher and higher, the number of interfaces is greatly increased, but the arrangement number of the interfaces on a plane is limited due to the problem of the area of a chip.

Example 1

At least in view of the foregoing, embodiments of the present application provide a semiconductor package including a stack of interface dies (also described below as IO Die, sometimes referred to in the industry as interface chips), with packages of two or more interconnected IO Die stacked at least in a vertical direction. In the following, two chips are vertically stacked, and of course, a vertical 3D stacked package may be implemented with more chips as needed.

As shown in fig. 1, in some embodiments, the semiconductor package 100 includes a package substrate 10, a first chip 20, and a second chip 30.

A first chip 20, located on the package substrate 10, including at least a first interface die 23; the method comprises the steps of,

a second chip 30, located on top of the first chip 20, comprising at least one second interface die 33;

at least one of the second interface dies 33 is interconnected with one of the first interface dies 23 in a direction perpendicular to the package substrate 10 to form an IO Die-based 3D stacked package structure.

In this embodiment, the interface dies respectively included in the second chip and the first chip are stacked and interconnected in the vertical direction, so that high-density stacking of the interface dies in the vertical direction can be realized, and the integration level and performance of the semiconductor package are improved, so that the limitation of the chip area on the number of more interfaces to be arranged can be solved to a certain extent.

In some embodiments, to increase the interconnection density, the second chip and the first chip may be connected in a face to back manner, that is, a front side (face) of the second chip is connected to a back side (back) of the first chip; the front surface refers to a chip device layer and a metal layer, and the density of the chip device layer and the metal layer is higher; the back surface refers to the other surface of the chip silicon substrate away from the device layer and the metal layer.

With continued reference to fig. 1, in some embodiments, the first chip further includes:

a first connection channel 24 connected to the first interface die 23 and passing through the first surface 21b of the first chip 20 in a direction perpendicular to the package substrate 10; wherein the second interface die 33 is connected to the first connection channel 24 at the first surface 21b of the first chip 20.

Referring to fig. 1, specifically, the first chip 20 further includes: a first substrate 21, the first interface die location 23 being located on the first substrate 20 (note: the first chip illustrated is flip-chip, the expression "on … …" does not imply or indicate a particular spatial positional relationship therebetween, but rather expresses a connection relationship therebetween); wherein the first surface 21b of the first chip 20 is a surface of the first substrate 21 remote from the first interface die 23.

Referring to fig. 2, in some embodiments, the second chip 30 further includes:

a second substrate 31, said second interface die 33 being located between said second substrate 31 and said first substrate 21.

Wherein the second interface die 33 is disposed corresponding to the first interface die 23 in a direction perpendicular to the package substrate 10.

With continued reference to fig. 2, the second substrate 31 is provided with a second connection channel 34, and one end of the second connection channel 34 is connected to the second interface die 33, penetrates the second substrate 31 in a direction perpendicular to the package substrate, and is exposed on the first surface 31b of the second substrate 31; wherein the first surface 31b of the second substrate 31 is a surface of the second substrate 31 remote from the second interface die 33.

Referring to fig. 2, in some embodiments, a first chip 20 includes a first substrate 21, a first semiconductor die 22, and a first interface die 23. The first substrate 21 has a first surface 21b and a second surface 21a opposite to the first surface 21b, and a first connection channel 24 leading out to the second surface 21 a.

Further comprises: the first semiconductor die 22 and the first interface die 23 are located on the first surface 21b of the first substrate 21, the first semiconductor die 22 is located laterally of the first interface die 23, and the first semiconductor die 22 and the first interface die 23 are interconnected by a first interconnect structure 25 and electrically connected to the package substrate 10.

A second chip 30 includes a second substrate 31, a second semiconductor die 32, and a second interface die 33. The second substrate 31 has a first surface 31b and a second surface 31a opposite to the first surface 31b, and a second connection channel 34 led out to the second surface 31 a.

A second semiconductor die 32 and a second interface die 33 are located on the first surface 31b of the second substrate 31, the second semiconductor die 32 being disposed in vertical correspondence with the first semiconductor die 22 and interconnected by the connection interface 24a of the first connection channel 24, the second interface die 33 being disposed in vertical correspondence with the first interface die 23 and interconnected by the connection interface 24a of the first connection channel 24, the second semiconductor die 32 and the second interface die 33 being electrically connected to the second surface 31a of the second substrate 31 by the second connection channel 34, respectively, for connecting peripherals.

In this embodiment, the first semiconductor die of the second chip and the second semiconductor die of the first chip are correspondingly interconnected through the first connection channel, and power supply of the first semiconductor die at the top can be achieved through the first chip, so in some embodiments, the second connection channel may not be provided at the position of the second substrate corresponding to the first semiconductor die, thereby saving the cost of the packaging process.

Wherein the first substrate 21 and the second substrate 31 may be made of silicon or other semiconductor materials. For example, a combination of one or more of the following materials may be included: silicon, silicon carbide, and gallium nitride. Alternatively or additionally, the first substrate 21 and the second substrate 31 may comprise other elemental semiconductor materials such as germanium. In some embodiments, the first substrate 21 and the second substrate 31 are made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In other embodiments, the first substrate 21 and the second substrate 31 may be made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, or the like.

In this embodiment, the first semiconductor Die may be one or more semiconductor Die of the same type or different semiconductor Die, for example, including two semiconductor Die of different types, i.e., one computing Die and a buffering Die, or include one or more computing Die, and may also include one or more buffering Die. The stacking mode can be selected according to the application scene, and the die stack cache die can be calculated, the die stack cache die can be cached, or other stacking modes can be adopted.

Referring to fig. 2, the first chip further includes at least one first semiconductor die, and the first semiconductor die is located at a side of the first interface die, and the first semiconductor die and the first interface die are interconnected by the metal layer and the conductive bump and electrically connected to the package substrate;

Specifically, the first semiconductor die 22 and the second semiconductor die 32 each include at least one of a compute die and a memory die.

With continued reference to fig. 2, in some embodiments, the first semiconductor die 22 includes a buffer die, the first interface die 23 includes at least two, one on each side of the buffer die, the second semiconductor die 32 includes a compute die, and the second interface die 33 includes at least two, one on each side of the compute die.

In other embodiments, the first semiconductor die 22 includes a buffer die, the first interface die 23 includes at least one on a side of the buffer die, the second semiconductor die 32 includes a compute die, and the second interface die 33 includes at least one on a side of the compute die and corresponds up and down to the first interface die.

The first semiconductor die 22 includes a computing die, the first interface die 23 includes at least two interface dies respectively located at two sides of the computing die, the second semiconductor die 32 includes a buffer die, and the second interface die 33 includes at least two interface dies respectively located at two sides of the buffer die.

In the stacking manner of the above embodiments, the stacking of the corresponding dies in the vertical direction may also be selected according to the interconnection density of the two, or the stacking manner may also be selected according to the face to face back manner.

In some embodiments, the second semiconductor die and the second interface die of the second chip may be provided integrally or separately.

Referring to fig. 2, in particular, the first connection via 24 and the second connection via 34 may be conductive vias, typically Through Silicon Vias (TSVs), formed by: a Hard Mask (Hard Mask) is used to pattern the circuit pattern in the through silicon via formation area. The open trenches are then typically formed by removing the areas not covered by the hard mask using a Dry Etching (Dry Etching) process. And preparing an insulating film, such as oxide and the like, on the inner surface of the open groove by utilizing a chemical vapor deposition process (Chemical Vapor Deposition), wherein the insulating film is used for isolating metal substances, such as copper and the like, filled in the groove and preventing the silicon chip from being polluted by the metal substances. And filling metal substances into the open grooves, and then performing subsequent polishing, grinding and other procedures to form the TSVs. TSVs are used for signal extraction, and in some embodiments, the first conductive vias 24 are used for inter-die interconnection, typically around 1.5 μm in diameter, around 7 μm in height, and typically around 10-20 μm in minimum pitch; after the first chip is thinned, the thickness is typically about 20 μm. Because the height of the TSV through silicon vias is very small, the interconnection distance is very short, so that a repeater is not needed, direct connection can be performed through the second chip and the first chip, and delay is reduced and frequency is improved. In addition, in this way, high density stacking in the vertical direction can be realized, improving the integration and performance of the semiconductor package.

The second conductive via 34 is used for interconnection of die and substrate, and has a height of about 50 μm to 100 μm (micrometers), a minimum pitch of about 130 μm to 150 μm, and a chip thickness of about 50 μm to 100 μm after thinning.

Referring to fig. 2, in some embodiments, the second connection channel 34 extends through the first surface 31b and the second surface 31a of the second substrate 31. One end (upper end in the drawing) of the second connection channel 34 is exposed to the second surface 31a of the second substrate 31, a substrate 35 for interconnection is provided on the second surface 31a of the second substrate 31, a connector 36 for connecting peripherals is interconnected on a surface of the substrate 35 remote from the second substrate 31, and the second connection channel 34 is interconnected with the substrate 35 for leading out an electrical signal of the second chip 30 to the connector 36 through the substrate 35. Wherein the connector 36 is used for connecting peripherals.

In some embodiments, the first connection channels are smaller in diameter and smaller in height than the second connection channels, and the pin spacing of adjacent two first connection channels is smaller than the pin spacing of adjacent two second connection channels.

Referring to fig. 3, in some embodiments, the area of the first connection channel 24 exposed to the first surface of the first substrate 21 forms a connection interface 24a, and the first interface die 23 and the second interface die 33 are respectively interconnected at the respective connection interfaces 24 a.

Specifically, the first connection channel 24 penetrates the first surface 21b and the second surface 21a of the first substrate 21. The area of the first connection via 24 exposed to the first surface 21b of the first substrate 21 forms a connection interface 24a (note: the dashed box is mainly for the sake of visual presentation of the finger lines, and is not a physical structure). The first and second semiconductor die 22, 32, the first and second interface die 23, 33 are connected at their respective corresponding connection interfaces 24a by hybrid bonding, e.g., copper to copper, silicon to silicon hybrid bonding. Alternatively, the hybrid bond pitch is around 10 to 20 μm and the copper bond diameter is around 2 μm, which can greatly increase the connection density and thus the bandwidth.

Referring again to fig. 2, in some embodiments, the first interconnect structure 25 includes a metal layer 25a and conductive bumps 25b. The metal layer 25a is located under the device layer where the first semiconductor die 22 and the first interface die 23 are located, and the conductive bumps 25b are located at the bottom of the metal layer 25a and electrically connected to the package substrate 10.

A second chip 30 includes a second substrate 31, a second semiconductor die 32, and a second interface die 33. The second substrate 31 has a first surface 31b and a second surface 31a opposite to the first surface 31b, and a second connection channel 34 led out to the second surface 31a. The second connection channel 34 is a conductive via, and penetrates the first surface 31b and the second surface 31a of the second substrate 31. One end of the second connection channel 34 is exposed to the second surface 31a of the second substrate 31.

In some embodiments, the second surface 31a of the second substrate 31 is provided with a substrate 35 for interconnection, and the surface of the substrate 35 remote from the second substrate 31 is interconnected with a connector 36 for connecting to a peripheral device, and the second connection channel 34 is interconnected with the substrate 35 for leading out the electrical signal of the second chip 30 to the connector 36 through the substrate 35.

In some embodiments, a power module 37 is also provided on top of the substrate 35 for supplying power.

The second semiconductor die 32 includes at least one of a compute die and a memory die, e.g., a cache die. The second interface die 33 includes at least two interface dies, one on each side of the buffer die, for exchanging data with the first interface die 23 of the first chip 20.

Referring to fig. 3, in some embodiments, the semiconductor package further comprises: the heat spreader 40 includes at least one bump 40a for bonding with a second substrate of the second chip 30, a second surface of a portion of the corresponding second semiconductor die 32, to dissipate heat. Steps 40b are provided on both sides of the boss 40a, and correspond to the power module on the substrate, and are used for dissipating heat generated by the power module of the second interface die. Through the arrangement, the heat of the second chip 30 can be effectively conducted out, the working temperature of the semiconductor package is reduced, and the stability and reliability of the semiconductor package are improved.

The semiconductor package of the embodiment can be applied to various electronic devices, such as computers, mobile phones, tablet computers, servers, internet of things devices and the like, and the high-speed, high-efficiency, low-power consumption and high-density interconnection among chips can be realized, so that the computing performance and the processing capacity of electrons applying the semiconductor package can be improved.

Further, by 3D stacking and interconnection of the interface dies, the signal interconnection distance can be shortened, so that signal delay and crosstalk are reduced, data transmission rate and bandwidth are improved, and the method is applicable to the fields of big data, artificial intelligence, cloud computing and the like.

Further, by 3D stacking and interconnecting the interface die, the chip area-to-interface number layout constraints may be alleviated.

Example 2

Fig. 4a is a flow chart illustrating a semiconductor packaging method according to an embodiment of the present disclosure; referring to fig. 4a, a semiconductor packaging method is provided according to a further embodiment of the present application, the semiconductor packaging method comprising the steps of:

s110, forming a first chip, wherein the first chip at least comprises a first interface die;

s120, forming a second chip, wherein the second chip at least comprises a second interface die;

S130 bonding the first and second chips such that at least one of the second interface dies is interconnected with one of the first interface dies in a direction perpendicular to the first and second chips.

In this embodiment, the interface dies respectively included in the second chip and the first chip are stacked and interconnected in the vertical direction, so that high-density stacking of the interface dies in the vertical direction can be realized, and the integration level and performance of the formed semiconductor package are improved, so that the limitation of the chip area on the number of the arranged interfaces can be solved to a certain extent.

In some embodiments, the first chip and the second chip may also be pre-prepared, and thus, referring to fig. 4b, the method may include: s210, providing a first chip and a second chip; the first chip comprises at least one first interface die; and, the second chip comprises at least one second interface die;

s220, stacking a second chip on the first chip, and vertically interconnecting at least one second interface die and one first interface die;

s230, integrally flip-chip mounting the first chip and the second chip on a packaging substrate, and interconnecting the first chip to the packaging substrate.

Fig. 5 is a flow chart of a semiconductor packaging method according to another embodiment of the present application; fig. 6 to 16 are schematic structural views of stages in the formation of stacked semiconductor packages according to an embodiment of the present application; taking a semiconductor package including a first chip and a second chip as an example, a specific process of forming the semiconductor package will be described below with reference to fig. 5 to 16 as follows:

s310, providing a first chip 20 and a second chip 30;

wherein the first chip comprises: comprises a first substrate having a first surface and a second surface opposite to the first surface; and a device layer at the first surface of the first substrate, comprising: a first semiconductor die and a first interface die. The second chip includes: comprises a second substrate having a first surface and a second surface opposite to the first surface; and a device layer on the first surface of the second substrate, comprising: a second semiconductor die and a second interface die. The first semiconductor die and the second semiconductor die include at least one of a compute die and a memory die, e.g., the first semiconductor die is a compute die and the second semiconductor die is a buffer die. The first interface die and the second interface die comprise at least two semiconductor dies respectively positioned at two sides of the semiconductor die for inputting and outputting signals.

The first chip and the second chip can be manufactured on site or obtained through external purchase.

S320, forming a plurality of first connecting channels led out to the second surface of the first substrate, and forming a plurality of second connecting channels led out to the second surface of the second substrate.

S330, mounting a second chip stack onto the first chip; the second semiconductor die and the first semiconductor die are correspondingly arranged in the vertical direction and are interconnected through the first connecting channel, the second interface die and the first interface die are correspondingly arranged in the vertical direction and are interconnected through the first connecting channel, and the second semiconductor die and the second interface die are respectively and electrically connected to the second surface of the second substrate through the second connecting channel;

s340, providing a packaging substrate carrying the first chip and the second chip, and reversely mounting the first chip on the packaging substrate.

Referring to fig. 2, in some embodiments bonding the first and second chips such that at least one of the second interface dies interconnects with one of the first interface dies in a direction perpendicular to the first and second chips comprises: and bonding, stacking and interconnecting the second surface of the second chip towards the first surface of the first chip, namely bonding, stacking and interconnecting the second chip and the first chip in a face-to-back (front-to-back) mode.

Or, the second surface of the second chip is bonded, stacked and interconnected towards the first surface of the first chip, namely, the second chip and the first chip are bonded, stacked and interconnected in a face-to-face (front face to front face) manner;

or, the second surface of the second chip is bonded, stacked and interconnected towards the second surface of the first chip, namely, the second chip and the first chip are bonded, stacked and interconnected in a back-to-back (back-to-back) mode;

In this embodiment, the first chip is mounted on the package substrate by flip-chip mounting (abbreviated as flip-chip mounting). The front surface is also called an active surface (active face).

In some embodiments, the first chip may include a first compute die or a first buffer die, and a first interface die, where the first interface die may lead the desired signal out to the back side (second surface of the first substrate) through a first connection channel formed by a through silicon via, interconnecting with the second chip. The second chip may also include a second compute die or a second buffer die, and a second interface die that leads the desired signals and power to the back side (second surface of the second substrate) through a second connection channel formed by the through silicon vias.

The through silicon via manufacturing process can adopt TSV first or TSV last. That is, the forming of the first connection via through the first surface of the first chip in a direction perpendicular to the first chip precedes or follows the first interface die on the first substrate. When the first chip includes a first semiconductor die, the forming of the plurality of first connection vias leading to the second surface of the first substrate is performed on the first substrate prior to or subsequent to the first semiconductor die and the first interface die. Alternatively, a TSV middle process may be used.

Referring to fig. 6 (a) to (d), if the TSV first process is adopted, the method specifically includes: a. a conductive via 24 formed on a first surface of the first substrate;

as shown in fig. 6 a, in this step, an opening trench may be etched on the first surface of the first substrate to form a conductive via, and an insulating film, such as an oxide, is prepared on the inner surface of the opening trench, and this insulating film will serve to isolate the metal substance, such as copper, filled in the trench, and prevent the silicon wafer from being contaminated by the metal substance. And filling metal substances into the open grooves. After the conductive vias are formed in the first substrate, fabrication of the device layer is next initiated, at least the first semiconductor die and the first interface die need to be fabricated on the device layer.

b. The first semiconductor die and the first interface die are prepared on the first surface of the first substrate, and the first semiconductor die and the first interface die are located on the device layer 2, i.e. the device layer 2 is fabricated. The manufacturing process of the device layer 2 can adopt the existing processes of photoetching, etching, doping, depositing and the like on a silicon wafer, and different semiconductor materials are manufactured on the silicon wafer layer by layer according to a chip design Layout (Layout), so that a circuit component layer with a structure is finally formed. In order to highlight the innovative gist of the present application, a detailed description of a manufacturing process of a device layer specifically forming the above-mentioned specific semiconductor device is omitted herein.

c. Forming a metal layer 25a for interconnection below the device layer and interconnecting with the lower end of the conductive via 24;

the metal layer 25a is a conductive layer in the chip for connecting various devices and circuits, and is typically made of a metal material such as copper or aluminum. The forming process of the metal layer mainly comprises the following steps: a metal film is typically deposited by metal deposition over the holes and insulating layer to form the connecting channels. And then removing the redundant metal film through metal etching, leaving needed metal wires and connection, and realizing horizontal interconnection of devices of the device layer.

d. And thinning the second surface of the first substrate to expose the upper end of the conductive through hole to the second surface of the first substrate for interconnection with the second semiconductor die and the second interface.

Wherein the thinning treatment can be realized by working procedures such as polishing, grinding and the like.

In this embodiment, the conductive through hole is prepared on the first substrate, and then the device layer and the metal layer are prepared, so that damage to the device layer and the metal layer is avoided, and the reliability and the yield of the manufacture are improved.

In this embodiment, for a first connection channel and a first interface die fabrication process, the forming of a first connection channel through a first surface of the first chip in a direction perpendicular to the first chip prior to fabrication of the first interface die on a first substrate comprises: a first connection channel formed on a first surface passing through the first substrate in a direction perpendicular to the first substrate;

Referring to fig. 7 (a) - (d), if a TSV last process is used, the forming of the plurality of first connection channels led out to the second surface of the first substrate is followed by the preparation of a first semiconductor die and a first interface die on the first substrate, comprising the steps of: a. preparing the first semiconductor die and a first interface die on a first surface of the first substrate, the first semiconductor die and first interface die being located at a device layer; b. forming a metal layer for interconnection under the device layer; c. thinning the second surface of the first substrate; d. a conductive via 24 formed on the first surface of the first substrate and having an upper end thereof exposed; and interconnecting the metal layer with the lower end of the conductive through hole.

The specific forming process is similar to the specific implementation of the TSV first process described above, and reference is made thereto.

In this embodiment, the device layer and the metal layer are prepared on the first substrate, and then the conductive via is prepared, so that pollution to the conductive via is avoided, and the quality and efficiency of manufacturing can be improved.

In this embodiment, for a first connection channel and a first interface die fabrication process, the forming of the first connection channel through the first surface of the first chip in a direction perpendicular to the first chip followed by fabrication of the first interface die on the first substrate comprises: preparing the first interface die on at least a second surface of the first substrate, the first interface die being located at a device layer, the second surface being opposite the first surface;

Similarly, a TSV middle process may be used, which is characterized in that the device layer is first fabricated, then several metal layers are fabricated, then the TSV is fabricated, and then the remaining metal layers are completed. And then performing thinning treatment on the second surface of the first substrate to expose the upper end of the conductive through hole to the second surface of the first substrate for interconnection with the second semiconductor die and the second interface.

The connecting channels formed by the TSVs are used for interconnection among die, and the minimum pitch of the adjacent connecting channels is generally about 10-20 mu m; after the back surface (second surface) of the first chip is thinned, the thickness is generally about 20 μm.

Next, a second chip is prepared, and in some embodiments, the forming the second chip includes: forming a second interface die on at least a second surface of a second substrate; and forming a second connection channel through the first surface of the second substrate in a direction perpendicular to the second chip, corresponding to the second interface die.

In some embodiments, the forming the first chip further comprises: forming a first semiconductor die, wherein the first semiconductor die is located laterally of the first interface die;

the forming the second chip further includes: forming a second semiconductor die, wherein the second semiconductor die is located laterally of the second interface die; the bonding of the first and second chips also interconnects at least one first semiconductor die and one second semiconductor die in a direction perpendicular to the first and second chips.

Referring to fig. 8, in some examples, forming the second chip includes: forming a second semiconductor die on the first surface of the second substrate; thinning the second surface of the second substrate; forming a second interface die on the first surface of the second substrate, the second interface die being located laterally of the second semiconductor die, the second interface die and the second semiconductor die being located in a device layer;

The forming a plurality of second connection channels leading out to the second surface of the second substrate includes: and forming a conductive through hole led out to the second surface of the second substrate on the second substrate in a region corresponding to the second interface die to form a second connection channel.

In this embodiment, as shown in fig. 9, a second semiconductor die may be first prepared, where the second semiconductor die may be a computing unit or a memory unit, and the TSV is not required to be prepared in the second substrate area corresponding to the second semiconductor die, and only thinning processing is required according to the requirement. Then cutting the whole wafer where the second chip is located into single pieces; next, as shown in fig. 10, a second interface die is prepared, and the required signals and power are led out to the back surface of the second substrate through the TSV through-silicon vias corresponding to the second interface die, wherein the TSV through-silicon vias process may be either TSV first or TSV last, and the TSV first process is adopted, and specific TSV fabrication processes are described above and can be referred to. The conductive through holes are used for leading out signals, the height is about 50-100 mu m, the minimum pitch is about 130-150 mu m, and the thinned second chip is about 50-100 mu m.

Referring to fig. 11, after the chips are all prepared, the first chip and the second chip are 3D stacked at the positions corresponding to the first chip and the second chip respectively by using mixed bonding of copper and silicon, and the connection between the interface dies and the connection between the die and the cache die are calculated at the connection interface. Thus, in some embodiments, said bonding the first and second chips such that at least one of the second interface dies interconnects with one of the first interface dies in a direction perpendicular to the first and second chips comprises: and bonding and connecting the connection interface of the second chip and the first chip by adopting mixed bonding of copper and silicon to form a vertical stack, and enabling the first interface tube core and the second interface tube core to vertically correspond.

In still other embodiments, where the first and second chips further comprise semiconductor die, respectively, said bonding the first and second chips such that at least one of the second interface die and one of the first interface die interconnect in a direction perpendicular to the first and second chips comprises: and bonding and connecting the connection interface of the second chip and the first chip by adopting mixed bonding of copper and silicon to form a vertical stack, enabling the first semiconductor die and the second semiconductor die to vertically correspond, and enabling the first interface die and the second interface die to vertically correspond, so as to realize a 3D stack structure comprising the interface dies.

The pitch of the hybrid bonding points is usually about 10 to 20 mu m, and the bonding density can be greatly improved through bonding connection, so that the bandwidth is increased; meanwhile, as the height of the TSV through silicon via is small, the interconnection distance is very short, so that a repeater is not needed, and the second chip and the first chip can be directly connected, thereby reducing delay and improving frequency.

Referring to fig. 12, next, after mounting a second chip stack onto the first chip, the method further comprises: a first conductive bump (bump) 25b is formed at the bottom of the metal layer at the bottom of the first semiconductor die, and a second conductive bump 35b is formed on the second surface of the second substrate.

In this embodiment, after the 3D stack structure is completed, the bottom first semiconductor die and the top second interface die are subjected to the bump bottom metal UBM and C4 bump preparation, respectively, as shown in fig. 12. The metal UBM is an under bump metallization layer (Under Bump Metallurgy) for short, which is a transition layer added between a chip surface metal layer and a solder bump, and is used for preventing metal or pollution ions from diffusing into the chip metal layer, causing corrosion or forming a hard and brittle intermetallic compound, and reducing the reliability of an interconnection system. The metal UBM is typically composed of multiple layers of metal materials, such as adhesion layers, barrier layers, wetting layers, and oxidation resistant layers, and may be fabricated by Physical Vapor Deposition (PVD) processes.

C4bump is an acronym for controlled collapse chip connection (Controlled Collapse Chip Connection), which refers to a spherical solder bump fabricated on a chip to provide electrical interconnection between the chip and a substrate or other chip. C4 The bulb can be manufactured by vapor deposition, electroplating, ball placement, printing or other processes.

After the C4bump is completed, it is soldered to the bottom ABF substrate (for the package substrate) by a flip-chip soldering process, in some embodiments, after bonding the first and second chips such that at least one of the second interface dies is interconnected with one of the first interface dies in a direction perpendicular to the first and second chips, the method further comprises: and integrally reversely mounting the first chip and the second chip which are vertically interconnected on the packaging substrate. The ABF substrate consists of a core material, a build-up film and metal, and the fan-out of signals and power supplies is completed. Specifically, in some embodiments, the integrally flip-chip mounting the first chip and the second chip that are vertically interconnected to the package substrate includes: and the first conductive bump is welded on the packaging substrate through an inverse-buckle welding process, and the substrate for interconnection is connected on the second substrate and the second surface corresponding to the second interface die through the second conductive bump, so that the electric signal of the second chip is led out to the connector through the substrate.

Referring to fig. 14, in the present embodiment, the power module 37 and the interface bus connector 36 on the front side of the top ABF substrate can be reflowed on the top ABF substrate 35 simultaneously while the bottom ABF substrate is soldered, so that the number of times of reflow of one advanced package can be reduced. And then the top ABF is welded at the corresponding position of the second chip through flip-chip bonding, as shown in fig. 15.

In some embodiments, as shown in FIG. 16, the semiconductor package may be an LGA package or a BGA package, with a pitch typically on the order of 400 μm to 1000 μm; if BGA packaging is adopted, ball mounting 11 is carried out on the back surface of the bottom ABF substrate (packaging substrate) through a ball mounting process, and the diameter is about 250-650 mu m; if LGA packaging is adopted, the socket is directly adopted for electric connection without ball placement.

As shown in fig. 17, a further embodiment of the present application provides an electronic device, which may be a server, a host, or the like, including a Printed Circuit Board (PCB) 200 and the semiconductor package 100 according to any one of the embodiments, wherein the semiconductor package 100 is interconnected to the PCB 200 through the package substrate. The semiconductor package 100 may be a CPU or a GPU, among others.

As shown in fig. 18, in some practical applications, if BGA packages are used, the advanced package is soldered to a motherboard (PCB) 200, and a heat spreader 40 is mounted, and a first interface die of a lower chip is connected through motherboard traces, and the lower chip is powered through motherboard power supply 27; the signals of the upper second interface die are connected by cables to the motherboard connector 26, and the power supply of the upper second interface die may be supplied by the power module 37 on the front side of the top ABF substrate.

According to the above disclosure, in the 3D stacked semiconductor packaging method provided by the embodiments of the present application, the interface dies of at least two chips are stacked and interconnected vertically, so that the problem of the bottleneck of the number of interfaces is solved, and the area utilization rate of the chips can be improved; in addition, through silicon vias and hybrid bonding are utilized to perform direct connection to shorten the interconnection distance. The interface frequency can be improved, the number of the interface connections is increased, and the bandwidth is improved.

It should be noted that, in this document, emphasis on the solutions described between the embodiments is different, but there is a certain interrelation between the embodiments, and when the solution of the present application is understood, the embodiments may be referred to each other; additionally, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or measurement control unit that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or the like. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude that an additional identical element is present in a process, method, article or measurement control unit comprising the element.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor package, comprising:

packaging a substrate;

at least one of the second interface die is interconnected with one of the first interface die in a direction perpendicular to the package substrate.

2. The semiconductor package of claim 1, wherein the semiconductor package is formed from,

the first chip further comprises:

3. The semiconductor package according to claim 2, wherein,

4. The semiconductor package according to claim 2, wherein,

the second chip further comprises:

5. The semiconductor package of claim 2, wherein the area of the first connection via exposed to the first surface of the first substrate forms a connection interface, the first interface die and the second interface die being interconnected at the respective connection interfaces.

6. The semiconductor package of claim 2, wherein the first and second interface dies are connected by hybrid bonding at the respective corresponding connection interfaces.

7. The semiconductor package according to claim 2, wherein a second connection channel is provided on the second substrate, and one end of the second connection channel is connected to the second interface die, penetrates the second substrate in a direction perpendicular to the package substrate, and is exposed on the first surface of the second substrate;

8. The semiconductor package according to claim 2, wherein a substrate for interconnection is provided on the first surface of the second substrate, a connector for connecting peripherals is interconnected on a surface of the substrate remote from the second substrate, and the second connection channel is interconnected with the substrate for leading out an electrical signal of the second chip to the connector through the substrate.

9. The semiconductor package of claim 2, wherein a metal layer for interconnection is further disposed under the device layer where the first interface die is located;

and a conductive bump is arranged at the bottom of the metal layer and is electrically connected to the packaging substrate.

10. The semiconductor package of claim 9, wherein the first chip further comprises at least one first semiconductor die, and the first semiconductor die is located laterally of the first interface die, the first semiconductor die and the first interface die being interconnected by the metal layer and conductive bumps and electrically connected to the package substrate;

11. A semiconductor packaging method, comprising:

12. The semiconductor packaging method of claim 11, wherein the forming the first chip comprises: forming a first connection channel passing through a first surface of the first chip in a direction perpendicular to the first chip;

13. The semiconductor packaging method of claim 11, wherein bonding the first and second chips such that at least one of the second interface dies interconnects with one of the first interface dies in a direction perpendicular to the first and second chips comprises: bonding, stacking and interconnecting the second surface of the second chip towards the first surface of the first chip;

14. The semiconductor packaging method of claim 12, wherein the forming a first connection via through the first surface of the first chip in a direction perpendicular to the first chip is prepared on a first substrate before or after a first interface die.

15. The semiconductor packaging method of claim 14, wherein the forming a first connection via through the first surface of the first chip in a direction perpendicular to the first chip is prepared on a first substrate prior to the first interface die, comprising: a first connection channel formed on a first surface passing through the first substrate in a direction perpendicular to the first substrate;

16. The semiconductor packaging method of claim 14, wherein the forming a first connection via through the first surface of the first chip in a direction perpendicular to the first chip is followed by the first interface die being prepared on a first substrate, comprising: preparing the first interface die on at least a second surface of the first substrate, the first interface die being located at a device layer, the second surface being opposite the first surface;

17. The semiconductor packaging method of claim 14, wherein the forming the second chip comprises:

18. The method of semiconductor packaging of claim 11, wherein bonding the first and second chips such that at least one of the second interface dies interconnects with one of the first interface dies in a direction perpendicular to the first and second chips comprises: and bonding and connecting the connection interface of the second chip and the first chip by adopting mixed bonding of copper and silicon to form a vertical stack, and enabling the first interface tube core and the second interface tube core to vertically correspond.

19. The semiconductor packaging method of claim 11, wherein after bonding the first and second chips such that at least one of the second interface dies is interconnected with one of the first interface dies in a direction perpendicular to the first and second chips, the method further comprises:

20. The semiconductor packaging method of claim 11, wherein the forming the first chip further comprises: forming a first semiconductor die, wherein the first semiconductor die is located laterally of the first interface die;

21. An electronic device comprising a printed circuit board and the semiconductor package of any one of claims 1 to 10, the semiconductor package being interconnected to the printed circuit board by the package substrate.