CN117591469A - FPGA self-adaptive FLASH method and FPGA - Google Patents

Abstract

The invention discloses a method for self-adapting FLASH of an FPGA and the FPGA, comprising the following steps: responding to detection instructions of a plurality of sectors to be detected carrying SPI FLASH sent by terminal equipment, sending control instructions to the SPI FLASH and receiving feedback information of the SPI FLASH; determining available sector information and invalid sector information according to the feedback information and the control instruction, and sending the available sector information to the terminal equipment; the terminal equipment is used for generating a self-adaptive instruction and sending the self-adaptive instruction to the FPGA when the number of the available sectors represented by the available sector information meets the preset storage requirement; storing failure sector information to an electronic fuse in response to the adaptive instruction, storing a configuration file received from the terminal device into an available sector; and after the FPGA is powered on again, acquiring configuration files from the plurality of sectors to be detected according to the failure sector information stored in the electronic fuse so as to perform functional configuration.

Description

FPGA self-adaptive FLASH method and FPGA

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a method for self-adapting an FPGA (field programmable gate array) to FLASH and the FPGA.

Background

With the continuous development of modern society, electronic information industry, especially semiconductor industry, has been rapidly developed, and the chip is a core technology, which has very wide roles in military, industry and daily life. At present, the complexity of the chip is higher and higher, the manufacturing process is more and more advanced, and corresponding failure modes are more and more. From the initial design to the final application on the product, there is a proportion of rejects at each stage. The loss caused by the failure of the chip manufacturer is minimal, because only single chips are removed, however, as the consumption chain grows, more and more chips form a larger application module, such as a common children toy, and further such as human aerospace equipment, and the loss caused by the failure of any chip in the use process cannot be estimated. It is becoming increasingly important for all chip manufacturers to adapt more robustly to peripheral devices while guaranteeing the quality of their own products.

A field programmable gate array (Field Programmable Gate Array, FPGA) is a semiconductor device containing programmable elements that can be programmed in the field by a user. The FPGA needs to download a set of special data streams through its configuration interface to implement configuration of FPGA functions. The configuration bit stream may be sent from an external host to the FPGA or read by the FPGA from a nonvolatile access register (Serial Peripheral Interface Flash EEPROM Memory, SPI FLASH) of the serial peripheral interface with an active initiation request. The FPGA contains an Electronic Fuse (EFUSE) for storing information such as a key, configuration settings, etc. EFUSE is a type of nonvolatile memory that can only be written once and data will not be lost after power is lost. The general FPGA does not have the function of storing the configuration data stream in a power-off mode, but the EFUSE memory capacity is too small to be used for storing the data stream, and the most common method is to store the configuration data stream into the external FLASH, and the FPGA actively loads data from the external FLASH after power-on. When the FPGA and the FLASH are matched for use, the FPGA can face the phenomenon that the configuration of the FPGA is unsuccessful due to the failure of part of the FLASH sectors, so that the whole equipment cannot normally operate, and a device is required to be removed for troubleshooting and replacement. In the general FLASH chip manufacturing process, redundant design is carried out, and on the basis of the original design, a plurality of sectors (sectors) are redundant and used for replacing the failed sectors. However, the number of redundant sectors is limited, and when the number of redundant sectors is less than the number of failed sectors, only FLASH can be scrapped.

That is, when the FPGA and the FLASH are used together, the FPGA may face the phenomenon that the failure of a part of the sectors of the FLASH causes unsuccessful configuration of the FPGA, although the failure sectors can be replaced by the redundancy design of the FLASH, when the number of the failure sectors does not affect the implementation of the overall design but exceeds the number of the redundancy design support of the FLASH, the FLASH chip has to be replaced; in addition, the redundancy schemes may be different from FLASH manufacturer to FLASH manufacturer, and the size of the redundancy area may be different. Therefore, the rejection rate of FLASH is high, the working unreliability and the instability of the FPGA are greatly increased, and the working efficiency is reduced.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a method for self-adapting an FPGA to FLASH and the FPGA.

The technical problems to be solved by the invention are realized by the following technical scheme:

the invention provides a method for self-adapting FLASH of an FPGA, which is applied to the FPGA and comprises the following steps:

responding to a detection FLASH sector instruction sent by terminal equipment, sending a control instruction to a connected SPI FLASH, and receiving feedback information which is returned by the SPI FLASH and is specific to the control instruction; the detection FLASH sector instruction carries a plurality of sectors to be detected of the SPI FLASH;

determining available sector information and invalid sector information according to the feedback information and the control instruction, and sending the available sector information to the terminal equipment; the terminal equipment is used for generating an adaptive instruction and sending the adaptive instruction to the FPGA when the number of the available sectors represented by the available sector information meets a preset storage requirement;

storing the failure sector information to an electronic fuse in response to the adaptive instruction, and storing a configuration file received from the terminal device into an available sector of the plurality of sectors to be detected according to the failure sector information;

and after the FPGA is powered on again, acquiring the configuration file from the plurality of sectors to be detected according to the failure sector information stored in the electronic fuse so as to perform functional configuration.

In some embodiments, the control instructions include: an erase instruction for erasing data stored in each sector to be detected, a storage instruction carrying data to be stored of each sector to be detected, and a read instruction for reading data stored in each sector to be detected; the responding to the detection FLASH sector instruction sent by the terminal equipment, sending a control instruction to the connected SPI FLASH, and receiving feedback information for the control instruction returned by the SPI FLASH, comprises the following steps:

responding to a FLASH sector detection instruction sent by the terminal equipment, and sending the erasure instruction to the connected SPI FLASH;

after receiving the successful erasure message returned by the SPI FLASH, sending the storage instruction to the SPI FLASH;

after receiving a message of successful data storage to be stored returned by the SPI FLASH, sending the reading instruction to the SPI FLASH;

and receiving the data read from each sector to be detected returned by the SPI FLASH.

In some embodiments, the feedback information includes: data read from each sector to be detected; the control instruction includes: a storage instruction carrying the data to be stored of each sector to be detected; the determining available sector information and invalid sector information according to the feedback information and the control instruction, and sending the available sector information to the terminal device, including:

comparing the data read from the sector to be detected with the data to be stored of the sector to be detected aiming at each sector to be detected to obtain a comparison result;

when the comparison result represents that the data are consistent, determining the sector to be detected as an available sector, and recording address information of the available sector;

when the comparison result represents that the data are inconsistent, determining the sector to be detected as a failure sector, and recording address information of the failure sector;

taking address information of all available sectors as the available sector information and address information of all failure sectors as the failure sector information;

and transmitting the available sector information to the terminal equipment.

In some embodiments, after the FPGA is powered up again, according to the failure sector information stored in the electronic fuse, the acquiring the configuration file from the plurality of sectors to be detected to perform functional configuration includes:

after the FPGA is powered on again, acquiring the failure sector information stored in the electronic fuse;

determining the address information of the configuration file to be read from the address information of the plurality of sectors to be detected according to the failure sector information;

generating a file reading instruction according to the address information of the configuration file to be read;

and sending the file reading instruction to the SPI FLASH to read the configuration file for function configuration.

In some embodiments, the storing the failure sector information to an electronic fuse in response to the adaptive instruction, and storing a configuration file received from the terminal device into an available sector of the plurality of sectors to be detected according to the failure sector information, includes:

responding to the self-adaptive instruction returned by the terminal equipment, and storing the failure sector information to the electronic fuse; the failure sector information comprises address information of all failure sectors;

generating a file storage instruction carrying the configuration file to be stored according to the configuration file received from the terminal equipment and address information except address information of all failure sectors in the address information of the plurality of sectors to be detected;

and sending the file storage instruction to the SPI FLASH to store the configuration file into an available sector in the plurality of sectors to be detected.

In some embodiments, the plurality of sectors to be detected are all sectors in the SPI FLASH or part of the sectors in the SPI FLASH.

The invention also provides an FPGA of the self-adaptive FLASH, which comprises the following steps:

the configuration module is used for receiving a FLASH sector detection instruction sent by the terminal equipment;

the FLASH self-checking logic module is used for responding to the FLASH sector detection instruction and sending a control instruction to the connected SPI FLASH through an SPI interface; the detection FLASH sector instruction carries a plurality of sectors to be detected of the SPI FLASH;

the configuration module is further used for receiving feedback information, returned by the SPI FLASH, of the control instruction;

the FLASH self-checking logic module is also used for determining available sector information and invalid sector information according to the feedback information and the control instruction;

the configuration module is further configured to send the available sector information to the terminal device through a first configuration interface; receiving an adaptive instruction returned by the terminal equipment through the first configuration interface, responding to the adaptive instruction, storing the failure sector information to an electronic fuse through a second configuration interface, and storing a configuration file received from the terminal equipment into an available sector in the plurality of sectors to be detected according to the failure sector information; after the FPGA is powered on again, acquiring the configuration files from the plurality of sectors to be detected through the second configuration interface according to the failure sector information stored in the electronic fuse so as to perform functional configuration; and the terminal equipment is used for generating the self-adaptive instruction and sending the self-adaptive instruction to the FPGA when the number of the available sectors represented by the available sector information meets a preset storage requirement.

Compared with the prior art, the invention has the beneficial effects that:

according to the method for the FPGA self-adaptive FLASH, the FPGA actively adapts to the FLASH through the cooperative work of the terminal equipment and the FPGA, after the proper FLASH is adapted, the configuration file is stored in the available sector, and then the FPGA correctly reads the configuration file by means of the electronic fuse after being electrified again, so that the FPGA can be passively and actively adapted to FLASH with different essence of different manufacturers, the rejection rate of the FLASH is greatly reduced, the working reliability and stability of the FPGA are improved, the working efficiency is greatly improved, the working time is shortened, the time cost is saved, and the waste of manpower is reduced, and the application advantage on large-scale equipment is more obvious.

The present invention will be described in further detail with reference to the accompanying drawings.

Drawings

Fig. 1 is a schematic flow chart of a method for FPGA to adapt to FLASH according to an embodiment of the present invention;

fig. 2 is a specific flowchart of a method for adaptive FLASH of an FPGA according to an embodiment of the present invention;

fig. 3 is another specific flowchart of a method for adapting FLASH by an FPGA according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.

Fig. 1 is a flow chart of a method for FPGA to adapt to FLASH according to an embodiment of the present invention, where the method includes:

s101, responding to a detection FLASH sector instruction sent by a terminal device, sending a control instruction to a connected SPI FLASH, and receiving feedback information which is returned by the SPI FLASH and is specific to the control instruction; and detecting a plurality of sectors to be detected of the SPI FLASH carried in the FLASH sector instruction.

Here, the terminal device may be a personal computer (Personal Compurter, PC) or an upper computer. SPI FLASH is connected with FPGA through the data line.

Here, the plurality of sectors to be detected may be determined by the terminal device according to a user instruction. The plurality of sectors to be detected may be all sectors in the SPI FLASH, or may be part of sectors in the SPI FLASH. For example, when the SPI FLASH includes 9 sectors, the terminal device may select all the 9 sectors as the sectors to be detected, or may select the first 3 or the first 5 or the last 6 of the 9 sectors as the sectors to be detected, which may be specifically determined according to actual needs.

In some embodiments, the control instructions include: the step S101 is implemented by:

s1011, responding to the detection FLASH sector instruction sent by the terminal equipment, and sending an erasure instruction for erasing the data stored in each sector to be detected to the connected SPI FLASH.

And S1012, after receiving the successful erasure message returned by the SPI FLASH, sending a storage instruction carrying the data to be stored of each sector to be detected to the SPI FLASH.

Here, the data to be stored may be arbitrary data. In some embodiments, the data to be stored of different sectors to be detected may be different, so that the problem that the data cannot be found in time when error storage or error reading occurs can be avoided; in some embodiments, the data to be stored in different sectors to be detected may be the same, so that the detection method may be simplified and the detection efficiency may be improved.

S1013, after receiving the successful message of the data storage to be stored returned by the SPI FLASH, sending a reading instruction for reading the data stored in each sector to be detected to the SPI FLASH.

S1014, receiving data read out from each sector to be detected returned by the SPI FLASH.

Here, after the SPI FLASH receives an instruction from the FPGA and executes the instruction, the FPGA will report its own status to the FPGA, and when the SPI FLASH is in an idle state, the FPGA will continue to send the next instruction to the SPI FLASH.

Here, the FPGA sends instructions to the SPI FLASH via a standard SPI interface.

S102, determining available sector information and invalid sector information according to feedback information and a control instruction, and sending the available sector information to a terminal device; and the terminal equipment is used for generating an adaptive instruction and sending the adaptive instruction to the FPGA when the number of the available sectors represented by the available sector information meets the preset storage requirement.

In some embodiments, S102 is implemented by:

s1021, comparing the data read from the sector to be detected with the data to be stored of the sector to be detected for each sector to be detected, and obtaining a comparison result.

And S1022, when the comparison result represents that the data are consistent, determining the sector to be detected as an available sector, and recording address information of the available sector.

S1023, when the comparison result represents that the data are inconsistent, determining the sector to be detected as a failure sector, and recording address information of the failure sector.

S1024, address information of all available sectors is used as available sector information, and address information of all failure sectors is used as failure sector information.

S1025, the available sector information is sent to the terminal equipment.

The terminal device is further configured to generate an adaptation failure instruction and send the adaptation failure instruction to the FPGA when the number of available sectors represented by the available sector information does not meet the preset storage requirement, and after receiving the adaptation failure instruction, the FPGA may reconnect other SPI FLASH and continue the adaptive operation until receiving the adaptive instruction sent by the terminal device, which indicates that the adapted SPI FLASH is found.

And S103, responding to the self-adaptive instruction, storing the failure sector information into the electronic fuse, and storing the configuration file received from the terminal equipment into an available sector in a plurality of sectors to be detected according to the failure sector information.

In some embodiments, S103 is implemented by:

s1031, responding to a self-adaptive instruction returned by the terminal equipment, and storing failure sector information to an electronic fuse; the failure sector information includes address information of all failure sectors.

S1032, generating a file storage instruction carrying the configuration file to be stored according to the configuration file received from the terminal equipment and address information except address information of all failure sectors in the address information of the plurality of sectors to be detected.

S1033, sending a file storage instruction to the SPI FLASH to store the configuration file into an available sector in the plurality of sectors to be detected.

And S104, after the FPGA is powered on again, acquiring configuration files from a plurality of sectors to be detected according to the failure sector information stored in the electronic fuse so as to perform functional configuration.

In some embodiments, S104 is implemented by:

s1041, after the FPGA is powered on again, acquiring failure sector information stored in the electronic fuse.

S1042, determining the address information of the configuration file to be read from the address information of a plurality of sectors to be detected according to the failure sector information.

Specifically, address information except all address information in failure sector information in address information of a plurality of sectors to be detected is used as address information of a configuration file to be read.

S1043, generating a file reading instruction according to the address information of the configuration file to be read.

S1044, a file reading instruction is sent to the SPI FLASH to read the configuration file for function configuration.

Compared with the traditional method which is simply regulated by FLASH, the method for self-adapting FLASH by the FPGA provided by the invention has the advantages that the FPGA actively adapts to the FLASH through the cooperative work of the terminal equipment and the FPGA, after the proper FLASH is adapted, the configuration file is stored in the available sector, and then the FPGA correctly reads the configuration file by means of the electronic fuse after being electrified again, so that the FPGA can be passively initiative and can adapt to FLASH with different essence of different manufacturers, thereby greatly reducing the rejection rate of the FLASH, greatly improving the working reliability and stability of the FPGA, greatly improving the working efficiency, shortening the working time, saving the time cost and reducing the waste of manpower, and especially, the application advantage on large-scale equipment is more obvious.

The invention also provides an FPGA of the self-adaptive FLASH, which comprises the following steps:

the configuration module is used for receiving a FLASH sector detection instruction sent by the terminal equipment;

the FLASH self-checking logic module is used for responding to the FLASH sector instruction detection and sending a control instruction to the connected SPI FLASH through the SPI interface; detecting a plurality of sectors to be detected carrying SPI FLASH in FLASH sector instructions;

the configuration module is also used for receiving feedback information which is returned by the SPI FLASH and is specific to the control instruction;

the FLASH self-checking logic module is also used for determining available sector information and failure sector information according to the feedback information and the control instruction;

the configuration module is also used for sending the available sector information to the terminal equipment through the first configuration interface; receiving an adaptive instruction returned by the terminal equipment through a first configuration interface, responding to the adaptive instruction, storing failure sector information to the electronic fuse through a second configuration interface, and storing a configuration file received from the terminal equipment into an available sector in a plurality of sectors to be detected according to the failure sector information; after the FPGA is powered on again, acquiring configuration files from a plurality of sectors to be detected through a second configuration interface according to the failure sector information stored in the electronic fuse so as to perform functional configuration; and the terminal equipment is used for generating an adaptive instruction and sending the adaptive instruction to the FPGA when the number of the available sectors represented by the available sector information meets the preset storage requirement.

The following describes exemplary flow of the method of FPGA adaptive FLASH according to the present invention by means of fig. 2 and 3.

As shown in fig. 2, after the FPGA and the SPI FLASH (in fig. 2, the SPI FLASH is represented by FLASH) are normally powered on, the configuration interface of the PC/host computer and the FPGA is connected, and then the following procedure is performed:

(1) the PC/upper computer sends an instruction for detecting the FLASH sector to the FPGA through a configuration interface, wherein the instruction carries a sector to be detected of the SPI FLASH;

(2) after receiving the FLASH sector detection instruction, a configuration module of the FPGA starts an SPI FLASH self-checking logic module in the FPGA;

(3) the SPI FLASH self-checking logic module sequentially sends an erasing instruction, a writing instruction and a reading instruction to the SPI FLASH through a standard SPI interface;

(4) the SPI FLASH erases all data stored in the sector to be detected when receiving the erasing instruction, stores the data carried in the writing instruction into the corresponding sector when receiving the writing instruction, reads the data from the corresponding sector when receiving the reading instruction, and returns the instruction execution result to the FPGA when the SPI FLASH executes an instruction from the FPGA;

(5) the configuration module transmits the data received from the SPI FLASH to the FLASH self-checking logic module;

(6) a FLASH self-checking logic module in the FPGA compares the data written into each sector to be detected with the data read out from the sector, and records the address information of the failure sector according to the comparison result; specifically, when the data written into a sector is inconsistent with the data read from the sector, determining that the sector is invalid, and recording address information of the sector at the moment;

(7) after all the sector to be detected of the SPI FLASH are detected, the configuration module returns a sector detection result to the PC/upper computer through the configuration interface, and the PC/upper computer judges whether the sector which is not invalid in the sector to be detected of the SPI FLASH meets the storage requirement or not according to the sector detection result;

(8) if the non-failure sector meets the storage requirement, the PC/upper computer sends a self-adaptive instruction to the configuration module through the configuration interface, the FPGA configuration module stores the address information of the failure sector of the SPI FLASH into the EFUSE of the FPGA through the configuration interface after receiving the instruction, and meanwhile, the FPGA starts a self-adaptive FLASH mode;

(9) the PC/upper computer downloads the latest configuration file from the PC/upper computer to the SPI FLASH through the configuration interface of the FPGA and the standard SPI interface, and when the SPI FLASH is in failure sector during the downloading process, the FPGA automatically skips the failure sector when writing data;

as shown in fig. 3, after the FPGA starts the adaptive FLASH mode, the following procedure is performed after the FPGA is powered up again (the SPI FLASH is also represented by FLASH in fig. 3):

(1) after the power supply voltage is stable, a configuration module of the FPGA starts to work, and the configuration module reads back the address information of the failure sector of the SPI FLASH stored in the EFUSE through a configuration interface;

(2) the configuration module of the FPGA actively initiates a request to read from the SPI FLASH through a standard SPI interface to obtain data, and a read instruction and a read address can be adjusted in real time according to the address information of the SPI FLASH failure sector in the reading process so as to avoid the failure sector;

(3) the FPGA uses the data stream read from the SPI FLASH to implement the configuration of the FPGA function (it should be noted that step (3) is not shown in fig. 3).

It should be noted that the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.

In the description, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. Some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce a good effect.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (7)

1. The method for self-adapting the FLASH by the FPGA is characterized by being applied to the FPGA and comprising the following steps of:

responding to a detection FLASH sector instruction sent by terminal equipment, sending a control instruction to a connected SPI FLASH, and receiving feedback information which is returned by the SPI FLASH and is specific to the control instruction; the detection FLASH sector instruction carries a plurality of sectors to be detected of the SPI FLASH;

determining available sector information and invalid sector information according to the feedback information and the control instruction, and sending the available sector information to the terminal equipment; the terminal equipment is used for generating an adaptive instruction and sending the adaptive instruction to the FPGA when the number of the available sectors represented by the available sector information meets a preset storage requirement;

storing the failure sector information to an electronic fuse in response to the adaptive instruction, and storing a configuration file received from the terminal device into an available sector of the plurality of sectors to be detected according to the failure sector information;

and after the FPGA is powered on again, acquiring the configuration file from the plurality of sectors to be detected according to the failure sector information stored in the electronic fuse so as to perform functional configuration.

2. The method of FPGA adaptive FLASH according to claim 1, wherein the control instructions comprise: an erase instruction for erasing data stored in each sector to be detected, a storage instruction carrying data to be stored of each sector to be detected, and a read instruction for reading data stored in each sector to be detected; the responding to the detection FLASH sector instruction sent by the terminal equipment, sending a control instruction to the connected SPI FLASH, and receiving feedback information for the control instruction returned by the SPI FLASH, comprises the following steps:

responding to a FLASH sector detection instruction sent by the terminal equipment, and sending the erasure instruction to the connected SPI FLASH;

after receiving the successful erasure message returned by the SPI FLASH, sending the storage instruction to the SPI FLASH;

after receiving a message of successful data storage to be stored returned by the SPI FLASH, sending the reading instruction to the SPI FLASH;

and receiving the data read from each sector to be detected returned by the SPI FLASH.

3. The method of FPGA adaptive FLASH according to claim 1, wherein the feedback information comprises: data read from each sector to be detected; the control instruction includes: a storage instruction carrying the data to be stored of each sector to be detected; the determining available sector information and invalid sector information according to the feedback information and the control instruction, and sending the available sector information to the terminal device, including:

comparing the data read from the sector to be detected with the data to be stored of the sector to be detected aiming at each sector to be detected to obtain a comparison result;

when the comparison result represents that the data are consistent, determining the sector to be detected as an available sector, and recording address information of the available sector;

when the comparison result represents that the data are inconsistent, determining the sector to be detected as a failure sector, and recording address information of the failure sector;

taking address information of all available sectors as the available sector information and address information of all failure sectors as the failure sector information;

and transmitting the available sector information to the terminal equipment.

4. The method for adaptive FLASH of FPGA of claim 1, wherein the obtaining the configuration file from the plurality of sectors to be detected for functional configuration according to the failure sector information stored in the electronic fuse after the FPGA is powered up again, comprises:

after the FPGA is powered on again, acquiring the failure sector information stored in the electronic fuse;

determining the address information of the configuration file to be read from the address information of the plurality of sectors to be detected according to the failure sector information;

generating a file reading instruction according to the address information of the configuration file to be read;

and sending the file reading instruction to the SPI FLASH to read the configuration file for function configuration.

5. The method of FPGA adaptive FLASH according to claim 1, wherein said storing the failure sector information to an electronic fuse in response to the adaptive command and storing a configuration file received from the terminal device to an available sector of the plurality of sectors to be detected according to the failure sector information comprises:

responding to the self-adaptive instruction returned by the terminal equipment, and storing the failure sector information to the electronic fuse; the failure sector information comprises address information of all failure sectors;

generating a file storage instruction carrying the configuration file to be stored according to the configuration file received from the terminal equipment and address information except address information of all failure sectors in the address information of the plurality of sectors to be detected;

and sending the file storage instruction to the SPI FLASH to store the configuration file into an available sector in the plurality of sectors to be detected.

6. The method of FPGA adaptive FLASH according to claim 1, wherein the plurality of sectors to be detected are all sectors in the SPI FLASH or part of sectors in the SPI FLASH.

7. An adaptive FLASH FPGA comprising:

the configuration module is used for receiving a FLASH sector detection instruction sent by the terminal equipment;

the FLASH self-checking logic module is used for responding to the FLASH sector detection instruction and sending a control instruction to the connected SPI FLASH through an SPI interface; the detection FLASH sector instruction carries a plurality of sectors to be detected of the SPI FLASH;

the configuration module is further used for receiving feedback information, returned by the SPI FLASH, of the control instruction;

the FLASH self-checking logic module is also used for determining available sector information and invalid sector information according to the feedback information and the control instruction;

the configuration module is further configured to send the available sector information to the terminal device through a first configuration interface; receiving an adaptive instruction returned by the terminal equipment through the first configuration interface, responding to the adaptive instruction, storing the failure sector information to an electronic fuse through a second configuration interface, and storing a configuration file received from the terminal equipment into an available sector in the plurality of sectors to be detected according to the failure sector information; after the FPGA is powered on again, acquiring the configuration files from the plurality of sectors to be detected through the second configuration interface according to the failure sector information stored in the electronic fuse so as to perform functional configuration; and the terminal equipment is used for generating the self-adaptive instruction and sending the self-adaptive instruction to the FPGA when the number of the available sectors represented by the available sector information meets a preset storage requirement.