CN117591380B

CN117591380B - Bus performance monitoring method and device

Info

Publication number: CN117591380B
Application number: CN202410070175.3A
Authority: CN
Inventors: 刘晓君; 谌彤
Original assignee: Xindong Microelectronics Technology Wuhan Co ltd
Current assignee: Xindong Microelectronics Technology Wuhan Co ltd
Priority date: 2024-01-18
Filing date: 2024-01-18
Publication date: 2024-05-03
Anticipated expiration: 2044-01-18
Also published as: CN117591380A

Abstract

The present invention relates to the field of performance monitoring, and in particular, to a method and apparatus for monitoring bus performance. Comprising the following steps: acquiring bus data on multiple buses, and selecting one path of bus data to be monitored from the acquired bus data through a multiple selector; the method comprises the steps of acquiring brief performance information in bus data to be monitored through a brief information monitoring component, writing the brief performance information into a register, and/or acquiring control information of each data request in the bus data to be monitored through a detailed information monitoring component, respectively splicing the control information with a time stamp and a packet header into data packets with fixed bit width alignment, and writing the data packets into external storage equipment; and acquiring performance information in the register and/or the external storage device, and analyzing a monitoring result of the bus to be monitored according to the performance information. The invention can pre-embed the observable means of the chip bus and realize the monitoring of the bus performance in the verification after silicon.

Description

Bus performance monitoring method and device

Technical Field

The present invention relates to the field of performance monitoring, and in particular, to a method and apparatus for monitoring bus performance.

Background

In the existing SOC (System On Chip) Chip design, a plurality of intellectual property (Intellectual Property, abbreviated as IP) modules with different functions are generally integrated, and the IPs with different functions are connected through a bus, so that the bus performance is a key factor affecting the performance of the whole SOC System. In the post-silicon verification process of the SOC, the conditions of bus blocking, too large bus delay, insufficient bus bandwidth and the like possibly exist in the cooperative work process between the IPs, so that the system performance cannot meet the design requirement, and therefore the post-silicon test is required to comprise bus performance monitoring.

In the post-silicon verification process, the means of locating faults or problems present in the bus are very limited. The current implementation technology method for bus performance monitoring of silicon post-verification comprises the following steps:

1. and leading out the internal logic signals of the chip through the pin signals. Defects: the number of pins of the chip is limited, the number of signals of the bus is generally larger, the frequency of the bus signals is higher, the frequency supported by the pins of the chip is generally lower, and the high-frequency signals cannot be directly led out. Therefore, bus logic signals are led out from the pins of the chip by observation on the premise of not affecting the normal function of the chip, so that bus information is difficult to completely monitor.

2. Only the average transmission efficiency of the bus and the data traffic of the system bus over a period of time are monitored. Defects: only the average transmission efficiency and the total data transmission amount in a period of time can be monitored, and no relevant record is made on information such as bus delay, and the bus delay is one of key indexes of bus performance.

In view of this, how to overcome the defects existing in the prior art, and solve the problem that the bus performance monitoring is inconvenient in the existing silicon post-verification process is a problem to be solved in the technical field.

Disclosure of Invention

Aiming at the defects or the improvement demands of the prior art, the invention solves the problem of inconvenient bus performance monitoring in the silicon post-verification process.

The embodiment of the invention adopts the following technical scheme:

In a first aspect, the present invention provides a method for monitoring bus performance, specifically: acquiring bus data on multiple buses, and selecting one path of bus data to be monitored from the acquired bus data through a multiple selector; the method comprises the steps of acquiring brief performance information in bus data to be monitored through a brief information monitoring component, writing the brief performance information into a register, and/or acquiring control information of each data request in the bus data to be monitored through a detailed information monitoring component, respectively splicing the control information with a time stamp and a packet header into data packets with fixed bit width alignment, and writing the data packets into external storage equipment; and acquiring performance information in the register and/or the external storage device, and analyzing a monitoring result of the bus to be monitored according to the performance information.

Preferably, the acquiring, by the brief information monitoring unit, brief performance information in bus data to be monitored specifically includes: when the brief information monitoring component monitors data requests on the bus to be monitored, data transmission monitoring and average delay calculation are carried out for corresponding times according to the number of configured data requests, meanwhile, the maximum delay and the minimum delay of bus transmission are updated in real time, data to be monitored in each data transmission are monitored, and brief performance information of the bus to be monitored is calculated according to all data transmission data to be monitored.

Preferably, the acquiring, by the detailed information monitoring unit, control information of each data request in the bus data to be monitored, and splicing the control information with a time stamp and a packet header into a data packet with aligned fixed bit width, includes: acquiring data to be monitored in bus data to be monitored, packaging each acquired data to be monitored and timestamp information of the data to be monitored, adding a packet header into the data to be monitored according to a specified format, generating a first data packet with a first bit width, and carrying out first data caching on the first data packet; acquiring a first data packet of a first data cache, extracting effective data to be monitored in the first data packet, extracting effective data from the first data packet according to a channel effective mark and a specified format of the first data packet, splicing the extracted effective data into a second data packet with a second bit width after aligning according to a specified bit width, carrying out second cache on the second data packet, and taking the cached second data packet as the spliced data packet.

Preferably, the obtaining the data to be monitored in the bus data to be monitored, packaging each obtained data to be monitored and timestamp information of the data to be monitored with a header according to a specified format, and generating a first data packet with a first bit width, further includes: the method comprises the steps of obtaining data to be monitored in each channel of a bus to be monitored, forming data to be monitored with the same time stamp in one channel into data packets with corresponding time stamps of the channel according to a designated sequence, binding the data packets with the same time stamp with the corresponding time stamps, and adding channel effective marks to the data packets with the same time stamp in all channels according to the channel sequence to form a first data packet with the time stamp.

Preferably, when one or more invalid data to be monitored exist in the data to be monitored of the corresponding time stamp, the forming the data to be monitored of the same time stamp in a channel into the data packet of the corresponding time stamp of the channel according to the specified sequence specifically includes: filling the data to be monitored of the invalid channel with 0 of the corresponding bit width, and forming the filled data to be monitored into a data packet.

Preferably, the extracting the valid data of the first data packet according to the channel valid flag and the specified format of the first data packet, and aligning the extracted valid data according to the specified bit width specifically includes: and determining a monitored effective channel according to the value of the channel effective mark of the first data packet, determining the effective monitoring data length of the first data packet according to the data to be monitored of the effective channel, extracting the effective monitoring data, and aligning the effective monitoring data according to the designated bit width to obtain the effective data packet.

Preferably, when the detailed information monitoring component is used, the analyzing the monitoring result of the bus to be monitored according to the monitoring information specifically includes: starting from the first effective data packet, acquiring the value of each bit in the channel effective mark of the current effective data packet and the data length of the data to be monitored of the channel corresponding to each bit; acquiring each piece of data to be monitored in the current effective data packet according to the data length of the data to be monitored, and acquiring monitoring information of a corresponding channel according to the corresponding position in the channel effective mark; and calculating the length of the current effective data packet according to the bit value and the length of the data to be monitored of the corresponding channel, acquiring the next current effective data packet according to the length of the current effective data packet until all effective data packets to be analyzed are acquired, and analyzing the performance monitoring result of the bus to be monitored according to the information to be monitored in all the acquired effective data packets.

In another aspect, the present invention provides a device for monitoring bus performance, specifically: comprising the following steps: a register, a multiplexer, a brief information monitoring unit and a detailed information monitoring unit, for implementing the method for monitoring bus performance provided in the first aspect, specifically: the register is used for storing the external configuration information and the performance information acquired by the brief information monitoring component; the multi-path selector is used for acquiring one path or multiple paths of bus data to be monitored in the external bus data to be monitored, and sending the acquired bus data to the selected brief information monitoring component and/or the detailed information monitoring component; the brief information monitoring component is used for acquiring brief performance information according to the acquired bus data and external configuration information and writing the brief performance information into the register; the detailed information monitoring part is used for acquiring detailed performance information according to the acquired bus data and external configuration information and writing the detailed monitoring information into an external storage device.

Preferably, the brief information monitoring means includes: the system comprises a read data brief information monitoring module and a write data brief information monitoring module; when the read data brief information monitoring module monitors the read data behavior in the external bus data to be monitored, the read data brief information monitoring module is used for calculating brief performance information in the acquired bus data; when the write data brief information monitoring module monitors the write data behavior in the bus data to be monitored, the write data brief information monitoring module is used for calculating brief performance information in the acquired bus data.

Preferably, the detailed information monitoring section includes: the system comprises a packet module, a data processing and buffering module and a write storage module, and specifically comprises: the method comprises the steps that a packet grouping module acquires data to be monitored from acquired bus data, and packages the data to be monitored into a first data packet with a first bit width and a fixed length; the data processing and caching module extracts effective data from the first data packet, performs splicing and caching according to the second bit width after aligning according to the designated bit width, and starts to transmit the data to the write storage module until the cached data quantity meets the configuration requirement or the overtime condition; the writing storage module is used for writing the second data packet into the external storage device as detailed monitoring information.

Compared with the prior art, the device provided by the invention has the beneficial effects that: the method comprises the steps of adding a bus performance monitoring design into a device in the early stage of chip design, pre-embedding a means that a chip bus can be observed in advance through a performance monitoring device, selectively observing transmission performances of different bus channels through a multiplexer, acquiring different performance data in bus data through a brief information monitoring component and a detailed information monitoring component, and storing the acquired performance data through a register or external storage equipment to realize monitoring of various bus performance data in silicon post-verification.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings that are required to be used in the embodiments of the present invention will be briefly described below. It is evident that the drawings described below are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a flow chart of a method for monitoring bus performance according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a brief information monitoring component in the device according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a detailed information monitoring component in the device according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a storage format of a data packet in an apparatus according to an embodiment of the present invention;

FIG. 5 is a flowchart of a method for monitoring bus performance according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a method for monitoring bus performance according to an embodiment of the present invention;

FIG. 7 is a flowchart of another method for bus performance monitoring according to an embodiment of the present invention;

FIG. 8 is a timing diagram of a data packet in each channel of the method according to the embodiment of the present invention;

FIG. 9 is a schematic diagram of a bus performance monitoring device according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of another bus performance monitoring device according to an embodiment of the present invention;

Fig. 11 is a schematic diagram of a first packet format in a method actual scenario provided in an embodiment of the present invention;

Fig. 12 is a schematic diagram of a second packet format in a practical scenario of the method according to the embodiment of the present invention;

fig. 13 is a schematic diagram of a second packet format in a practical scenario of the method according to the embodiment of the present invention;

Fig. 14 is a schematic diagram of a second packet format in a practical scenario of the method according to the embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The present invention is an architecture of a specific functional system, so that in a specific embodiment, functional logic relationships of each structural module are mainly described, and specific software and hardware implementations are not limited.

In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other. The invention will be described in detail below with reference to the drawings and examples.

In the existing silicon post-verification process, the bus fault root found during verification cannot be determined due to lack of bus performance observation means inside the silicon chip. Aiming at the defects, the embodiment provides a bus performance monitoring method, and in the early stage of chip design, the performance monitoring device is added with the design logic for bus performance monitoring, logic signals in the chip are not required to be led out through pins, so that the total data transmission amount of a bus can be monitored, and the information such as bus bandwidth, bus delay and the like can be monitored.

As shown in fig. 1, the method for monitoring bus performance provided by the embodiment of the invention specifically includes the following steps:

step 101: and acquiring bus data on the multiple buses, and selecting one path of bus data to be monitored by the acquired bus data through a multiplexer.

The bus to be monitored is used for carrying out data transmission between the master device and the slave device according to the data request as shown in fig. 2, and a performance monitoring device is connected between a master (master) and a slave (slave) of the bus to be monitored in the chip design stage, so that the information to be monitored transmitted on the bus can be obtained. The method provided in this embodiment supports monitoring of multiple buses, which may be understood as multiple sets of buses, each set of buses having multiple channels, for example: AW, W, B, AR, R, etc. channels in AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) protocol proposed by ARM company. "N" shown in fig. 2 represents the number of groups of the bus, and may be a natural number greater than or equal to 1. In the actual monitoring process, only one bus can be selected from the plurality of buses to monitor at the same time, so that after the multi-path bus data containing the information to be monitored is obtained, the performance monitoring device can select one path from the multi-path bus data as one bus data to be monitored through the multi-path selector, and corresponding data processing is performed by the method provided by the embodiment, so that the monitoring of the bus performance is realized

Step 102: the method comprises the steps of acquiring brief performance information in bus data to be monitored through a brief information monitoring component, writing the brief performance information into a register, and/or acquiring control information of each data request in the bus data to be monitored through a detailed information monitoring component, respectively splicing the control information with a time stamp and a packet header into data packets with fixed bit width alignment, and writing the data packets into an external storage device.

The input information of bus performance monitoring comprises multi-path bus data and monitored configuration information, and the input multi-path bus data is monitored according to the configuration information. For example: monitoring brief performance information such as data transmission quantity, delay between data transmission request and response and the like through a brief information monitoring component, and storing the acquired brief performance information into a register; or, the detailed information monitoring means monitors detailed information such as control information prescribed by the protocol, and saves the acquired detailed monitoring information to an external storage device (memory).

For the detailed information monitoring part, after the data packet is written into the data processing and buffering module, the writing storage module can judge whether the data volume in the data processing and buffering module meets the data volume required by the writing storage module. If the required data volume is met, writing the effective data into the external storage device; if the required data size is not met, the module is provided with a timeout mechanism, and if the timeout mechanism is overtime, the data in the second cache module is written into the storage device. In a specific implementation, the data volume required by the writing storage module and the timeout duration of the timeout mechanism can be configured according to specific application scenarios.

Step 103: and acquiring performance information in the register and/or the external storage device, and analyzing a monitoring result of the bus to be monitored according to the performance information.

In practical implementations, different performance data needs to be acquired and analyzed in different ways and written into different storage devices for use. In this embodiment, the obtained corresponding performance information is written into the register or the storage device by the brief information monitoring section and the detailed information monitoring section. In the post-silicon test process, the monitoring information in the register or the storage device can be read in real time or at a designated time, and the read bus monitoring information is analyzed to obtain the performance monitoring result of the bus to be monitored. The monitoring result can be determined according to the acquired performance information type and actual requirements, for example: bus delay, bus transfer bandwidth, whether the bus is stuck, total data volume of bus data transfer, etc.

After steps 101 to 103 provided in this embodiment, performance monitoring of the bus can be achieved.

In actual implementation, the specific manner in which the information in the registers or external storage device is obtained may be determined based on the actual implementation.

In a certain scenario, the shared register can be used as the register used in the method of the embodiment, so that other chips or functional devices can directly perform the method on the designated address of the register, and data in the register can be quickly acquired. Because the data acquisition through the register is simple and convenient and the real-time performance is high, other chips or functional devices can quickly judge or respond through the performance data, and the performance data is used as control information to control other functions. For example: when the performance information in the register shows that the delay on the current bus exceeds a set threshold or is stuck, a fault log output program, a fault detection program, or a fault handling program is started.

In another scenario, the performance information in the storage device may be further saved to a database or saved to a cloud, so that the performance information is conveniently analyzed by using other performance analysis programs, or batch tests are performed on a plurality of bus devices in a distributed test environment, and data aggregation and overall analysis are completed.

In another scenario, the data in the profile monitoring component and the detailed information monitoring component may also be co-analyzed and controlled. For example, when the performance threshold value is not exceeded, the detailed information monitoring part does not monitor, and when the performance information in the brief information monitoring part displays that the bus works abnormally, the detailed information monitoring part is triggered to start monitoring.

In the method provided by the embodiment, the brief information monitoring component and the detailed information monitoring component are used, and when monitoring is performed, a monitoring module and a corresponding data storage mode which are needed to be used can be selected according to the needs.

For the brief information monitoring part, the statistics of the transmission data quantity and the calculation of time delay are mainly carried out, and the concrete time delay calculation mode is as follows: delay = moment of slave response request-moment of master initiation request. When the brief information is monitored, read-write request information and response data for the read-write request may continuously exist on the bus to be monitored. In order to calculate the average delay of the data requests, the delay data of the read-write requests need to be acquired for a plurality of times to calculate the average value, so when the brief information monitoring component monitors the data requests on the bus to be monitored, the data transmission monitoring calculation average delay of corresponding times is carried out according to the number of the configured data requests. On the other hand, the data such as the maximum delay and the minimum delay also need to be cached, and the delay of the secondary transmission is compared with the cached maximum delay and minimum delay, so that the maximum delay and the minimum delay of the bus transmission also need to be updated in real time. After the data are obtained, the data to be monitored in each data transmission can be monitored, and the brief performance information of the bus to be monitored is calculated according to the data to be monitored of all data transmission. In implementations, registers may be used to store and count data of multiple read and write requests to calculate average latency; at the same time, registers may also be used to buffer the current maximum and minimum delays for comparison and updating. In particular implementations, the corresponding profile performance data may be calculated based on characteristics of the performance data. The following is a brief example of a manner of calculating delay information in performance data, and in actual implementation, the delay information or other specific manner of calculating performance data may be determined as needed.

(1) The delay information monitored by the read data brief information module is calculated as follows: the time delay between the sending of the read request signal by the read address channel and the return of the data by the read data channel on the bus, i.e. the time from the initiation of the read request signal to the actual completion of the transmission of the read data, is calculated. According to the configured number of bus data transmission to be monitored, carrying out corresponding times of data transmission monitoring, obtaining time delay during each monitoring, and calculating average delay of the bus data transmission to be monitored according to the time delay; and the delay information such as the maximum delay, the minimum delay and the like is adjusted in real time according to the monitoring result.

(2) The delay information of the write data brief information monitoring module is calculated as follows: calculating the time delay between the transmission of a write request signal by a write address channel on a bus and the return of a response signal by a write response channel, namely the time from the initiation of the write request to the actual response of data writing, carrying out corresponding times of write data transmission monitoring according to the configured number of bus data transmission to be monitored, and calculating the average delay of the bus write transmission to be monitored according to the time delay; and the delay information such as the maximum delay, the minimum delay and the like is adjusted in real time according to the monitoring result.

In the actual monitoring process, the multichannel monitoring data input to the detailed information monitoring component are not valid at the same time. In order to solve the above problem and facilitate subsequent analysis, the control information may be spliced into a data packet. Specific: acquiring data to be monitored in bus data to be monitored, packaging each acquired monitoring data and timestamp information of the monitoring data, adding a packet header according to a specified format, generating a first data packet with a first bit width, and carrying out first data caching on the first data packet; acquiring a first data packet of a first data cache, extracting effective monitoring data in the first data packet, performing fixed bit width alignment on the extracted data according to a specified format of the first data packet, splicing a second data packet with a second bit width, and performing second cache on the second data packet. In practical implementation, the valid data packet may be aligned with the designated bit width, and if the valid data packet cannot be aligned, the corresponding number of 0 s is complemented to be aligned with the designated bit width. For example, when the length of the obtained actual valid data packet is 90 bits and the designated alignment bit width is 32bits, 6 0's are required to be added, so that the packet length is 96 bits, and the alignment of 32bits is satisfied. In the packet grouping mode, the length of the actual effective data packet is variable, and the length is related to the data monitored by the effective channel, so that the data of the ineffective channel is not subjected to 0 supplementing treatment in order to keep the length of each actual effective data packet consistent, and therefore, the storage of the ineffective data can be effectively reduced, and the bandwidth and the storage consumption are reduced.

In practical implementation, the first data packet is used for supplementing the invalid channel data with 0 corresponding to the length according to the complete channel, arranging the valid channel data according to the designated sequence, and adding the information such as the channel valid flag, the time stamp and the like. And the data packet with aligned bit width is designated as the effective data packet after the effective data in the first data packet is extracted. The second data packet is used for spliced data packets with fixed bit width, and may comprise a plurality of actual valid data packets.

In practical implementations, the bit widths of the first data packet and the second data packet may be determined according to practical needs.

(1) The bit width of the first data packet is related to the monitored bus information, the more detailed the monitored information, the greater the bit width. For example: the aw channel of the axi protocol, including awaddr, awid, awlen, awlen, awsize waiting for monitoring data, in one specific scenario, monitors awaddr, awid, awlen only, then determines the field definition and bit width of the first packet based on the data length of the 3 pieces of information only.

(2) The bit width of the second data packet is related to the data bit width of the system bus. In a certain scene, if the data bit width of the bus connected with the writing storage module in the system is 256Bits, the data bit width of the second data packet is set to be 256Bits correspondingly, so that the monitored effective data packet can be written into the memory module mounted in the system more conveniently.

(3) The valid data alignment bit width is used for designating the alignment width of the valid data packet, and after the valid data of the first data packet is extracted, if the bit width of the valid data is not aligned with the valid data alignment bit width, the data is aligned by supplementing 0 according to the valid data alignment bit width. Through bit width alignment, a part of invalid data 0 can be removed, the system bandwidth occupied by the invalid data 0 is reduced, the problem that the chip area is increased due to the fact that the actual valid data is completely stored is avoided, and the functional design of the chip is complex.

In some scenarios, the memory space for packet buffering may be opened with a overwrite function, in which case the last address of the write is monitored, and data is read from the memory space after the address when data is fetched from the memory space for analysis, and the packet from the address may be overwritten, resulting in incomplete packets. In a specific implementation, each data packet comprises the following components: header + timestamp + valid channel monitor data. When the coverage function is opened, there is a case where a packet header of one data packet is covered, and therefore, a fixed header identifier may be added to the packet header, and the added packet header includes: fixed header identifier +chvalid. With the fixed header identifier, even if part of the data of the previous packet is covered, the fixed header identifier of the next packet can be found, the data is started to be parsed, and the data packet of the previous cover can be directly discarded until the data is started to be parsed after the fixed header identifier is found.

Meanwhile, in order to facilitate the determination of the channel corresponding to each monitoring data during analysis, a channel effective flag is added into the first data packet, fixed bits are corresponding to the channel effective flag according to the fixed channel sequence, the bit corresponding to the data to be monitored of the effective channel in the channel effective flag is set to be 1, and the bit corresponding to the monitoring data of the ineffective channel in the channel effective flag is set to be 0.

After the effective data packet of the storage device is obtained, the monitoring result of the bus to be monitored can be analyzed according to the monitoring data. Specific: starting from the first effective data packet, acquiring the value of each bit in the channel effective mark of the current effective data packet and the data length of the data to be monitored of the channel corresponding to each bit; acquiring each piece of data to be monitored in the current effective data packet according to the data length of the data to be monitored, and acquiring monitoring information of a corresponding channel according to the corresponding position in the channel effective mark; and calculating the length of the current effective data packet according to the bit value and the length of the data to be monitored of the corresponding channel, acquiring the next current effective data packet according to the length of the current effective data packet until all effective data packets to be analyzed are acquired, and analyzing the performance monitoring result of the bus to be monitored according to the information to be monitored in all the acquired effective data packets.

Further, the monitoring information may also be spliced into fixed-bit-width data packets in a manner as shown in fig. 3 for facilitating subsequent analysis and data use.

Step 201: acquiring monitoring data in the multi-path bus data, packaging each acquired monitoring data and timestamp information of the monitoring data according to a specified format, generating a first data packet with a first bit width, and carrying out first data caching on the first data packet.

After the multi-path bus data enter the detailed information monitoring component, the monitoring data and the timestamp information in the multi-path bus data are packaged into a first data packet with a fixed bit width a in a specified format, and after the first data packet is packaged by using the fixed bit width, each monitoring data in the data packet can be conveniently acquired according to the bit width during subsequent analysis. After packaging is completed, the first data packet is stored in a first buffer module so as to be used by a subsequent processing module.

Furthermore, because the information of the five channels on the bus is not necessarily valid at the same time, only part of channels are valid, in order to ensure that the bit width of each monitoring data in the first data packet is consistent, the data to be monitored of the invalid channel is filled with 0 with the corresponding bit width, and the filled data to be monitored is formed into the data packet, so that the data bit width stored in the first cache module is always consistent.

Furthermore, since the method provided in this embodiment supports monitoring of multiple paths of bus data, in order to perform overall evaluation on multiple paths of channels in the multiple paths of bus, when packaging a first data packet, it is also necessary to uniformly package data at the same time point in different paths, that is, uniformly package data packets with the same timestamp. Specifically, the data to be monitored in each channel of the bus to be monitored is sequentially obtained, the data to be monitored with the same time stamp in one channel is formed into a data packet with the corresponding time stamp of the channel according to the appointed sequence, the data packet with the same time stamp and the corresponding time stamp are bound, and then the data packets with the same time stamp bound in all channels are added with a channel effective mark according to the channel sequence to form a first data packet with the time stamp.

Step 202: acquiring a first data packet of a first data cache, extracting effective data to be monitored in the first data packet, extracting effective data from the first data packet according to a channel effective mark and a specified format of the first data packet, splicing the extracted effective data into a second data packet with a second bit width after aligning according to a specified bit width, carrying out second cache on the second data packet, and taking the cached second data packet as the spliced data packet.

In order to improve the utilization rate of the space of the external storage device and reduce the occupancy rate of the system bandwidth as much as possible, the effective data extraction and bit width splicing module can be used for obtaining the first data packet from the first buffer module, and effective data to be monitored is extracted from the first data packet and spliced again so as to remove invalid data in the first data packet. Specifically, each effective data to be monitored in the first data packet is obtained, and the effective data to be monitored is extracted to form an effective data packet according to specified bit width alignment.

Further, after invalid data is removed, the position of the data in the valid data packet is changed, in order to determine a channel corresponding to each monitoring data in the valid data packet during analysis, a channel valid flag may be added in the first data packet, and the original position of each valid data is marked by using the channel valid flag, so that the channel corresponding to the monitoring data is judged according to the original position. And adding a channel effective mark into the first data packet, correspondingly fixing bits according to a fixed channel sequence, setting the bit corresponding to the monitoring data of the effective channel in the channel effective mark to be 1, and setting the bit corresponding to the monitoring data of the ineffective channel in the channel effective mark to be 0.

Meanwhile, the effective channels corresponding to the data monitored by the same time stamp are not necessarily consistent each time, so that the length of an effective data packet is variable, the bus data width (second bit width) connected with the write memory module in the system is fixed, the effective data is spliced into a second data packet according to the second bit width in order to be compatible with the bus bit width written and stored by the system, and the second data packet is cached by the second cache module so as to solve the burst transmission condition.

After steps 201 to 202 provided in this embodiment, the splicing of the data to be monitored can be completed.

When the first data packet is packed, the monitoring data of each channel is arranged in a fixed sequence according to a specified format, and the monitoring data of the invalid channel is filled with 0 with a corresponding bit width, so that the channel corresponding to each monitoring data can be judged directly through the position of the monitoring data in the first data packet. After the valid data packet is generated, the position of each channel monitoring data is changed because the invalid data is removed, and the corresponding channel cannot be judged directly according to the performance data.

And judging the channel corresponding to the performance data. In step 202, the actual position corresponding to each piece of performance data in the effective data packet is identified by the channel effective mark, and accordingly, when parsing is performed, the actual position of each piece of performance data in the effective data packet is obtained by the effective mark, so that the channel corresponding to each piece of performance data is obtained.

In practical implementations, one second packet may contain multiple valid packets because the bit width of the valid packet is variable and the bit width of the second packet is fixed. A complete second data packet can be regarded as a part of effective data packet, an effective data packet or a plurality of effective data packets, the length of the effective data packet after the designated bit width is aligned can be deduced according to the channel effective mark, therefore, the length of the packet can be determined according to the channel effective mark and the channel effective mark of the next packet can be found to determine the next effective data packet when analyzing, and the like until all the data packets are analyzed. If the bit width of a first packet is greater than the bit width of a second packet in an actual application system, then an actual valid packet may be distributed among multiple second packets. In practical implementation, the storage format of the actual valid data packet according to the above-described packet format and implementation is shown in fig. 4. In the actual scenario of fig. 4, the data bit width corresponding to each timestamp is 64 bits, the actual valid data packets are aligned with 32 bits, the header identifier is 8 bits, and 8' h5a.

The upper layer software reads the data in the memory, finds the first header indicator, then finds the corresponding ch_valid to analyze the length and the monitoring data of the actual effective data packet, and determines the next ch_ vaild, thereby determining the length and the monitoring data of the next actual effective data packet.

As shown in fig. 5, the data in the effective data packet may be analyzed by the following method, and the monitoring result of the bus to be monitored may be analyzed according to the analyzed data.

Step 301: starting from the obtained first valid data packet, taking each valid data packet as the current valid data packet in sequence, and obtaining the value of each bit in the channel valid flag of the current valid data packet and the data length of the performance data corresponding to each bit.

And when analysis is carried out, each effective data packet is acquired in sequence, and the performance data in each data packet is analyzed. In the channel valid flag used in this embodiment, each bit corresponds to a position of a channel in the first packet specified format, and each performance data in the valid packet corresponds to a bit with a median of 1 in the channel valid flag. Therefore, the valid data packet can be parsed according to the value of each bit in the valid flag and the data length of the performance data corresponding to each bit.

Step 302: and acquiring the channel corresponding to each piece of performance data according to the position corresponding to the performance data in the channel effective mark, acquiring the performance data of the corresponding channel and the data length of the corresponding channel according to the fixed packet format, and taking the performance data as the performance information of the corresponding channel.

Because each bit in the channel effective mark corresponds to the position of one channel in the first data packet appointed format, the channel corresponding to the performance data can be obtained according to the position of the corresponding performance data in the channel effective mark, and then the analysis of each performance data in the effective data packet is completed according to the information composition to be monitored and the analysis channel of each channel.

Step 303: and calculating the length of the current effective data packet according to the bit value and the length of the corresponding channel performance data, acquiring the next current effective data packet according to the length of the current effective data packet until all effective data packets to be analyzed are acquired, and analyzing the monitoring result of the bus to be monitored according to the performance information in all the acquired effective data packets.

After steps 301 to 303 provided in this embodiment, analysis of performance information can be completed according to the monitoring data written into the storage device by the detailed information monitoring unit.

According to the bus performance monitoring method, the brief performance information is directly obtained through the brief information monitoring component, or the detailed information monitoring component packs information such as data to be monitored, time stamps and the like of the bus to be monitored, and the detailed performance information is obtained according to the packed monitoring data. In addition, in order to support burst transmission of the write storage device, the bandwidth utilization rate of the system bus is improved, and effective data extraction and secondary caching are also performed. The method provided by the embodiment can monitor the related indexes on the bus according to the actual application scene: such as bus delay, bus bandwidth, total amount of bus transfer data over time, etc. In the post-silicon test, the fault detection efficiency caused by bus abnormality is improved, and a means is provided for confirming the post-silicon test problem of the SOC chip so as to shorten the chip marketing period.

On the basis of the method for monitoring bus performance provided in the foregoing embodiment, this embodiment further provides a device for monitoring bus performance for performance monitoring using the device in this embodiment, where the device is used to implement the method for monitoring bus performance provided in this embodiment.

Fig. 6 is a schematic diagram of the device architecture of the present embodiment, in which the dotted line portion represents the device provided by the present embodiment. The device comprises: a register, a multiplexer, a profile monitoring unit and a detailed information monitoring unit. The configuration interface of the register is used as an external configuration information input interface of the device, the first data interface of the register is connected with the brief information monitoring component, the second data interface of the register is connected with the detailed information monitoring component, the input interface of the multiplexer is used as an external bus data input interface to be monitored of the device, the first output interface of the multiplexer is connected with the brief information monitoring component, the second output interface of the multiplexer is connected with the detailed information monitoring component, and the data output interface of the detailed information monitoring component is connected with an external storage device.

The register is used for storing external configuration information and performance information acquired by the brief information monitoring component. When performance monitoring is carried out, external configuration information such as bus channels to be monitored, performance data storage and the like which are input by a configuration interface are stored in a register for use in monitoring. On the other hand, the performance information data volume that the brief information monitoring part obtained is smaller, also save in the register, can obtain the brief performance data of bus to be monitored under the precondition that does not occupy the system bandwidth, and read and fetch promptly, do not need the data to analyze in order to raise the read-write efficiency.

The multiplexer is used for selecting one path of bus data to be monitored from the external acquired multi-path bus data and sending the acquired bus data to the selected brief information monitoring component and/or the detailed information monitoring component. In an SOC system, the system bus interfaces are usually more than one way, so as to flexibly monitor different bus interfaces. The one or more paths of bus data selected by the multiplexer are used as the input of the two parts of the brief information monitoring part and the detailed information monitoring part.

In the device provided in this embodiment, in order to meet the monitoring needs of different performance indexes, the bus monitoring portion mainly includes two components, namely a detailed information monitoring component and a brief information monitoring component. The implementation mode and the result storage mode of the two modules are different, different choices are provided for different performance index acquisition requirements in the silicon post-verification process by combining the two monitoring modes, and in actual implementation, different performance indexes can be monitored by selecting different modules according to the requirements.

The brief information monitoring part is used for acquiring brief performance information according to the acquired bus data and external configuration information and writing the brief performance information into the register. In the post-silicon verification process, bus transfer characteristics to be monitored, such as the id of a read request or write request that needs to be monitored, may be set by configuration information. The brief information monitoring section monitors transmission requests conforming to the bus transmission characteristics of the configuration based on the configuration information and calculates brief performance information as brief performance information, for example: total amount of transmission data, average delay, maximum delay, minimum delay, etc. The performance information obtained by the brief information monitoring part is stored in a register, and in actual bus monitoring, the transmission characteristic of the bus can be rapidly obtained only by reading the performance information stored in the register.

As shown in fig. 7, the brief information monitoring section includes: the system comprises a read data brief information monitoring module and a write data brief information monitoring module. The first output interface of the multiplexer is connected with the read data brief information monitoring module, and the first output interface of the multiplexer is connected with the write data brief information monitoring module.

When the read data brief information monitoring module monitors the read data behavior in the bus data to be monitored, the read data brief information monitoring module is used for calculating brief performance information in the acquired bus data. When the write data brief information monitoring module monitors the write data behavior in the bus data to be monitored, the write data brief information monitoring module is used for calculating brief performance information in the acquired bus data. The brief information monitoring component is mainly used for monitoring the data transmission condition on the bus, and because the memory capacity of the register is limited, the quantity of the performance information which can be stored is limited, in order to facilitate repeated monitoring, the performance data such as the maximum time delay and the minimum time delay in the register can be directly updated when each read-write request responds, the performance data is directly read through the register, the total transmission bandwidth of the system bus is not occupied, and the monitoring result is easy to obtain.

The detailed information monitoring component is used for acquiring detailed monitoring information according to the acquired bus data and external configuration information and writing the detailed monitoring information into an external storage device. In the detailed information monitoring section: in practical system application, bus information to be monitored can be determined by an instantiation parameter transmission mode, effective bus information monitored on each channel is packaged into data packets by adding a time stamp, then the data packets at the same time point of all channels are spliced into data packets with fixed bit width, and the spliced data packets are used as detailed monitoring information to be written into a storage device. If a plurality of monitoring devices provided in this embodiment are used in the same test system, bus information input by way of instantiation may be different in each monitoring device. In the timing shown in fig. 8, the corresponding packet format at each time is as follows: wherein: t1 to T4 are time stamps at respective times, respectively; AW1 is monitoring data of an AW channel corresponding to the moment T1; AW2 is the monitoring data of the AW channel corresponding to the moment T3; b1 is the monitoring data of the B channel corresponding to the moment T4; AR1 refers to the monitored data of the AR channel corresponding to time T3.

Data packet corresponding to time T1: head (fixed head identifier +5' b 00001) +t1+aw1;

data packet corresponding to time T2: head (fixed head identifier +5' b 00010) +t2+w1;

Data packet corresponding to time T3: head (fixed head identifier +5' b 01001) +t3+aw2+ar1;

data packet corresponding to time T4: head (fixed head identifier +5' B00100) +t4+b1;

At other times, if none of the five channels has valid data transmission, no packetization will take place.

As shown in fig. 9, the detailed information monitoring section includes: the system comprises a packet module, a data processing and buffering module and a write storage module, and specifically comprises: the packet module acquires data to be monitored from the acquired bus data, and packages the data to be monitored into a first data packet with aligned designated bit width; the data processing and caching module extracts effective data from the first data packet, performs splicing and caching according to the second bit width after aligning according to the designated bit width, and starts to transmit the data to the write storage module until the cached data quantity meets the configuration requirement or the overtime condition; the writing storage module is used for writing the second data packet into the external storage device as detailed monitoring information.

Further, as shown in fig. 10, the detailed information monitoring section includes: the device comprises a packet module, a first buffer module, an effective data extraction and bit width splicing module, a second buffer module and a write storage module. The second output interface of the multiplexer is connected with a packet module, the first buffer memory module, the effective data extraction and bit width splicing module, the second buffer memory module and the write memory module are sequentially connected, and the write memory module is connected with external memory equipment.

The packet module is used for acquiring data to be monitored from the acquired bus data and packaging the monitored data into a first data packet with a first bit width. And the packet grouping module packages the monitoring data and the timestamp information in the bus to be monitored into a first data packet with a fixed bit width a in a specified format. In practice, the specific format and fixed bit width a of the package is determined by the monitoring information required. In the scenario shown in fig. 8, if the actual length of the first packet at the time T1 is 90 bits and the alignment bit width is designated as 32 bits, the length of the aligned first packet is 96 bits.

Since the first data packet contains a time stamp, the first data packet can be used to monitor a time-dependent bus performance index, for example: the transmission delay, transmission bandwidth and the like on the bus can also be used for judging whether the bus is jammed or not. In the example shown in fig. 8, in the first packet produced at time T1, the r, ar, b, w channels are not valid, and the corresponding fields are all filled with 0 s; in the first data packet at the time of T3, r, b and w channels are invalid, and corresponding fields are filled with 0. It can be seen that in the first data packet, the effective channel and the effective data length of the packet can be resolved according to the value of ch_valid, and then the effective data is extracted according to the information, and the designated bit width alignment is performed.

The first packet may contain invalid performance data since it repacks the monitoring data of the invalid channel by 0. In the device provided in this embodiment, in order to clear invalid performance data, to improve the bandwidth utilization rate, a first buffer module is further required to be used. The first buffer module is used for buffering the first data packet so as to facilitate the subsequent effective data extraction.

The effective data extraction and bit width splicing module is used for extracting effective performance data in the first data packet, splicing effective monitoring data into a second data packet with a second bit width after aligning according to the appointed bit width, and splicing the appointed bit width into the second data packet with a fixed bit width after aligning according to the appointed bit width. Because the second data packet is of a fixed bit width, when the length of the first data packet with the aligned designated bit width is smaller than the fixed bit width required by the second data packet, a plurality of effective data packets can be loaded in the same second data packet, so that the utilization rate of bandwidth is improved, and bandwidth resources are saved. In the scenario shown in fig. 8, if the valid data packet aligned at the time T1 is 96 bits, the valid data packet aligned at the time T2 is 64 bits, the second data packet requires that the spliced data bit width be 128 bits, the valid data packet at the time T1 and the first 32 bits in the valid data packet at the time T2 may be combined to form a second data packet of 128 bits, and the last 32 bits in the valid data packet at the time T2 is used as the second data packet.

In the actual data transmission process of the bus, the situation of burst transmission may occur, and under the situation of burst transmission, after the bus transmits an address request and a data request length once, the requested data is transmitted in a plurality of clock beats, so that the influence on the bandwidth utilization rate of the bus caused by repeated address request transmission is avoided, the bandwidth utilization rate is improved, and the bus transmission overhead is reduced. The device provided in this embodiment further includes a second buffer module, where the second buffer module is configured to buffer the second data packet, so as to support burst transmission.

The write storage module is used for writing the second data packet into the external storage device as detailed monitoring performance information. The external storage device can acquire a larger storage space, and the acquired detailed monitoring information is stored in the external storage device, so that the storage of the detailed monitoring information with larger data volume can be supported. However, since the detailed monitoring result needs to be written into the storage device, the path interface and the bandwidth between the writing storage module and the external storage device need to be additionally considered when the system is integrated.

The bus performance monitoring device provided by the embodiment is not limited by the number of pins of the chip, and can realize different monitoring modes through the brief information monitoring component and the detailed information monitoring component so as to support two monitoring schemes of bus detailed information and bus brief information, and can be used independently; supporting multichannel input through a multiplexer, and performing bus monitoring switching through user configuration; the monitoring data of each path of bus can be respectively input into the required detection component by multiplexing the brief information monitoring component and the detailed information monitoring component, so as to realize simultaneous monitoring of multiple paths of buses.

Based on the method and the device for monitoring the bus performance provided by the embodiment, the embodiment provides an example of performance monitoring in an actual scene. In this embodiment, the SOC system is described using a high-performance expansion bus interface (Advanced eXtensible Interface, abbreviated as AXI) protocol. It will be appreciated that the present embodiment is merely an implementation example in a specific scenario, and the method and apparatus provided in the present embodiment are not limited to monitoring only bus transmission of axi protocol, and in other protocols or other scenarios, adaptation and variation may be performed with reference to the specific implementation method in the present embodiment, and feature extraction and monitoring of performance data may be performed according to read-write characteristics specified by other protocols.

When monitoring is performed, firstly, according to step 101, the device provided in this embodiment is accessed to the position of the "performance monitoring device" on the bus to be monitored in the manner shown in fig. 2. Then, according to step 102, the multi-channel bus data and the corresponding configuration data are input to the brief information monitoring unit or the detailed information monitoring unit, corresponding performance information is obtained, and the obtained performance information is stored.

In a complete write data transfer: after the address, id number, length and other information are sent by the write address channel of the host (master), the write data channel sends the relevant data. After receiving the write data, the slave (slave) replies a response signal corresponding to the id number to inform the master whether the write request is successful.

In one complete read data transfer: and after receiving the read request, the slave returns information such as the corresponding id number, the data with the corresponding length and the like in the read data channel.

In the apparatus provided in this embodiment, the brief information monitoring unit and the detailed information monitoring unit both receive configuration information of the monitoring bus, for example: fixing the id of the read or write request in the axi protocol; it is also necessary to receive monitoring configuration information for setting items such as the number of detected data requests, for calculating average delay information of the bus, and the like. When the actual behavior of the bus to be tested is monitored to meet the expected behavior of the configured bus, the calculation of the brief performance information such as total data quantity of the bus transmission request is started, or the monitoring results such as data transmission errors are analyzed according to the detailed monitoring information.

The axi protocol is divided into five channels: the device comprises a write address channel, a write data channel, a write response channel, a read address channel and a read data channel, wherein the five channels are mutually independent. In this embodiment, an axi bus protocol is used as an example, and a specific format when the detailed information monitoring unit concatenates control information into a first data packet is described. Other protocols can also compose the control information of the read-write request into a first data packet according to the fixed format according to the scheme, acquire a second data packet according to the first data packet, and then write the second data packet into the memory device (memory).

(1) Write address channel: and forming control information such as awsize, awlen, awid, awaddr into a write address channel monitoring information packet (aw_pack_data) according to a fixed sequence. By monitoring the information in the information packet, whether the address transmission request meets the expectations when the master initiates the write request, the transmission length of the write data request and other information can be judged.

(2) Read address channel: and forming arsize, arlen, arid, araddr and other control information into a read address channel detection information packet (ar_pack_data) according to a fixed sequence. By monitoring the information, whether the address transmission request meets the expectations when the master initiates the read request or not and the information such as the transmission length of the read data request can be judged.

(3) Write data channel: and forming control information such as wid into a write data channel monitoring information packet (w_pack_data) according to a fixed sequence. The wid may be configured according to a user requirement whether monitoring is needed, and if the wid information is not needed to be monitored, w_pack_data is empty. By monitoring this information, it can be judged whether or not abnormality occurs in the write data channel.

(4) Write response channel: and forming control information such as bresp, bid and the like into a write response channel monitoring information packet (b_pack_data) according to a fixed sequence. By monitoring this information, it can be determined whether a master initiated write request transmission is erroneous, etc.

(5) Read data channel: control information such as rresp, rid and the like is formed into a read data channel detection information packet (r_pack_data) according to a fixed sequence. By monitoring this information, it can be judged whether or not an error has occurred in the read transfer request, or the like.

In order to facilitate comprehensive analysis of performance data of five channels, the pack_data packets of the five channels may also be formed into a first data packet pack_data according to a fixed sequence. In one practical scenario, as shown in fig. 11, the first packet specifies the format as: r_pack_data, ar_pack_data, b_pack_data, w_pack_data, aw_pack_data, time_stamp, ch_valid, in the figure: MSB (Most Significant Bit) denotes the most significant bit; LSB (LEAST SIGNIFICANT Bit) represents the least significant Bit. When a current point in time of a certain channel is invalid performance data, a corresponding number of 0 s are used for filling in corresponding positions.

The time_stamp is time stamp information, and by binding the effective information monitored each time with the time stamp, delay information, transmission bandwidth and other information in the data transmission process can be flexibly analyzed.

When the ch_valid is a channel valid flag and a first data packet is generated, the valid monitoring data are spliced according to the sequence, a space is reserved for the monitoring data of the invalid channel, and the ch_valid is used for indicating the channel corresponding to each valid monitoring data. The bit width of chvalid is determined by the number of channels. In this embodiment, the axi protocol contains 5 channels, so ch_valid is 1 data of 5 bits. In practical implementation, the channel corresponding to each bit of ch_valid may be determined according to the sequence of the pack_data of each channel in the first data packet. In this embodiment, the channels corresponding to each bit of ch_valid are respectively: r_ chvld, ar_ chvld, b_ chvld, w_ chvld, aw_ chvld.

In a specific scenario, when only the data of the aw_ chvld channel is valid, r_pack_data, ar_pack_data, b_pack_data and w_pack_data are invalid data. The aw_pack_data is valid data, the real data is directly written in the first packet according to the designated bit width, and the corresponding bit is set to 1 in ch_valid. chvalid=5' b00001.

In the analysis in step 103, it may be determined whether the monitoring data to each channel in the data packet is valid or not according to the value of each bit in the chvalid. For example: in a specific scenario, only the write data channel is valid, and when ch_valid=0b 00010, the valid packet written into the storage device is as shown in fig. 12, which is: { w_pack_data, time_stamp, ch_valid }, if the system is not set to monitor wid at this time, the packet written into the memory is: { time_stamp, ch_valid }; in another specific scenario, when chvalid=0b10010, the valid packet written to the storage device is as shown in fig. 13, which is: { r_pack_data, w_pack_data, time_stamp, ch_valid }; in another specific scenario, when chvalid=0b 01001, the valid packet indicating writing into the storage device is { ar_pack_data, aw_pack_data, time_stamp, chvalid } as shown in fig. 14.

In the process of the post-silicon test, the data length of the actual effective data packet monitored by the bus at each time can be determined according to the value of the ch_valid read at each time and the fixed format formed by the data packets, so that the data position corresponding to the ch_valid of the next actual effective data packet is presumed, and the like, all bus transmission information of the monitoring can be obtained, and the data read in the memory device can be analyzed by correlating the control signals of each request and response with the time stamp, so that the information of the data bandwidth, bus delay, whether the bus is jammed and the like can be presumed.

Therefore, the method and the device provided by the embodiment can realize the acquisition and analysis of the data to be monitored of the multi-path bus under different scenes, and complete the performance monitoring of the multi-path bus.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims

1. A method of bus performance monitoring, comprising:

Acquiring bus data on multiple buses, and selecting one path of bus data to be monitored from the acquired bus data through a multiple selector;

Acquiring brief performance information in bus data to be monitored through a brief information monitoring component, and writing the brief performance information into a register;

The method comprises the steps of obtaining data to be monitored in a bus to be monitored through a detailed information monitoring component, packaging each obtained data to be monitored and timestamp information of the data to be monitored, adding a packet header into the obtained data to be monitored according to a specified format, generating a first data packet with a first bit width, and carrying out first data caching on the first data packet; acquiring a first data packet of a first data cache, extracting effective data to be monitored in the first data packet, extracting effective data from the first data packet according to a channel effective mark and a specified format of the first data packet, splicing the extracted effective data into a second data packet with a second bit width after aligning according to a specified bit width, carrying out second cache on the second data packet, taking the cached second data packet as a spliced data packet, and writing the spliced data packet into an external storage device; the data to be monitored is control information of each data request in the bus data to be monitored;

And respectively acquiring performance information in the register and the external storage device, and analyzing a monitoring result of the bus to be monitored according to the performance information.

2. The method for monitoring bus performance according to claim 1, wherein the acquiring, by the profile monitoring unit, profile performance information in the bus data to be monitored includes:

When the brief information monitoring component monitors data requests on the bus to be monitored, data transmission monitoring and average delay calculation are carried out for corresponding times according to the number of configured data requests, meanwhile, the maximum delay and the minimum delay of bus transmission are updated in real time, data to be monitored in each data transmission are monitored, and brief performance information of the bus to be monitored is calculated according to all data transmission data to be monitored.

3. The method for monitoring bus performance according to claim 1, wherein the obtaining data to be monitored in the bus data to be monitored, and the step of adding a packet header to each obtained data to be monitored and timestamp information of the data to be monitored and packaging the obtained data to be monitored according to a specified format, and the step of generating a first data packet with a first bit width comprises:

The method comprises the steps of obtaining data to be monitored in each channel of a bus to be monitored, forming data to be monitored with the same time stamp in one channel into data packets with corresponding time stamps of the channel according to a designated sequence, binding the data packets with the same time stamp with the corresponding time stamps, and adding channel effective marks to the data packets with the same time stamp in all channels according to the channel sequence to form a first data packet with the time stamp.

4. A method for monitoring bus performance according to claim 3, wherein when there are one or more invalid data to be monitored in the data to be monitored of the corresponding time stamp, the grouping the data to be monitored of the same time stamp in a channel into the data packets of the corresponding time stamp of the channel according to the designated sequence includes:

filling the data to be monitored of the invalid channel with 0 of the corresponding bit width, and forming the filled data to be monitored into a data packet.

5. The method for monitoring bus performance according to claim 1, wherein the extracting valid data from the first data packet according to the channel valid flag and the specified format of the first data packet, and aligning the extracted valid data according to the specified bit width comprises:

And determining a monitored effective channel according to the value of the channel effective mark of the first data packet, determining the effective monitoring data length of the first data packet according to the data to be monitored of the effective channel, extracting the effective monitoring data, and aligning the effective monitoring data according to the designated bit width to obtain the effective data packet.

6. The method for monitoring bus performance according to claim 5, wherein when using the detailed information monitoring unit, the analyzing the monitoring result of the bus to be monitored according to the performance information includes:

starting from the first effective data packet, acquiring the value of each bit in the channel effective mark of the current effective data packet and the data length of the data to be monitored of the channel corresponding to each bit;

acquiring each piece of data to be monitored in the current effective data packet according to the data length of the data to be monitored, and acquiring monitoring information of a corresponding channel according to the corresponding position in the channel effective mark;

And calculating the length of the current effective data packet according to the bit value and the length of the data to be monitored of the corresponding channel, acquiring the next current effective data packet according to the length of the current effective data packet until all effective data packets to be analyzed are acquired, and analyzing the performance monitoring result of the bus to be monitored according to the information to be monitored in all the acquired effective data packets.

7. An apparatus for bus performance monitoring, comprising: a register, a multiplexer, a profile monitoring unit and a detail monitoring unit for implementing the method of bus performance monitoring of any one of claims 1 to 6, wherein:

the register is used for storing the external configuration information and the performance information acquired by the brief information monitoring component;

The multi-path selector is used for acquiring one path or multiple paths of bus data to be monitored in the external bus data to be monitored, and sending the acquired bus data to the selected brief information monitoring component and/or the detailed information monitoring component;

the brief information monitoring component is used for acquiring brief performance information according to the acquired bus data and external configuration information and writing the brief performance information into the register;

The detailed information monitoring part is used for acquiring detailed performance information according to the acquired bus data and external configuration information and writing the detailed monitoring information into an external storage device.

8. The apparatus for bus performance monitoring according to claim 7, wherein the profile monitoring means comprises: the system comprises a read data brief information monitoring module and a write data brief information monitoring module;

when the read data brief information monitoring module monitors the read data behavior in the external bus data to be monitored, the read data brief information monitoring module is used for calculating brief performance information in the acquired bus data;

When the write data brief information monitoring module monitors the write data behavior in the bus data to be monitored, the write data brief information monitoring module is used for calculating brief performance information in the acquired bus data.

9. The apparatus for bus performance monitoring according to claim 7, wherein the detailed information monitoring means includes: the system comprises a packet module, a data processing and buffering module and a write storage module, wherein:

the method comprises the steps that a packet grouping module acquires data to be monitored from acquired bus data, and packages the data to be monitored into a first data packet with a first bit width and a fixed length;

The data processing and caching module extracts effective data from the first data packet, performs splicing and caching according to the second bit width after aligning according to the designated bit width, and starts to transmit the data to the write storage module until the cached data quantity meets the configuration requirement or the overtime condition;

the writing storage module is used for writing the second data packet into the external storage device as detailed monitoring information.