CN117590207A - Pseudo-random number generation system and method in multi-channel interleaving mode in ATE - Google Patents
Pseudo-random number generation system and method in multi-channel interleaving mode in ATE Download PDFInfo
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Abstract
The invention discloses a pseudo-random number generation system and method under a multipath interleaving mode in ATE, and belongs to the field of chip automatic test equipment. The device comprises a pseudo-random number generation module, a cross mixing module MUX and an output module, wherein the pseudo-random number generation module is in communication connection with the cross mixing module MUX, the cross mixing module MUX is in communication connection with the output module, the output module is in communication connection with a test pin of a device under test DUT, and the output pin of the device under test DUT is in communication connection with a comparison judging module. The invention provides an interleaving multi-path mode, each path generates independent pseudo random number and outputs, thus the high-frequency continuous output pseudo random number stream can be realized in the interleaving multi-path mode, the learning period is short, and the programming limit is less; longer, higher quality random numbers can be generated to meet test requirements. The programmer can flexibly select any path or paths without outputting random numbers, and can select all paths to output random numbers.
Description
Technical Field
The invention relates to automatic chip testing equipment, in particular to a pseudo-random number generation system and method in a multipath interleaving mode in ATE.
Background
Chip automation test equipment, that is, ATE, is equipment for quality detection of produced IC integrated circuit chips in the chip production process, and the main purpose is to distinguish qualified chips from unqualified chips and ensure the quality and reliability of products. With the rapid development of integrated circuits, the scale of the integrated circuits is larger and larger, the requirements on the quality and the reliability of the circuits are further improved, and the testing method of the integrated circuits is also becoming more and more difficult. Therefore, research and development of IC testing are of great significance. As a test vector is an important part of IC testing, research into a method for generating the test vector is increasingly important.
At present, the chip automatic test equipment supports the generation and output of pseudo random numbers in a single-path mode, and manufacturers of automatic test equipment ATE do not support the generation of each path of pseudo random numbers in an interleaving multi-path mode, and each path of pseudo random numbers generates independent pseudo random numbers and outputs. This does not allow a high frequency continuous output of the pseudo-random number stream, which is required by high frequency continuous pseudo-random number stream clients.
Disclosure of Invention
In view of the above-mentioned problems, it is an object of the present invention to provide a pseudo-random number generating system and method in multi-path interleaving mode in ATE, which solves the above-mentioned problems.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a pseudo-random number generating system in a multipath interleaving mode in ATE comprises a pseudo-random number generating module, a cross mixing module MUX and an output module,
the pseudo-random number generation module is in communication connection with the cross mixing module MUX, and is used for producing random numbers and providing random numbers with N bits, wherein N is a positive integer;
the cross mixing module MUX is used for cross mixing a plurality of pseudo random numbers;
the cross mixing module MUX is in communication connection with the output module, and the output module is used for outputting the finally generated random number;
the output module is in communication connection with a test pin of the DUT, the output module takes the generated random number as a test vector, the test vector is an input excitation flow, the input excitation flow is input to the test pin of the DUT in each clock cycle, and the DUT outputs logic 1 and logic 0 data for testing or operation;
the output pin of the DUT is in communication connection with the comparison and judgment module, the comparison and judgment module is connected with the expected response database, and the comparison and judgment module is used for comparing the output response of the DUT in the ATE test with the expected response of the comparison and judgment module so as to judge whether the DUT is qualified or not.
As a further scheme of the invention: the pseudo-random number generation module comprises an algorithm vector Pattern program, the algorithm vector Pattern program is in communication connection with an ALPG executing program instruction, and the program instruction executes the ALPG executing algorithm vector Pattern program instruction;
the program instruction execution ALPG is in communication connection with a random number generator PR set and a random number result memory set, the random number generator PR set is in communication connection with the random number result memory, the random number generator PR set comprises a plurality of groups of random number generators, the random number result memory set comprises a plurality of groups of random number result registers, a value of any one of the random number result registers is output as a test vector, the program instruction execution ALPG is provided with a maximum of N random number generators, and the N random number result registers are provided for storing random numbers generated by the random number generators.
A method for generating pseudo random numbers in a multipath interleaving mode in ATE comprises the following steps:
s1, a pseudo-random number generating module generates a random number group and provides a random number with N bits, wherein N is a positive integer;
an algorithm vector Pattern program in the pseudo-random number generation module executes ALPG according to a program instruction to generate a random array, the program instruction executes ALPG to set up N maximum random number generators PR, N random number result registers RP are set to store results of the random number generators PR, and each instruction period RATE of a plurality of paths is interleaved, a pseudo-random generation instruction of 'RP=RP 2' is generated once, N random number generators are pushed, and N random number generators which are continuous are output once;
the output of the random number generator PR (m) is taken as input, the output of the random number generator PR (m-1) is equivalent to the output of m+1 times of random number algorithm shift operation, wherein m is a positive integer which is greater than or equal to 0 and less than or equal to N-1, and each WAY can take the value of any one of N random number result registers as a test vector to output;
s2, the cross mixing module MUX carries out cross mixing on the plurality of pseudo random numbers generated by the pseudo random number generating module according to a certain rule, the cross mixing module MUX transmits the mixed random numbers to the output module, the output module transmits the finally generated random numbers to the DUT, and the finally generated random numbers of the output module are test vectors;
s3, outputting a test result to a comparison and judgment module by the DUT, and judging whether the DUT is qualified or not by comparing the output response of the DUT in the ATE test with the expected response of the comparison and judgment module.
As a further scheme of the invention: the specific steps of the step S1 are as follows,
(1) the random number result register RP of the random number generator PR is initialized;
(2) random number generation: the value of a random number result register RP is used as input to drive N random number generators to perform linear feedback shift register LFSR or pseudo random binary sequence PRBS shift operation, and N random numbers are generated at one time;
taking the value of one of the registers RP, RP1..RPN-1 as input, driving N random number generators to make linear feedback shift register LFSR or pseudo random binary sequence PRBS, and generating N random numbers at one time;
(3) random number output: 2N bits of the random number result register RP are output to the D and SD of the WAY;
and outputting 2N bits of one register of RP1 to RPN-1 to the D and SD of the WAY to replace the original output of the D and SD.
Compared with the prior art; the beneficial effects of the invention are as follows: the invention provides an interleaving multi-path mode, each path generates independent pseudo random numbers and outputs, so that the high-frequency continuous output pseudo random number stream can be realized in the interleaving multi-path mode. The random number of the ATE tester with the multipath interleaving mode generates Pattern programming, which is similar to the programming of a single-path tester, and has short learning period. The ATE tester with the multipath interleaving mode has less random number generation Pattern programming limit; longer, higher quality random numbers can be generated to meet test requirements. The programmer can flexibly select any path or paths without outputting random numbers, and can select all paths to output random numbers.
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FIG. 1 is a schematic diagram of a pseudo-random number generation system and method in a multipath interleaving mode in ATE.
FIG. 2 is a schematic diagram of a pseudo-random number generating system and method in a multi-path interleaving mode in ATE.
FIG. 3 is a schematic diagram of an algorithm vector Pattern program output of an 8-WAY (8 WAY) algorithm in a system and method for generating pseudo-random numbers in a multi-WAY interleaving mode in ATE.
FIG. 4 is a block diagram of a system and method for generating 16-WAY (16 WAY) random numbers in a multi-WAY interleaving mode in ATE.
Detailed Description
The drawings in the embodiments of the present invention will be combined; the technical scheme in the embodiment of the invention is clearly and completely described; obviously; the described embodiments are only a few embodiments of the present invention; but not all embodiments. Based on the embodiments in the present invention; all other embodiments obtained by those skilled in the art without undue burden; all falling within the scope of the present invention.
In the description of the present invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "mounted," "provided," "connected," and "connected" are to be construed broadly; for example, the connection may be fixed connection, detachable connection, or integral connection, mechanical connection, electrical connection, direct connection, indirect connection via an intermediate medium, or communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1-2, a pseudo-random number generating system in a multi-path interleaving mode in an ate includes a pseudo-random number generating module, a cross-mixing module MUX and an output module, wherein the pseudo-random number generating module is connected with the cross-mixing module MUX and is used for providing a random number with N bits, wherein N is a positive integer, and the pseudo-random number generating module is used for producing the random number; the cross-mixing module MUX is used for cross-mixing the plurality of pseudo-random numbers according to a certain rule. This rule may be mixed by means of a simple exclusive-or operation, addition or multiplication, etc. The cross-mix module MUX may be implemented at the hardware level or at the software level. The output sequences of the plurality of pseudo-random number generators are cross-mixed according to a certain rule, thereby generating longer pseudo-random numbers. By cross-mixing multiple pseudorandom numbers, the periodicity and predictability of a single pseudorandom number generator may be reduced, thereby increasing the randomness of the random numbers generated by the overall system. The cross mixing module MUX is used for cross mixing a plurality of sequences according to a certain rule, and in addition, the length of the random number can be increased by the multi-path interleaving mode, so that the statistical property of the random number is improved, and the generated random number is more uniform and random.
The cross mixing module MUX is connected with the output module, and the output module is used for outputting the finally generated random number. The output module may output the random number to an external interface of the test equipment or directly to other modules within the ATE.
The output module is connected with a test pin of the DUT, and the output module transmits the generated random number to the DUT as a test vector, wherein the test vector is an input excitation flow and is logic 1 and logic 0 data applied to pins of the DUT device for testing or operation in each clock cycle.
The output pin of the DUT is connected with a comparison judging module, the comparison judging module is connected with an expected response database, the comparison judging module is used for judging whether the DUT is qualified by comparing the output response of the DUT in ATE test with the expected response of the comparison judging module, the DUT provides test excitation (X), and whether the DUT is qualified is judged by comparing the measured DUT output response (Y) with the expected output.
The pseudo-random number generation module comprises an algorithm vector Pattern program, the algorithm vector Pattern program is connected with an ALPG (execution ALPG) which is a vector generator of the algorithm vector Pattern program, and random numbers are generated conveniently.
The program instruction execution ALPG is connected with the random number generator PR group and the random number result memory group, the random number generator PR group is connected with the random number result memory in a communication mode, the program instruction execution ALPG is provided with a maximum of N random number generators, and N random number result registers are provided for storing results of the random number generators. In each large period RATE of the interleaving multiple paths, a pseudo-random generation instruction of 'rp=rpx2' pushes the N random number generators, and outputs the N random number generators in succession at a time. The random number generator PR group includes a plurality of sets of random number generators, and the random number result memory group includes a plurality of sets of random number result registers, the value of any one of which is output as a test vector.
A method for generating pseudo random numbers in a multipath interleaving mode in ATE comprises the following steps:
s1, a pseudo-random number generating module generates a random array, and transmits the generated random array to a cross mixing module MUX to provide a random number with N bits, wherein N is a positive integer;
vector, logic 1 and logic 0 data for test or operation applied to the DUT device pins per clock cycle;
the algorithm vector Pattern program in the pseudo-random number generation module executes ALPG according to a program instruction to generate a random array, the program instruction executes ALPG to be a vector generator of the algorithm vector Pattern program, the program instruction executes ALPG to set up a maximum N random number generators PR, and sets up N random number result registers RP to store results of the random number generators PR, and each instruction period RATE of the interleaving multiple paths is interleaved with a pseudo-random generation instruction of 'RP=RP 2', so that N random number generators are pushed and N random number generators are output at one time; n is a positive integer;
the output of the random number generator PR (m) is input with the output of the random number generator PR (m-1), and the output of the random number generator PR (m) corresponds to the output of m+1 times of random number algorithm shift operation. Each WAY may take the value of any one of the N random number result registers as a test vector output.
If the ATE supports a maximum of 16WAY, ALPG sets 16 random number generators, named random number generator PR0 to random number generator PR15, and sets up 16 random number generators RP and RP1-RP15 to store the results of the random number generators.
The random number generator PR1 takes the output of the random number generator PR0 as input, and the output of the random number generator PR1 corresponds to the output of 2 times of random number arithmetic shift operation; the random number generator PR2 takes the output of the random number generator PR1 as input, and the output of the random number generator PR2 corresponds to the output of 3 shift operations of the random number algorithm.
The input to the random number generator PR0 may be any of the registers RP and RP1-RP 15.
(1) The random number result register RP of the random number generator PR is initialized;
(2) random number generation: the value of the random number result register RP is used as input to drive N random number generators to perform linear feedback shift register LFSR or pseudo random binary sequence PRBS shift operation, and N random numbers are generated at one time.
(2) Random number generation: the value of a random number result register RP is used as input to drive N random number generators to perform linear feedback shift register LFSR or pseudo random binary sequence PRBS shift operation, and N random numbers are generated at one time;
taking the maximum support 16WAY of ATE as an example, taking the value of one of the registers RP, RP1..RPN-1 as input, driving N random number generators to make linear feedback shift register LFSR or pseudo random binary sequence PRBS, and generating N random numbers at one time;
(3) random number output: outputting 2N bits of a random number result register RP to the D and SD of the WAY;
and outputting 2N bits of one register of RP1 to RPN-1 to the D and SD of the WAY to replace the original output of the D and SD.
Taking the maximum support 16WAY of ATE as an example, the 32bit output of one register of RP1 to RP15 is output to the D and SD of the WAY to replace the original output of the D and SD.
For "d=rpn", "rp=rpn×2", the compiler performs the following compiling check on RPn, and if the available register is exceeded, the error is reported:
2Way available RP, RP1 register
4Way available RP, RP1-RP3 registers
8Way available RP, RP1-RP7 registers
16Way enable RP, RP1-RP15 register
Each WAY may use any RPn register as output.
In the instruction "rp=rpn×2" for generating a random number for the next cycle in one NWAY large cycle, if RPn is not the RPn of the maximum output of the cycle, the random number generated for the next cycle may be repeated with the present cycle.
S2, the cross mixing module MUX carries out cross mixing on a plurality of pseudo random numbers according to a certain rule, so that longer pseudo random numbers are generated, the periodicity and predictability of a single pseudo random number generator can be reduced, and the randomness of random numbers generated by the whole system is improved; the cross mixing module MUX transmits the mixed random number to the output module, the output module transmits the finally generated random number to the DUT, and the finally generated random number of the output module is the test.
S3, outputting a test result to a comparison and judgment module by the DUT, and judging whether the DUT is qualified or not by comparing the output response of the DUT in the ATE test with the expected response of the comparison and judgment module.
The multipath interleaving mode can also increase the length of the random number, improve the statistical property of the random number and enable the generated random number to be more uniform and random.
In order to test high-frequency IC chips, interleaving (interleaving) and multiplexing (NWAY) technologies have been proposed. The method is that more sub-cycle instructions are contained in a Pattern instruction of one cycle. FIG. 3 is an example of a Pattern output of 8 paths (8 WAY).
As shown in FIG. 3, RATE is a Pattern instruction cycle and RATE1 through RATE8 are sub-cycles that end up on the chip under test.
In the case of multiple interleaving, all Pattern instructions at one RATE output test vectors simultaneously. The original method for generating the instruction by the single-path random number needs to be adjusted, otherwise, only one random number can be generated under one RATE, and the random number cannot be continuously output in the high-frequency subcycle under the RATE.
To achieve the generation of each pseudo random number in the interleaved multi-path mode. The ALPG of the automated test equipment ATE sets up a maximum of N random number generators and sets up N random number result registers storing the results of these random number generators.
In each large period RATE of the interleaving multiple paths, a pseudo-random generation instruction of 'rp=rpx2' pushes the N random number generators, and outputs the N random number generators in succession at a time.
Each WAY may take the value of any one of the N random number result registers as a test vector output.
The NWAY random number generation flow framework is shown in fig. 4 below, which is a maximum 16-way ALPG, and the number of random number generators and registers increases to N for more ways.
The invention provides an interleaving multi-path mode, each path generates independent pseudo random numbers and outputs, so that the high-frequency continuous output pseudo random number stream can be realized in the interleaving multi-path mode. The random number of the ATE tester with the multipath interleaving mode generates Pattern programming, which is similar to the programming of a single-path tester, and has short learning period. The ATE tester with the multipath interleaving mode has less random number generation Pattern programming limit; the programmer can flexibly select any path or paths without outputting random numbers, and can select all paths to output random numbers.
The pseudo random number generation system in the multi-interleaving mode is a system for generating a higher quality random number by cross-mixing a plurality of pseudo random numbers. In the multiple interleaving mode, the output sequences of the multiple pseudo random number generators are cross-mixed according to a certain rule, thereby generating longer pseudo random numbers.
In ATE, pseudo-random number generation in a multiple interleave mode is commonly used to test and verify the performance, reliability, and security of a system. By using multiple pseudo random numbers to cross mix, longer, higher quality random numbers can be generated to meet test requirements.
As would be apparent to one skilled in the art; it is obvious that the invention is not limited to the details of the above-described exemplary embodiments; and without departing from the spirit or essential characteristics of the invention; the invention can be embodied in other specific forms. Thus, the method comprises the steps of; from either point of view; the embodiments should be considered as exemplary; and is non-limiting; the scope of the invention is indicated by the appended claims rather than by the foregoing description; it is therefore intended to include within the invention all changes that fall within the meaning and range of equivalency of the claims. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it is provided that; it should be understood that; although the present description describes embodiments; but not every embodiment contains only one independent technical solution; this manner of description is for clarity only; the skilled artisan should recognize the specification as a whole; the technical solutions in the embodiments may also be combined appropriately; forming other embodiments as will be appreciated by those skilled in the art.
Claims (4)
- A pseudo-random number generating system in a multipath interleaving mode in ATE is characterized by comprising a pseudo-random number generating module, a cross mixing module MUX and an output module,the pseudo-random number generation module is in communication connection with the cross mixing module MUX, and is used for producing random numbers and providing random numbers with N bits, wherein N is a positive integer;the cross mixing module MUX is used for cross mixing a plurality of pseudo random numbers;the cross mixing module MUX is in communication connection with the output module, and the output module is used for outputting the finally generated random number;the output module is in communication connection with a test pin of the DUT, the output module takes the generated random number as a test vector, the test vector is an input excitation flow, the input excitation flow is input to the test pin of the DUT in each clock cycle, and the DUT outputs logic 1 and logic 0 data for testing or operation;the output pin of the DUT is in communication connection with the comparison and judgment module, the comparison and judgment module is connected with the expected response database, and the comparison and judgment module is used for comparing the output response of the DUT in the ATE test with the expected response of the comparison and judgment module so as to judge whether the DUT is qualified or not.
- 2. The system according to claim 1, wherein the pseudo-random number generating module comprises an algorithm vector Pattern program, wherein a program instruction execution ALPG is provided in the algorithm vector Pattern program, and the program instruction execution ALPG executes the instruction of the algorithm vector Pattern program;the program instruction execution ALPG is in communication connection with a random number generator PR set and a random number result memory set, the random number generator PR set is in communication connection with the random number result memory, the random number generator PR set comprises a plurality of groups of random number generators, the random number result memory set comprises a plurality of groups of random number result registers, a value of any one of the random number result registers is output as a test vector, the program instruction execution ALPG is provided with a maximum of N random number generators, and the N random number result registers are provided for storing random numbers generated by the random number generators.
- 3. A method according to any of claims 1-2 for a pseudo-random number generating system in a multipath interleaving mode in ATE, characterized by the method steps of:s1, a pseudo-random number generating module generates a random number group and provides a random number with N bits, wherein N is a positive integer;an algorithm vector Pattern program in the pseudo-random number generation module executes ALPG according to a program instruction to generate a random array, the program instruction executes ALPG to set up N maximum random number generators PR, N random number result registers RP are set to store results of the random number generators PR, and each instruction period RATE of a plurality of paths is interleaved, a pseudo-random generation instruction of 'RP=RP 2' is generated once, N random number generators are pushed, and N random number generators which are continuous are output once;the output of the random number generator PR (m) is taken as input, the output of the random number generator PR (m-1) is equivalent to the output of m+1 times of random number algorithm shift operation, wherein m is a positive integer which is greater than or equal to 0 and less than or equal to N-1, and each WAY can take the value of any one of N random number result registers as a test vector to output;s2, the cross mixing module MUX carries out cross mixing on the plurality of pseudo random numbers generated by the pseudo random number generating module according to a certain rule, the cross mixing module MUX transmits the mixed random numbers to the output module, the output module transmits the finally generated random numbers to the DUT, and the finally generated random numbers of the output module are test vectors;s3, outputting a test result to a comparison and judgment module by the DUT, and judging whether the DUT is qualified or not by comparing the output response of the DUT in the ATE test with the expected response of the comparison and judgment module.
- 4. The method of claim 3, wherein said step S1 is performed by,(1) the random number result register RP of the random number generator PR is initialized;(2) random number generation: the value of a random number result register RP is used as input to drive N random number generators to perform linear feedback shift register LFSR or pseudo random binary sequence PRBS shift operation, and N random numbers are generated at one time;taking the value of one of the registers RP, RP1..RPN-1 as input, driving N random number generators to make linear feedback shift register LFSR or pseudo random binary sequence PRBS, and generating N random numbers at one time;(3) random number output: 2N bits of the random number result register RP are output to the D and SD of the WAY;and outputting 2N bits of one register of RP1 to RPN-1 to the D and SD of the WAY to replace the original output of the D and SD.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080320066A1 (en) * | 2007-06-22 | 2008-12-25 | Lsi Logic Corporation | Cryptographic random number generator using finite field operations |
| US20090222667A1 (en) * | 2005-03-01 | 2009-09-03 | Nxp B.V. | Generator for generating a message authentication code, method of generating a message authentication code, program element and computer-readable medium |
| CN108139889A (en) * | 2015-10-12 | 2018-06-08 | 甲骨文国际公司 | Pseudo-random number sequence is generated by the non-linear mixing of multiple auxiliary pseudo-random number generator |
-
2023
- 2023-11-22 CN CN202311566017.9A patent/CN117590207B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090222667A1 (en) * | 2005-03-01 | 2009-09-03 | Nxp B.V. | Generator for generating a message authentication code, method of generating a message authentication code, program element and computer-readable medium |
| US20080320066A1 (en) * | 2007-06-22 | 2008-12-25 | Lsi Logic Corporation | Cryptographic random number generator using finite field operations |
| CN108139889A (en) * | 2015-10-12 | 2018-06-08 | 甲骨文国际公司 | Pseudo-random number sequence is generated by the non-linear mixing of multiple auxiliary pseudo-random number generator |
Non-Patent Citations (2)
| Title |
|---|
| 张江江: "高速量子随机数产生中熵含量实时评测及后处理", 基础科学;信息科技, 15 February 2023 (2023-02-15) * |
| 张金宝;李新阳;陈波;: "基于FPGA的伪随机序列的生成方法及应用", 微计算机信息, no. 29, 15 October 2009 (2009-10-15) * |
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